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[74.87.59.234]) by smtp.gmail.com with ESMTPSA id d17-20020aa78691000000b0058d99337381sm10337011pfo.172.2023.02.14.08.30.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 08:30:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 01/14] target/arm: Normalize aarch64 gdbstub get/set function names Date: Tue, 14 Feb 2023 06:30:35 -1000 Message-Id: <20230214163048.903964-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230214163048.903964-1-richard.henderson@linaro.org> References: <20230214163048.903964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Make the form of the function names between fp and sve the same: - arm_gdb_*_svereg -> aarch64_gdb_*_sve_reg. - aarch64_fpu_gdb_*_reg -> aarch64_gdb_*_fpu_reg. Signed-off-by: Richard Henderson Reviewed-by: Fabiano Rosas --- target/arm/internals.h | 8 ++++---- target/arm/gdbstub.c | 9 +++++---- target/arm/gdbstub64.c | 8 ++++---- 3 files changed, 13 insertions(+), 12 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index e1e018da46..69b5e7ba73 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1340,10 +1340,10 @@ static inline uint64_t pmu_counter_mask(CPUARMState *env) } #ifdef TARGET_AARCH64 -int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg); -int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg); -int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg); -int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg); +int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg); +int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg); +int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg); +int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg); void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 2f806512d0..cf1c01e3cf 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -466,12 +466,13 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) */ #ifdef TARGET_AARCH64 if (isar_feature_aa64_sve(&cpu->isar)) { - gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg, - arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs), + int nreg = arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs); + gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg, + aarch64_gdb_set_sve_reg, nreg, "sve-registers.xml", 0); } else { - gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, - aarch64_fpu_gdb_set_reg, + gdb_register_coprocessor(cs, aarch64_gdb_get_fpu_reg, + aarch64_gdb_set_fpu_reg, 34, "aarch64-fpu.xml", 0); } #endif diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 07a6746944..c598cb0375 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -72,7 +72,7 @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) return 0; } -int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) +int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg) { switch (reg) { case 0 ... 31: @@ -92,7 +92,7 @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) } } -int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) +int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg) { switch (reg) { case 0 ... 31: @@ -116,7 +116,7 @@ int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) } } -int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg) +int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg) { ARMCPU *cpu = env_archcpu(env); @@ -164,7 +164,7 @@ int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg) return 0; } -int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg) +int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg) { ARMCPU *cpu = env_archcpu(env); From patchwork Tue Feb 14 16:30:36 2023 Content-Type: text/plain; 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[74.87.59.234]) by smtp.gmail.com with ESMTPSA id d17-20020aa78691000000b0058d99337381sm10337011pfo.172.2023.02.14.08.30.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 08:30:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 02/14] target/arm: Unexport arm_gen_dynamic_sysreg_xml Date: Tue, 14 Feb 2023 06:30:36 -1000 Message-Id: <20230214163048.903964-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230214163048.903964-1-richard.henderson@linaro.org> References: <20230214163048.903964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This function is not used outside gdbstub.c. Signed-off-by: Richard Henderson Reviewed-by: Fabiano Rosas --- target/arm/cpu.h | 1 - target/arm/gdbstub.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7bc97fece9..b2c49b3605 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1114,7 +1114,6 @@ int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); * Helpers to dynamically generates XML descriptions of the sysregs * and SVE registers. Returns the number of registers in each set. */ -int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg); int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); /* Returns the dynamically generated XML for the gdb stub. diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index cf1c01e3cf..52581e9784 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -305,7 +305,7 @@ static void arm_register_sysreg_for_xml(gpointer key, gpointer value, } } -int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg) +static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg) { ARMCPU *cpu = ARM_CPU(cs); GString *s = g_string_new(NULL); From patchwork Tue Feb 14 16:30:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 653474 Delivered-To: patch@linaro.org Received: by 2002:adf:f90f:0:0:0:0:0 with SMTP id b15csp3146967wrr; Tue, 14 Feb 2023 08:32:57 -0800 (PST) X-Google-Smtp-Source: AK7set/ZIEyPOEeQn/JjY7Gu1ho+RTdxnmQTzXloP4c2WOBMPdcRNVEqr1SPtrc1KShs/Kc8ijXT X-Received: by 2002:a05:6214:20a4:b0:568:89e3:c5ca with SMTP id 4-20020a05621420a400b0056889e3c5camr5849342qvd.13.1676392377765; Tue, 14 Feb 2023 08:32:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676392377; cv=none; d=google.com; s=arc-20160816; b=vgOGxGC5ChrJMX9+Kmtkg3059s5eXaVXGuzbl1mjvL3wye42R1nBUa1vboYcS1KikR tyPn29sIVCmu5QR3BY4p5NebHaYva6e5m0OD64grb3vUCHQlrVAotvOTjLy5eg/xxzWK /JIfJN/Agp7r96ZqjzOv1b8H+3Av0fyOP4hs07H6RK5QJyqM7ITNJNZ7QPSIPFbrXEzs oSRr2kxW52PvgLFSgUAZGEXkdtDogv48C8X2HZKBqKiFMU/l1ZWBzxnFGBanJa/6rimG m1YIYUlH5p/XtM7Pp7yo0Mj/kwoguSgI+wmYemmQTeJiFfVVpyQh+kQ90xVNwUiA3pwP 8OJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=mvgiDpyQbdYw4jcH8pTJPq847zR7SPy67CXXghghUYE=; b=Dw7F9biAFLsfQz10enLQ5R7vxOrMwXrJDjlxH638J9B7CeIij2CZGNrpr86JgE2xsI q+e5aagjqW2CB4iCe/6kp9ycL0dKqAbvWpPsZSIF8K7x3Mav3TJIZhT1jXwUSFTQVslC pZ2/tfflJrFp0jvAvrlXb4LksbG4v/m+KNyfhyPQg4mPTGoiWegysolPSBuH9ilPSt4H VCr2k+vDOG8CvqGpHZtvlk/67hoDf+36JjUqemVkFj1mYUjYZXcbTYxa7XGCHSTKi6rW d/R4KKotCKE1SnGdv53Z7Zh0stfXrxZfTps7E41kslIFiHcizHGIWyFoXDBrbaxf/svK UXdg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="LZZ/dH8z"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[74.87.59.234]) by smtp.gmail.com with ESMTPSA id d17-20020aa78691000000b0058d99337381sm10337011pfo.172.2023.02.14.08.30.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 08:30:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 03/14] target/arm: Move arm_gen_dynamic_svereg_xml to gdbstub64.c Date: Tue, 14 Feb 2023 06:30:37 -1000 Message-Id: <20230214163048.903964-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230214163048.903964-1-richard.henderson@linaro.org> References: <20230214163048.903964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The function is only used for aarch64, so move it to the file that has the other aarch64 gdbstub stuff. Move the declaration to internals.h. Signed-off-by: Richard Henderson Reviewed-by: Fabiano Rosas --- target/arm/cpu.h | 6 --- target/arm/internals.h | 1 + target/arm/gdbstub.c | 120 ----------------------------------------- target/arm/gdbstub64.c | 118 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 119 insertions(+), 126 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b2c49b3605..c9f768f945 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1110,12 +1110,6 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -/* - * Helpers to dynamically generates XML descriptions of the sysregs - * and SVE registers. Returns the number of registers in each set. - */ -int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); - /* Returns the dynamically generated XML for the gdb stub. * Returns a pointer to the XML contents for the specified XML file or NULL * if the XML name doesn't match the predefined one. diff --git a/target/arm/internals.h b/target/arm/internals.h index 69b5e7ba73..c98482561e 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1340,6 +1340,7 @@ static inline uint64_t pmu_counter_mask(CPUARMState *env) } #ifdef TARGET_AARCH64 +int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg); int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg); int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg); diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 52581e9784..bf8aff7824 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -322,126 +322,6 @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg) return cpu->dyn_sysreg_xml.num; } -struct TypeSize { - const char *gdb_type; - int size; - const char sz, suffix; -}; - -static const struct TypeSize vec_lanes[] = { - /* quads */ - { "uint128", 128, 'q', 'u' }, - { "int128", 128, 'q', 's' }, - /* 64 bit */ - { "ieee_double", 64, 'd', 'f' }, - { "uint64", 64, 'd', 'u' }, - { "int64", 64, 'd', 's' }, - /* 32 bit */ - { "ieee_single", 32, 's', 'f' }, - { "uint32", 32, 's', 'u' }, - { "int32", 32, 's', 's' }, - /* 16 bit */ - { "ieee_half", 16, 'h', 'f' }, - { "uint16", 16, 'h', 'u' }, - { "int16", 16, 'h', 's' }, - /* bytes */ - { "uint8", 8, 'b', 'u' }, - { "int8", 8, 'b', 's' }, -}; - - -int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) -{ - ARMCPU *cpu = ARM_CPU(cs); - GString *s = g_string_new(NULL); - DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; - g_autoptr(GString) ts = g_string_new(""); - int i, j, bits, reg_width = (cpu->sve_max_vq * 128); - info->num = 0; - g_string_printf(s, ""); - g_string_append_printf(s, ""); - g_string_append_printf(s, ""); - - /* First define types and totals in a whole VL */ - for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { - int count = reg_width / vec_lanes[i].size; - g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix); - g_string_append_printf(s, - "", - ts->str, vec_lanes[i].gdb_type, count); - } - /* - * Now define a union for each size group containing unsigned and - * signed and potentially float versions of each size from 128 to - * 8 bits. - */ - for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { - const char suf[] = { 'q', 'd', 's', 'h', 'b' }; - g_string_append_printf(s, "", suf[i]); - for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { - if (vec_lanes[j].size == bits) { - g_string_append_printf(s, "", - vec_lanes[j].suffix, - vec_lanes[j].sz, vec_lanes[j].suffix); - } - } - g_string_append(s, ""); - } - /* And now the final union of unions */ - g_string_append(s, ""); - for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { - const char suf[] = { 'q', 'd', 's', 'h', 'b' }; - g_string_append_printf(s, "", - suf[i], suf[i]); - } - g_string_append(s, ""); - - /* Finally the sve prefix type */ - g_string_append_printf(s, - "", - reg_width / 8); - - /* Then define each register in parts for each vq */ - for (i = 0; i < 32; i++) { - g_string_append_printf(s, - "", - i, reg_width, base_reg++); - info->num++; - } - /* fpscr & status registers */ - g_string_append_printf(s, "", base_reg++); - g_string_append_printf(s, "", base_reg++); - info->num += 2; - - for (i = 0; i < 16; i++) { - g_string_append_printf(s, - "", - i, cpu->sve_max_vq * 16, base_reg++); - info->num++; - } - g_string_append_printf(s, - "", - cpu->sve_max_vq * 16, base_reg++); - g_string_append_printf(s, - "", - base_reg++); - info->num += 2; - g_string_append_printf(s, ""); - cpu->dyn_svereg_xml.desc = g_string_free(s, false); - - return cpu->dyn_svereg_xml.num; -} - - const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) { ARMCPU *cpu = ARM_CPU(cs); diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index c598cb0375..59fb5465d5 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -209,3 +209,121 @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg) return 0; } + +struct TypeSize { + const char *gdb_type; + short size; + char sz, suffix; +}; + +static const struct TypeSize vec_lanes[] = { + /* quads */ + { "uint128", 128, 'q', 'u' }, + { "int128", 128, 'q', 's' }, + /* 64 bit */ + { "ieee_double", 64, 'd', 'f' }, + { "uint64", 64, 'd', 'u' }, + { "int64", 64, 'd', 's' }, + /* 32 bit */ + { "ieee_single", 32, 's', 'f' }, + { "uint32", 32, 's', 'u' }, + { "int32", 32, 's', 's' }, + /* 16 bit */ + { "ieee_half", 16, 'h', 'f' }, + { "uint16", 16, 'h', 'u' }, + { "int16", 16, 'h', 's' }, + /* bytes */ + { "uint8", 8, 'b', 'u' }, + { "int8", 8, 'b', 's' }, +}; + +int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) +{ + ARMCPU *cpu = ARM_CPU(cs); + GString *s = g_string_new(NULL); + DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; + g_autoptr(GString) ts = g_string_new(""); + int i, j, bits, reg_width = (cpu->sve_max_vq * 128); + info->num = 0; + g_string_printf(s, ""); + g_string_append_printf(s, ""); + g_string_append_printf(s, ""); + + /* First define types and totals in a whole VL */ + for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { + int count = reg_width / vec_lanes[i].size; + g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix); + g_string_append_printf(s, + "", + ts->str, vec_lanes[i].gdb_type, count); + } + /* + * Now define a union for each size group containing unsigned and + * signed and potentially float versions of each size from 128 to + * 8 bits. + */ + for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { + const char suf[] = { 'q', 'd', 's', 'h', 'b' }; + g_string_append_printf(s, "", suf[i]); + for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { + if (vec_lanes[j].size == bits) { + g_string_append_printf(s, "", + vec_lanes[j].suffix, + vec_lanes[j].sz, vec_lanes[j].suffix); + } + } + g_string_append(s, ""); + } + /* And now the final union of unions */ + g_string_append(s, ""); + for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { + const char suf[] = { 'q', 'd', 's', 'h', 'b' }; + g_string_append_printf(s, "", + suf[i], suf[i]); + } + g_string_append(s, ""); + + /* Finally the sve prefix type */ + g_string_append_printf(s, + "", + reg_width / 8); + + /* Then define each register in parts for each vq */ + for (i = 0; i < 32; i++) { + g_string_append_printf(s, + "", + i, reg_width, base_reg++); + info->num++; + } + /* fpscr & status registers */ + g_string_append_printf(s, "", base_reg++); + g_string_append_printf(s, "", base_reg++); + info->num += 2; + + for (i = 0; i < 16; i++) { + g_string_append_printf(s, + "", + i, cpu->sve_max_vq * 16, base_reg++); + info->num++; + } + g_string_append_printf(s, + "", + cpu->sve_max_vq * 16, base_reg++); + g_string_append_printf(s, + "", + base_reg++); + info->num += 2; + g_string_append_printf(s, ""); + info->desc = g_string_free(s, false); + + return info->num; +} From patchwork Tue Feb 14 16:30:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 653473 Delivered-To: patch@linaro.org Received: by 2002:adf:f90f:0:0:0:0:0 with SMTP id b15csp3146837wrr; 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[74.87.59.234]) by smtp.gmail.com with ESMTPSA id d17-20020aa78691000000b0058d99337381sm10337011pfo.172.2023.02.14.08.30.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 08:30:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 04/14] target/arm: Split out output_vector_union_type Date: Tue, 14 Feb 2023 06:30:38 -1000 Message-Id: <20230214163048.903964-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230214163048.903964-1-richard.henderson@linaro.org> References: <20230214163048.903964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Create a subroutine for creating the union of unions of the various type sizes that a vector may contain. Signed-off-by: Richard Henderson Reviewed-by: Fabiano Rosas Reviewed-by: Peter Maydell --- target/arm/gdbstub64.c | 83 +++++++++++++++++++++++------------------- 1 file changed, 45 insertions(+), 38 deletions(-) diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 59fb5465d5..811833d8de 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -210,44 +210,39 @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg) return 0; } -struct TypeSize { - const char *gdb_type; - short size; - char sz, suffix; -}; - -static const struct TypeSize vec_lanes[] = { - /* quads */ - { "uint128", 128, 'q', 'u' }, - { "int128", 128, 'q', 's' }, - /* 64 bit */ - { "ieee_double", 64, 'd', 'f' }, - { "uint64", 64, 'd', 'u' }, - { "int64", 64, 'd', 's' }, - /* 32 bit */ - { "ieee_single", 32, 's', 'f' }, - { "uint32", 32, 's', 'u' }, - { "int32", 32, 's', 's' }, - /* 16 bit */ - { "ieee_half", 16, 'h', 'f' }, - { "uint16", 16, 'h', 'u' }, - { "int16", 16, 'h', 's' }, - /* bytes */ - { "uint8", 8, 'b', 'u' }, - { "int8", 8, 'b', 's' }, -}; - -int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) +static void output_vector_union_type(GString *s, int reg_width) { - ARMCPU *cpu = ARM_CPU(cs); - GString *s = g_string_new(NULL); - DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; + struct TypeSize { + const char *gdb_type; + short size; + char sz, suffix; + }; + + static const struct TypeSize vec_lanes[] = { + /* quads */ + { "uint128", 128, 'q', 'u' }, + { "int128", 128, 'q', 's' }, + /* 64 bit */ + { "ieee_double", 64, 'd', 'f' }, + { "uint64", 64, 'd', 'u' }, + { "int64", 64, 'd', 's' }, + /* 32 bit */ + { "ieee_single", 32, 's', 'f' }, + { "uint32", 32, 's', 'u' }, + { "int32", 32, 's', 's' }, + /* 16 bit */ + { "ieee_half", 16, 'h', 'f' }, + { "uint16", 16, 'h', 'u' }, + { "int16", 16, 'h', 's' }, + /* bytes */ + { "uint8", 8, 'b', 'u' }, + { "int8", 8, 'b', 's' }, + }; + + static const char suf[] = { 'q', 'd', 's', 'h', 'b' }; + g_autoptr(GString) ts = g_string_new(""); - int i, j, bits, reg_width = (cpu->sve_max_vq * 128); - info->num = 0; - g_string_printf(s, ""); - g_string_append_printf(s, ""); - g_string_append_printf(s, ""); + int i, j, bits; /* First define types and totals in a whole VL */ for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { @@ -263,7 +258,6 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) * 8 bits. */ for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { - const char suf[] = { 'q', 'd', 's', 'h', 'b' }; g_string_append_printf(s, "", suf[i]); for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { if (vec_lanes[j].size == bits) { @@ -277,11 +271,24 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) /* And now the final union of unions */ g_string_append(s, ""); for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { - const char suf[] = { 'q', 'd', 's', 'h', 'b' }; g_string_append_printf(s, "", suf[i], suf[i]); } g_string_append(s, ""); +} + +int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) +{ + ARMCPU *cpu = ARM_CPU(cs); + GString *s = g_string_new(NULL); + DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; + int i, reg_width = (cpu->sve_max_vq * 128); + info->num = 0; + g_string_printf(s, ""); + g_string_append_printf(s, ""); + g_string_append_printf(s, ""); + + output_vector_union_type(s, reg_width); /* Finally the sve prefix type */ g_string_append_printf(s, From patchwork Tue Feb 14 16:30:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 653477 Delivered-To: patch@linaro.org Received: by 2002:adf:f90f:0:0:0:0:0 with SMTP id b15csp3147396wrr; Tue, 14 Feb 2023 08:33:37 -0800 (PST) X-Google-Smtp-Source: AK7set/g7gT+IPKhP4O8JK1QExIXcFxPbo2rZFgLcA6bWJTcRIfO2bflQ3Nm/jXKH6gjIomOxApK X-Received: by 2002:ac8:5d88:0:b0:3b6:9b37:e03c with SMTP id d8-20020ac85d88000000b003b69b37e03cmr4747928qtx.7.1676392417705; Tue, 14 Feb 2023 08:33:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676392417; cv=none; d=google.com; s=arc-20160816; b=KGrpUdVLlcAq2vsL6e/GXxGFG1OO0ggs8GLlxVcTSyBnAceAzx24V3kj1FnH6udx31 AWSyiztHJHi22Ftd3D8bqY00sFfeGZ5EVQCgZK5F9Gb4v5gKgjd3eOc+8PnjAJKq3OH4 EywGVAH6V9PDt9g5XY7PAt2WDSPKz59MA1wBP6Z7js3Q5qgf+rSvNubYKN146NHJvLmp 1Bz6hyCIYeIdzhGm7bV6kwVYzj9TK+F9w55wwZNth5Atq8EfjUoUYvShdS8gR5f2TUiR i0KzGVQ7uqSfUtb7sPEU4yYk4+0j79KzCMta469GQaQfT2Pzts0Zo9LfGZMlHx+BBHCh TNBw== ARC-Message-Signature: i=1; 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[74.87.59.234]) by smtp.gmail.com with ESMTPSA id d17-20020aa78691000000b0058d99337381sm10337011pfo.172.2023.02.14.08.30.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 08:30:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 05/14] target/arm: Simplify register counting in arm_gen_dynamic_svereg_xml Date: Tue, 14 Feb 2023 06:30:39 -1000 Message-Id: <20230214163048.903964-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230214163048.903964-1-richard.henderson@linaro.org> References: <20230214163048.903964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Rather than increment base_reg and num, compute num from the change to base_reg at the end. Clean up some nearby comments. Signed-off-by: Richard Henderson --- target/arm/gdbstub64.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 811833d8de..8d174ff6e0 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -277,32 +277,35 @@ static void output_vector_union_type(GString *s, int reg_width) g_string_append(s, ""); } -int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) +int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) { ARMCPU *cpu = ARM_CPU(cs); GString *s = g_string_new(NULL); DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; - int i, reg_width = (cpu->sve_max_vq * 128); - info->num = 0; + int reg_width = cpu->sve_max_vq * 128; + int base_reg = orig_base_reg; + int i; + g_string_printf(s, ""); g_string_append_printf(s, ""); g_string_append_printf(s, ""); + /* Create the vector union type. */ output_vector_union_type(s, reg_width); - /* Finally the sve prefix type */ + /* Create the predicate vector type. */ g_string_append_printf(s, "", reg_width / 8); - /* Then define each register in parts for each vq */ + /* Define the vector registers. */ for (i = 0; i < 32; i++) { g_string_append_printf(s, "", i, reg_width, base_reg++); - info->num++; } + /* fpscr & status registers */ g_string_append_printf(s, "", base_reg++); - info->num += 2; + /* Define the predicate registers. */ for (i = 0; i < 16; i++) { g_string_append_printf(s, "", cpu->sve_max_vq * 16, base_reg++); + + /* Define the vector length pseudo-register. */ g_string_append_printf(s, "", base_reg++); - info->num += 2; - g_string_append_printf(s, ""); - info->desc = g_string_free(s, false); + g_string_append_printf(s, ""); + + info->desc = g_string_free(s, false); + info->num = base_reg - orig_base_reg; return info->num; } From patchwork Tue Feb 14 16:30:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 653471 Delivered-To: patch@linaro.org Received: by 2002:adf:f90f:0:0:0:0:0 with SMTP id b15csp3146702wrr; Tue, 14 Feb 2023 08:32:34 -0800 (PST) X-Google-Smtp-Source: AK7set9D4wEAucgFKKvG/OVFZFMzvofkRLrJrjDk6nMkImAbNq+OGIkvI2h1wObt7Il8GBRJRCjJ X-Received: by 2002:ac8:4e4d:0:b0:3ba:807:99d9 with SMTP id e13-20020ac84e4d000000b003ba080799d9mr5132749qtw.6.1676392354681; Tue, 14 Feb 2023 08:32:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676392354; cv=none; d=google.com; s=arc-20160816; b=ejnPwS6b0e+sGawyegQYfkGiRTCSOSJejW18poVv/kY334rY0LepyQgmisKiUsIxn+ zI7c155z+CEJ0M5F2Yyxr/CHDfU2/Ag3VuufQBzm297TOdTfotQsNueW5mzbkIVHNT3h DJpeoolowmAujrurAcinELqFEisRhY3DGXvn3shsDtJNdpZIkqZRd8bbmSDYH/9vc5Wm vxjpcAEDSP/yaBaVOztBZmwvCeg7wXpobF+d2vxScSXV0D/lSBpjVoHNWO9DKQGuDKLv ECZwxlyIoO/C6GcHOnDU7Uye4kJeFcS75nDeFS55o7eQmWAB9BDeiR2QkeDS8cx9XEK7 9htg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=xtIpJs6CDJTguU2qwCAmHY7gW26H1KWvwqoyvB56KYY=; b=XbXj/wgMO/IXDyWrfdbMGIz5AQ06mok8dAARbUTl+00FztxZDNE1cTPHr95FMpJtp7 UCRjZ6yZ50QXclFfC3QQuXfoNzUknbrPweRTKd2a+BRyNE0oIFqZZlhLouZpUy4Rf3lk 5O0GokSn/gmR2syrOupsWk1J1VSh53PQMieBSDgGW2tipaxbH5RVTseOI6h3fWsatrid cO4FWeNklrXA/AhaJeP9sNIKNHzaWydSEAvXoHNcSX2S7W8zB7rvqFfR0LzTI8t7qunp aWgQdAtFPlK5sATFPo4McLdwxI8kQMXRFhilhbKyYRl59U60dTlqCq6Is5/65xvW7GNK Awuw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=evHAF1Ai; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[74.87.59.234]) by smtp.gmail.com with ESMTPSA id d17-20020aa78691000000b0058d99337381sm10337011pfo.172.2023.02.14.08.30.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 08:31:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 06/14] target/arm: Hoist pred_width in arm_gen_dynamic_svereg_xml Date: Tue, 14 Feb 2023 06:30:40 -1000 Message-Id: <20230214163048.903964-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230214163048.903964-1-richard.henderson@linaro.org> References: <20230214163048.903964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Fabiano Rosas --- target/arm/gdbstub64.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 8d174ff6e0..02a0256c5c 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -283,6 +283,7 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) GString *s = g_string_new(NULL); DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; int reg_width = cpu->sve_max_vq * 128; + int pred_width = cpu->sve_max_vq * 16; int base_reg = orig_base_reg; int i; @@ -319,14 +320,14 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) g_string_append_printf(s, "", - i, cpu->sve_max_vq * 16, base_reg++); + i, pred_width, base_reg++); info->num++; } g_string_append_printf(s, "", - cpu->sve_max_vq * 16, base_reg++); + pred_width, base_reg++); /* Define the vector length pseudo-register. */ g_string_append_printf(s, From patchwork Tue Feb 14 16:30:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 653478 Delivered-To: patch@linaro.org Received: by 2002:adf:f90f:0:0:0:0:0 with SMTP id b15csp3147675wrr; Tue, 14 Feb 2023 08:34:00 -0800 (PST) X-Google-Smtp-Source: AK7set+4DAP5ImiJgRIVv6UaZYqO++gIIZo7L/6E9RrHgN/MHVzV6CNqtdjy5YSzxGBYcFxLsZKk X-Received: by 2002:ac8:7fcf:0:b0:3b8:6a92:c8d6 with SMTP id b15-20020ac87fcf000000b003b86a92c8d6mr4453046qtk.60.1676392440194; Tue, 14 Feb 2023 08:34:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676392440; cv=none; d=google.com; s=arc-20160816; b=gafaRWvVPoZmgC6l6SXlMmoWMmVkmUgpTq8GTGKoWLoOH2SmPT63DPh5DMK7fGUAdr +808j+Jy712gz1gSnnmJvS7pbWZ+AapOq9kUSO/p/g8I7BmO5oDGyIEnSDBQR2fPAJ5X mopH/zQfWkL8l7hVD6Jw2thAozxr0HsRogDhBJ1xMEy5eto9fV15MP0evDP/TLv9Eaye qOXBq0AIRFZjCnsIUMMZjjF/oNIOP6fkP+ktZ4ja6Xala8h50vLCwIW26f6zh9ea87wo CaUn4XbU7ydaMfs8yegi9n5Cm65eP98asTJrSgNYoraS5BUZ2c00Qkxb6VEztco5+L5E VjLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=DHtifVEb490wvqlj18C8e7MT6laK9IGTMe9tkX1/5mQ=; b=Fh5T+sSSR1wCIf2IIuzuvvnFwZn7DmAAiLEqcqu76flx0+ZtsenaGgzukM6DFPMUZV brhGPb8joKaBPPPr5s2Z3jMYMD0Hev4WPSuih+vm44EWGdi/8FP+kP56Hk0HAHNfW3Lr mFZz9xTvqLLXYXLjU3VJLZqJTT5KGBtxi2sOU9C2n7XyCCccfIYKs6lyxtAMrKeNl04R 9QFt0K08TASHDspriZ1GTS5T7/tZGD8GijYiIVfo6d83H8+69SDqJEFP2CNxjr+T2+xw G0gKxHjv9xDSMgWFl7+YxpGyzmcl/+S4J0dMskBY1T6c0WPxSjmonBaLRoowry0RrgQJ r1pA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iLrf6cVv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[74.87.59.234]) by smtp.gmail.com with ESMTPSA id d17-20020aa78691000000b0058d99337381sm10337011pfo.172.2023.02.14.08.31.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 08:31:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 07/14] target/arm: Fix svep width in arm_gen_dynamic_svereg_xml Date: Tue, 14 Feb 2023 06:30:41 -1000 Message-Id: <20230214163048.903964-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230214163048.903964-1-richard.henderson@linaro.org> References: <20230214163048.903964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Define svep based on the size of the predicates, not the primary vector registers. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/gdbstub64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 02a0256c5c..ec61211949 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -297,7 +297,7 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) /* Create the predicate vector type. */ g_string_append_printf(s, "", - reg_width / 8); + pred_width / 8); /* Define the vector registers. */ for (i = 0; i < 32; i++) { From patchwork Tue Feb 14 16:30:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 653475 Delivered-To: patch@linaro.org Received: by 2002:adf:f90f:0:0:0:0:0 with SMTP id b15csp3147195wrr; Tue, 14 Feb 2023 08:33:20 -0800 (PST) X-Google-Smtp-Source: AK7set+Urht7l5ZU7PcdT95fGnnOSHOUH7v6m/g3MRpo/SyJZQZrPjQTHnnTczSin7dywFYGvHAX X-Received: by 2002:ac8:578b:0:b0:3b9:ba24:4f38 with SMTP id v11-20020ac8578b000000b003b9ba244f38mr5152380qta.56.1676392399926; Tue, 14 Feb 2023 08:33:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676392399; cv=none; d=google.com; s=arc-20160816; b=F/Jm/eOvhWEEVqzkUq61kzZ44Ta+rrmeF42m70q618kgqfOkCX95wIpiTYaUi59436 YE/69ekBi+Dgf/muTOcyUmDPZs4iQMyybJwoe0uooTenl+iON4kp5IEnh3bkNWhKBea7 6Wq1njGnPPhWxadcLYsnkWwzCeSVMiSJaWjT5TCQxteFU4lXhoqQQQy/P2HQYP6PtVTb mMM1zFu6qm4Hd4FTlimYXCEwwUSo1HQvldiT04tIxEJHTkQTfsfqjS9NmAkr90tqC4e4 bnvEC8yVDaXSSU5zgCkVHeoAs7xTiHGTu6vmn0Jk0Gh7FBxGClnCS3LIJO0WIsYY9nVt ePdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=5U6nLfif2wOhX5Oed2Osbgbcfi6KWrVp6W4p+qPIqc0=; b=fnkM9iE4lf0Ng+tNoHjEffyUMEK6kZnOucldqexedC/Qrl0KND2zYL9E8OxyW12MiL 910AWLEvr7budUxHilefr2Go2y3IgHSQ4DAN76gwfhqs0WVC+JDC7WPmx12Hcu1o9zSx szbSb/kuMQa5oUCg3IWlNY7HaShkBdCou7q1+8Ye0hrBXI0whluSpRhn612VwLxjyHbm eGbeax/Qjjy/0Iwuz6UlQfjxwjhAWduAZYTd8N8QY7fxlI9OZvotk+dpJFUGh+N+dlcM 5tDSAuFTVns7SXZsy4wXiUctGf7Frx1GNqZ2E3/soPMxzWAbH06J5bafxLJX1e7vxLqZ lO+w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=s7Sbpvi1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[74.87.59.234]) by smtp.gmail.com with ESMTPSA id d17-20020aa78691000000b0058d99337381sm10337011pfo.172.2023.02.14.08.31.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 08:31:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 08/14] target/arm: Add name argument to output_vector_union_type Date: Tue, 14 Feb 2023 06:30:42 -1000 Message-Id: <20230214163048.903964-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230214163048.903964-1-richard.henderson@linaro.org> References: <20230214163048.903964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This will make the function usable between SVE and SME. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/gdbstub64.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index ec61211949..166cb288cd 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -210,7 +210,8 @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg) return 0; } -static void output_vector_union_type(GString *s, int reg_width) +static void output_vector_union_type(GString *s, int reg_width, + const char *name) { struct TypeSize { const char *gdb_type; @@ -240,39 +241,38 @@ static void output_vector_union_type(GString *s, int reg_width) }; static const char suf[] = { 'q', 'd', 's', 'h', 'b' }; - - g_autoptr(GString) ts = g_string_new(""); int i, j, bits; /* First define types and totals in a whole VL */ for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { - int count = reg_width / vec_lanes[i].size; - g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix); g_string_append_printf(s, - "", - ts->str, vec_lanes[i].gdb_type, count); + "", + name, vec_lanes[i].sz, vec_lanes[i].suffix, + vec_lanes[i].gdb_type, reg_width / vec_lanes[i].size); } + /* * Now define a union for each size group containing unsigned and * signed and potentially float versions of each size from 128 to * 8 bits. */ for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { - g_string_append_printf(s, "", suf[i]); + g_string_append_printf(s, "", name, suf[i]); for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { if (vec_lanes[j].size == bits) { - g_string_append_printf(s, "", - vec_lanes[j].suffix, + g_string_append_printf(s, "", + vec_lanes[j].suffix, name, vec_lanes[j].sz, vec_lanes[j].suffix); } } g_string_append(s, ""); } + /* And now the final union of unions */ - g_string_append(s, ""); + g_string_append_printf(s, "", name); for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { - g_string_append_printf(s, "", - suf[i], suf[i]); + g_string_append_printf(s, "", + suf[i], name, suf[i]); } g_string_append(s, ""); } @@ -292,7 +292,7 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) g_string_append_printf(s, ""); /* Create the vector union type. */ - output_vector_union_type(s, reg_width); + output_vector_union_type(s, reg_width, "svev"); /* Create the predicate vector type. */ g_string_append_printf(s, From patchwork Tue Feb 14 16:30:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 653472 Delivered-To: patch@linaro.org Received: by 2002:adf:f90f:0:0:0:0:0 with SMTP id b15csp3146712wrr; Tue, 14 Feb 2023 08:32:35 -0800 (PST) X-Google-Smtp-Source: AK7set9yqQFjboOirZAdCro2yQFYzOnazjHs5bnLji5azWTJRPxpWF3ZVpYH/xGzyZ5LCs4mIwpU X-Received: by 2002:ad4:5b84:0:b0:56e:9f05:6267 with SMTP id 4-20020ad45b84000000b0056e9f056267mr5825596qvp.48.1676392355305; Tue, 14 Feb 2023 08:32:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676392355; cv=none; d=google.com; s=arc-20160816; b=D26peswFbjmqPqQq1hbxlou9HEKFw8m/Je2Aum3pRlAitRpWtig4MAlvwjrW+5XDN8 nYEFkZ3TafpJU/MJQzlXj6Ss0hkl60+NNfS3Quh+ifFW6c/Qs3bxoJOeIVNfRL/wUef1 h+BxDqv33CFBNk2WLVggjkGAP9FUksbnj9rRRQsf59BB8yItB5BOd7jukTBnYej81rK9 rXBeO4yCGg7NGORbSUOFPrQ02iPusBIgHsqI4jurGeLq1u2a5UYv6NEW5UaDXbGm5PVN 0BROlKOJdFSdFsWYWbBAfSt0VJkul/AnS6w4EciWQ8g35gNWZ5Yp0HLTP957IfoqyVLj I+rQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=YRBnSRYi8o+DLHiV3s59zUytH0Yp49LyljZa3CvYZ4E=; b=vEVWLIS4eOorYn1FmWqUGvxZBvE3CvbGzRSxxng2ZAN7R1BmgqeFmCqZhJepq+O+97 Vn4+p7R+WSXYWQF8PNWSTRhmgM2xJLaXsfs+t7D4amgfB/cA3cTq66POSTUGo3P49kT8 I1ds+94zNhNkOUn2lIn/pUXcKIelzfgXSqeR4CUYmdktIZ+899GFtF7g50CUymG2/FSE Od+LxgCFabAfv8AcaL5caqxy/PqlJN0f+TCZn7LP2PVdILx8bc17ojB59Tqa6IJokoId mUjlwjdLy4opcHuXGF/AXyj+ugKXV0mcVndeDEDsbLAI6z8zdO6Uu9eHxSc1s5EzgqQS G0rQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fWI7kDHi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[74.87.59.234]) by smtp.gmail.com with ESMTPSA id d17-20020aa78691000000b0058d99337381sm10337011pfo.172.2023.02.14.08.31.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 08:31:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 09/14] target/arm: Simplify iteration over bit widths Date: Tue, 14 Feb 2023 06:30:43 -1000 Message-Id: <20230214163048.903964-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230214163048.903964-1-richard.henderson@linaro.org> References: <20230214163048.903964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Order suf[] by the log8 of the width. Use ARRAY_SIZE instead of hard-coding 128. This changes the order of the union definitions, but retains the order of the union-of-union members. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/gdbstub64.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 166cb288cd..a6a8e7eb40 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -240,8 +240,8 @@ static void output_vector_union_type(GString *s, int reg_width, { "int8", 8, 'b', 's' }, }; - static const char suf[] = { 'q', 'd', 's', 'h', 'b' }; - int i, j, bits; + static const char suf[] = { 'b', 'h', 's', 'd', 'q' }; + int i, j; /* First define types and totals in a whole VL */ for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { @@ -256,7 +256,9 @@ static void output_vector_union_type(GString *s, int reg_width, * signed and potentially float versions of each size from 128 to * 8 bits. */ - for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { + for (i = 0; i < ARRAY_SIZE(suf); i++) { + int bits = 8 << i; + g_string_append_printf(s, "", name, suf[i]); for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { if (vec_lanes[j].size == bits) { @@ -270,7 +272,7 @@ static void output_vector_union_type(GString *s, int reg_width, /* And now the final union of unions */ g_string_append_printf(s, "", name); - for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { + for (i = ARRAY_SIZE(suf) - 1; i >= 0; i--) { g_string_append_printf(s, "", suf[i], name, suf[i]); } From patchwork Tue Feb 14 16:30:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 653466 Delivered-To: patch@linaro.org Received: by 2002:adf:f90f:0:0:0:0:0 with SMTP id b15csp3146421wrr; Tue, 14 Feb 2023 08:32:06 -0800 (PST) X-Google-Smtp-Source: AK7set+pKp6yqX6jHiuBnKzeDgG/WUc06uWQ+Nkl3IvUoJMzKc5mvhNLG8xs4eI57MIUkWxeq1ie X-Received: by 2002:ac8:5a87:0:b0:3b9:e1a2:6261 with SMTP id c7-20020ac85a87000000b003b9e1a26261mr5049637qtc.36.1676392326616; Tue, 14 Feb 2023 08:32:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676392326; cv=none; d=google.com; s=arc-20160816; b=QF7nkHDxoUf2JfHAL7lXqRlnj86DGx3Pi6TMV/O6y3z7iIzGUB0AUaTeT+q+89+JVA wqwpbkP1/Qw0Bo8txsFH3fKsbpRujRcC5tsdqEiIHuITF1YyrMKj39x27CNjt6xZ539g 6OyBRn8Wz3lF4VPp77/ncos/VM7u6T+dWu5wh20uDyNwtS27gYKVVbJZqd0TM2xIazT9 IJqEh7/rsyOffDFUuvRr/s/Tf618XAHKJvqILpfrunz0TAkod6d+YKyUmQ5e+pQdc44G BpVEyYPJ/sJlAr/2Vid168Ua536S2bSJfdnd3+RKudIxtc+DtpuFA79TC5s5L6X/HT3R EqfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=O4L2aD/rteJmwpjNgOeST3MFgjCAfq0kho6AOw6LVxY=; b=F66BwsxcTcBySvYKNWE4AoAYo+nekgwYGHoDRdMe1Se4wqkBgtlYncJSKlFPajXq2V M509usiRPT9mO66e3J7S+KCNj+TLI4iQyMpbAG5rfTCbL/0rWVQZrE9dNOf9D4RhPI8D TUfmcstXNDgCPPShdVwHX2PZx9Rieejl5od0MzC+AwsixImvMKSriVI37FAUZrHB4B/T FcCrxaapHEuR3jTZvBDh3VMF1x9+oSDUqdUan+p2KZFQrsKNtU3YDkK78IN4ZiNBSaNA Cx/1B49ECBZlUFsMGz0UzVDgViS+CnwZp92B7iAqNSwlX+YXJw3nSfwhI6jkFKMlR327 GaSQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FNOu001b; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[74.87.59.234]) by smtp.gmail.com with ESMTPSA id d17-20020aa78691000000b0058d99337381sm10337011pfo.172.2023.02.14.08.31.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 08:31:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 10/14] target/arm: Create pauth_ptr_mask Date: Tue, 14 Feb 2023 06:30:44 -1000 Message-Id: <20230214163048.903964-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230214163048.903964-1-richard.henderson@linaro.org> References: <20230214163048.903964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Keep the logic for pauth within pauth_helper.c, and expose a helper function for use with the gdbstub pac extension. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 10 ++++++++++ target/arm/pauth_helper.c | 26 ++++++++++++++++++++++---- 2 files changed, 32 insertions(+), 4 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index c98482561e..bb3983645d 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1364,6 +1364,16 @@ int exception_target_el(CPUARMState *env); bool arm_singlestep_active(CPUARMState *env); bool arm_generate_debug_exceptions(CPUARMState *env); +/** + * pauth_ptr_mask: + * @env: cpu context + * @ptr: selects between TTBR0 and TTBR1 + * @data: selects between TBI and TBID + * + * Return a mask of the bits of @ptr that contain the authentication code. + */ +uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data); + /* Add the cpreg definitions for debug related system registers */ void define_debug_regs(ARMCPU *cpu); diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index d0483bf051..20f347332d 100644 --- a/target/arm/pauth_helper.c +++ b/target/arm/pauth_helper.c @@ -339,14 +339,32 @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, return pac | ext | ptr; } -static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param) +static uint64_t pauth_ptr_mask_internal(ARMVAParameters param) { - /* Note that bit 55 is used whether or not the regime has 2 ranges. */ - uint64_t extfield = sextract64(ptr, 55, 1); int bot_pac_bit = 64 - param.tsz; int top_pac_bit = 64 - 8 * param.tbi; - return deposit64(ptr, bot_pac_bit, top_pac_bit - bot_pac_bit, extfield); + return MAKE_64BIT_MASK(bot_pac_bit, top_pac_bit - bot_pac_bit); +} + +static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param) +{ + uint64_t mask = pauth_ptr_mask_internal(param); + + /* Note that bit 55 is used whether or not the regime has 2 ranges. */ + if (extract64(ptr, 55, 1)) { + return ptr | mask; + } else { + return ptr & ~mask; + } +} + +uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data) +{ + ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data); + + return pauth_ptr_mask_internal(param); } static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, From patchwork Tue Feb 14 16:30:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 653479 Delivered-To: patch@linaro.org Received: by 2002:adf:f90f:0:0:0:0:0 with SMTP id b15csp3147680wrr; Tue, 14 Feb 2023 08:34:00 -0800 (PST) X-Google-Smtp-Source: AK7set/PqvZ/JRMe5ZNEjxn4NSEp2c5FlOlePvXo4elk7QOzh3PVogbRNmMWQOnGrjyjtGsO2viy X-Received: by 2002:a05:622a:180c:b0:3b9:c44e:361 with SMTP id t12-20020a05622a180c00b003b9c44e0361mr3911350qtc.64.1676392440768; Tue, 14 Feb 2023 08:34:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676392440; cv=none; d=google.com; s=arc-20160816; b=1LAJqsBTXSnA1Nb8k9baIiF0vwtVEvCi+djuCzvcMj/0ZYnKAr7tHnCAttZdbBYfyP QuDbTw/KBSY/eTFwvg73uwlvIL9f4laTz9TiC2spv9lcVGS7K8Yh4vwzumA4+2Q/cJSX iCuJgDsAvlT3rRomxNUhYempsBas/xa77lWNUeLWa86d3E9/DXOMEuK+gT8BqtYpqeor 0iPplEDEt6ErlzOXkBVgUrr/3w6/OAL3bRfCfq0ZdzspizkfkWEehpjWfh9cIdVXN4+2 Xy/SE0eQb1y5j/91hgfIPh+4oOBe1PM2tgusvT/A1fcL8P15yQmt7+I+sy9grx11ztO5 ygKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=I2TaPq9VaeUx5FG1r+qvVw6gD0hnlJ7wu2KVNSomLWo=; b=ZdLPZwvn8zUcR4btQPPvm6Wbcpw92udkXPLT6NBmYC12dLzf/Lvck3sXt10R1j8l3k qkh8CqncBgBBup5dD9xLMdJw3T1NAajBxDhH67KW0yAgYkC0iTnQ62Y2suG9R5PIsEUF q7WZXPTjsIKbDPMOKLO49WfIRewTb+rwQv5I3i7N60d6C/GaBkMMcjggmPStLHDoKaRl e/nk+HR1GEAsK8BZXHBAnevGb+HXLlP4R8WwTdKn3qHIQ0TxQm6E29Y7nol75aFfDn59 +TxASd1HtCiaYfMaYRgcrFiYkeC1PZvUneZ5+m2ZdJ0ppJ4k4DRF7/wHZbMmeX0BYipH 1shQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jOFtG0jQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[74.87.59.234]) by smtp.gmail.com with ESMTPSA id d17-20020aa78691000000b0058d99337381sm10337011pfo.172.2023.02.14.08.31.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 08:31:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Luis Machado , Thiago Jung Bauermann Subject: [PATCH 11/14] target/arm: Implement gdbstub pauth extension Date: Tue, 14 Feb 2023 06:30:45 -1000 Message-Id: <20230214163048.903964-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230214163048.903964-1-richard.henderson@linaro.org> References: <20230214163048.903964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x444.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The extension is primarily defined by the Linux kernel NT_ARM_PAC_MASK ptrace register set. The original gdb feature consists of two masks, data and code, which are used to mask out the authentication code within a pointer. Following discussion with Luis Machado, add two more masks in order to support pointers within the high half of the address space (i.e. TTBR1 vs TTBR0). Cc: Luis Machado Cc: Thiago Jung Bauermann Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1105 Signed-off-by: Richard Henderson --- configs/targets/aarch64-linux-user.mak | 2 +- configs/targets/aarch64-softmmu.mak | 2 +- configs/targets/aarch64_be-linux-user.mak | 2 +- target/arm/internals.h | 2 ++ target/arm/gdbstub.c | 5 ++++ target/arm/gdbstub64.c | 29 +++++++++++++++++++++++ gdb-xml/aarch64-pauth.xml | 15 ++++++++++++ 7 files changed, 54 insertions(+), 3 deletions(-) create mode 100644 gdb-xml/aarch64-pauth.xml diff --git a/configs/targets/aarch64-linux-user.mak b/configs/targets/aarch64-linux-user.mak index db552f1839..ba8bc5fe3f 100644 --- a/configs/targets/aarch64-linux-user.mak +++ b/configs/targets/aarch64-linux-user.mak @@ -1,6 +1,6 @@ TARGET_ARCH=aarch64 TARGET_BASE_ARCH=arm -TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml +TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml TARGET_HAS_BFLT=y CONFIG_SEMIHOSTING=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-softmmu.mak index d489e6da83..b4338e9568 100644 --- a/configs/targets/aarch64-softmmu.mak +++ b/configs/targets/aarch64-softmmu.mak @@ -1,5 +1,5 @@ TARGET_ARCH=aarch64 TARGET_BASE_ARCH=arm TARGET_SUPPORTS_MTTCG=y -TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml +TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml gdb-xml/aarch64-pauth.xml TARGET_NEED_FDT=y diff --git a/configs/targets/aarch64_be-linux-user.mak b/configs/targets/aarch64_be-linux-user.mak index dc78044fb1..acb5620cdb 100644 --- a/configs/targets/aarch64_be-linux-user.mak +++ b/configs/targets/aarch64_be-linux-user.mak @@ -1,7 +1,7 @@ TARGET_ARCH=aarch64 TARGET_BASE_ARCH=arm TARGET_BIG_ENDIAN=y -TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml +TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml TARGET_HAS_BFLT=y CONFIG_SEMIHOSTING=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/target/arm/internals.h b/target/arm/internals.h index bb3983645d..4b60355a7e 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1345,6 +1345,8 @@ int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg); int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg); int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg); int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg); +int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg); +int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg); void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index bf8aff7824..062c8d447a 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -355,6 +355,11 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) aarch64_gdb_set_fpu_reg, 34, "aarch64-fpu.xml", 0); } + if (isar_feature_aa64_pauth(&cpu->isar)) { + gdb_register_coprocessor(cs, aarch64_gdb_get_pauth_reg, + aarch64_gdb_set_pauth_reg, + 4, "aarch64-pauth.xml", 0); + } #endif } else { if (arm_feature(env, ARM_FEATURE_NEON)) { diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index a6a8e7eb40..465d7fb196 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -210,6 +210,35 @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg) return 0; } +int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg) +{ + switch (reg) { + case 0: /* pauth_dmask */ + case 1: /* pauth_cmask */ + case 2: /* pauth_dmask_high */ + case 3: /* pauth_cmask_high */ + /* + * Note that older versions of this feature only contained + * pauth_{d,c}mask, for use with Linux user processes, and + * thus exclusively in the low half of the address space. + * + * To support system mode, and to debug kernels, two new regs + * were added to cover the high half of the address space. + * For the purpose of pauth_ptr_mask, we can use any well-formed + * address within the address space half -- here, 0 and -2. + */ + return gdb_get_reg64(buf, pauth_ptr_mask(env, -(reg & 2), ~reg & 1)); + default: + return 0; + } +} + +int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg) +{ + /* All pseudo registers are read-only. */ + return 0; +} + static void output_vector_union_type(GString *s, int reg_width, const char *name) { diff --git a/gdb-xml/aarch64-pauth.xml b/gdb-xml/aarch64-pauth.xml new file mode 100644 index 0000000000..24af5f903c --- /dev/null +++ b/gdb-xml/aarch64-pauth.xml @@ -0,0 +1,15 @@ + + + + + + + + + + + From patchwork Tue Feb 14 16:30:46 2023 Content-Type: text/plain; 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[74.87.59.234]) by smtp.gmail.com with ESMTPSA id d17-20020aa78691000000b0058d99337381sm10337011pfo.172.2023.02.14.08.31.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 08:31:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, David Reiss Subject: [PATCH 12/14] target/arm: Export arm_v7m_mrs_control Date: Tue, 14 Feb 2023 06:30:46 -1000 Message-Id: <20230214163048.903964-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230214163048.903964-1-richard.henderson@linaro.org> References: <20230214163048.903964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: David Reiss Allow the function to be used outside of m_helper.c. Rename with an "arm_" prefix. Signed-off-by: David Reiss [rth: Split out of a larger patch] Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 3 +++ target/arm/m_helper.c | 6 +++--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 4b60355a7e..127a425961 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1353,6 +1353,9 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); #endif +/* Read the CONTROL register as the MRS instruction would. */ +uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure); + #ifdef CONFIG_USER_ONLY static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } #else diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index e7e746ea18..c20bcac977 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -53,7 +53,7 @@ static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg, unsigned el) return xpsr_read(env) & mask; } -static uint32_t v7m_mrs_control(CPUARMState *env, uint32_t secure) +uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure) { uint32_t value = env->v7m.control[secure]; @@ -90,7 +90,7 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) case 0 ... 7: /* xPSR sub-fields */ return v7m_mrs_xpsr(env, reg, 0); case 20: /* CONTROL */ - return v7m_mrs_control(env, 0); + return arm_v7m_mrs_control(env, 0); default: /* Unprivileged reads others as zero. */ return 0; @@ -2420,7 +2420,7 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) case 0 ... 7: /* xPSR sub-fields */ return v7m_mrs_xpsr(env, reg, el); case 20: /* CONTROL */ - return v7m_mrs_control(env, env->v7m.secure); + return arm_v7m_mrs_control(env, env->v7m.secure); case 0x94: /* CONTROL_NS */ /* * We have to handle this here because unprivileged Secure code From patchwork Tue Feb 14 16:30:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 653468 Delivered-To: patch@linaro.org Received: by 2002:adf:f90f:0:0:0:0:0 with SMTP id b15csp3146504wrr; Tue, 14 Feb 2023 08:32:15 -0800 (PST) X-Google-Smtp-Source: AK7set/nHxoEKoidGygZGje/SNqTnfSJ5SUc+LOPbMfwtxM0qiLtM7eECmsDMtNMJTP92qUemUxH X-Received: by 2002:a05:622a:1491:b0:3b9:bca3:d93d with SMTP id t17-20020a05622a149100b003b9bca3d93dmr4509015qtx.22.1676392335020; Tue, 14 Feb 2023 08:32:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676392335; cv=none; d=google.com; s=arc-20160816; b=edUkG2+W5MVmvYny5gwJ99tVKVbRaKpWHMPRilE304PmobqUtSbdIW4aA7erOrM0g+ zp0FnRAzQxaQaO68lVRj1ySz0eMbKCu8g2ZTwBh2j++6LIAsdc63J6c0xMckvBeeJT1v d4jOFw9RpIxH1MEg/qM75diSTD/N52AkE+auviz56vpF/7rAGUO5z5ygKARO3XMzYwrh UdaG6tMWvjoDhXNVQwmQOSdwYpmFZZugKS5i2TNTf+dA+8VFw4YtpnHv1ARzliviEBOe lnxdfbVMiwJakHLrkRZAsTHR6M0M/d433FAubGmekbipkxQyfTQOEnoKzYPSjUZuHkIo Q3Rw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=GVeEC1XgZv+0JDQi5rIgvqYs5+9oYvw4P4dYcheYUZc=; b=KuC/IbiYVBwA/GUvQsN5jGII18i5WbjdR3Z9jVHytnBqVr+Wghv0Of8r4XppS3KqgW UK2+kC0/KDewjcdjh4YMZc9+GAS/q+i0qGlhJtl0ifZzEEJGn0LW4KSbZiN3HliCGcPH ZmaTtmAgqxQswU3pRjb1AL391Ph8m+/2CcNp3nqk8w3UZjXzsizTltT1EtD2DUMZ2q8O 7FNU/4OkAYagnH2cxc4/y5dktgLFR554MR5JHzxxeF1vY8vQBb5tm2bns2PmlQmq94Ea vI/aFaPh3NraMsV71d+Iq9EuG1O5V2oDHEW0PJ5N4vXHTLwIzPVC3ttQ5c9j7N0XbHXk 1D4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wNJcnkVe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[74.87.59.234]) by smtp.gmail.com with ESMTPSA id d17-20020aa78691000000b0058d99337381sm10337011pfo.172.2023.02.14.08.31.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 08:31:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, David Reiss Subject: [PATCH 13/14] target/arm: Export arm_v7m_get_sp_ptr Date: Tue, 14 Feb 2023 06:30:47 -1000 Message-Id: <20230214163048.903964-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230214163048.903964-1-richard.henderson@linaro.org> References: <20230214163048.903964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: David Reiss Allow the function to be used outside of m_helper.c. Move to be outside of ifndef CONFIG_USER_ONLY block. Rename from get_v7m_sp_ptr. Signed-off-by: David Reiss [rth: Split out of a larger patch] Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 10 +++++ target/arm/m_helper.c | 84 +++++++++++++++++++++--------------------- 2 files changed, 51 insertions(+), 43 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 127a425961..6ad14048db 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1356,6 +1356,16 @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); /* Read the CONTROL register as the MRS instruction would. */ uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure); +/* + * Return a pointer to the location where we currently store the + * stack pointer for the requested security state and thread mode. + * This pointer will become invalid if the CPU state is updated + * such that the stack pointers are switched around (eg changing + * the SPSEL control bit). + */ +uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure, + bool threadmode, bool spsel); + #ifdef CONFIG_USER_ONLY static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } #else diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index c20bcac977..87e30c59a8 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -605,42 +605,6 @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) arm_rebuild_hflags(env); } -static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode, - bool spsel) -{ - /* - * Return a pointer to the location where we currently store the - * stack pointer for the requested security state and thread mode. - * This pointer will become invalid if the CPU state is updated - * such that the stack pointers are switched around (eg changing - * the SPSEL control bit). - * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode(). - * Unlike that pseudocode, we require the caller to pass us in the - * SPSEL control bit value; this is because we also use this - * function in handling of pushing of the callee-saves registers - * part of the v8M stack frame (pseudocode PushCalleeStack()), - * and in the tailchain codepath the SPSEL bit comes from the exception - * return magic LR value from the previous exception. The pseudocode - * opencodes the stack-selection in PushCalleeStack(), but we prefer - * to make this utility function generic enough to do the job. - */ - bool want_psp = threadmode && spsel; - - if (secure == env->v7m.secure) { - if (want_psp == v7m_using_psp(env)) { - return &env->regs[13]; - } else { - return &env->v7m.other_sp; - } - } else { - if (want_psp) { - return &env->v7m.other_ss_psp; - } else { - return &env->v7m.other_ss_msp; - } - } -} - static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure, uint32_t *pvec) { @@ -765,8 +729,8 @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain, !mode; mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, M_REG_S, priv); - frame_sp_p = get_v7m_sp_ptr(env, M_REG_S, mode, - lr & R_V7M_EXCRET_SPSEL_MASK); + frame_sp_p = arm_v7m_get_sp_ptr(env, M_REG_S, mode, + lr & R_V7M_EXCRET_SPSEL_MASK); want_psp = mode && (lr & R_V7M_EXCRET_SPSEL_MASK); if (want_psp) { limit = env->v7m.psplim[M_REG_S]; @@ -1611,10 +1575,8 @@ static void do_v7m_exception_exit(ARMCPU *cpu) * use 'frame_sp_p' after we do something that makes it invalid. */ bool spsel = env->v7m.control[return_to_secure] & R_V7M_CONTROL_SPSEL_MASK; - uint32_t *frame_sp_p = get_v7m_sp_ptr(env, - return_to_secure, - !return_to_handler, - spsel); + uint32_t *frame_sp_p = arm_v7m_get_sp_ptr(env, return_to_secure, + !return_to_handler, spsel); uint32_t frameptr = *frame_sp_p; bool pop_ok = true; ARMMMUIdx mmu_idx; @@ -1920,7 +1882,7 @@ static bool do_v7m_function_return(ARMCPU *cpu) threadmode = !arm_v7m_is_handler_mode(env); spsel = env->v7m.control[M_REG_S] & R_V7M_CONTROL_SPSEL_MASK; - frame_sp_p = get_v7m_sp_ptr(env, true, threadmode, spsel); + frame_sp_p = arm_v7m_get_sp_ptr(env, true, threadmode, spsel); frameptr = *frame_sp_p; /* @@ -2856,6 +2818,42 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) #endif /* !CONFIG_USER_ONLY */ +uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure, bool threadmode, + bool spsel) +{ + /* + * Return a pointer to the location where we currently store the + * stack pointer for the requested security state and thread mode. + * This pointer will become invalid if the CPU state is updated + * such that the stack pointers are switched around (eg changing + * the SPSEL control bit). + * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode(). + * Unlike that pseudocode, we require the caller to pass us in the + * SPSEL control bit value; this is because we also use this + * function in handling of pushing of the callee-saves registers + * part of the v8M stack frame (pseudocode PushCalleeStack()), + * and in the tailchain codepath the SPSEL bit comes from the exception + * return magic LR value from the previous exception. The pseudocode + * opencodes the stack-selection in PushCalleeStack(), but we prefer + * to make this utility function generic enough to do the job. + */ + bool want_psp = threadmode && spsel; + + if (secure == env->v7m.secure) { + if (want_psp == v7m_using_psp(env)) { + return &env->regs[13]; + } else { + return &env->v7m.other_sp; + } + } else { + if (want_psp) { + return &env->v7m.other_ss_psp; + } else { + return &env->v7m.other_ss_msp; + } + } +} + ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, bool secstate, bool priv, bool negpri) { From patchwork Tue Feb 14 16:30:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 653465 Delivered-To: patch@linaro.org Received: by 2002:adf:f90f:0:0:0:0:0 with SMTP id b15csp3146160wrr; Tue, 14 Feb 2023 08:31:42 -0800 (PST) X-Google-Smtp-Source: AK7set+ZI018tWUaWYxYF5SBRhpf7Z9NBCJ/2aplBNmCf50AocqeSOjt8No0htrBJcJRYJ6oTsOn X-Received: by 2002:ac8:580e:0:b0:3b8:6c4d:488a with SMTP id g14-20020ac8580e000000b003b86c4d488amr5159524qtg.37.1676392302320; Tue, 14 Feb 2023 08:31:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676392302; cv=none; d=google.com; s=arc-20160816; b=PUap6OwJkJ7+XVD/oj//jW+RZexSPqRrFJUT2aVtb5X/k9Vru2r+Fz2D1A2P8Et8j/ k7fw5nUKsisDimn9qsD9UlEb7+s2Ae5/0S5WARCN4x+AyJlTAoM+AKjfT/v+nuU+Cofi eICn5sx2PzbMotk50gpGyRC06SHtlm51Ai6YrXVrvQcMKh36+Rp7s4cEh9lvbR2Thbm8 p5leMhSuQGTnB9MFJWsBbf8Ebmrv2Q4BmACo/ro5+Vcb9srZuuDcVJ+93cRMrwHy79+2 bimpYAkPbqK9gUWO/qPSCtlpS6IT5Ti1kVtZHcVQrR5F3D1fo1bl1WC9i8x9GFJo0fsb RKTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=GY8+XZXt1WwhGHNe4w41pwNJufQrqsV0Unpbj9QQTJg=; b=QgoyJcyHSUZKJnx99cBdL2zzT306CrFq7lKJlvrdbcFhCVFzt0S0As6xkZ5ON+P3HW ERnFtbFkWl7qAbAaTyXTip6oVYn+0CSW+CZhkjhj9P3XGffuRPsiUlQtDsELcT5RATZ/ gMJSBIcp5p1HmlvPR0u64eK5jDvhZkJ4ZGROwoWNM2f8DmtXeKT+mHInU8nOCgZvLQDt 9XfdfNQDY3RZtTvAnOOV+tH2jkNI1cozPxT4mEqAaDKf4s45A1vl0O/u/XF2FkcQSdcJ zj7zSFwYAWYRWe2t0ETRYynBPvLYXw7XCgu+JzLufrjm0SC2xREzoLwAMaZoITotposF 4/LA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AAXYLp84; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[74.87.59.234]) by smtp.gmail.com with ESMTPSA id d17-20020aa78691000000b0058d99337381sm10337011pfo.172.2023.02.14.08.31.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 08:31:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, David Reiss Subject: [PATCH 14/14] target/arm: Support reading m-profile system registers from gdb Date: Tue, 14 Feb 2023 06:30:48 -1000 Message-Id: <20230214163048.903964-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230214163048.903964-1-richard.henderson@linaro.org> References: <20230214163048.903964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: David Reiss Follows a fairly similar pattern to the existing special register debug support. Only reading is implemented, but it should be possible to implement writes. Signed-off-by: David Reiss [rth: Split out from two other patches; Use an enumeration to locally number the registers. Use a structure to list and control runtime visibility. Handle security extension with the same code.] Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/gdbstub.c | 169 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 170 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c9f768f945..536e60d48c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -867,6 +867,7 @@ struct ArchCPU { DynamicGDBXMLInfo dyn_sysreg_xml; DynamicGDBXMLInfo dyn_svereg_xml; + DynamicGDBXMLInfo dyn_m_systemreg_xml; /* Timers used by the generic (architected) timer */ QEMUTimer *gt_timer[NUM_GTIMERS]; diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 062c8d447a..a8848c7fee 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -322,6 +322,167 @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg) return cpu->dyn_sysreg_xml.num; } +enum { + M_SYSREG_MSP = 0, + M_SYSREG_PSP = 1, + M_SYSREG_PRIMASK = 2, + M_SYSREG_CONTROL = 3, + M_SYSREG_BASEPRI = 4, + M_SYSREG_FAULTMASK = 5, + M_SYSREG_MSPLIM = 6, + M_SYSREG_PSPLIM = 7, + M_SYSREG_REG_MASK = 7, + + /* + * NOTE: MSP, PSP, MSPLIM, PSPLIM technically don't exist if the + * secure extension is present (replaced by MSP_S, MSP_NS, et al). + * However, the MRS instruction is still allowed to read from MSP and PSP, + * and will return the value associated with the current security state. + * We replicate this behavior for the convenience of users, who will see + * GDB behave similarly to their assembly code, even if they are oblivious + * to the security extension. + */ + M_SYSREG_CURRENT = 0 << 3, + M_SYSREG_NONSECURE = 1 << 3, + M_SYSREG_SECURE = 2 << 3, + M_SYSREG_MODE_MASK = 3 << 3, +}; + +static const struct { + const char *name; + int feature; +} m_systemreg_def[] = { + [M_SYSREG_MSP] = { "msp", ARM_FEATURE_M }, + [M_SYSREG_PSP] = { "psp", ARM_FEATURE_M }, + [M_SYSREG_PRIMASK] = { "primask", ARM_FEATURE_M }, + [M_SYSREG_CONTROL] = { "control", ARM_FEATURE_M }, + [M_SYSREG_BASEPRI] = { "basepri", ARM_FEATURE_M_MAIN }, + [M_SYSREG_FAULTMASK] = { "faultmask", ARM_FEATURE_M_MAIN }, + [M_SYSREG_MSPLIM] = { "msplim", ARM_FEATURE_V8 }, + [M_SYSREG_PSPLIM] = { "psplim", ARM_FEATURE_V8 }, +}; + +static int arm_gdb_get_m_systemreg(CPUARMState *env, GByteArray *buf, int reg) +{ + int mode = reg & M_SYSREG_MODE_MASK; + bool secure; + uint32_t val; + + switch (mode) { + case M_SYSREG_CURRENT: + secure = env->v7m.secure; + break; + case M_SYSREG_NONSECURE: + secure = false; + break; + case M_SYSREG_SECURE: + secure = true; + break; + default: + return 0; + } + + reg &= M_SYSREG_REG_MASK; + if (reg >= ARRAY_SIZE(m_systemreg_def)) { + return 0; + } + if (!arm_feature(env, m_systemreg_def[reg].feature)) { + return 0; + } + + /* NOTE: This implementation shares a lot of logic with v7m_mrs. */ + switch (reg) { + case M_SYSREG_MSP: + val = *arm_v7m_get_sp_ptr(env, secure, false, true); + break; + case M_SYSREG_PSP: + val = *arm_v7m_get_sp_ptr(env, secure, true, true); + break; + case M_SYSREG_MSPLIM: + val = env->v7m.msplim[secure]; + break; + case M_SYSREG_PSPLIM: + val = env->v7m.psplim[secure]; + break; + case M_SYSREG_PRIMASK: + val = env->v7m.primask[secure]; + break; + case M_SYSREG_BASEPRI: + val = env->v7m.basepri[secure]; + break; + case M_SYSREG_FAULTMASK: + val = env->v7m.faultmask[secure]; + break; + case M_SYSREG_CONTROL: + /* + * NOTE: CONTROL has a mix of banked and non-banked bits. + * For "current", we emulate the MRS instruction. + * Unfortunately, this gives GDB no way to read the SFPA bit + * when the CPU is in a non-secure state. + */ + if (mode == M_SYSREG_CURRENT) { + val = arm_v7m_mrs_control(env, secure); + } else { + val = env->v7m.control[secure]; + } + break; + default: + g_assert_not_reached(); + } + + return gdb_get_reg32(buf, val); +} + +static int arm_gdb_set_m_systemreg(CPUARMState *env, uint8_t *buf, int reg) +{ + /* TODO: Implement. */ + return 0; +} + +static int arm_gen_dynamic_m_systemreg_xml(CPUState *cs, int base_reg) +{ + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + GString *s = g_string_new(NULL); + int i, ret; + + g_string_printf(s, ""); + g_string_append_printf(s, ""); + g_string_append_printf(s, "\n"); + + QEMU_BUILD_BUG_ON(M_SYSREG_CURRENT != 0); + ret = ARRAY_SIZE(m_systemreg_def); + + for (i = 0; i < ret; i++) { + if (arm_feature(env, m_systemreg_def[i].feature)) { + g_string_append_printf(s, + "\n", + m_systemreg_def[i].name, base_reg + i); + } + } + + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + for (i = 0; i < ret; i++) { + g_string_append_printf(s, + "\n", + m_systemreg_def[i].name, base_reg + (i | M_SYSREG_NONSECURE)); + } + for (i = 0; i < ret; i++) { + g_string_append_printf(s, + "\n", + m_systemreg_def[i].name, base_reg + (i | M_SYSREG_SECURE)); + } + QEMU_BUILD_BUG_ON(M_SYSREG_SECURE < M_SYSREG_NONSECURE); + ret |= M_SYSREG_SECURE; + } + + g_string_append_printf(s, ""); + + cpu->dyn_m_systemreg_xml.desc = g_string_free(s, false); + cpu->dyn_m_systemreg_xml.num = ret; + return ret; +} + const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) { ARMCPU *cpu = ARM_CPU(cs); @@ -330,6 +491,8 @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) return cpu->dyn_sysreg_xml.desc; } else if (strcmp(xmlname, "sve-registers.xml") == 0) { return cpu->dyn_svereg_xml.desc; + } else if (strcmp(xmlname, "arm-m-system.xml") == 0) { + return cpu->dyn_m_systemreg_xml.desc; } return NULL; } @@ -389,4 +552,10 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs), "system-registers.xml", 0); + if (arm_feature(env, ARM_FEATURE_M)) { + gdb_register_coprocessor(cs, + arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg, + arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs), + "arm-m-system.xml", 0); + } }