From patchwork Tue Feb 14 16:41:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Devi Priya X-Patchwork-Id: 653540 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E84FC64ED9 for ; Tue, 14 Feb 2023 16:42:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232489AbjBNQmt (ORCPT ); Tue, 14 Feb 2023 11:42:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60792 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232447AbjBNQmq (ORCPT ); Tue, 14 Feb 2023 11:42:46 -0500 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 06A0D26CE8; Tue, 14 Feb 2023 08:42:29 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Feb 2023 16:42:16 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 31EGgF5b003546 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 14 Feb 2023 16:42:15 GMT Received: from devipriy-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Tue, 14 Feb 2023 08:42:07 -0800 From: Devi Priya To: , , , , , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH 1/7] dt-bindings: PCI: qcom: Add IPQ9574 specific compatible Date: Tue, 14 Feb 2023 22:11:29 +0530 Message-ID: <20230214164135.17039-2-quic_devipriy@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230214164135.17039-1-quic_devipriy@quicinc.com> References: <20230214164135.17039-1-quic_devipriy@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: zfj7fQTMm17HILr31r_RwDC8Hg3nmepj X-Proofpoint-GUID: zfj7fQTMm17HILr31r_RwDC8Hg3nmepj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.170.22 definitions=2023-02-14_11,2023-02-14_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 impostorscore=0 adultscore=0 mlxlogscore=999 malwarescore=0 priorityscore=1501 bulkscore=0 suspectscore=0 lowpriorityscore=0 mlxscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2302140142 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document the compatible for IPQ9574 Signed-off-by: Devi Priya --- .../devicetree/bindings/pci/qcom,pcie.yaml | 72 ++++++++++++++++++- 1 file changed, 70 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 872817d6d2bd..dabdf2684e2d 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -26,6 +26,7 @@ properties: - qcom,pcie-ipq8064-v2 - qcom,pcie-ipq8074 - qcom,pcie-ipq8074-gen3 + - qcom,pcie-ipq9574 - qcom,pcie-msm8996 - qcom,pcie-qcs404 - qcom,pcie-sa8540p @@ -44,11 +45,11 @@ properties: reg: minItems: 4 - maxItems: 5 + maxItems: 6 reg-names: minItems: 4 - maxItems: 5 + maxItems: 6 interrupts: minItems: 1 @@ -105,6 +106,8 @@ properties: items: - const: pciephy + msi-parent: true + power-domains: maxItems: 1 @@ -173,6 +176,27 @@ allOf: - const: parf # Qualcomm specific registers - const: config # PCIe configuration space + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-ipq9574 + then: + properties: + reg: + minItems: 5 + maxItems: 6 + reg-names: + minItems: 5 + items: + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: parf # Qualcomm specific registers + - const: config # PCIe configuration space + - const: aggr_noc #PCIe aggr_noc + - if: properties: compatible: @@ -365,6 +389,39 @@ allOf: - const: ahb # AHB Reset - const: axi_m_sticky # AXI Master Sticky reset + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-ipq9574 + then: + properties: + clocks: + minItems: 6 + maxItems: 6 + clock-names: + items: + - const: ahb # AHB clock + - const: aux # Auxiliary clock + - const: axi_m # AXI Master clock + - const: axi_s # AXI Slave clock + - const: axi_bridge # AXI bridge clock + - const: rchng + resets: + minItems: 8 + maxItems: 8 + reset-names: + items: + - const: pipe # PIPE reset + - const: sticky # Core Sticky reset + - const: axi_s_sticky # AXI Slave Sticky reset + - const: axi_s # AXI Slave reset + - const: axi_m_sticky # AXI Master Sticky reset + - const: axi_m # AXI Master reset + - const: aux # AUX Reset + - const: ahb # AHB Reset + - if: properties: compatible: @@ -681,6 +738,16 @@ allOf: - interconnects - interconnect-names + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-ipq9574 + then: + required: + - msi-parent + - if: not: properties: @@ -693,6 +760,7 @@ allOf: - qcom,pcie-ipq8064v2 - qcom,pcie-ipq8074 - qcom,pcie-ipq8074-gen3 + - qcom,pcie-ipq9574 - qcom,pcie-qcs404 then: required: From patchwork Tue Feb 14 16:41:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Devi Priya X-Patchwork-Id: 653539 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org 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vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.170.22 definitions=2023-02-14_11,2023-02-14_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 impostorscore=0 bulkscore=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 spamscore=0 malwarescore=0 mlxlogscore=999 adultscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2302140142 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the compatible for the PCIe QMP PHYs found on IPQ9574 Signed-off-by: Devi Priya --- .../phy/qcom,ipq8074-qmp-pcie-phy.yaml | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml index 62045dcfb20c..1131f0d87a9c 100644 --- a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml @@ -22,6 +22,8 @@ properties: - qcom,ipq6018-qmp-pcie-phy - qcom,ipq8074-qmp-gen3-pcie-phy - qcom,ipq8074-qmp-pcie-phy + - qcom,ipq9574-qmp-gen3x1-pcie-phy + - qcom,ipq9574-qmp-gen3x2-pcie-phy - qcom,msm8998-qmp-pcie-phy - qcom,sc8180x-qmp-pcie-phy - qcom,sdm845-qhp-pcie-phy @@ -165,6 +167,30 @@ allOf: - const: phy - const: common + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq9574-qmp-gen3x1-pcie-phy + - qcom,ipq9574-qmp-gen3x2-pcie-phy + then: + properties: + clocks: + maxItems: 4 + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: anoc_lane + - const: snoc_lane + resets: + maxItems: 2 + reset-names: + items: + - const: phy + - const: common + - if: properties: compatible: @@ -203,6 +229,7 @@ allOf: compatible: contains: enum: + - qcom,ipq9574-qmp-gen3x2-pcie-phy - qcom,sm8250-qmp-gen3x2-pcie-phy - qcom,sm8250-qmp-modem-pcie-phy - qcom,sm8450-qmp-gen4x2-pcie-phy @@ -224,6 +251,7 @@ allOf: compatible: contains: enum: + - qcom,ipq9574-qmp-gen3x1-pcie-phy - qcom,sc8180x-qmp-pcie-phy - qcom,sdm845-qmp-pcie-phy - qcom,sdx55-qmp-pcie-phy From patchwork Tue Feb 14 16:41:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Devi Priya X-Patchwork-Id: 653538 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0140FC61DA4 for ; Tue, 14 Feb 2023 16:43:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232531AbjBNQna (ORCPT ); Tue, 14 Feb 2023 11:43:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33860 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id 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Feb 2023 22:11:33 +0530 Message-ID: <20230214164135.17039-6-quic_devipriy@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230214164135.17039-1-quic_devipriy@quicinc.com> References: <20230214164135.17039-1-quic_devipriy@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: CHWhO0FJ2T3eqIs4Wn6qmnCOC1J-wZb_ X-Proofpoint-ORIG-GUID: CHWhO0FJ2T3eqIs4Wn6qmnCOC1J-wZb_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.170.22 definitions=2023-02-14_11,2023-02-14_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 malwarescore=0 mlxlogscore=999 phishscore=0 lowpriorityscore=0 bulkscore=0 mlxscore=0 adultscore=0 impostorscore=0 suspectscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2302140142 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add PCIe clock definitions for IPQ9574 SoC Co-developed-by: Anusha Rao Signed-off-by: Anusha Rao Signed-off-by: Devi Priya --- include/dt-bindings/clock/qcom,ipq9574-gcc.h | 276 ++++++++++--------- 1 file changed, 140 insertions(+), 136 deletions(-) diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h index feedfdd5e00a..c89e96d568c6 100644 --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h @@ -74,140 +74,144 @@ #define GCC_PCIE3_AXI_S_BRIDGE_CLK 65 #define GCC_PCIE3_AXI_S_CLK 66 #define PCIE0_PIPE_CLK_SRC 67 -#define PCIE1_PIPE_CLK_SRC 68 -#define PCIE2_PIPE_CLK_SRC 69 -#define PCIE3_PIPE_CLK_SRC 70 -#define PCIE_AUX_CLK_SRC 71 -#define GCC_PCIE0_AUX_CLK 72 -#define GCC_PCIE1_AUX_CLK 73 -#define GCC_PCIE2_AUX_CLK 74 -#define GCC_PCIE3_AUX_CLK 75 -#define PCIE0_RCHNG_CLK_SRC 76 -#define GCC_PCIE0_RCHNG_CLK 77 -#define PCIE1_RCHNG_CLK_SRC 78 -#define GCC_PCIE1_RCHNG_CLK 79 -#define PCIE2_RCHNG_CLK_SRC 80 -#define GCC_PCIE2_RCHNG_CLK 81 -#define PCIE3_RCHNG_CLK_SRC 82 -#define GCC_PCIE3_RCHNG_CLK 83 -#define GCC_PCIE0_AHB_CLK 84 -#define GCC_PCIE1_AHB_CLK 85 -#define GCC_PCIE2_AHB_CLK 86 -#define GCC_PCIE3_AHB_CLK 87 -#define USB0_AUX_CLK_SRC 88 -#define GCC_USB0_AUX_CLK 89 -#define USB0_MASTER_CLK_SRC 90 -#define GCC_USB0_MASTER_CLK 91 -#define GCC_SNOC_USB_CLK 92 -#define GCC_ANOC_USB_AXI_CLK 93 -#define USB0_MOCK_UTMI_CLK_SRC 94 -#define USB0_MOCK_UTMI_DIV_CLK_SRC 95 -#define GCC_USB0_MOCK_UTMI_CLK 96 -#define USB0_PIPE_CLK_SRC 97 -#define GCC_USB0_PHY_CFG_AHB_CLK 98 -#define SDCC1_APPS_CLK_SRC 99 -#define GCC_SDCC1_APPS_CLK 100 -#define SDCC1_ICE_CORE_CLK_SRC 101 -#define GCC_SDCC1_ICE_CORE_CLK 102 -#define GCC_SDCC1_AHB_CLK 103 -#define PCNOC_BFDCD_CLK_SRC 104 -#define GCC_NSSCFG_CLK 105 -#define GCC_NSSNOC_NSSCC_CLK 106 -#define GCC_NSSCC_CLK 107 -#define GCC_NSSNOC_PCNOC_1_CLK 108 -#define GCC_QDSS_DAP_AHB_CLK 109 -#define GCC_QDSS_CFG_AHB_CLK 110 -#define GCC_QPIC_AHB_CLK 111 -#define GCC_QPIC_CLK 112 -#define GCC_BLSP1_AHB_CLK 113 -#define GCC_MDIO_AHB_CLK 114 -#define GCC_PRNG_AHB_CLK 115 -#define GCC_UNIPHY0_AHB_CLK 116 -#define GCC_UNIPHY1_AHB_CLK 117 -#define GCC_UNIPHY2_AHB_CLK 118 -#define GCC_CMN_12GPLL_AHB_CLK 119 -#define GCC_CMN_12GPLL_APU_CLK 120 -#define SYSTEM_NOC_BFDCD_CLK_SRC 121 -#define GCC_NSSNOC_SNOC_CLK 122 -#define GCC_NSSNOC_SNOC_1_CLK 123 -#define GCC_QDSS_ETR_USB_CLK 124 -#define WCSS_AHB_CLK_SRC 125 -#define GCC_Q6_AHB_CLK 126 -#define GCC_Q6_AHB_S_CLK 127 -#define GCC_WCSS_ECAHB_CLK 128 -#define GCC_WCSS_ACMT_CLK 129 -#define GCC_SYS_NOC_WCSS_AHB_CLK 130 -#define WCSS_AXI_M_CLK_SRC 131 -#define GCC_ANOC_WCSS_AXI_M_CLK 132 -#define QDSS_AT_CLK_SRC 133 -#define GCC_Q6SS_ATBM_CLK 134 -#define GCC_WCSS_DBG_IFC_ATB_CLK 135 -#define GCC_NSSNOC_ATB_CLK 136 -#define GCC_QDSS_AT_CLK 137 -#define GCC_SYS_NOC_AT_CLK 138 -#define GCC_PCNOC_AT_CLK 139 -#define GCC_USB0_EUD_AT_CLK 140 -#define GCC_QDSS_EUD_AT_CLK 141 -#define QDSS_STM_CLK_SRC 142 -#define GCC_QDSS_STM_CLK 143 -#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 144 -#define QDSS_TRACECLKIN_CLK_SRC 145 -#define GCC_QDSS_TRACECLKIN_CLK 146 -#define QDSS_TSCTR_CLK_SRC 147 -#define GCC_Q6_TSCTR_1TO2_CLK 148 -#define GCC_WCSS_DBG_IFC_NTS_CLK 149 -#define GCC_QDSS_TSCTR_DIV2_CLK 150 -#define GCC_QDSS_TS_CLK 151 -#define GCC_QDSS_TSCTR_DIV4_CLK 152 -#define GCC_NSS_TS_CLK 153 -#define GCC_QDSS_TSCTR_DIV8_CLK 154 -#define GCC_QDSS_TSCTR_DIV16_CLK 155 -#define GCC_Q6SS_PCLKDBG_CLK 156 -#define GCC_Q6SS_TRIG_CLK 157 -#define GCC_WCSS_DBG_IFC_APB_CLK 158 -#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 159 -#define GCC_QDSS_DAP_CLK 160 -#define GCC_QDSS_APB2JTAG_CLK 161 -#define GCC_QDSS_TSCTR_DIV3_CLK 162 -#define QPIC_IO_MACRO_CLK_SRC 163 -#define GCC_QPIC_IO_MACRO_CLK 164 -#define Q6_AXI_CLK_SRC 165 -#define GCC_Q6_AXIM_CLK 166 -#define GCC_WCSS_Q6_TBU_CLK 167 -#define GCC_MEM_NOC_Q6_AXI_CLK 168 -#define Q6_AXIM2_CLK_SRC 169 -#define NSSNOC_MEMNOC_BFDCD_CLK_SRC 170 -#define GCC_NSSNOC_MEMNOC_CLK 171 -#define GCC_NSSNOC_MEM_NOC_1_CLK 172 -#define GCC_NSS_TBU_CLK 173 -#define GCC_MEM_NOC_NSSNOC_CLK 174 -#define LPASS_AXIM_CLK_SRC 175 -#define LPASS_SWAY_CLK_SRC 176 -#define ADSS_PWM_CLK_SRC 177 -#define GCC_ADSS_PWM_CLK 178 -#define GP1_CLK_SRC 179 -#define GP2_CLK_SRC 180 -#define GP3_CLK_SRC 181 -#define DDRSS_SMS_SLOW_CLK_SRC 182 -#define GCC_XO_CLK_SRC 183 -#define GCC_XO_CLK 184 -#define GCC_NSSNOC_QOSGEN_REF_CLK 185 -#define GCC_NSSNOC_TIMEOUT_REF_CLK 186 -#define GCC_XO_DIV4_CLK 187 -#define GCC_UNIPHY0_SYS_CLK 188 -#define GCC_UNIPHY1_SYS_CLK 189 -#define GCC_UNIPHY2_SYS_CLK 190 -#define GCC_CMN_12GPLL_SYS_CLK 191 -#define GCC_NSSNOC_XO_DCD_CLK 192 -#define GCC_Q6SS_BOOT_CLK 193 -#define UNIPHY_SYS_CLK_SRC 194 -#define NSS_TS_CLK_SRC 195 -#define GCC_ANOC_PCIE0_1LANE_M_CLK 196 -#define GCC_ANOC_PCIE1_1LANE_M_CLK 197 -#define GCC_ANOC_PCIE2_2LANE_M_CLK 198 -#define GCC_ANOC_PCIE3_2LANE_M_CLK 199 -#define GCC_SNOC_PCIE0_1LANE_S_CLK 200 -#define GCC_SNOC_PCIE1_1LANE_S_CLK 201 -#define GCC_SNOC_PCIE2_2LANE_S_CLK 202 -#define GCC_SNOC_PCIE3_2LANE_S_CLK 203 +#define GCC_PCIE0_PIPE_CLK 68 +#define PCIE1_PIPE_CLK_SRC 69 +#define GCC_PCIE1_PIPE_CLK 70 +#define PCIE2_PIPE_CLK_SRC 71 +#define GCC_PCIE2_PIPE_CLK 72 +#define PCIE3_PIPE_CLK_SRC 73 +#define GCC_PCIE3_PIPE_CLK 74 +#define PCIE_AUX_CLK_SRC 75 +#define GCC_PCIE0_AUX_CLK 76 +#define GCC_PCIE1_AUX_CLK 77 +#define GCC_PCIE2_AUX_CLK 78 +#define GCC_PCIE3_AUX_CLK 79 +#define PCIE0_RCHNG_CLK_SRC 80 +#define GCC_PCIE0_RCHNG_CLK 81 +#define PCIE1_RCHNG_CLK_SRC 82 +#define GCC_PCIE1_RCHNG_CLK 83 +#define PCIE2_RCHNG_CLK_SRC 84 +#define GCC_PCIE2_RCHNG_CLK 85 +#define PCIE3_RCHNG_CLK_SRC 86 +#define GCC_PCIE3_RCHNG_CLK 87 +#define GCC_PCIE0_AHB_CLK 88 +#define GCC_PCIE1_AHB_CLK 89 +#define GCC_PCIE2_AHB_CLK 90 +#define GCC_PCIE3_AHB_CLK 91 +#define USB0_AUX_CLK_SRC 92 +#define GCC_USB0_AUX_CLK 93 +#define USB0_MASTER_CLK_SRC 94 +#define GCC_USB0_MASTER_CLK 95 +#define GCC_SNOC_USB_CLK 96 +#define GCC_ANOC_USB_AXI_CLK 97 +#define USB0_MOCK_UTMI_CLK_SRC 98 +#define USB0_MOCK_UTMI_DIV_CLK_SRC 99 +#define GCC_USB0_MOCK_UTMI_CLK 100 +#define USB0_PIPE_CLK_SRC 101 +#define GCC_USB0_PHY_CFG_AHB_CLK 102 +#define SDCC1_APPS_CLK_SRC 103 +#define GCC_SDCC1_APPS_CLK 104 +#define SDCC1_ICE_CORE_CLK_SRC 105 +#define GCC_SDCC1_ICE_CORE_CLK 106 +#define GCC_SDCC1_AHB_CLK 107 +#define PCNOC_BFDCD_CLK_SRC 108 +#define GCC_NSSCFG_CLK 109 +#define GCC_NSSNOC_NSSCC_CLK 110 +#define GCC_NSSCC_CLK 111 +#define GCC_NSSNOC_PCNOC_1_CLK 112 +#define GCC_QDSS_DAP_AHB_CLK 113 +#define GCC_QDSS_CFG_AHB_CLK 114 +#define GCC_QPIC_AHB_CLK 115 +#define GCC_QPIC_CLK 116 +#define GCC_BLSP1_AHB_CLK 117 +#define GCC_MDIO_AHB_CLK 118 +#define GCC_PRNG_AHB_CLK 119 +#define GCC_UNIPHY0_AHB_CLK 120 +#define GCC_UNIPHY1_AHB_CLK 121 +#define GCC_UNIPHY2_AHB_CLK 122 +#define GCC_CMN_12GPLL_AHB_CLK 123 +#define GCC_CMN_12GPLL_APU_CLK 124 +#define SYSTEM_NOC_BFDCD_CLK_SRC 125 +#define GCC_NSSNOC_SNOC_CLK 126 +#define GCC_NSSNOC_SNOC_1_CLK 127 +#define GCC_QDSS_ETR_USB_CLK 128 +#define WCSS_AHB_CLK_SRC 129 +#define GCC_Q6_AHB_CLK 130 +#define GCC_Q6_AHB_S_CLK 131 +#define GCC_WCSS_ECAHB_CLK 132 +#define GCC_WCSS_ACMT_CLK 133 +#define GCC_SYS_NOC_WCSS_AHB_CLK 134 +#define WCSS_AXI_M_CLK_SRC 135 +#define GCC_ANOC_WCSS_AXI_M_CLK 136 +#define QDSS_AT_CLK_SRC 137 +#define GCC_Q6SS_ATBM_CLK 138 +#define GCC_WCSS_DBG_IFC_ATB_CLK 139 +#define GCC_NSSNOC_ATB_CLK 140 +#define GCC_QDSS_AT_CLK 141 +#define GCC_SYS_NOC_AT_CLK 142 +#define GCC_PCNOC_AT_CLK 143 +#define GCC_USB0_EUD_AT_CLK 144 +#define GCC_QDSS_EUD_AT_CLK 145 +#define QDSS_STM_CLK_SRC 146 +#define GCC_QDSS_STM_CLK 147 +#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 148 +#define QDSS_TRACECLKIN_CLK_SRC 149 +#define GCC_QDSS_TRACECLKIN_CLK 150 +#define QDSS_TSCTR_CLK_SRC 151 +#define GCC_Q6_TSCTR_1TO2_CLK 152 +#define GCC_WCSS_DBG_IFC_NTS_CLK 153 +#define GCC_QDSS_TSCTR_DIV2_CLK 154 +#define GCC_QDSS_TS_CLK 155 +#define GCC_QDSS_TSCTR_DIV4_CLK 156 +#define GCC_NSS_TS_CLK 157 +#define GCC_QDSS_TSCTR_DIV8_CLK 158 +#define GCC_QDSS_TSCTR_DIV16_CLK 159 +#define GCC_Q6SS_PCLKDBG_CLK 160 +#define GCC_Q6SS_TRIG_CLK 161 +#define GCC_WCSS_DBG_IFC_APB_CLK 162 +#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 163 +#define GCC_QDSS_DAP_CLK 164 +#define GCC_QDSS_APB2JTAG_CLK 165 +#define GCC_QDSS_TSCTR_DIV3_CLK 166 +#define QPIC_IO_MACRO_CLK_SRC 167 +#define GCC_QPIC_IO_MACRO_CLK 168 +#define Q6_AXI_CLK_SRC 169 +#define GCC_Q6_AXIM_CLK 170 +#define GCC_WCSS_Q6_TBU_CLK 171 +#define GCC_MEM_NOC_Q6_AXI_CLK 172 +#define Q6_AXIM2_CLK_SRC 173 +#define NSSNOC_MEMNOC_BFDCD_CLK_SRC 174 +#define GCC_NSSNOC_MEMNOC_CLK 175 +#define GCC_NSSNOC_MEM_NOC_1_CLK 176 +#define GCC_NSS_TBU_CLK 177 +#define GCC_MEM_NOC_NSSNOC_CLK 178 +#define LPASS_AXIM_CLK_SRC 179 +#define LPASS_SWAY_CLK_SRC 180 +#define ADSS_PWM_CLK_SRC 181 +#define GCC_ADSS_PWM_CLK 182 +#define GP1_CLK_SRC 183 +#define GP2_CLK_SRC 184 +#define GP3_CLK_SRC 185 +#define DDRSS_SMS_SLOW_CLK_SRC 186 +#define GCC_XO_CLK_SRC 187 +#define GCC_XO_CLK 188 +#define GCC_NSSNOC_QOSGEN_REF_CLK 189 +#define GCC_NSSNOC_TIMEOUT_REF_CLK 190 +#define GCC_XO_DIV4_CLK 191 +#define GCC_UNIPHY0_SYS_CLK 192 +#define GCC_UNIPHY1_SYS_CLK 193 +#define GCC_UNIPHY2_SYS_CLK 194 +#define GCC_CMN_12GPLL_SYS_CLK 195 +#define GCC_NSSNOC_XO_DCD_CLK 196 +#define GCC_Q6SS_BOOT_CLK 197 +#define UNIPHY_SYS_CLK_SRC 198 +#define NSS_TS_CLK_SRC 199 +#define GCC_ANOC_PCIE0_1LANE_M_CLK 200 +#define GCC_ANOC_PCIE1_1LANE_M_CLK 201 +#define GCC_ANOC_PCIE2_2LANE_M_CLK 202 +#define GCC_ANOC_PCIE3_2LANE_M_CLK 203 +#define GCC_SNOC_PCIE0_1LANE_S_CLK 204 +#define GCC_SNOC_PCIE1_1LANE_S_CLK 205 +#define GCC_SNOC_PCIE2_2LANE_S_CLK 206 +#define GCC_SNOC_PCIE3_2LANE_S_CLK 207 #endif From patchwork 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platform. The PCIe0 & PCIe1 are 1-lane Gen3 host whereas PCIe2 & PCIe3 are 2-lane Gen3 host. Co-developed-by: Anusha Rao Signed-off-by: Anusha Rao Signed-off-by: Devi Priya --- arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts | 28 ++ arch/arm64/boot/dts/qcom/ipq9574.dtsi | 477 ++++++++++++++++++- 2 files changed, 499 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts index 2c8430197ec0..21b53f34ce84 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts @@ -8,6 +8,7 @@ /dts-v1/; +#include #include "ipq9574.dtsi" / { @@ -29,6 +30,33 @@ status = "okay"; }; +&pcie1_phy { + status = "okay"; +}; + +&pcie1_x1 { + perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie2_phy { + status = "okay"; +}; + +&pcie2_x2 { + perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie3_phy { + status = "okay"; +}; + +&pcie3_x2 { + perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + &sdhc_1 { pinctrl-0 = <&sdc_default_state>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 062f80798ebb..a32dbdeb5bed 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -6,8 +6,8 @@ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ -#include #include +#include #include / { @@ -22,11 +22,41 @@ #clock-cells = <0>; }; + pcie30_phy0_pipe_clk: pcie30_phy0_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <250000000>; + #clock-cells = <0>; + }; + + pcie30_phy1_pipe_clk: pcie30_phy1_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <250000000>; + #clock-cells = <0>; + }; + + pcie30_phy2_pipe_clk: pcie30_phy2_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <250000000>; + #clock-cells = <0>; + }; + + pcie30_phy3_pipe_clk: pcie30_phy3_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <250000000>; + #clock-cells = <0>; + }; + sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; }; + usb3phy_0_cc_pipe_clk: usb3phy_0_cc_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + #clock-cells = <0>; + }; + xo_board_clk: xo-board-clk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -121,6 +151,155 @@ #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + pcie0_phy: phy@84000 { + compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy"; + reg = <0x00084000 0x1bc>; /* Serdes PLL */ + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_PCIE0_AUX_CLK>, + <&gcc GCC_PCIE0_AHB_CLK>, + <&gcc GCC_ANOC_PCIE0_1LANE_M_CLK>, + <&gcc GCC_SNOC_PCIE0_1LANE_S_CLK>; + clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane"; + + assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>; + assigned-clock-rates = <20000000>; + + resets = <&gcc GCC_PCIE0_PHY_BCR>, + <&gcc GCC_PCIE0PHY_PHY_BCR>; + reset-names = "phy", "common"; + + status = "disabled"; + + pcie0_lane: phy@84200 { + reg = <0x00084200 0x16c>, /* Serdes Tx */ + <0x00084400 0x200>, /* Serdes Rx */ + <0x00084800 0x1f0>, /* PCS: Lane0, COM, PCIE */ + <0x00084c00 0xf4>; /* pcs_misc */ + #phy-cells = <0>; + + clocks = <&gcc GCC_PCIE0_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "gcc_pcie0_pipe_clk_src"; + #clock-cells = <0>; + }; + }; + + pcie2_phy: phy@8c000 { + compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy"; + reg = <0x0008c000 0x1bc>; /* Serdes PLL */ + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_PCIE2_AUX_CLK>, + <&gcc GCC_PCIE2_AHB_CLK>, + <&gcc GCC_ANOC_PCIE2_2LANE_M_CLK>, + <&gcc GCC_SNOC_PCIE2_2LANE_S_CLK>; + clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane"; + + assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>; + assigned-clock-rates = <20000000>; + + resets = <&gcc GCC_PCIE2_PHY_BCR>, + <&gcc GCC_PCIE2PHY_PHY_BCR>; + reset-names = "phy", "common"; + + status = "disabled"; + + pcie2_lanes: phy@8c200 { + reg = <0x0008c200 0x16c>, /* Serdes Tx0 */ + <0x0008c400 0x200>, /* Serdes Rx0 */ + <0x0008d000 0x1f0>, /* PCS: Lane0, COM, PCIE */ + <0x0008c600 0x16c>, /* Serdes Tx1 */ + <0x0008c800 0x200>, /* Serdes Rx1 */ + <0x0008d400 0x0f8>; /* pcs_misc */ + + #phy-cells = <0>; + + clocks = <&gcc GCC_PCIE2_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "gcc_pcie2_pipe_clk_src"; + #clock-cells = <0>; + }; + }; + + pcie3_phy: phy@f4000 { + compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy"; + reg = <0x000f4000 0x1bc>; /* Serdes PLL */ + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_PCIE3_AUX_CLK>, + <&gcc GCC_PCIE3_AHB_CLK>, + <&gcc GCC_ANOC_PCIE3_2LANE_M_CLK>, + <&gcc GCC_SNOC_PCIE3_2LANE_S_CLK>; + clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane"; + + assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>; + assigned-clock-rates = <20000000>; + + resets = <&gcc GCC_PCIE3_PHY_BCR>, + <&gcc GCC_PCIE3PHY_PHY_BCR>; + reset-names = "phy", "common"; + + status = "disabled"; + + pcie3_lanes: phy@f4200 { + reg = <0x000f4200 0x16c>, /* Serdes Tx0 */ + <0x000f4400 0x200>, /* Serdes Rx0 */ + <0x000f5000 0x1f0>, /* PCS: Lane0, COM, PCIE */ + <0x000f4600 0x16c>, /* Serdes Tx1 */ + <0x000f4800 0x200>, /* Serdes Rx1 */ + <0x000f5400 0x0f8>; /* pcs_misc */ + + #phy-cells = <0>; + + clocks = <&gcc GCC_PCIE3_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "gcc_pcie3_pipe_clk_src"; + #clock-cells = <0>; + }; + }; + + pcie1_phy: phy@fc000 { + compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy"; + reg = <0x000fc000 0x1bc>; /* Serdes PLL */ + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_PCIE1_AUX_CLK>, + <&gcc GCC_PCIE1_AHB_CLK>, + <&gcc GCC_ANOC_PCIE1_1LANE_M_CLK>, + <&gcc GCC_SNOC_PCIE1_1LANE_S_CLK>; + clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane"; + + assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>; + assigned-clock-rates = <20000000>; + + resets = <&gcc GCC_PCIE1_PHY_BCR>, + <&gcc GCC_PCIE1PHY_PHY_BCR>; + reset-names = "phy", "common"; + + status = "disabled"; + + pcie1_lane: phy@fc200 { + reg = <0x000fc200 0x16c>, /* Serdes Tx */ + <0x000fc400 0x200>, /* Serdes Rx */ + <0x000fc800 0x1f0>, /* PCS: Lane0, COM, PCIE */ + <0x000fcc00 0xf4>; /* pcs_misc */ + #phy-cells = <0>; + + clocks = <&gcc GCC_PCIE1_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "gcc_pcie1_pipe_clk_src"; + #clock-cells = <0>; + }; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq9574-tlmm"; reg = <0x01000000 0x300000>; @@ -145,11 +324,11 @@ clocks = <&xo_board_clk>, <&sleep_clk>, <&bias_pll_ubi_nc_clk>, - <0>, - <0>, - <0>, - <0>, - <0>; + <&pcie30_phy0_pipe_clk>, + <&pcie30_phy1_pipe_clk>, + <&pcie30_phy2_pipe_clk>, + <&pcie30_phy3_pipe_clk>, + <&usb3phy_0_cc_pipe_clk>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; @@ -282,6 +461,292 @@ status = "disabled"; }; }; + + pcie1_x1: pci@10000000 { + compatible = "qcom,pcie-ipq9574"; + reg = <0x10000000 0xf1d>, + <0x10000F20 0xa8>, + <0x10001000 0x1000>, + <0x000F8000 0x4000>, + <0x10100000 0x1000>, + <0x00618108 0x4>; + reg-names = "dbi", "elbi", "atu", "parf", "config", "aggr_noc"; + device_type = "pci"; + linux,pci-domain = <2>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x81000000 0 0x10200000 0x10200000 + 0 0x00100000 /* downstream I/O */ + 0x82000000 0 0x10300000 0x10300000 + 0 0x07d00000>; /* non-prefetchable memory */ + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 35 + IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 49 + IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 84 + IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 85 + IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + interrupts = ; + interrupt-names = "global_irq"; + + /* clocks and clock-names are used to enable the clock in CBCR */ + clocks = <&gcc GCC_PCIE1_AHB_CLK>, + <&gcc GCC_PCIE1_AUX_CLK>, + <&gcc GCC_PCIE1_AXI_M_CLK>, + <&gcc GCC_PCIE1_AXI_S_CLK>, + <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE1_RCHNG_CLK>; + clock-names = "ahb", + "aux", + "axi_m", + "axi_s", + "axi_bridge", + "rchng"; + + resets = <&gcc GCC_PCIE1_PIPE_ARES>, + <&gcc GCC_PCIE1_CORE_STICKY_ARES>, + <&gcc GCC_PCIE1_AXI_S_STICKY_ARES>, + <&gcc GCC_PCIE1_AXI_S_ARES>, + <&gcc GCC_PCIE1_AXI_M_STICKY_ARES>, + <&gcc GCC_PCIE1_AXI_M_ARES>, + <&gcc GCC_PCIE1_AUX_ARES>, + <&gcc GCC_PCIE1_AHB_ARES>; + reset-names = "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + + phys = <&pcie1_lane>; + phy-names = "pciephy"; + msi-parent = <&v2m0>; + status = "disabled"; + }; + + pcie3_x2: pci@18000000 { + compatible = "qcom,pcie-ipq9574"; + reg = <0x18000000 0xf1d>, + <0x18000F20 0xa8>, + <0x18001000 0x1000>, + <0x000F0000 0x4000>, + <0x18100000 0x1000>; + reg-names = "dbi", "elbi", "atu", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <4>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x81000000 0 0x18200000 0x18200000 + 0 0x00100000 /* downstream I/O */ + 0x82000000 0 0x18300000 0x18300000 + 0 0x07d00000>; /* non-prefetchable memory */ + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 189 + IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 190 + IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 191 + IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 192 + IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + interrupts = ; + interrupt-names = "global_irq"; + + /* clocks and clock-names are used to enable the clock in CBCR */ + clocks = <&gcc GCC_PCIE3_AHB_CLK>, + <&gcc GCC_PCIE3_AUX_CLK>, + <&gcc GCC_PCIE3_AXI_M_CLK>, + <&gcc GCC_PCIE3_AXI_S_CLK>, + <&gcc GCC_PCIE3_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE3_RCHNG_CLK>; + clock-names = "ahb", + "aux", + "axi_m", + "axi_s", + "axi_bridge", + "rchng"; + + resets = <&gcc GCC_PCIE3_PIPE_ARES>, + <&gcc GCC_PCIE3_CORE_STICKY_ARES>, + <&gcc GCC_PCIE3_AXI_S_STICKY_ARES>, + <&gcc GCC_PCIE3_AXI_S_ARES>, + <&gcc GCC_PCIE3_AXI_M_STICKY_ARES>, + <&gcc GCC_PCIE3_AXI_M_ARES>, + <&gcc GCC_PCIE3_AUX_ARES>, + <&gcc GCC_PCIE3_AHB_ARES>; + reset-names = "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + + phys = <&pcie3_lanes>; + phy-names = "pciephy"; + msi-parent = <&v2m0>; + status = "disabled"; + }; + + pcie2_x2: pci@20000000 { + compatible = "qcom,pcie-ipq9574"; + reg = <0x20000000 0xf1d>, + <0x20000F20 0xa8>, + <0x20001000 0x1000>, + <0x00088000 0x4000>, + <0x20100000 0x1000>; + reg-names = "dbi", "elbi", "atu", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <3>; + bus-range = <0x00 0xff>; + num-lanes =<2>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x81000000 0 0x20200000 0x20200000 + 0 0x00100000 /* downstream I/O */ + 0x82000000 0 0x20300000 0x20300000 + 0 0x07d00000>; /* non-prefetchable memory */ + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 164 + IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 165 + IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 186 + IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 187 + IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + interrupts = ; + interrupt-names = "global_irq"; + + /* clocks and clock-names are used to enable the clock in CBCR */ + clocks = <&gcc GCC_PCIE2_AHB_CLK>, + <&gcc GCC_PCIE2_AUX_CLK>, + <&gcc GCC_PCIE2_AXI_M_CLK>, + <&gcc GCC_PCIE2_AXI_S_CLK>, + <&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE2_RCHNG_CLK>; + clock-names = "ahb", + "aux", + "axi_m", + "axi_s", + "axi_bridge", + "rchng"; + + resets = <&gcc GCC_PCIE2_PIPE_ARES>, + <&gcc GCC_PCIE2_CORE_STICKY_ARES>, + <&gcc GCC_PCIE2_AXI_S_STICKY_ARES>, + <&gcc GCC_PCIE2_AXI_S_ARES>, + <&gcc GCC_PCIE2_AXI_M_STICKY_ARES>, + <&gcc GCC_PCIE2_AXI_M_ARES>, + <&gcc GCC_PCIE2_AUX_ARES>, + <&gcc GCC_PCIE2_AHB_ARES>; + reset-names = "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + + phys = <&pcie2_lanes>; + phy-names = "pciephy"; + msi-parent = <&v2m0>; + status = "disabled"; + }; + + pcie0_x1: pci@28000000 { + compatible = "qcom,pcie-ipq9574"; + reg = <0x28000000 0xf1d>, + <0x28000F20 0xa8>, + <0x28001000 0x1000>, + <0x00080000 0x2000>, + <0x28100000 0x1000>, + <0x00618088 0x4>; + reg-names = "dbi", "elbi", "atu", "parf", "config", "aggr_noc"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x81000000 0 0x28200000 0x28200000 + 0 0x00100000 /* downstream I/O */ + 0x82000000 0 0x28300000 0x28300000 + 0 0x07d00000>; /* non-prefetchable memory */ + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 75 + IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 78 + IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 79 + IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 83 + IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + interrupts = ; + interrupt-names = "global_irq"; + + /* clocks and clock-names are used to enable the clock in CBCR */ + clocks = <&gcc GCC_PCIE0_AHB_CLK>, + <&gcc GCC_PCIE0_AUX_CLK>, + <&gcc GCC_PCIE0_AXI_M_CLK>, + <&gcc GCC_PCIE0_AXI_S_CLK>, + <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE0_RCHNG_CLK>; + clock-names = "ahb", + "aux", + "axi_m", + "axi_s", + "axi_bridge", + "rchng"; + + resets = <&gcc GCC_PCIE0_PIPE_ARES>, + <&gcc GCC_PCIE0_CORE_STICKY_ARES>, + <&gcc GCC_PCIE0_AXI_S_STICKY_ARES>, + <&gcc GCC_PCIE0_AXI_S_ARES>, + <&gcc GCC_PCIE0_AXI_M_STICKY_ARES>, + <&gcc GCC_PCIE0_AXI_M_ARES>, + <&gcc GCC_PCIE0_AUX_ARES>, + <&gcc GCC_PCIE0_AHB_ARES>; + reset-names = "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + + phys = <&pcie0_lane>; + phy-names = "pciephy"; + msi-parent = <&v2m0>; + status = "disabled"; + }; }; timer {