From patchwork Thu Apr 21 08:04:02 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 102487 Delivered-To: patch@linaro.org Received: by 10.140.93.198 with SMTP id d64csp2900732qge; Thu, 21 Apr 2016 01:06:38 -0700 (PDT) X-Received: by 10.66.79.197 with SMTP id l5mr18697369pax.61.1461225998638; Thu, 21 Apr 2016 01:06:38 -0700 (PDT) Return-Path: Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id x1si25102387pfb.185.2016.04.21.01.06.38 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Apr 2016 01:06:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@jms.id.au; spf=pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1at9cJ-000554-PR; Thu, 21 Apr 2016 08:05:39 +0000 Received: from mail-pf0-x234.google.com ([2607:f8b0:400e:c00::234]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1at9br-0003aC-9u for linux-arm-kernel@lists.infradead.org; Thu, 21 Apr 2016 08:05:12 +0000 Received: by mail-pf0-x234.google.com with SMTP id n1so27722547pfn.2 for ; Thu, 21 Apr 2016 01:04:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jms.id.au; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=AK8VJuru84i5wdeMhe5WEpTdJOdUxMHOxZOH3ilxABw=; b=Pm0R0zm3iUuCvDA9eUe5EJKT3gxKZslTe3xNGASZPggMVYI5IH8/FPsDpEJTkz3DZU GbWh/gkC2Tc18rwJ1KlaiSx6tQDDspIQ9RIstBKNhNZ+eyvsYHYEPj25x48n5C/5PyQX b3D8/ra+afddfrjq6hzDKaNI+mPyZPMQmmGKY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=AK8VJuru84i5wdeMhe5WEpTdJOdUxMHOxZOH3ilxABw=; b=W21B+iFMGgDtup5vGewkPCeEPugcsrQbH9KK4P/ZK7oBZG/lqyQdM+UGq9Pnaa3UGi sWcqIn3/Qw5hMDSn5RloC3pqvT1c9SpE/ubiNUoafJafotAK5oaKtl8AB/h0dOl5mwCw e1a1MT8AGU4VjECHSDzMoUWUM4IuVycICGlZ8pBtIiwdFOpulWwTKFS07c6UBtdMuU+8 QUrLbyqqBX+Qqz//FSYEuqPiusLY9i10rkHhoNSZoNnnannSGOQkgoxSDCH/rC+tIZnx 5LzVaycomZ/R0q3DG8xcf1gOvwjV45/YZGecqTNAPWgPLEJ0oijeMEBpIkp3k7d9awFS dBdg== X-Gm-Message-State: AOPr4FXBH1Ilv1d6W/AjW801HHvPrxpVjglh1c+oIhkg44TjXwkvrq2RgpQKdwLx6YQmUA== X-Received: by 10.98.23.201 with SMTP id 192mr18719058pfx.122.1461225890586; Thu, 21 Apr 2016 01:04:50 -0700 (PDT) Received: from icarus.au.ibm.com ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id uw2sm2650897pac.10.2016.04.21.01.04.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 21 Apr 2016 01:04:48 -0700 (PDT) From: Joel Stanley To: linux-arm-kernel@lists.infradead.org, arnd@arndb.de Subject: [PATCH v2 04/11] clocksource/moxart: Generalise timer for use on other socs Date: Thu, 21 Apr 2016 17:34:02 +0930 Message-Id: <1461225849-28074-5-git-send-email-joel@jms.id.au> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1461225849-28074-1-git-send-email-joel@jms.id.au> References: <1461225849-28074-1-git-send-email-joel@jms.id.au> In-Reply-To: <1460627269-21721-1-git-send-email-joel@jms.id.au> References: <1460627269-21721-1-git-send-email-joel@jms.id.au> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160421_010511_452333_4CFE4C1C X-CRM114-Status: GOOD ( 18.33 ) X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [2607:f8b0:400e:c00:0:0:0:234 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: benh@kernel.crashing.org, jk@ozlabs.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org The moxart timer IP is shared with another soc made by Aspeed. Generalise the registers that differ so the same driver can be used for both. As we now depend on CLKSRC_MMIO, create a Kconfig symbol for the driver so we can express this dependency. Signed-off-by: Joel Stanley --- .../bindings/timer/moxa,moxart-timer.txt | 4 +- drivers/clocksource/Kconfig | 6 ++ drivers/clocksource/Makefile | 2 +- drivers/clocksource/moxart_timer.c | 90 +++++++++++++++++----- 4 files changed, 79 insertions(+), 23 deletions(-) -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt b/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt index da2d510cae47..4569757142f8 100644 --- a/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt +++ b/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt @@ -2,7 +2,9 @@ MOXA ART timer Required properties: -- compatible : Must be "moxa,moxart-timer" +- compatible : Must be one of + - "moxa,moxart-timer" + - "aspeed,ast2400-timer" - reg : Should contain registers location and length - interrupts : Should contain the timer interrupt number - clocks : Should contain phandle for the clock that drives the counter diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index c346be650892..b14ac4db6961 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -411,4 +411,10 @@ config CLKSRC_ST_LPC Enable this option to use the Low Power controller timer as clocksource. +config MOXART_TIMER + def_bool ARCH_MOXART || ARCH_ASPEED + depends on ARM && OF + select CLKSRC_OF + select CLKSRC_MMIO + endmenu diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index dc2b8997f6e6..14fe8172c174 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -22,7 +22,7 @@ obj-$(CONFIG_ORION_TIMER) += time-orion.o obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o obj-$(CONFIG_ARCH_CLPS711X) += clps711x-timer.o obj-$(CONFIG_ARCH_ATLAS7) += timer-atlas7.o -obj-$(CONFIG_ARCH_MOXART) += moxart_timer.o +obj-$(CONFIG_MOXART_TIMER) += moxart_timer.o obj-$(CONFIG_ARCH_MXS) += mxs_timer.o obj-$(CONFIG_CLKSRC_PXA) += pxa_timer.o obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o diff --git a/drivers/clocksource/moxart_timer.c b/drivers/clocksource/moxart_timer.c index 19857af651c1..47ecef0725bd 100644 --- a/drivers/clocksource/moxart_timer.c +++ b/drivers/clocksource/moxart_timer.c @@ -36,45 +36,66 @@ #define TIMER_INTR_MASK 0x38 /* - * TIMER_CR flags: + * Moxart TIMER_CR flags: * * TIMEREG_CR_*_CLOCK 0: PCLK, 1: EXT1CLK * TIMEREG_CR_*_INT overflow interrupt enable bit */ -#define TIMEREG_CR_1_ENABLE BIT(0) -#define TIMEREG_CR_1_CLOCK BIT(1) -#define TIMEREG_CR_1_INT BIT(2) -#define TIMEREG_CR_2_ENABLE BIT(3) -#define TIMEREG_CR_2_CLOCK BIT(4) -#define TIMEREG_CR_2_INT BIT(5) -#define TIMEREG_CR_3_ENABLE BIT(6) -#define TIMEREG_CR_3_CLOCK BIT(7) -#define TIMEREG_CR_3_INT BIT(8) -#define TIMEREG_CR_COUNT_UP BIT(9) - -#define TIMER1_ENABLE (TIMEREG_CR_2_ENABLE | TIMEREG_CR_1_ENABLE) -#define TIMER1_DISABLE (TIMEREG_CR_2_ENABLE) +#define MOXART_CR_1_ENABLE BIT(0) +#define MOXART_CR_1_CLOCK BIT(1) +#define MOXART_CR_1_INT BIT(2) +#define MOXART_CR_2_ENABLE BIT(3) +#define MOXART_CR_2_CLOCK BIT(4) +#define MOXART_CR_2_INT BIT(5) +#define MOXART_CR_3_ENABLE BIT(6) +#define MOXART_CR_3_CLOCK BIT(7) +#define MOXART_CR_3_INT BIT(8) +#define MOXART_CR_COUNT_UP BIT(9) + +#define MOXART_TIMER1_ENABLE (MOXART_CR_2_ENABLE | MOXART_CR_1_ENABLE) +#define MOXART_TIMER1_DISABLE (MOXART_CR_2_ENABLE) + +/* + * The ASpeed variant of the IP block has a different layout + * for the control register + */ +#define ASPEED_CR_1_ENABLE BIT(0) +#define ASPEED_CR_1_CLOCK BIT(1) +#define ASPEED_CR_1_INT BIT(2) +#define ASPEED_CR_2_ENABLE BIT(4) +#define ASPEED_CR_2_CLOCK BIT(5) +#define ASPEED_CR_2_INT BIT(6) +#define ASPEED_CR_3_ENABLE BIT(8) +#define ASPEED_CR_3_CLOCK BIT(9) +#define ASPEED_CR_3_INT BIT(10) + +#define ASPEED_TIMER1_ENABLE (ASPEED_CR_2_ENABLE | ASPEED_CR_1_ENABLE) +#define ASPEED_TIMER1_DISABLE (ASPEED_CR_2_ENABLE) static void __iomem *base; static unsigned int clock_count_per_tick; +static unsigned int t1_disable_val, t1_enable_val; static int moxart_shutdown(struct clock_event_device *evt) { - writel(TIMER1_DISABLE, base + TIMER_CR); + writel(t1_disable_val, base + TIMER_CR); return 0; } static int moxart_set_oneshot(struct clock_event_device *evt) { - writel(TIMER1_DISABLE, base + TIMER_CR); + writel(t1_disable_val, base + TIMER_CR); writel(~0, base + TIMER1_BASE + REG_LOAD); return 0; } static int moxart_set_periodic(struct clock_event_device *evt) { + writel(t1_disable_val, base + TIMER_CR); writel(clock_count_per_tick, base + TIMER1_BASE + REG_LOAD); - writel(TIMER1_ENABLE, base + TIMER_CR); + writel(0, base + TIMER1_BASE + REG_MATCH1); + writel(t1_enable_val, base + TIMER_CR); + return 0; } @@ -83,12 +104,12 @@ static int moxart_clkevt_next_event(unsigned long cycles, { u32 u; - writel(TIMER1_DISABLE, base + TIMER_CR); + writel(t1_disable_val, base + TIMER_CR); u = readl(base + TIMER1_BASE + REG_COUNT) - cycles; writel(u, base + TIMER1_BASE + REG_MATCH1); - writel(TIMER1_ENABLE, base + TIMER_CR); + writel(t1_enable_val, base + TIMER_CR); return 0; } @@ -119,7 +140,7 @@ static struct irqaction moxart_timer_irq = { .dev_id = &moxart_clockevent, }; -static void __init moxart_timer_init(struct device_node *node) +static void __init __moxart_timer_init(struct device_node *node) { int ret, irq; unsigned long pclk; @@ -150,8 +171,19 @@ static void __init moxart_timer_init(struct device_node *node) clock_count_per_tick = DIV_ROUND_CLOSEST(pclk, HZ); + /* Clear match registers */ + writel(0, base + TIMER1_BASE + REG_MATCH1); + writel(0, base + TIMER1_BASE + REG_MATCH2); + writel(0, base + TIMER2_BASE + REG_MATCH1); + writel(0, base + TIMER2_BASE + REG_MATCH2); + + /* Start timer 2 rolling as our main wall clock source, keep timer 1 + * disabled + */ + writel(0, base + TIMER_CR); writel(~0, base + TIMER2_BASE + REG_LOAD); - writel(TIMEREG_CR_2_ENABLE, base + TIMER_CR); + writel(t1_disable_val, base + TIMER_CR); + moxart_clockevent.cpumask = cpumask_of(0); moxart_clockevent.irq = irq; @@ -165,4 +197,20 @@ static void __init moxart_timer_init(struct device_node *node) clockevents_config_and_register(&moxart_clockevent, pclk, 0x4, 0xfffffffe); } + +static void __init moxart_timer_init(struct device_node *node) +{ + t1_enable_val = MOXART_TIMER1_ENABLE; + t1_disable_val = MOXART_TIMER1_DISABLE; + __moxart_timer_init(node); +} + +static void __init aspeed_timer_init(struct device_node *node) +{ + t1_enable_val = ASPEED_TIMER1_ENABLE; + t1_disable_val = ASPEED_TIMER1_DISABLE; + __moxart_timer_init(node); +} + CLOCKSOURCE_OF_DECLARE(moxart, "moxa,moxart-timer", moxart_timer_init); +CLOCKSOURCE_OF_DECLARE(aspeed, "aspeed,ast2400-timer", aspeed_timer_init); From patchwork Thu Apr 21 08:04:06 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 102486 Delivered-To: patch@linaro.org Received: by 10.140.93.198 with SMTP id d64csp2900997qge; Thu, 21 Apr 2016 01:07:10 -0700 (PDT) X-Received: by 10.66.132.37 with SMTP id or5mr18721359pab.144.1461226030178; Thu, 21 Apr 2016 01:07:10 -0700 (PDT) Return-Path: Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id c63si2202227pfd.116.2016.04.21.01.07.10 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Apr 2016 01:07:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@jms.id.au; spf=pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1at9cv-0005h2-Pc; Thu, 21 Apr 2016 08:06:17 +0000 Received: from mail-pf0-x22c.google.com ([2607:f8b0:400e:c00::22c]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1at9c5-0004em-36 for linux-arm-kernel@lists.infradead.org; Thu, 21 Apr 2016 08:05:26 +0000 Received: by mail-pf0-x22c.google.com with SMTP id y69so10768774pfb.1 for ; Thu, 21 Apr 2016 01:05:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jms.id.au; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=7nCGpBe2pSiY4W5yOQL4eYlSwWdMAldcmcVPfDazMaQ=; b=HqfeoETmk1jvJDahWQ4Zon/ZZClNsAAXiZH2t7xNgDGMgfO6S29H7yrWP5GSs3/Bu1 EBvcbrYAeFXLbnkKm3vVHqLpoeOpkSCp6Lv10rmQJ5K5ZYMYf+aDL1XX/VZRWPl+PbAY Ktf2r6JuG3Vpr0XuAW50mVQ1t3fK+pKpoPYaY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=7nCGpBe2pSiY4W5yOQL4eYlSwWdMAldcmcVPfDazMaQ=; b=Cj0RIypBP4jWXXNLCuqXD+32z53/Bj98kFpMackjQoRBGguwBQJcUf9z4h9wExqAG3 tU8jKdSb5yXiH8CnCu/2784s+fLGE3UTrRQ5v7Z+pd7ro9Ec+BJCS/FFl0RW/NgqvdNR SdtKoMBtud8Ta+EA72Ikg2s/CgYIq+xCH0jZZdwkpu1cQkLbq61shy9NL19OdE90GXTG ikkAak7TPJxYbRijE/AVvxlnj81/vSRLFtN2ld0x1gqLWTKBSEQ3zSMSkfWM9AUVyeXe VBlxtNg01OfNktq0CGhU2cUWZwQ1f42wrG6leNSccxM2qpmd+l8gCjtKiuL1QkgA+LBP bouA== X-Gm-Message-State: AOPr4FW1W/WGNVNuqS5OPpgBfi6wVB7eO/s2fV1e71oo3hF86OFJ5ZfcGKgwXekIeu7ZKQ== X-Received: by 10.98.42.207 with SMTP id q198mr18842920pfq.103.1461225908265; Thu, 21 Apr 2016 01:05:08 -0700 (PDT) Received: from icarus.au.ibm.com ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id uw2sm2650897pac.10.2016.04.21.01.05.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 21 Apr 2016 01:05:06 -0700 (PDT) From: Joel Stanley To: linux-arm-kernel@lists.infradead.org, arnd@arndb.de Subject: [PATCH v2 08/11] arm/dts: Add Aspeed ast2400 device tree Date: Thu, 21 Apr 2016 17:34:06 +0930 Message-Id: <1461225849-28074-9-git-send-email-joel@jms.id.au> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1461225849-28074-1-git-send-email-joel@jms.id.au> References: <1461225849-28074-1-git-send-email-joel@jms.id.au> In-Reply-To: <1460627269-21721-1-git-send-email-joel@jms.id.au> References: <1460627269-21721-1-git-send-email-joel@jms.id.au> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160421_010525_245974_272E29F9 X-CRM114-Status: GOOD ( 15.26 ) X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [2607:f8b0:400e:c00:0:0:0:22c listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: benh@kernel.crashing.org, jk@ozlabs.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org A common device tree for all forth gen/ast2400 systems and a board specific dts for the Palmetto OpenPower developemnt machine which was used for testing. Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 21 ++++ arch/arm/boot/dts/aspeed-g4.dtsi | 152 ++++++++++++++++++++++++++ 3 files changed, 174 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts create mode 100644 arch/arm/boot/dts/aspeed-g4.dtsi -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 95c1923ce6fa..dee3a92cbd3c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -839,6 +839,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt8127-moose.dtb \ mt8135-evbp1.dtb dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb +dtb-$(CONFIG_ARCH_ASPEED) += aspeed-bmc-opp-palmetto.dtb endif dtstree := $(srctree)/$(src) diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts new file mode 100644 index 000000000000..29015c4b70bb --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts @@ -0,0 +1,21 @@ +/dts-v1/; + +#include "aspeed-g4.dtsi" + +/ { + model = "Palmetto BMC"; + compatible = "tyan,palmetto-bmc", "aspeed,ast2400"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,38400"; + }; + + memory { + reg = < 0x40000000 0x10000000 >; + }; +}; + +&uart5 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi new file mode 100644 index 000000000000..64c720cfacfe --- /dev/null +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -0,0 +1,152 @@ +#include "skeleton.dtsi" + +/ { + model = "Aspeed BMC"; + compatible = "aspeed,ast2400"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&vic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + reg = <0>; + }; + }; + + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + }; + + clocks { + clk_clkin: clk_clkin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <48000000>; + }; + + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vic: interrupt-controller@1e6c0080 { + compatible = "aspeed,ast2400-vic"; + interrupt-controller; + #interrupt-cells = <1>; + valid-sources = <0xffffffff 0x0007ffff>; + reg = <0x1e6c0080 0x80>; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clk_hpll: clk_hpll@1e6e2070 { + #clock-cells = <0>; + compatible = "aspeed,g4-hpll-clock"; + reg = <0x1e6e2070 0x4>; + clocks = <&clk_clkin>; + }; + + clk_apb: clk_apb@1e6e2008 { + #clock-cells = <0>; + compatible = "aspeed,g4-apb-clock"; + reg = <0x1e6e2008 0x4>; + clocks = <&clk_hpll>; + }; + + sram@1e720000 { + compatible = "mmio-sram"; + reg = <0x1e720000 0x8000>; // 32K + }; + + timer: timer@1e782000 { + compatible = "aspeed,ast2400-timer"; + reg = <0x1e782000 0x90>; + // The moxart_timer driver registers only one + // interrupt and assumes it's for timer 1 + //interrupts = <16 17 18 35 36 37 38 39>; + interrupts = <16>; + clocks = <&clk_apb>; + }; + + uart1: serial@1e783000 { + compatible = "ns16550a"; + reg = <0x1e783000 0x1000>; + reg-shift = <2>; + interrupts = <9>; + clock-frequency = <1843200>; + no-loopback-test; + status = "disabled"; + }; + + uart2: serial@1e78d000 { + compatible = "ns16550a"; + reg = <0x1e78d000 0x1000>; + reg-shift = <2>; + interrupts = <32>; + clock-frequency = <1843200>; + no-loopback-test; + status = "disabled"; + }; + + uart3: serial@1e78e000 { + compatible = "ns16550a"; + reg = <0x1e78e000 0x1000>; + reg-shift = <2>; + interrupts = <33>; + clock-frequency = <1843200>; + no-loopback-test; + status = "disabled"; + }; + + uart4: serial@1e78f000 { + compatible = "ns16550a"; + reg = <0x1e78f000 0x1000>; + reg-shift = <2>; + interrupts = <34>; + clock-frequency = <1843200>; + current-speed = <115200>; + no-loopback-test; + status = "disabled"; + }; + + uart5: serial@1e784000 { + compatible = "ns16550a"; + reg = <0x1e784000 0x1000>; + reg-shift = <2>; + interrupts = <10>; + clock-frequency = <1843200>; + current-speed = <38400>; + no-loopback-test; + status = "disabled"; + }; + + uart6: serial@1e787000 { + compatible = "ns16550a"; + reg = <0x1e787000 0x1000>; + reg-shift = <2>; + interrupts = <10>; + clock-frequency = <1843200>; + current-speed = <38400>; + no-loopback-test; + status = "disabled"; + }; + }; + }; +}; From patchwork Thu Apr 21 08:04:08 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 102485 Delivered-To: patch@linaro.org Received: by 10.140.93.198 with SMTP id d64csp2901787qge; Thu, 21 Apr 2016 01:08:47 -0700 (PDT) X-Received: by 10.66.162.101 with SMTP id xz5mr18671679pab.157.1461226127869; Thu, 21 Apr 2016 01:08:47 -0700 (PDT) Return-Path: Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id e65si22744925pfd.212.2016.04.21.01.08.47 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Apr 2016 01:08:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@jms.id.au; spf=pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1at9eM-0007gj-Co; Thu, 21 Apr 2016 08:07:46 +0000 Received: from mail-pa0-x229.google.com ([2607:f8b0:400e:c03::229]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1at9cI-0004rO-95 for linux-arm-kernel@lists.infradead.org; Thu, 21 Apr 2016 08:05:40 +0000 Received: by mail-pa0-x229.google.com with SMTP id er2so26722872pad.3 for ; Thu, 21 Apr 2016 01:05:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jms.id.au; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=PcNlkHJhdhJ38eJvjdhgp0sGhu+Xo0VYPOR5+6+ihAg=; b=Mw2iRLr8HPPoyvTE9jEZHLtyY5YQdKoQx8hqWSHxS3PpstHeealObLWe937hpX/3Ku lUEQF4aWG+SbiGZtBLKPwd2eqEEGVoaWb+j0M4b/3kblKFqTXSUQTEn6RJoQbq4vQKtC UthA7UvyPrhclrD4ojQhJwRRtAVAdLqgKb+hU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=PcNlkHJhdhJ38eJvjdhgp0sGhu+Xo0VYPOR5+6+ihAg=; b=ZI0COIXSdJNkGo00mjxa9GIgIHMNHgDyEXWLlltk6Dkqo6tmW90seyZW6fCEEJ44GX UljeQ29NUHx/5sRKe5CIl9ySJjpRH9PAKjVs0amyJ2mfMzBCclx56I7403eZf7+9JjBo VXMMB96ekUYV/H7XN69jHDivacMtJfpdr71PENzTYISxoXZjp0PxaLEQjrHyXEWYuS1a bFn7DUUQUnTODacTI7q7mE0vqYyWmqyvXqGFVVzYsXDzG0DJ7tAjam0+uKghIvGCG/E2 6JRGgROLbtDzOZWy/+9ZzU4eBHPKK6HS6cUj5YUZuqhBDAqjT5FcaBySPLlECaVUq3A+ ZG/g== X-Gm-Message-State: AOPr4FV4XLW3yoBOuwnDFlRgZ4yN9G6XNgz0k+LQj87dk/i4/v6x9IWPBHGU70SjOrgc6Q== X-Received: by 10.66.255.65 with SMTP id ao1mr18740532pad.38.1461225917836; Thu, 21 Apr 2016 01:05:17 -0700 (PDT) Received: from icarus.au.ibm.com ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id uw2sm2650897pac.10.2016.04.21.01.05.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 21 Apr 2016 01:05:14 -0700 (PDT) From: Joel Stanley To: linux-arm-kernel@lists.infradead.org, arnd@arndb.de Subject: [PATCH v2 10/11] arm: Add Aspeed machine Date: Thu, 21 Apr 2016 17:34:08 +0930 Message-Id: <1461225849-28074-11-git-send-email-joel@jms.id.au> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1461225849-28074-1-git-send-email-joel@jms.id.au> References: <1461225849-28074-1-git-send-email-joel@jms.id.au> In-Reply-To: <1460627269-21721-1-git-send-email-joel@jms.id.au> References: <1460627269-21721-1-git-send-email-joel@jms.id.au> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160421_010538_424818_38812C66 X-CRM114-Status: GOOD ( 21.15 ) X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [2607:f8b0:400e:c03:0:0:0:229 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: benh@kernel.crashing.org, jk@ozlabs.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Aspeed devices are a common Baseboard Management Controller (BMC) system on chip containing an ARM9 or ARM11 core, off-chip DDR RAM and support for a large number of peripherals. This patch adds basic support for the ast2400 and ast2500 machines, capable of booting to a prompt in QEMU (-M palmetto-bmc), on an Palmetto OpenPower development machine, and on the ast2500 EVB. Signed-off-by: Joel Stanley --- MAINTAINERS | 8 +++++ arch/arm/Kconfig | 2 ++ arch/arm/Makefile | 1 + arch/arm/mach-aspeed/Kconfig | 28 +++++++++++++++ arch/arm/mach-aspeed/Makefile | 3 ++ arch/arm/mach-aspeed/aspeed.c | 83 +++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 125 insertions(+) create mode 100644 arch/arm/mach-aspeed/Kconfig create mode 100644 arch/arm/mach-aspeed/Makefile create mode 100644 arch/arm/mach-aspeed/aspeed.c -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/MAINTAINERS b/MAINTAINERS index 61a323a6b2cf..d0a1962f7753 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -975,6 +975,14 @@ F: arch/arm/mach-artpec F: arch/arm/boot/dts/artpec6* F: drivers/clk/clk-artpec6.c +ARM/ASPEED MACHINE SUPPORT +M: Joel Stanley +S: Maintained +F: arch/arm/mach-aspeed/ +F: arch/arm/boot/dts/aspeed-* +F: arch/arm/boot/dts/ast2400.dtsi +F: drivers/*/*aspeed* + ARM/ATMEL AT91RM9200, AT91SAM9 AND SAMA5 SOC SUPPORT M: Nicolas Ferre M: Alexandre Belloni diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index cdfa6c2b7626..c4512f6b77f6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -775,6 +775,8 @@ source "arch/arm/mach-meson/Kconfig" source "arch/arm/mach-moxart/Kconfig" +source "arch/arm/mach-aspeed/Kconfig" + source "arch/arm/mach-mv78xx0/Kconfig" source "arch/arm/mach-imx/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 8c3ce2ac44c4..8ab09fb78e1c 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -184,6 +184,7 @@ machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx machine-$(CONFIG_ARCH_MESON) += meson machine-$(CONFIG_ARCH_MMP) += mmp machine-$(CONFIG_ARCH_MOXART) += moxart +machine-$(CONFIG_ARCH_ASPEED) += aspeed machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0 machine-$(CONFIG_ARCH_MVEBU) += mvebu machine-$(CONFIG_ARCH_MXC) += imx diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig new file mode 100644 index 000000000000..30bafc0bbd8b --- /dev/null +++ b/arch/arm/mach-aspeed/Kconfig @@ -0,0 +1,28 @@ +menuconfig ARCH_ASPEED + bool "Aspeed BMC architectures" + select OF + select SRAM + help + Say Y here if you want to run your kernel on hardware with an + ASpeed BMC SoC. + +if ARCH_ASPEED + +config MACH_AST_G4 + bool "Aspeed SoC 4th Generation" if ARCH_MULTI_V5 + depends on ARCH_ASPEED + select CPU_ARM926T + help + Say yes if you intend to run on an Aspeed ast2400 or similar + fourth generation BMCs, such as those used by OpenPower Power8 + systems. + +config MACH_AST_G5 + bool "Aspeed SoC 5th Generation" if ARCH_MULTI_V6 + depends on ARCH_ASPEED + select CPU_V6 + help + Say yes if you intend to run on an Aspeed ast2500 or similar + fifth generation Aspeed BMCs. + +endif diff --git a/arch/arm/mach-aspeed/Makefile b/arch/arm/mach-aspeed/Makefile new file mode 100644 index 000000000000..3a4f025dd520 --- /dev/null +++ b/arch/arm/mach-aspeed/Makefile @@ -0,0 +1,3 @@ +# Object file lists. + +obj-$(CONFIG_ARCH_ASPEED) += aspeed.o diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c new file mode 100644 index 000000000000..822939113d95 --- /dev/null +++ b/arch/arm/mach-aspeed/aspeed.c @@ -0,0 +1,83 @@ +/* + * Copyright IBM Corporation 2016 + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define AST_BASE_WDT 0x1E785000 /* Watchdog Timer (WDT) */ +#define AST_BASE_SCU 0x1E6E2000 /* System Control Unit (SCU) */ + +static void __init aspeed_dt_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +#define AST_IO_VA 0xf0000000 +#define AST_IO_PA 0x1e600000 +#define AST_IO_SZ 0x00200000 + +#define AST_IO(__pa) ((void __iomem *)(((__pa) & 0x001fffff) | AST_IO_VA)) + +static struct map_desc aspeed_io_desc[] __initdata __maybe_unused = { + { + .virtual = AST_IO_VA, + .pfn = __phys_to_pfn(AST_IO_PA), + .length = AST_IO_SZ, + .type = MT_DEVICE + }, +}; + +#define SCU_PASSWORD 0x1688A8A8 + +static void __init aspeed_init_early(void) +{ + u32 reg; + + /* + * Unlock SCU + */ + writel(SCU_PASSWORD, AST_IO(AST_BASE_SCU)); + + /* We enable the UART clock divisor in the SCU's misc control + * register, as the baud rates in aspeed.dtb all assume that the + * divisor is active + */ + reg = readl(AST_IO(AST_BASE_SCU | 0x2c)); + writel(reg | 0x00001000, AST_IO(AST_BASE_SCU | 0x2c)); + + /* + * Disable the watchdogs + */ + writel(0, AST_IO(AST_BASE_WDT | 0x0c)); + writel(0, AST_IO(AST_BASE_WDT | 0x2c)); +} + +static void __init aspeed_map_io(void) +{ + debug_ll_io_init(); + iotable_init(aspeed_io_desc, ARRAY_SIZE(aspeed_io_desc)); +} + +static const char *const aspeed_dt_match[] __initconst = { + "aspeed,ast2400", + "aspeed,ast2500", + NULL, +}; + +DT_MACHINE_START(aspeed_dt, "ASpeed SoC") + .map_io = aspeed_map_io, + .init_early = aspeed_init_early, + .init_machine = aspeed_dt_init, + .dt_compat = aspeed_dt_match, +MACHINE_END From patchwork Thu Apr 21 08:04:09 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 102484 Delivered-To: patch@linaro.org Received: by 10.140.93.198 with SMTP id d64csp2901811qge; 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<1461225849-28074-12-git-send-email-joel@jms.id.au> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1461225849-28074-1-git-send-email-joel@jms.id.au> References: <1461225849-28074-1-git-send-email-joel@jms.id.au> In-Reply-To: <1460627269-21721-1-git-send-email-joel@jms.id.au> References: <1460627269-21721-1-git-send-email-joel@jms.id.au> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160421_010543_660295_41F30C1B X-CRM114-Status: GOOD ( 12.31 ) X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [2607:f8b0:400e:c03:0:0:0:22e listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.0 UPPERCASE_50_75 message body is 50-75% uppercase X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: benh@kernel.crashing.org, jk@ozlabs.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Signed-off-by: Joel Stanley --- arch/arm/configs/aspeed_g4_defconfig | 86 +++++++++++++++++++++++++++++++++++ arch/arm/configs/aspeed_g5_defconfig | 88 ++++++++++++++++++++++++++++++++++++ 2 files changed, 174 insertions(+) create mode 100644 arch/arm/configs/aspeed_g4_defconfig create mode 100644 arch/arm/configs/aspeed_g5_defconfig -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm/configs/aspeed_g4_defconfig b/arch/arm/configs/aspeed_g4_defconfig new file mode 100644 index 000000000000..83691bf98d09 --- /dev/null +++ b/arch/arm/configs/aspeed_g4_defconfig @@ -0,0 +1,86 @@ +CONFIG_KERNEL_XZ=y +CONFIG_SYSVIPC=y +CONFIG_USELIB=y +CONFIG_IRQ_DOMAIN_DEBUG=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_CGROUPS=y +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_BPF_SYSCALL=y +# CONFIG_SHMEM is not set +# CONFIG_AIO is not set +CONFIG_EMBEDDED=y +# CONFIG_COMPAT_BRK is not set +CONFIG_SLAB=y +CONFIG_CC_STACKPROTECTOR_STRONG=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLOCK is not set +# CONFIG_ARCH_MULTI_V7 is not set +CONFIG_ARCH_ASPEED=y +CONFIG_MACH_AST_G4=y +CONFIG_DEBUG_RODATA=y +CONFIG_AEABI=y +CONFIG_UACCESS_WITH_MEMCPY=y +CONFIG_SECCOMP=y +# CONFIG_ATAGS is not set +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_KEXEC=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_INPUT is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=6 +CONFIG_SERIAL_8250_RUNTIME_UARTS=6 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_HW_RANDOM is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_FIRMWARE_MEMMAP=y +CONFIG_FANOTIFY=y +CONFIG_PRINTK_TIME=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_STRIP_ASM_SYMS=y +CONFIG_PAGE_POISONING=y +CONFIG_DEBUG_KMEMLEAK=y +CONFIG_DEBUG_SHIRQ=y +CONFIG_LOCKUP_DETECTOR=y +CONFIG_WQ_WATCHDOG=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_SCHED_STACK_END_CHECK=y +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y +# CONFIG_FTRACE is not set +CONFIG_MEMTEST=y +CONFIG_UBSAN=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_LL_UART_8250=y +CONFIG_DEBUG_UART_PHYS=0x1e784000 +CONFIG_DEBUG_UART_VIRT=0xe8784000 +CONFIG_EARLY_PRINTK=y +CONFIG_DEBUG_SET_MODULE_RONX=y +# CONFIG_XZ_DEC_X86 is not set +# CONFIG_XZ_DEC_POWERPC is not set +# CONFIG_XZ_DEC_IA64 is not set +# CONFIG_XZ_DEC_SPARC is not set diff --git a/arch/arm/configs/aspeed_g5_defconfig b/arch/arm/configs/aspeed_g5_defconfig new file mode 100644 index 000000000000..274f96e1e3bf --- /dev/null +++ b/arch/arm/configs/aspeed_g5_defconfig @@ -0,0 +1,88 @@ +CONFIG_KERNEL_XZ=y +CONFIG_SYSVIPC=y +CONFIG_USELIB=y +CONFIG_IRQ_DOMAIN_DEBUG=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_CGROUPS=y +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_BPF_SYSCALL=y +# CONFIG_SHMEM is not set +# CONFIG_AIO is not set +CONFIG_EMBEDDED=y +# CONFIG_COMPAT_BRK is not set +CONFIG_SLAB=y +CONFIG_CC_STACKPROTECTOR_STRONG=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLOCK is not set +CONFIG_ARCH_MULTI_V6=y +# CONFIG_ARCH_MULTI_V7 is not set +CONFIG_ARCH_ASPEED=y +CONFIG_MACH_AST_G5=y +CONFIG_DEBUG_RODATA=y +CONFIG_AEABI=y +CONFIG_UACCESS_WITH_MEMCPY=y +CONFIG_SECCOMP=y +# CONFIG_ATAGS is not set +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_KEXEC=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_INPUT is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=6 +CONFIG_SERIAL_8250_RUNTIME_UARTS=6 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_HW_RANDOM is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_FIRMWARE_MEMMAP=y +CONFIG_FANOTIFY=y +CONFIG_PRINTK_TIME=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_STRIP_ASM_SYMS=y +CONFIG_PAGE_POISONING=y +CONFIG_DEBUG_KMEMLEAK=y +CONFIG_DEBUG_SHIRQ=y +CONFIG_LOCKUP_DETECTOR=y +CONFIG_WQ_WATCHDOG=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_SCHED_STACK_END_CHECK=y +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y +# CONFIG_FTRACE is not set +CONFIG_MEMTEST=y +CONFIG_UBSAN=y +CONFIG_UBSAN_ALIGNMENT=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_LL_UART_8250=y +CONFIG_DEBUG_UART_PHYS=0x1e784000 +CONFIG_DEBUG_UART_VIRT=0xe8784000 +CONFIG_EARLY_PRINTK=y +CONFIG_DEBUG_SET_MODULE_RONX=y +# CONFIG_XZ_DEC_X86 is not set +# CONFIG_XZ_DEC_POWERPC is not set +# CONFIG_XZ_DEC_IA64 is not set +# CONFIG_XZ_DEC_SPARC is not set