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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a5d4dcc000000b002c556a4f1casm2049107wru.42.2023.02.16.09.11.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 09:11:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/30] hw/intc/armv7m_nvic: Use OBJECT_DECLARE_SIMPLE_TYPE() macro Date: Thu, 16 Feb 2023 17:10:54 +0000 Message-Id: <20230216171123.2518285-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216171123.2518285-1-peter.maydell@linaro.org> References: <20230216171123.2518285-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Manually convert to OBJECT_DECLARE_SIMPLE_TYPE() macro, similarly to automatic conversion from commit 8063396bf3 ("Use OBJECT_DECLARE_SIMPLE_TYPE when possible"). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20230206223502.25122-2-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/intc/armv7m_nvic.h | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index 0180c7b0ca1..07f9c21a5f3 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -16,10 +16,7 @@ #include "qom/object.h" #define TYPE_NVIC "armv7m_nvic" - -typedef struct NVICState NVICState; -DECLARE_INSTANCE_CHECKER(NVICState, NVIC, - TYPE_NVIC) +OBJECT_DECLARE_SIMPLE_TYPE(NVICState, NVIC) /* Highest permitted number of exceptions (architectural limit) */ #define NVIC_MAX_VECTORS 512 From patchwork Thu Feb 16 17:10:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 654069 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp86606wrc; Thu, 16 Feb 2023 09:15:44 -0800 (PST) X-Google-Smtp-Source: AK7set9HJK4Si3QYoQWushBCAtVpLCPd5pKaT9nQb3RiHp3ZB7w7+4TO6WFfdS6CZ1k+Ll6fVLJF X-Received: by 2002:a05:6214:21a9:b0:56e:fe99:b2b1 with SMTP id t9-20020a05621421a900b0056efe99b2b1mr2883606qvc.12.1676567743827; Thu, 16 Feb 2023 09:15:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676567743; cv=none; d=google.com; s=arc-20160816; b=tQf/we3gtNkM33FDhhhnDMKThcegvWcHMHParP0jl71Apstt+eddfroj8BySN/8fmZ oW5Frmyob2qVU0fCjO8tff7VZYq6NmNS1EiRIdcRVhThdq4I871KIayGA0O26Z/rjxz9 gjMH+iAMOkPVPfrbMmzbRDnHWLPn1CLQZwEHdpZ3QUY0qQhVoevAXDNY93o5xHyGUljc /HzyAI4/BwmOY/B6uYPQTPdcuGz/gkaO23nfLmm68IAhGwljAqALCcLGiB+KPN/7k5U8 CyJ7TnaZ9V1VyuheKy3lRDZJNMG03RUsQlZJlQk+YTKYJeYdw+bzPswAgobZBNxxqiD0 ++aQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=r4krdA8Qnd36kyIKBvwPSIAkaJ6bsOagP1i8kYOboYQ=; b=nIysS9G5HaP6flWksPQSkSVS5mtRnV+gIb8UcDuIkdNblViNcm6E+HIqNqW3QX6CQm 8bw6pRI2BRxU6rUWl5FnX8r9rXRIoI4vxTCewUVgGRa6HXm42ucU3QaAo4We7ZU/sxEu WkI/jGX5Wy3ANTMhRR3LVE3QKBEnvH7aa3AJDOn83oYRH8KTwOHXxa9ugyXH9fF0etzm CSWARVSEHA+1HIXOebYsCmO4xFFNGUgy0w1tSSTrhbDVTthNqKoDA3EUNE/dMI5oalLG +I50sZRm0Xx+AYaZyNxLaOYkn87P7N1gdF54vjEPbCYzsijjD+bD1dBJF1P8ovdXXijY f1ng== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cDC8VgDV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a5d4dcc000000b002c556a4f1casm2049107wru.42.2023.02.16.09.11.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 09:11:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/30] target/arm: Simplify arm_v7m_mmu_idx_for_secstate() for user emulation Date: Thu, 16 Feb 2023 17:10:55 +0000 Message-Id: <20230216171123.2518285-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216171123.2518285-1-peter.maydell@linaro.org> References: <20230216171123.2518285-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20230206223502.25122-3-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/m_helper.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index e7e746ea182..76239c9abe9 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -150,7 +150,12 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) return 0; } -#else +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) +{ + return ARMMMUIdx_MUser; +} + +#else /* !CONFIG_USER_ONLY */ /* * What kind of stack write are we doing? This affects how exceptions @@ -2854,8 +2859,6 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) return tt_resp; } -#endif /* !CONFIG_USER_ONLY */ - ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, bool secstate, bool priv, bool negpri) { @@ -2892,3 +2895,5 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); } + +#endif /* !CONFIG_USER_ONLY */ From patchwork Thu Feb 16 17:10:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 654051 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp85102wrc; Thu, 16 Feb 2023 09:12:55 -0800 (PST) X-Google-Smtp-Source: AK7set+oHdEz1bBAVxM5vFOQhCUxE+fndWHIRX91k2NJidh9XjTpGErXQSXqiu+i5vHBOMol3t8/ X-Received: by 2002:a05:6214:20a6:b0:53a:151:b650 with SMTP id 6-20020a05621420a600b0053a0151b650mr11746422qvd.35.1676567574944; Thu, 16 Feb 2023 09:12:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676567574; cv=none; d=google.com; s=arc-20160816; b=spuGx/bm+bifykqjYqh8pnw2xsydUdy5oujIQe+oE+7vdEgc1PJwbvnFHpiXcVObsk R1TkdUGrBZVtLQ+rbQlp4dyS8PC/HIArfzmRXBMuxB2kLi4NFl9LLP1qhVz/J7Sac4Oi me/AGputR+31F2LQ/zDWUOPFSPIAqIxZ/hj/t5VnT6UEBUn3scDOpqMadI8qA+X4+ALj 73A5qgc4mrszqT5earaTHQM8xoOCSys8nBY4kpCRX7QcLcm/8gFyt17BZsqW/+ExgUtY xvHi09Ps5H5d0Vj/+nQsy1YaWRVCFpE7qhBMqd9mN1sgnmw/DUROHMhkOCUkGw2gA+JG oa7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1bJSQcpdAE5XdmRoJPsx4gO+dGl9PnbwqH6SWwJRQ6s=; b=lX9NiFJCWJ4a7eMUIGqEHlLM0SWAlWF056XYt78Ng1XBhunc+4TB8mb/FaO5fP77r3 oA1mIFAYW8SWzJFaSQWr4rUeYHGYm19IfAYId6L4fFQgchUm09wgVJ3kp16TUjqhGOpE Lymb17/2ceP9xz01oyJSmQcIVwXtTlXIi5Jp6YQV34cTXU38MLMh3hxgG079KTNwpFKQ +Fmx4kOmUVnZVdgz1mUtHftBMFMFxQZOeydBKGcMyVpK8+oa5zWk39clMxM6IsL3fdQZ CXQeeqYKycCFhuZBDxZrf5cJCjE9MuarKl4hB6rEh870iqGWBjnouLo21XoYa7gXw3Wb VsNA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=K1TsMCXd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a5d4dcc000000b002c556a4f1casm2049107wru.42.2023.02.16.09.11.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 09:11:27 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/30] target/arm: Reduce arm_v7m_mmu_idx_[all/for_secstate_and_priv]() scope Date: Thu, 16 Feb 2023 17:10:56 +0000 Message-Id: <20230216171123.2518285-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216171123.2518285-1-peter.maydell@linaro.org> References: <20230216171123.2518285-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé arm_v7m_mmu_idx_all() and arm_v7m_mmu_idx_for_secstate_and_priv() are only used for system emulation in m_helper.c. Move the definitions to avoid prototype forward declarations. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20230206223502.25122-4-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 14 -------- target/arm/m_helper.c | 74 +++++++++++++++++++++--------------------- 2 files changed, 37 insertions(+), 51 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index e1e018da463..759b70c646f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -597,20 +597,6 @@ static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx) int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx); -/* - * Return the MMU index for a v7M CPU with all relevant information - * manually specified. - */ -ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, - bool secstate, bool priv, bool negpri); - -/* - * Return the MMU index for a v7M CPU in the specified security and - * privilege state. - */ -ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, - bool secstate, bool priv); - /* Return the MMU index for a v7M CPU in the specified security state */ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 76239c9abe9..b4964dca8a8 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -157,6 +157,43 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) #else /* !CONFIG_USER_ONLY */ +static ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, + bool secstate, bool priv, bool negpri) +{ + ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; + + if (priv) { + mmu_idx |= ARM_MMU_IDX_M_PRIV; + } + + if (negpri) { + mmu_idx |= ARM_MMU_IDX_M_NEGPRI; + } + + if (secstate) { + mmu_idx |= ARM_MMU_IDX_M_S; + } + + return mmu_idx; +} + +static ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, + bool secstate, bool priv) +{ + bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate); + + return arm_v7m_mmu_idx_all(env, secstate, priv, negpri); +} + +/* Return the MMU index for a v7M CPU in the specified security state */ +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) +{ + bool priv = arm_v7m_is_handler_mode(env) || + !(env->v7m.control[secstate] & 1); + + return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); +} + /* * What kind of stack write are we doing? This affects how exceptions * generated during the stacking are treated. @@ -2859,41 +2896,4 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) return tt_resp; } -ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, - bool secstate, bool priv, bool negpri) -{ - ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; - - if (priv) { - mmu_idx |= ARM_MMU_IDX_M_PRIV; - } - - if (negpri) { - mmu_idx |= ARM_MMU_IDX_M_NEGPRI; - } - - if (secstate) { - mmu_idx |= ARM_MMU_IDX_M_S; - } - - return mmu_idx; -} - -ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, - bool secstate, bool priv) -{ - bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate); - - return arm_v7m_mmu_idx_all(env, secstate, priv, negpri); -} - -/* Return the MMU index for a v7M CPU in the specified security state */ -ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) -{ - bool priv = arm_v7m_is_handler_mode(env) || - !(env->v7m.control[secstate] & 1); - - return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); -} - #endif /* !CONFIG_USER_ONLY */ From patchwork Thu Feb 16 17:10:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 654050 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp84885wrc; Thu, 16 Feb 2023 09:12:36 -0800 (PST) X-Google-Smtp-Source: AK7set8j3sQ0gIh/HsFymVVTMmMmvblenYnKq/r3NfbOyaUCIeDnexvGB0lncFUopwNVNu+/Acmx X-Received: by 2002:a05:6214:401a:b0:56b:f215:1d7a with SMTP id kd26-20020a056214401a00b0056bf2151d7amr11359753qvb.52.1676567556542; Thu, 16 Feb 2023 09:12:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676567556; cv=none; d=google.com; s=arc-20160816; b=03bU40csOa1vsVzr7UrNsXyTv+B854rR8kabQr3OV8bSYYlU0xPkiQMy6/FBmbUIja RsS+vRDA2zj/wT3vphF8Y3C+519sMXc6UrKw1E1f3wt6D1hZ9FahP03Vz35okpQywZAU wvsDhOcWxDbC1DjA/N9gkEhkbhDfi9dUEqwVZjFUzmoquHESpyinAAcYbnFq2HNdaBf4 TZ2XnNBtS4n85cGDakN2Nwta+O3pfJ3Wjz4owahA4Ir7VlpeqgvCqqEkwHF3341jlthM hE4bwGDqI/0tugE6GSVfQFCycgvZH6s5lwelxfFs94zUvQJ3HduiAil8T5AZvsNxMPjA T2Fg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=7RlBfSYt1zg9bweFFHbEwDZ61Sd/0Ke4XEfLYhGOXrY=; b=mDnqWShHz12cuGl13/JF8nD/9C6Y6vwjdrxDEr802zhlA/GrzI26tJP+kZfpsJqGJJ HJ6MAz/2AyROn33eafSdRB6cyvdeS6RbNo+pGr02lW1vB3CFu0GYI5C12oCUb1vI8GNM egWilrlEwRqXZqSmvSaNzQC1PEuz3RLoXLX6It42dkn1MQ7kaNVvqtbk4iRlHIGeHsVM Q4Z/jbLeQ5AUDcrtir2ODZlsKSdUuSOGLHIRFOP1scv6NAXIO9c1uOrCrzKvrEqqBZh9 xUWx62GuJ/rIx1HBwUM1Da7BEdW7+6RpH4uG4MKDWSWiUphgKatcS1Rb0s1HTH3wwju0 pVeQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jg+R5bWZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a5d4dcc000000b002c556a4f1casm2049107wru.42.2023.02.16.09.11.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 09:11:28 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/30] target/arm: Constify ID_PFR1 on user emulation Date: Thu, 16 Feb 2023 17:10:57 +0000 Message-Id: <20230216171123.2518285-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216171123.2518285-1-peter.maydell@linaro.org> References: <20230216171123.2518285-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-id: 20230206223502.25122-5-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index c62ed05c122..22670c20c00 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7021,6 +7021,7 @@ static void define_pmu_regs(ARMCPU *cpu) } } +#ifndef CONFIG_USER_ONLY /* * We don't know until after realize whether there's a GICv3 * attached, and that is what registers the gicv3 sysregs. @@ -7038,7 +7039,6 @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) return pfr1; } -#ifndef CONFIG_USER_ONLY static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu = env_archcpu(env); @@ -7998,8 +7998,16 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, .access = PL1_R, .type = ARM_CP_NO_RAW, .accessfn = access_aa32_tid3, +#ifdef CONFIG_USER_ONLY + .type = ARM_CP_CONST, + .resetvalue = cpu->isar.id_pfr1, +#else + .type = ARM_CP_NO_RAW, + .accessfn = access_aa32_tid3, .readfn = id_pfr1_read, - .writefn = arm_cp_write_ignore }, + .writefn = arm_cp_write_ignore +#endif + }, { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST, From patchwork Thu Feb 16 17:10:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 654058 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp86065wrc; Thu, 16 Feb 2023 09:14:43 -0800 (PST) X-Google-Smtp-Source: AK7set+4/B3iMvUMQP/QUj+KlZCYejH8z7REBCpcrhcE9EG1i5WHCAqoO6O/wpg77LjmOQDNHoen X-Received: by 2002:ac8:7d10:0:b0:3b9:b817:e9ae with SMTP id g16-20020ac87d10000000b003b9b817e9aemr11763280qtb.5.1676567683660; Thu, 16 Feb 2023 09:14:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676567683; cv=none; d=google.com; s=arc-20160816; b=OAAjAkXnpXTtH0vtGp3KpT5YcV0/1YMnf2iYNyBjnUHCSyWNwhMnbBx1hZStPwprjh tyhSLhYhit9O3CmJew/UyJWVY2vPItvaAkGAwzbGFamI66e707cy13AZaNmj77a7zFNB 2QKh8TtmEKjGtSl4VdfcVvj1gTEklN+BXAapJUCfJQ/jgfQrRaWbtVYD+DWmWtfQZH7O F2WYCqsrV6NmniCkvMlkPTJYFZh+fAI3VWNco5tgFvpiypysNFOW/D0apMyhQDpEn70t 5MH9O/qmYXm3iVYkoW8rOxXdxEgTUVrERc0qW9nNXmcUE1JoiaeA2iUIPV17Hv/hwrGn Aipw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0mZsyYHXMMzgbZQYO+cjM5qTlEPxz+umbuwXPDLbPoQ=; b=rnwVlSJs8zUjeLe0KzzmaF0fESJiR6cynrCpClDTj/GgmbygDs+zWO+gIKz4agLdL9 h4vHwIDVgrHLumRPqBku87mHjWmxyFsPt9rGfnj23gMxtyCqKC3sog+/Y7M+ZyjmWvgZ Kgd4q7r6a8aDsxQ97vQ445xbm1/qytp8qimMLEoo7j8XRo4woFAgSD+96faKU5t6lkK/ /rOcpuScmpXI5eHCEO2uY3m9rhK5Yc2b/G9K/2LFKw/kxDnPPQm9JuBe5cfoo6AGpACL ykNv8ecw8RJu+/Vz5gJPAmkoGvVxSE+s+bNRP1pwALKrZsMwCMdwAkMZZj0DV3x3CJTC fnpA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ia6tSNF2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a5d4dcc000000b002c556a4f1casm2049107wru.42.2023.02.16.09.11.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 09:11:29 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/30] target/arm: Convert CPUARMState::eabi to boolean Date: Thu, 16 Feb 2023 17:10:58 +0000 Message-Id: <20230216171123.2518285-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216171123.2518285-1-peter.maydell@linaro.org> References: <20230216171123.2518285-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20230206223502.25122-6-philmd@linaro.org Signed-off-by: Peter Maydell --- linux-user/user-internals.h | 2 +- target/arm/cpu.h | 2 +- linux-user/arm/cpu_loop.c | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/linux-user/user-internals.h b/linux-user/user-internals.h index 0280e76addd..3576da413f4 100644 --- a/linux-user/user-internals.h +++ b/linux-user/user-internals.h @@ -135,7 +135,7 @@ void print_termios(void *arg); #ifdef TARGET_ARM static inline int regpairs_aligned(CPUArchState *cpu_env, int num) { - return cpu_env->eabi == 1; + return cpu_env->eabi; } #elif defined(TARGET_MIPS) && defined(TARGET_ABI_MIPSO32) static inline int regpairs_aligned(CPUArchState *cpu_env, int num) { return 1; } diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7bc97fece97..05b9012cee9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -723,7 +723,7 @@ typedef struct CPUArchState { #if defined(CONFIG_USER_ONLY) /* For usermode syscall translation. */ - int eabi; + bool eabi; #endif struct CPUBreakpoint *cpu_breakpoint[16]; diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index c0790f3246b..a9924232578 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -356,7 +356,7 @@ void cpu_loop(CPUARMState *env) break; case EXCP_SWI: { - env->eabi = 1; + env->eabi = true; /* system call */ if (env->thumb) { /* Thumb is always EABI style with syscall number in r7 */ @@ -382,7 +382,7 @@ void cpu_loop(CPUARMState *env) * > 0xfffff and are handled below as out-of-range. */ n ^= ARM_SYSCALL_BASE; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a5d4dcc000000b002c556a4f1casm2049107wru.42.2023.02.16.09.11.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 09:11:30 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/30] target/arm: Avoid resetting CPUARMState::eabi field Date: Thu, 16 Feb 2023 17:10:59 +0000 Message-Id: <20230216171123.2518285-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216171123.2518285-1-peter.maydell@linaro.org> References: <20230216171123.2518285-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Although the 'eabi' field is only used in user emulation where CPU reset doesn't occur, it doesn't belong to the area to reset. Move it after the 'end_reset_fields' for consistency. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-id: 20230206223502.25122-7-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 05b9012cee9..1c1e0334f01 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -721,11 +721,6 @@ typedef struct CPUArchState { ARMVectorReg zarray[ARM_MAX_VQ * 16]; #endif -#if defined(CONFIG_USER_ONLY) - /* For usermode syscall translation. */ - bool eabi; -#endif - struct CPUBreakpoint *cpu_breakpoint[16]; struct CPUWatchpoint *cpu_watchpoint[16]; @@ -776,6 +771,10 @@ typedef struct CPUArchState { const struct arm_boot_info *boot_info; /* Store GICv3CPUState to access from this struct */ void *gicv3state; +#if defined(CONFIG_USER_ONLY) + /* For usermode syscall translation. */ + bool eabi; +#endif /* CONFIG_USER_ONLY */ #ifdef TARGET_TAGGED_ADDRESSES /* Linux syscall tagged address support */ From patchwork Thu Feb 16 17:11:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 654071 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp86643wrc; Thu, 16 Feb 2023 09:15:48 -0800 (PST) X-Google-Smtp-Source: AK7set+oiURgLH5EufNVZBy3fnu+z1XNpehbfRVvWBG3FO+3ltclNCwuCPFqrCcdCsm3hhkDGmBT X-Received: by 2002:ad4:5baa:0:b0:56f:225:8e2a with SMTP id 10-20020ad45baa000000b0056f02258e2amr2451333qvq.17.1676567748176; Thu, 16 Feb 2023 09:15:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676567748; cv=none; d=google.com; s=arc-20160816; b=itL/4Pg7Oec6KmanUETafAl7LXuLkjgLmcJ+5ujdYxY/vHS9/daZ7S5h5Phwh5chOW DiW1sLf6Gra4n7uELtjMp1E5bij2Tv3HVLMiyXm3oXlRgaXevCkA5GWJMGwAYwwMvs6i +q+qx3SuQAoSsJRUjTotEnXHWX5wXBRkPCwWGoyUXtsMSL+cLXRHRiljqFKqPwZ0VM/a cR5ktlwX4kfmYd5c+46Y+FGbohCFTLA7MoKismwDjNkv3RHW5QJB1uKV8TK4js2468za Yf1CvNNpgGkTO0QANfk6LrrCnO40v0nULpIHPlLDcUB9rj/52mesTyyFQpJdd5GIlKWs VQQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=yZdYj4xUNtAS17eIdljWMHqlEpUmYI5NCeKfPxqq7Ng=; b=uYUB8bRUwssX+0AU+oVDqocj98cfmBrifDiJhOQXOgJ1skarMvXV01b89GCg48tRod ekN6PpKktwhcqapUc3WnP/JO1C520kMs8sLhrtoIQyXTj5GUeWnQq471f0aB9qnP/G1z an8MIky8xKizJFgNQ+miTijG9z8WoT/0DjXkuNIks1SE0Nzq0/6L7t3bdX8Hcxjx7/Mu acfbTJSvjeXK8iw2hJqHLZSRDhV0UO1Tuf3PSDKniLH40gcLeT9hmL1uI0mS6jiPqZ2H gCkn2QB+yV0KwFBnhXyE4Xp785U3NYNYxcjGWfNcnOKN82y6APpS6vgKhWAWYv6fIwNj 7VYA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TpgL2bJz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a5d4dcc000000b002c556a4f1casm2049107wru.42.2023.02.16.09.11.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 09:11:30 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/30] target/arm: Restrict CPUARMState::gicv3state to sysemu Date: Thu, 16 Feb 2023 17:11:00 +0000 Message-Id: <20230216171123.2518285-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216171123.2518285-1-peter.maydell@linaro.org> References: <20230216171123.2518285-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-id: 20230206223502.25122-8-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1c1e0334f01..002082eb5b6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -769,9 +769,10 @@ typedef struct CPUArchState { void *nvic; const struct arm_boot_info *boot_info; +#if !defined(CONFIG_USER_ONLY) /* Store GICv3CPUState to access from this struct */ void *gicv3state; -#if defined(CONFIG_USER_ONLY) +#else /* CONFIG_USER_ONLY */ /* For usermode syscall translation. */ bool eabi; #endif /* CONFIG_USER_ONLY */ From patchwork Thu Feb 16 17:11:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 654054 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp85642wrc; Thu, 16 Feb 2023 09:13:54 -0800 (PST) X-Google-Smtp-Source: AK7set91vODG54mhFjN7ZI40Is8bNCjFanBS8kop+G6hCOC5eYtbPuyjl9ZJH6sigIwCoxvRo6OQ X-Received: by 2002:a05:6214:4108:b0:4c7:595c:9940 with SMTP id kc8-20020a056214410800b004c7595c9940mr12397528qvb.51.1676567634682; Thu, 16 Feb 2023 09:13:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676567634; cv=none; d=google.com; s=arc-20160816; b=FovJH8vuhRwR5LSsiD64PU/wl2P46/TIp7lVkWKBv33cp90b3ztNP0qQQYPCuyW5Q+ mAvd5tEypKqKreHKxnpPBoZJBJkaivHJ/AXRmIJMqscd1CdWrPtIhqQC4kV55XA3qXiP Qn59XK1TBRxURDuGQ1M9uWbDuEpidBM5biIOKesU+ZSTpC+X8HDsGpbhZUpkSWNQ+1QI ey9k1XhIs+H+K6pP8BH4bh2WLiceDH3hi5eOPQW6BeNwcWTg7mjkqE0xnJS/YCGQW/jw x9EfCpqscXm3Scr84CeSPsFF9x4ocWApzTBzSF1lRPO4BDuAXdRJ0/4qrwQyCG+dubjr S5Ag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1+Kck9JVYjKMa8PaarZ6RWpFOfo4WuN9uUAQ2s5nrFI=; b=zTrKUXDB4sxtylhy4VX4y850WsMZcWNttv89lh445ib0rgsYQb7F5b2K1KQLkL57Dl o5JnCBQjuRbt+SlGl84eAeBhh3cqv3wKz5a+9xPiWfjXrEbxFFd/K+QNEjwRXSOVnnr8 1GnKvPE6aPSOebsNyqFTeTPPI/6dPWgDqP2Mee9N22Sy7uSmOzfF1hU4/071j70s4UOX 7goVWA9FFF+c5Xwd8zRkU2XbuAj1fKwiV0p32a3h0i/dDsvPUNdkgjIm3+aX+VdmvsiE eiPh9pJN7JLQ1gVNj29kEQU3QYIUg3t1OzOeMowv77r9n2Ew2FyLIC9Z0O9AbEpJiGqX DZYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Gi+qmk5a; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a5d4dcc000000b002c556a4f1casm2049107wru.42.2023.02.16.09.11.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 09:11:31 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/30] target/arm: Restrict CPUARMState::arm_boot_info to sysemu Date: Thu, 16 Feb 2023 17:11:01 +0000 Message-Id: <20230216171123.2518285-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216171123.2518285-1-peter.maydell@linaro.org> References: <20230216171123.2518285-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-id: 20230206223502.25122-9-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 002082eb5b6..a574e85b769 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -768,8 +768,8 @@ typedef struct CPUArchState { } sau; void *nvic; - const struct arm_boot_info *boot_info; #if !defined(CONFIG_USER_ONLY) + const struct arm_boot_info *boot_info; /* Store GICv3CPUState to access from this struct */ void *gicv3state; #else /* CONFIG_USER_ONLY */ From patchwork Thu Feb 16 17:11:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 654045 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp84603wrc; Thu, 16 Feb 2023 09:12:06 -0800 (PST) X-Google-Smtp-Source: AK7set8Wif0MtkA/Ksq2ultHuTc1JKZC+5BHHc9E7+hodsEQ0Aj92ePQ5zPXlgH2v5SYpUmuXEQq X-Received: by 2002:a05:6214:d87:b0:56b:fc7c:e57c with SMTP id e7-20020a0562140d8700b0056bfc7ce57cmr10968138qve.51.1676567526191; Thu, 16 Feb 2023 09:12:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676567526; cv=none; d=google.com; s=arc-20160816; b=IjDYl7vMX5ZBu79w6917SonNaX6AFViODarkxqY8VmL2UE4ydP0cjuvw68MskKMTQ2 QBAYJBe9H+12hVxh+HUFnfzHF567mnf9MKX2KFgOhZnXqEbghdGs2IVr4Er1FJl1n+RK U0F5oZthplQ4nTWorlPw9Wh4XTIVsBMVQ6s+08m+ytprGVFqoCWyTBcUceRzycoPllH4 DSw3s5twyQLnGtQVJronfz8izIbpVdwLWwWCA5OMHCPX8mWYgkOZpOC42rCJB2jPghu6 1ZI3DdInA+SSpoO0obLiIo361ikxTXt+nJqesv0dFn1SLXlPoCDBH3cM4BJFEI2eImrd YLtA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=eFRMxmxSaJfBplZt4RLAoAfhh4Czqb3lB+D76vM9a7w=; b=zRwFXDCrrCO+SSSko1m/dsDg2YS+DB2O15F7wP9GPUVIThdL3BoFnTxBNY+GMi5Kqt jTvXhM9l1Su/DoywvkeoTZIfKxaM76vNZKaP1Eu1cnNERvVoQ9iDT9aG0rLB2i8JFICb TrB09pBMnh6sBjUosWT/+kCFf/EoAmhFoppfM5+7ND//4CzAg2sRuz3ZPrSBKsh8ONLW Wo9JGaO+8mfNyBb2f3GZNrYh30hWPxn9ZfuUJgafBFD+eoX2bZ9rNwO2KtVOEsOrfhax Uvuwd/FZl5SnoBObS8pJlWiSs7JI0FY3kKSKhIKFcM8d9hckWFDN1ihjrcVfK/xQ4Slo n2cA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WSAROooV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a5d4dcc000000b002c556a4f1casm2049107wru.42.2023.02.16.09.11.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 09:11:32 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/30] target/arm: Restrict CPUARMState::nvic to sysemu Date: Thu, 16 Feb 2023 17:11:02 +0000 Message-Id: <20230216171123.2518285-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216171123.2518285-1-peter.maydell@linaro.org> References: <20230216171123.2518285-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20230206223502.25122-10-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a574e85b769..01f9566a1b4 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -767,8 +767,8 @@ typedef struct CPUArchState { uint32_t ctrl; } sau; - void *nvic; #if !defined(CONFIG_USER_ONLY) + void *nvic; const struct arm_boot_info *boot_info; /* Store GICv3CPUState to access from this struct */ void *gicv3state; From patchwork Thu Feb 16 17:11:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 654049 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp84758wrc; Thu, 16 Feb 2023 09:12:21 -0800 (PST) X-Google-Smtp-Source: AK7set9bLbK4ptrhOu4uexq3uIB19Mcb6wJFeRusujOS+4zy2AgIjx3uJ/36UBg0ATwnZhWVfiR+ X-Received: by 2002:a05:622a:14cb:b0:3b9:a532:a1c with SMTP id u11-20020a05622a14cb00b003b9a5320a1cmr10790574qtx.25.1676567541810; Thu, 16 Feb 2023 09:12:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676567541; cv=none; d=google.com; s=arc-20160816; b=WzCKzjbzLNfNHL8gphV+Mgvbz1qY9ab6kOII72Nov8SLr/gVZfg9EDTMQdEufRTfIP s2jVfNzWETWv8PkxW2+he4fuVjcx+PGHd3g3kR8ovsGoITmNkXr4ohO3DrDstZRyOELt 13BLMIZTUH8EZap6IOR66V3bvKIv1+GZK8jsejqmjvI9ue9JvOf+J2ffpbcIeLg2T0qF uCcLotvCqFHcG/fe/4yEa4bqObs3rifRAIKbUJD7kqfWbejX9iofawar2vXdVsTwpXUy CNQ9DSM0X7l7e/N6QnWBptDs5TYm+Cmw58TyhP9I0h6yp8wAQFE9l6H2KirouLSKHy0B wSOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=CnzN2GsIWldMGo1Fxbr7+H5dNxnuKYX80l1WIoduxfk=; b=PfgXEkmxd2id0NJOpqpyMfm2SjX6nqv+0XIP5WHBMiaQ+70qQmbLCd7xEcs4yzfNc2 EKQ/eBwBsuq5uOQHvaazaHDQZvA4qRghPDRLMelQsYgQK8v/jqcZVk1rsrPGW+C14G21 +zsU/0VFfKV+E8Pb/nBMzye/qVmi0XfVL17I1XRE5HKbISG5FV7kvM48RtqJnYHS5G1g UpvAEYmY37oMtPFkPpgiPZVY5LDSxvD41mulv8nEnkSogJUz5HBBzU0l/NhW0lyvejvW qnjugnr0GKk7g9BV4RG05bODB8g9awL8ZpghIJbEnrL9cJBHpd/k3vye7HymDrvUQHQg oE7A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fjApAMic; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a5d4dcc000000b002c556a4f1casm2049107wru.42.2023.02.16.09.11.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 09:11:33 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/30] target/arm: Store CPUARMState::nvic as NVICState* Date: Thu, 16 Feb 2023 17:11:03 +0000 Message-Id: <20230216171123.2518285-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216171123.2518285-1-peter.maydell@linaro.org> References: <20230216171123.2518285-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé There is no point in using a void pointer to access the NVIC. Use the real type to avoid casting it while debugging. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20230206223502.25122-11-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 46 ++++++++++++++++++++++--------------------- hw/intc/armv7m_nvic.c | 38 ++++++++++++----------------------- target/arm/cpu.c | 1 + target/arm/m_helper.c | 2 +- 4 files changed, 39 insertions(+), 48 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 01f9566a1b4..9a80819d8d9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -227,6 +227,8 @@ typedef struct CPUARMTBFlags { typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; +typedef struct NVICState NVICState; + typedef struct CPUArchState { /* Regs for current mode. */ uint32_t regs[16]; @@ -768,7 +770,7 @@ typedef struct CPUArchState { } sau; #if !defined(CONFIG_USER_ONLY) - void *nvic; + NVICState *nvic; const struct arm_boot_info *boot_info; /* Store GICv3CPUState to access from this struct */ void *gicv3state; @@ -2559,16 +2561,16 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, /* Interface between CPU and Interrupt controller. */ #ifndef CONFIG_USER_ONLY -bool armv7m_nvic_can_take_pending_exception(void *opaque); +bool armv7m_nvic_can_take_pending_exception(NVICState *s); #else -static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) +static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s) { return true; } #endif /** * armv7m_nvic_set_pending: mark the specified exception as pending - * @opaque: the NVIC + * @s: the NVIC * @irq: the exception number to mark pending * @secure: false for non-banked exceptions or for the nonsecure * version of a banked exception, true for the secure version of a banked @@ -2578,10 +2580,10 @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) * if @secure is true and @irq does not specify one of the fixed set * of architecturally banked exceptions. */ -void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure); /** * armv7m_nvic_set_pending_derived: mark this derived exception as pending - * @opaque: the NVIC + * @s: the NVIC * @irq: the exception number to mark pending * @secure: false for non-banked exceptions or for the nonsecure * version of a banked exception, true for the secure version of a banked @@ -2591,10 +2593,10 @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); * exceptions (exceptions generated in the course of trying to take * a different exception). */ -void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure); /** * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending - * @opaque: the NVIC + * @s: the NVIC * @irq: the exception number to mark pending * @secure: false for non-banked exceptions or for the nonsecure * version of a banked exception, true for the secure version of a banked @@ -2603,11 +2605,11 @@ void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); * Similar to armv7m_nvic_set_pending(), but specifically for exceptions * generated in the course of lazy stacking of FP registers. */ -void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure); /** * armv7m_nvic_get_pending_irq_info: return highest priority pending * exception, and whether it targets Secure state - * @opaque: the NVIC + * @s: the NVIC * @pirq: set to pending exception number * @ptargets_secure: set to whether pending exception targets Secure * @@ -2617,20 +2619,20 @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); * to true if the current highest priority pending exception should * be taken to Secure state, false for NS. */ -void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, +void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq, bool *ptargets_secure); /** * armv7m_nvic_acknowledge_irq: make highest priority pending exception active - * @opaque: the NVIC + * @s: the NVIC * * Move the current highest priority pending exception from the pending * state to the active state, and update v7m.exception to indicate that * it is the exception currently being handled. */ -void armv7m_nvic_acknowledge_irq(void *opaque); +void armv7m_nvic_acknowledge_irq(NVICState *s); /** * armv7m_nvic_complete_irq: complete specified interrupt or exception - * @opaque: the NVIC + * @s: the NVIC * @irq: the exception number to complete * @secure: true if this exception was secure * @@ -2639,10 +2641,10 @@ void armv7m_nvic_acknowledge_irq(void *opaque); * 0 if there is still an irq active after this one was completed * (Ignoring -1, this is the same as the RETTOBASE value before completion.) */ -int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure); /** * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) - * @opaque: the NVIC + * @s: the NVIC * @irq: the exception number to mark pending * @secure: false for non-banked exceptions or for the nonsecure * version of a banked exception, true for the secure version of a banked @@ -2653,28 +2655,28 @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); * interrupt the current execution priority. This controls whether the * RDY bit for it in the FPCCR is set. */ -bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure); /** * armv7m_nvic_raw_execution_priority: return the raw execution priority - * @opaque: the NVIC + * @s: the NVIC * * Returns: the raw execution priority as defined by the v8M architecture. * This is the execution priority minus the effects of AIRCR.PRIS, * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. * (v8M ARM ARM I_PKLD.) */ -int armv7m_nvic_raw_execution_priority(void *opaque); +int armv7m_nvic_raw_execution_priority(NVICState *s); /** * armv7m_nvic_neg_prio_requested: return true if the requested execution * priority is negative for the specified security state. - * @opaque: the NVIC + * @s: the NVIC * @secure: the security state to test * This corresponds to the pseudocode IsReqExecPriNeg(). */ #ifndef CONFIG_USER_ONLY -bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure); #else -static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) +static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) { return false; } diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 1f7763964c3..e54553283f4 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -389,7 +389,7 @@ static inline int nvic_exec_prio(NVICState *s) return MIN(running, s->exception_prio); } -bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) { /* Return true if the requested execution priority is negative * for the specified security state, ie that security state @@ -399,8 +399,6 @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) * mean we don't allow FAULTMASK_NS to actually make the execution * priority negative). Compare pseudocode IsReqExcPriNeg(). */ - NVICState *s = opaque; - if (s->cpu->env.v7m.faultmask[secure]) { return true; } @@ -418,17 +416,13 @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) return false; } -bool armv7m_nvic_can_take_pending_exception(void *opaque) +bool armv7m_nvic_can_take_pending_exception(NVICState *s) { - NVICState *s = opaque; - return nvic_exec_prio(s) > nvic_pending_prio(s); } -int armv7m_nvic_raw_execution_priority(void *opaque) +int armv7m_nvic_raw_execution_priority(NVICState *s) { - NVICState *s = opaque; - return s->exception_prio; } @@ -506,9 +500,8 @@ static void nvic_irq_update(NVICState *s) * if @secure is true and @irq does not specify one of the fixed set * of architecturally banked exceptions. */ -static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure) +static void armv7m_nvic_clear_pending(NVICState *s, int irq, bool secure) { - NVICState *s = (NVICState *)opaque; VecInfo *vec; assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); @@ -666,17 +659,17 @@ static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure, } } -void armv7m_nvic_set_pending(void *opaque, int irq, bool secure) +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure) { - do_armv7m_nvic_set_pending(opaque, irq, secure, false); + do_armv7m_nvic_set_pending(s, irq, secure, false); } -void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure) +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure) { - do_armv7m_nvic_set_pending(opaque, irq, secure, true); + do_armv7m_nvic_set_pending(s, irq, secure, true); } -void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure) +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure) { /* * Pend an exception during lazy FP stacking. This differs @@ -684,7 +677,6 @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure) * whether we should escalate depends on the saved context * in the FPCCR register, not on the current state of the CPU/NVIC. */ - NVICState *s = (NVICState *)opaque; bool banked = exc_is_banked(irq); VecInfo *vec; bool targets_secure; @@ -773,9 +765,8 @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure) } /* Make pending IRQ active. */ -void armv7m_nvic_acknowledge_irq(void *opaque) +void armv7m_nvic_acknowledge_irq(NVICState *s) { - NVICState *s = (NVICState *)opaque; CPUARMState *env = &s->cpu->env; const int pending = s->vectpending; const int running = nvic_exec_prio(s); @@ -814,10 +805,9 @@ static bool vectpending_targets_secure(NVICState *s) exc_targets_secure(s, s->vectpending); } -void armv7m_nvic_get_pending_irq_info(void *opaque, +void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq, bool *ptargets_secure) { - NVICState *s = (NVICState *)opaque; const int pending = s->vectpending; bool targets_secure; @@ -831,9 +821,8 @@ void armv7m_nvic_get_pending_irq_info(void *opaque, *pirq = pending; } -int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure) +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure) { - NVICState *s = (NVICState *)opaque; VecInfo *vec = NULL; int ret = 0; @@ -915,7 +904,7 @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure) return ret; } -bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure) { /* * Return whether an exception is "ready", i.e. it is enabled and is @@ -926,7 +915,6 @@ bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) * for non-banked exceptions secure is always false; for banked exceptions * it indicates which of the exceptions is required. */ - NVICState *s = (NVICState *)opaque; bool banked = exc_is_banked(irq); VecInfo *vec; int running = nvic_exec_prio(s); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5f63316dbf2..b3a2275b087 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -36,6 +36,7 @@ #if !defined(CONFIG_USER_ONLY) #include "hw/loader.h" #include "hw/boards.h" +#include "hw/intc/armv7m_nvic.h" #endif #include "sysemu/tcg.h" #include "sysemu/qtest.h" diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index b4964dca8a8..25de64c43c9 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -1015,7 +1015,7 @@ static void v7m_update_fpccr(CPUARMState *env, uint32_t frameptr, * that we will need later in order to do lazy FP reg stacking. */ bool is_secure = env->v7m.secure; - void *nvic = env->nvic; + NVICState *nvic = env->nvic; /* * Some bits are unbanked and live always in fpccr[M_REG_S]; some bits * are banked and we want to update the bit in the bank for the From patchwork Thu Feb 16 17:11:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 654075 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp86828wrc; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a5d4dcc000000b002c556a4f1casm2049107wru.42.2023.02.16.09.11.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 09:11:34 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/30] target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h' Date: Thu, 16 Feb 2023 17:11:04 +0000 Message-Id: <20230216171123.2518285-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216171123.2518285-1-peter.maydell@linaro.org> References: <20230216171123.2518285-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé While dozens of files include "cpu.h", only 3 files require these NVIC helper declarations. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-id: 20230206223502.25122-12-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/intc/armv7m_nvic.h | 123 ++++++++++++++++++++++++++++++++++ target/arm/cpu.h | 123 ---------------------------------- target/arm/cpu.c | 4 +- target/arm/cpu_tcg.c | 3 + target/arm/m_helper.c | 3 + 5 files changed, 132 insertions(+), 124 deletions(-) diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index 07f9c21a5f3..1ca262fbf82 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -83,4 +83,127 @@ struct NVICState { qemu_irq sysresetreq; }; +/* Interface between CPU and Interrupt controller. */ +/** + * armv7m_nvic_set_pending: mark the specified exception as pending + * @s: the NVIC + * @irq: the exception number to mark pending + * @secure: false for non-banked exceptions or for the nonsecure + * version of a banked exception, true for the secure version of a banked + * exception. + * + * Marks the specified exception as pending. Note that we will assert() + * if @secure is true and @irq does not specify one of the fixed set + * of architecturally banked exceptions. + */ +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure); +/** + * armv7m_nvic_set_pending_derived: mark this derived exception as pending + * @s: the NVIC + * @irq: the exception number to mark pending + * @secure: false for non-banked exceptions or for the nonsecure + * version of a banked exception, true for the secure version of a banked + * exception. + * + * Similar to armv7m_nvic_set_pending(), but specifically for derived + * exceptions (exceptions generated in the course of trying to take + * a different exception). + */ +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure); +/** + * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending + * @s: the NVIC + * @irq: the exception number to mark pending + * @secure: false for non-banked exceptions or for the nonsecure + * version of a banked exception, true for the secure version of a banked + * exception. + * + * Similar to armv7m_nvic_set_pending(), but specifically for exceptions + * generated in the course of lazy stacking of FP registers. + */ +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure); +/** + * armv7m_nvic_get_pending_irq_info: return highest priority pending + * exception, and whether it targets Secure state + * @s: the NVIC + * @pirq: set to pending exception number + * @ptargets_secure: set to whether pending exception targets Secure + * + * This function writes the number of the highest priority pending + * exception (the one which would be made active by + * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure + * to true if the current highest priority pending exception should + * be taken to Secure state, false for NS. + */ +void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq, + bool *ptargets_secure); +/** + * armv7m_nvic_acknowledge_irq: make highest priority pending exception active + * @s: the NVIC + * + * Move the current highest priority pending exception from the pending + * state to the active state, and update v7m.exception to indicate that + * it is the exception currently being handled. + */ +void armv7m_nvic_acknowledge_irq(NVICState *s); +/** + * armv7m_nvic_complete_irq: complete specified interrupt or exception + * @s: the NVIC + * @irq: the exception number to complete + * @secure: true if this exception was secure + * + * Returns: -1 if the irq was not active + * 1 if completing this irq brought us back to base (no active irqs) + * 0 if there is still an irq active after this one was completed + * (Ignoring -1, this is the same as the RETTOBASE value before completion.) + */ +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure); +/** + * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) + * @s: the NVIC + * @irq: the exception number to mark pending + * @secure: false for non-banked exceptions or for the nonsecure + * version of a banked exception, true for the secure version of a banked + * exception. + * + * Return whether an exception is "ready", i.e. whether the exception is + * enabled and is configured at a priority which would allow it to + * interrupt the current execution priority. This controls whether the + * RDY bit for it in the FPCCR is set. + */ +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure); +/** + * armv7m_nvic_raw_execution_priority: return the raw execution priority + * @s: the NVIC + * + * Returns: the raw execution priority as defined by the v8M architecture. + * This is the execution priority minus the effects of AIRCR.PRIS, + * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. + * (v8M ARM ARM I_PKLD.) + */ +int armv7m_nvic_raw_execution_priority(NVICState *s); +/** + * armv7m_nvic_neg_prio_requested: return true if the requested execution + * priority is negative for the specified security state. + * @s: the NVIC + * @secure: the security state to test + * This corresponds to the pseudocode IsReqExecPriNeg(). + */ +#ifndef CONFIG_USER_ONLY +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure); +#else +static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) +{ + return false; +} +#endif +#ifndef CONFIG_USER_ONLY +bool armv7m_nvic_can_take_pending_exception(NVICState *s); +#else +static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s) +{ + return true; +} +#endif + #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9a80819d8d9..d623afe84af 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2559,129 +2559,6 @@ void arm_cpu_list(void); uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, uint32_t cur_el, bool secure); -/* Interface between CPU and Interrupt controller. */ -#ifndef CONFIG_USER_ONLY -bool armv7m_nvic_can_take_pending_exception(NVICState *s); -#else -static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s) -{ - return true; -} -#endif -/** - * armv7m_nvic_set_pending: mark the specified exception as pending - * @s: the NVIC - * @irq: the exception number to mark pending - * @secure: false for non-banked exceptions or for the nonsecure - * version of a banked exception, true for the secure version of a banked - * exception. - * - * Marks the specified exception as pending. Note that we will assert() - * if @secure is true and @irq does not specify one of the fixed set - * of architecturally banked exceptions. - */ -void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure); -/** - * armv7m_nvic_set_pending_derived: mark this derived exception as pending - * @s: the NVIC - * @irq: the exception number to mark pending - * @secure: false for non-banked exceptions or for the nonsecure - * version of a banked exception, true for the secure version of a banked - * exception. - * - * Similar to armv7m_nvic_set_pending(), but specifically for derived - * exceptions (exceptions generated in the course of trying to take - * a different exception). - */ -void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure); -/** - * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending - * @s: the NVIC - * @irq: the exception number to mark pending - * @secure: false for non-banked exceptions or for the nonsecure - * version of a banked exception, true for the secure version of a banked - * exception. - * - * Similar to armv7m_nvic_set_pending(), but specifically for exceptions - * generated in the course of lazy stacking of FP registers. - */ -void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure); -/** - * armv7m_nvic_get_pending_irq_info: return highest priority pending - * exception, and whether it targets Secure state - * @s: the NVIC - * @pirq: set to pending exception number - * @ptargets_secure: set to whether pending exception targets Secure - * - * This function writes the number of the highest priority pending - * exception (the one which would be made active by - * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure - * to true if the current highest priority pending exception should - * be taken to Secure state, false for NS. - */ -void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq, - bool *ptargets_secure); -/** - * armv7m_nvic_acknowledge_irq: make highest priority pending exception active - * @s: the NVIC - * - * Move the current highest priority pending exception from the pending - * state to the active state, and update v7m.exception to indicate that - * it is the exception currently being handled. - */ -void armv7m_nvic_acknowledge_irq(NVICState *s); -/** - * armv7m_nvic_complete_irq: complete specified interrupt or exception - * @s: the NVIC - * @irq: the exception number to complete - * @secure: true if this exception was secure - * - * Returns: -1 if the irq was not active - * 1 if completing this irq brought us back to base (no active irqs) - * 0 if there is still an irq active after this one was completed - * (Ignoring -1, this is the same as the RETTOBASE value before completion.) - */ -int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure); -/** - * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) - * @s: the NVIC - * @irq: the exception number to mark pending - * @secure: false for non-banked exceptions or for the nonsecure - * version of a banked exception, true for the secure version of a banked - * exception. - * - * Return whether an exception is "ready", i.e. whether the exception is - * enabled and is configured at a priority which would allow it to - * interrupt the current execution priority. This controls whether the - * RDY bit for it in the FPCCR is set. - */ -bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure); -/** - * armv7m_nvic_raw_execution_priority: return the raw execution priority - * @s: the NVIC - * - * Returns: the raw execution priority as defined by the v8M architecture. - * This is the execution priority minus the effects of AIRCR.PRIS, - * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. - * (v8M ARM ARM I_PKLD.) - */ -int armv7m_nvic_raw_execution_priority(NVICState *s); -/** - * armv7m_nvic_neg_prio_requested: return true if the requested execution - * priority is negative for the specified security state. - * @s: the NVIC - * @secure: the security state to test - * This corresponds to the pseudocode IsReqExecPriNeg(). - */ -#ifndef CONFIG_USER_ONLY -bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure); -#else -static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) -{ - return false; -} -#endif - /* Interface for defining coprocessor registers. * Registers are defined in tables of arm_cp_reginfo structs * which are passed to define_arm_cp_regs(). diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b3a2275b087..876ab8f3bf8 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -36,8 +36,10 @@ #if !defined(CONFIG_USER_ONLY) #include "hw/loader.h" #include "hw/boards.h" +#ifdef CONFIG_TCG #include "hw/intc/armv7m_nvic.h" -#endif +#endif /* CONFIG_TCG */ +#endif /* !CONFIG_USER_ONLY */ #include "sysemu/tcg.h" #include "sysemu/qtest.h" #include "sysemu/hw_accel.h" diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index ccde5080eb7..df0c45e523b 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -19,6 +19,9 @@ #include "hw/boards.h" #endif #include "cpregs.h" +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) +#include "hw/intc/armv7m_nvic.h" +#endif /* Share AArch32 -cpu max features with AArch64. */ diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 25de64c43c9..f94e87e7289 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -18,6 +18,9 @@ #include "exec/cpu_ldst.h" #include "semihosting/common-semi.h" #endif +#if !defined(CONFIG_USER_ONLY) +#include "hw/intc/armv7m_nvic.h" +#endif static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, uint32_t reg, uint32_t val) From patchwork Thu Feb 16 17:11:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 654057 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp86058wrc; Thu, 16 Feb 2023 09:14:43 -0800 (PST) X-Google-Smtp-Source: AK7set9+w+zZ8iL1g06UHNNkvqiW/BhtEao4dgIB7bS3m3WSP/eLVh6yWHrYqJpqNerG/ldxkdlB X-Received: by 2002:ac8:7e94:0:b0:3b9:a4c4:ca09 with SMTP id w20-20020ac87e94000000b003b9a4c4ca09mr12130293qtj.10.1676567682916; Thu, 16 Feb 2023 09:14:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676567682; cv=none; d=google.com; s=arc-20160816; b=Zz/6TkVAylvd1NdG6ewAUvIiAuOn5Bw1GQBf+iTLBHgt5UST8m+a+25gPl4cxiLjj7 oos+eaNvAQj3VdsQ0SIBzGvmQoMvkar5IrgS0pqQjDqpo+NWo5Mfy4Pt23srK24IYOl7 rnPqVqxFqiKqAbSel9gQWxFM1QNh7bUyqJ2BDUgDxU7vGZ0I8jR8WEmqX8sJfrVWGTY2 BLa8drdqDYZap4FuZrecLVIscYaeAq8iOIDyMZ+gFTLdT+IcqEETll2bv5qNz5+lGTYS T5WdcL74yrGcWLkQHBCwaxLbUKj4/3vFbHKCQUwEhbDT/JJb6Im2EaLCz96ldh+Z22Vy wFOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=I41Rq1BCBKNBN1fSGYnJWT1+PVJR4PoFDqsrj7M3m7k=; b=DJKSm6edQyMDKlyQJgY3xm7wG0HPtc2fOp/r0bMOIKGW/MU3BqcNhBUa5DvLF6nzAt mkxqB74sXiBSYAhNJyWTtleZw4Zh7ikCbLnmpa9FZ+Woc4Ngt8ukalB+PMOEQjG90H3W 3zeff8o2CMPVTY7KDn0Uic7fQ3mQ5PsFk9goS1fnaTBKCcHd2RDHXhJypL1zIwTn7swO ZexIr11f1h4jHeE072PEPGH46UJKrC4ThN3BQWJzslScanN19cABiM40xF0dFNuHtbb0 ADEPF3ygKtwpTaYo28UViRa3+W8CnSb/k4y/gqyaRRpWoHB6CqTooo8MskkS2/eQkgI7 F40w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bJ45PsBV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a5d4dcc000000b002c556a4f1casm2049107wru.42.2023.02.16.09.11.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 09:11:35 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/30] tests/avocado: retire the Aarch64 TCG tests from boot_linux.py Date: Thu, 16 Feb 2023 17:11:05 +0000 Message-Id: <20230216171123.2518285-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216171123.2518285-1-peter.maydell@linaro.org> References: <20230216171123.2518285-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Alex Bennée The two TCG tests for GICv2 and GICv3 are very heavy weight distros that take a long time to boot up, especially for an --enable-debug build. The total code coverage they give is: Overall coverage rate: lines......: 11.2% (59584 of 530123 lines) functions..: 15.0% (7436 of 49443 functions) branches...: 6.3% (19273 of 303933 branches) We already get pretty close to that with the machine_aarch64_virt tests which only does one full boot (~120s vs ~600s) of alpine. We expand the kernel+initrd boot (~8s) to test both GICs and also add an RNG device and a block device to generate a few IRQs and exercise the storage layer. With that we get to a coverage of: Overall coverage rate: lines......: 11.0% (58121 of 530123 lines) functions..: 14.9% (7343 of 49443 functions) branches...: 6.0% (18269 of 303933 branches) which I feel is close enough given the massive time saving. If we want to target any more sub-systems we can use lighter weight more directed tests. Signed-off-by: Alex Bennée Reviewed-by: Fabiano Rosas Acked-by: Richard Henderson Message-id: 20230203181632.2919715-1-alex.bennee@linaro.org Cc: Peter Maydell Signed-off-by: Peter Maydell --- tests/avocado/boot_linux.py | 48 ++++---------------- tests/avocado/machine_aarch64_virt.py | 63 ++++++++++++++++++++++++--- 2 files changed, 65 insertions(+), 46 deletions(-) diff --git a/tests/avocado/boot_linux.py b/tests/avocado/boot_linux.py index b3e58fa3093..fe0bb180d90 100644 --- a/tests/avocado/boot_linux.py +++ b/tests/avocado/boot_linux.py @@ -58,52 +58,16 @@ def test_pc_q35_kvm(self): self.launch_and_wait(set_up_ssh_connection=False) -# For Aarch64 we only boot KVM tests in CI as the TCG tests are very -# heavyweight. There are lighter weight distros which we use in the -# machine_aarch64_virt.py tests. +# For Aarch64 we only boot KVM tests in CI as booting the current +# Fedora OS in TCG tests is very heavyweight. There are lighter weight +# distros which we use in the machine_aarch64_virt.py tests. class BootLinuxAarch64(LinuxTest): """ :avocado: tags=arch:aarch64 :avocado: tags=machine:virt - :avocado: tags=machine:gic-version=2 """ timeout = 720 - def add_common_args(self): - self.vm.add_args('-bios', - os.path.join(BUILD_DIR, 'pc-bios', - 'edk2-aarch64-code.fd')) - self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0') - self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom') - - @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab') - def test_fedora_cloud_tcg_gicv2(self): - """ - :avocado: tags=accel:tcg - :avocado: tags=cpu:max - :avocado: tags=device:gicv2 - """ - self.require_accelerator("tcg") - self.vm.add_args("-accel", "tcg") - self.vm.add_args("-cpu", "max,lpa2=off") - self.vm.add_args("-machine", "virt,gic-version=2") - self.add_common_args() - self.launch_and_wait(set_up_ssh_connection=False) - - @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab') - def test_fedora_cloud_tcg_gicv3(self): - """ - :avocado: tags=accel:tcg - :avocado: tags=cpu:max - :avocado: tags=device:gicv3 - """ - self.require_accelerator("tcg") - self.vm.add_args("-accel", "tcg") - self.vm.add_args("-cpu", "max,lpa2=off") - self.vm.add_args("-machine", "virt,gic-version=3") - self.add_common_args() - self.launch_and_wait(set_up_ssh_connection=False) - def test_virt_kvm(self): """ :avocado: tags=accel:kvm @@ -112,7 +76,11 @@ def test_virt_kvm(self): self.require_accelerator("kvm") self.vm.add_args("-accel", "kvm") self.vm.add_args("-machine", "virt,gic-version=host") - self.add_common_args() + self.vm.add_args('-bios', + os.path.join(BUILD_DIR, 'pc-bios', + 'edk2-aarch64-code.fd')) + self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0') + self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom') self.launch_and_wait(set_up_ssh_connection=False) diff --git a/tests/avocado/machine_aarch64_virt.py b/tests/avocado/machine_aarch64_virt.py index c2b2ba2cf87..25dab8dc00a 100644 --- a/tests/avocado/machine_aarch64_virt.py +++ b/tests/avocado/machine_aarch64_virt.py @@ -10,11 +10,14 @@ import time import os +import logging from avocado_qemu import QemuSystemTest from avocado_qemu import wait_for_console_pattern from avocado_qemu import exec_command from avocado_qemu import BUILD_DIR +from avocado.utils import process +from avocado.utils.path import find_command class Aarch64VirtMachine(QemuSystemTest): KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 ' @@ -65,16 +68,15 @@ def test_alpine_virt_tcg_gic_max(self): self.wait_for_console_pattern('Welcome to Alpine Linux 3.16') - def test_aarch64_virt(self): + def common_aarch64_virt(self, machine): """ - :avocado: tags=arch:aarch64 - :avocado: tags=machine:virt - :avocado: tags=accel:tcg - :avocado: tags=cpu:max + Common code to launch basic virt machine with kernel+initrd + and a scratch disk. """ + logger = logging.getLogger('aarch64_virt') + kernel_url = ('https://fileserver.linaro.org/s/' 'z6B2ARM7DQT3HWN/download') - kernel_hash = 'ed11daab50c151dde0e1e9c9cb8b2d9bd3215347' kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash) @@ -83,13 +85,62 @@ def test_aarch64_virt(self): 'console=ttyAMA0') self.require_accelerator("tcg") self.vm.add_args('-cpu', 'max,pauth-impdef=on', + '-machine', machine, '-accel', 'tcg', '-kernel', kernel_path, '-append', kernel_command_line) + + # A RNG offers an easy way to generate a few IRQs + self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0') + self.vm.add_args('-object', + 'rng-random,id=rng0,filename=/dev/urandom') + + # Also add a scratch block device + logger.info('creating scratch qcow2 image') + image_path = os.path.join(self.workdir, 'scratch.qcow2') + qemu_img = os.path.join(BUILD_DIR, 'qemu-img') + if not os.path.exists(qemu_img): + qemu_img = find_command('qemu-img', False) + if qemu_img is False: + self.cancel('Could not find "qemu-img", which is required to ' + 'create the temporary qcow2 image') + cmd = '%s create -f qcow2 %s 8M' % (qemu_img, image_path) + process.run(cmd) + + # Add the device + self.vm.add_args('-blockdev', + f"driver=qcow2,file.driver=file,file.filename={image_path},node-name=scratch") + self.vm.add_args('-device', + 'virtio-blk-device,drive=scratch') + self.vm.launch() self.wait_for_console_pattern('Welcome to Buildroot') time.sleep(0.1) exec_command(self, 'root') time.sleep(0.1) + exec_command(self, 'dd if=/dev/hwrng of=/dev/vda bs=512 count=4') + time.sleep(0.1) + exec_command(self, 'md5sum /dev/vda') + time.sleep(0.1) + exec_command(self, 'cat /proc/interrupts') + time.sleep(0.1) exec_command(self, 'cat /proc/self/maps') time.sleep(0.1) + + def test_aarch64_virt_gicv3(self): + """ + :avocado: tags=arch:aarch64 + :avocado: tags=machine:virt + :avocado: tags=accel:tcg + :avocado: tags=cpu:max + """ + self.common_aarch64_virt("virt,gic_version=3") + + def test_aarch64_virt_gicv2(self): + """ + :avocado: tags=arch:aarch64 + :avocado: tags=machine:virt + :avocado: tags=accel:tcg + :avocado: tags=cpu:max + """ + self.common_aarch64_virt("virt,gic-version=2") From patchwork Thu Feb 16 17:11:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 654070 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp86631wrc; Thu, 16 Feb 2023 09:15:47 -0800 (PST) X-Google-Smtp-Source: AK7set9bD6JU+iQiMKibv+ecFi1cCtTlvEw5ivLYcDEbIopUzKkyr54k7L0ufsZXpE0oQ3PsY6o0 X-Received: by 2002:ac8:570f:0:b0:3b9:abfb:61cd with SMTP id 15-20020ac8570f000000b003b9abfb61cdmr10956330qtw.26.1676567746974; Thu, 16 Feb 2023 09:15:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676567746; cv=none; d=google.com; s=arc-20160816; b=qTYjaNCT7OdfTGEMhAUyF0mfzoGpY+NjHc4Cop1ZiIiEzh9GLUmrBe2wbHF2B4UJuJ tWBUMcQzWEGmQ7UPMd1WTURCMM0OIVEDTuh4RXOERWPmILiiDcZDOuz0Djah4X0KDGo4 jXwFt//EdwEsb/5JmnGzyQ12KroZ1ZKwB9sFd3AC7rWUieLGl5KzDhe7hyNBTP7UvCXo tHRkhFNRSF/JohVMpTbumWi8KSC06vjr2XzIqjv1PXnli7nk9rTfnUW8pFsE8mrqVH3+ zcV2VSRs4/iRX3F0uZQY1JVauNeDdUGldqAj4349qWE5TGec5/bhnYqPtXULrEQkLdL7 ERpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=if/qVtarW27gDMcczuPNTXDooSW2u0gTRRM5vrJgeIM=; b=yxxfMm00OPu+abyEmGsSSXf69CNEvpvgulsgwpfaNMfd7/OLJ+7q0OQqMCp3FilgZZ op2iGTK40PCrbGhiK/UI+pmK/FkmNf0cCXODZnk+csaQyRUyLlamL+Apk+oVMRBowuBJ 4U8RKeUKtI33s81unUf9oK+G7JrlpnScZCK+mCmkAzDE2qjjCg9pgXPJw0HSk6BV2Zbk nMdfdCXIIZAfhDoNksbDJmFhX0iUvOmzT9VExOTcbcCdFT6ZvZkBVtvGuLCbOq7YfhQ+ 2xuekck1c4GTBTFLTgTHs7EArne1xhdncZki3vqNMSwVickE8nSRWxruTdbJxzzX+tew whrg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UIKX+HkT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a5d4dcc000000b002c556a4f1casm2049107wru.42.2023.02.16.09.11.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 09:11:35 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/30] hw/arm/smmuv3: Add GBPA register Date: Thu, 16 Feb 2023 17:11:06 +0000 Message-Id: <20230216171123.2518285-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216171123.2518285-1-peter.maydell@linaro.org> References: <20230216171123.2518285-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Mostafa Saleh GBPA register can be used to globally abort all transactions. It is described in the SMMU manual in "6.3.14 SMMU_GBPA". ABORT reset value is IMPLEMENTATION DEFINED, it is chosen to be zero(Do not abort incoming transactions). Other fields have default values of Use Incoming. If UPDATE is not set, the write is ignored. This is the only permitted behavior in SMMUv3.2 and later.(6.3.14.1 Update procedure) As this patch adds a new state to the SMMU (GBPA), it is added in a new subsection for forward migration compatibility. GBPA is only migrated if its value is different from the reset value. It does this to be backward migration compatible if SW didn't write the register. Signed-off-by: Mostafa Saleh Reviewed-by: Richard Henderson Reviewed-by: Eric Auger Message-id: 20230214094009.2445653-1-smostafa@google.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/smmuv3-internal.h | 7 +++++++ include/hw/arm/smmuv3.h | 1 + hw/arm/smmuv3.c | 43 +++++++++++++++++++++++++++++++++++++++- 3 files changed, 50 insertions(+), 1 deletion(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index bce161870f6..e8f0ebf25e3 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -79,6 +79,13 @@ REG32(CR0ACK, 0x24) REG32(CR1, 0x28) REG32(CR2, 0x2c) REG32(STATUSR, 0x40) +REG32(GBPA, 0x44) + FIELD(GBPA, ABORT, 20, 1) + FIELD(GBPA, UPDATE, 31, 1) + +/* Use incoming. */ +#define SMMU_GBPA_RESET_VAL 0x1000 + REG32(IRQ_CTRL, 0x50) FIELD(IRQ_CTRL, GERROR_IRQEN, 0, 1) FIELD(IRQ_CTRL, PRI_IRQEN, 1, 1) diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index b6dd0875264..a0c026402e1 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -45,6 +45,7 @@ struct SMMUv3State { uint32_t cr[3]; uint32_t cr0ack; uint32_t statusr; + uint32_t gbpa; uint32_t irq_ctrl; uint32_t gerror; uint32_t gerrorn; diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 955b89c8d59..270c80b665f 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -285,6 +285,7 @@ static void smmuv3_init_regs(SMMUv3State *s) s->gerror = 0; s->gerrorn = 0; s->statusr = 0; + s->gbpa = SMMU_GBPA_RESET_VAL; } static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf, @@ -659,7 +660,11 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, qemu_mutex_lock(&s->mutex); if (!smmu_enabled(s)) { - status = SMMU_TRANS_DISABLE; + if (FIELD_EX32(s->gbpa, GBPA, ABORT)) { + status = SMMU_TRANS_ABORT; + } else { + status = SMMU_TRANS_DISABLE; + } goto epilogue; } @@ -1170,6 +1175,16 @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset, case A_GERROR_IRQ_CFG2: s->gerror_irq_cfg2 = data; return MEMTX_OK; + case A_GBPA: + /* + * If UPDATE is not set, the write is ignored. This is the only + * permitted behavior in SMMUv3.2 and later. + */ + if (data & R_GBPA_UPDATE_MASK) { + /* Ignore update bit as write is synchronous. */ + s->gbpa = data & ~R_GBPA_UPDATE_MASK; + } + return MEMTX_OK; case A_STRTAB_BASE: /* 64b */ s->strtab_base = deposit64(s->strtab_base, 0, 32, data); return MEMTX_OK; @@ -1318,6 +1333,9 @@ static MemTxResult smmu_readl(SMMUv3State *s, hwaddr offset, case A_STATUSR: *data = s->statusr; return MEMTX_OK; + case A_GBPA: + *data = s->gbpa; + return MEMTX_OK; case A_IRQ_CTRL: case A_IRQ_CTRL_ACK: *data = s->irq_ctrl; @@ -1482,6 +1500,25 @@ static const VMStateDescription vmstate_smmuv3_queue = { }, }; +static bool smmuv3_gbpa_needed(void *opaque) +{ + SMMUv3State *s = opaque; + + /* Only migrate GBPA if it has different reset value. */ + return s->gbpa != SMMU_GBPA_RESET_VAL; +} + +static const VMStateDescription vmstate_gbpa = { + .name = "smmuv3/gbpa", + .version_id = 1, + .minimum_version_id = 1, + .needed = smmuv3_gbpa_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT32(gbpa, SMMUv3State), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_smmuv3 = { .name = "smmuv3", .version_id = 1, @@ -1512,6 +1549,10 @@ static const VMStateDescription vmstate_smmuv3 = { VMSTATE_END_OF_LIST(), }, + .subsections = (const VMStateDescription * []) { + &vmstate_gbpa, + NULL + } }; static void smmuv3_instance_init(Object *obj) From patchwork Thu Feb 16 17:11:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 654064 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp86404wrc; Thu, 16 Feb 2023 09:15:21 -0800 (PST) X-Google-Smtp-Source: AK7set+rA6x6T6e4RjE2rNhQuLV7sWfQuMruFGBrbsJEuzARCwyykSTyyktCdup9Aq+8CTqLa0XS X-Received: by 2002:ac8:4e8d:0:b0:3b8:6cd5:eda with SMTP id 13-20020ac84e8d000000b003b86cd50edamr10621562qtp.47.1676567721022; Thu, 16 Feb 2023 09:15:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676567721; cv=none; d=google.com; s=arc-20160816; b=tDSNLEVIr7WqHle7yHOnfLx7sodTuAqxMZ7i4RnZgquzxQ0eqW6ORVu/zE8Cwvfw4r BD38bbLYQOq3XZArJ2IQag4B8JKKIkwmD49vIOhaohF9lA5XAEyIBaLwcop5ia+xbjAl c/3NH/5YWO83IqMYNe4dXO6VGG8QdqnJ8c+lRUqRPMMsUdr1oBW56B8Y1gS9I9gZ7Qey dxdWy3x8r6mF5bvPf5ANcywAtirBkyi3++BGNevB8CwEERXljd4FZPbM4Wv2sPXaCeLs RygSmLQJqC0dmQXmWnV4/CXnGEMb4SG3LQCO/rjwQmAZhRloSj87rg5a5ZbOAbxAP2Le 7/SA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=AerA0OknWJqQzriuIbTWlCJrYfPW5ifmeAoCsYc7SKg=; b=E0gNjZmIhcKOq7xNV+H+hpKzQrYr8sa8H3Ecl198FRlbkRdCAGtapayBwfrm5egwNo FfXJJ9ynGDOj7oEsiSdqB0DeGGAWSU5ra8UhSJYooU5o8ilTeW1tSAnZs4X3xgqPatEi pEfsfx5X6kRBHiUuExHq3SBN3JpG4DC2eTsFs2qKw54lo8HQ4JuQDPNn7ghlO6RTkb7Y FCLL0LldshZ+2V2LNksrWW4NCaaGPSZoJDaFN79+n0jZg2wvADR42LJXYHqz9wDIH6RF gxkM7y3WQqGuA1ApHypDozckfWl8WcM/YAcblKBqP4Wj+utbyjfCEKTXjYn0m4EkyJpB 5Nxw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=r7mTDzJA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a5d4dcc000000b002c556a4f1casm2049107wru.42.2023.02.16.09.11.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 09:11:36 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/30] hw/arm: Add missing XLNX_ZYNQMP_ARM -> USB_DWC3 Kconfig dependency Date: Thu, 16 Feb 2023 17:11:07 +0000 Message-Id: <20230216171123.2518285-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216171123.2518285-1-peter.maydell@linaro.org> References: <20230216171123.2518285-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Since commit acc0b8b05a when running the ZynqMP ZCU102 board with a QEMU configured using --without-default-devices, we get: $ qemu-system-aarch64 -M xlnx-zcu102 qemu-system-aarch64: missing object type 'usb_dwc3' Abort trap: 6 Fix by adding the missing Kconfig dependency. Fixes: acc0b8b05a ("hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers") Signed-off-by: Philippe Mathieu-Daudé Message-id: 20230216092327.2203-1-philmd@linaro.org Reviewed-by: Francisco Iglesias Signed-off-by: Peter Maydell --- hw/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 2d157de9b8b..b5aed4aff56 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -389,6 +389,7 @@ config XLNX_ZYNQMP_ARM select XLNX_CSU_DMA select XLNX_ZYNQMP select XLNX_ZDMA + select USB_DWC3 config XLNX_VERSAL bool From patchwork Thu Feb 16 17:11:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 654068 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp86573wrc; Thu, 16 Feb 2023 09:15:42 -0800 (PST) X-Google-Smtp-Source: AK7set87yk23IUjDy+b/sdfrYNO30GBixznzOBYaKWVbrH4/eil7jToGoCbQ0Ml9/4eAqFh+PcwF X-Received: by 2002:a05:6214:c63:b0:56e:b91f:aeb4 with SMTP id t3-20020a0562140c6300b0056eb91faeb4mr12230438qvj.36.1676567741858; Thu, 16 Feb 2023 09:15:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676567741; cv=none; d=google.com; s=arc-20160816; b=jQlbuWI4EZwHVJpaP2Yx+Bo0AzWn0wDiggSoTmRIF2oqYSOqO0KNlF43u5gaNh66Tb avyroU1z1QcsTJkfR3WUTCGnJJN5Do7McO5SaSV0pVeydkPiyvTjZk+PgWAEeS5YGlWs BwCPmXkszlfOR2LY62yvhI/4eaGMR7AaxdbuWDgsDeyWyTgxdVb8HcotqCokkoeeyNvb EtfbeUXNkyyfHmdXxehr4wAlh+1ydqV6ZusgWemFEA/ZPLyDLwPrFqXMZr6+waMrm6aF Np1tK7Ri3x4VZk1G8xfSAkFSKPfSc0w9e9vmWX6HuGr0WWbvk9kQfWaLJnkx2z1AaB7J /eng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=b/ZJPvKYLNs02JbKxyWAve6/lJ0RBSn21cgFd8J9qhw=; b=j2Vdl6eh6xQ3nc3Fhw69I+046XZBxDkb8QCw8GzDnsHJLYr7EVGFVyvVnQURMwtS8u I8YcUGPV9JwQd2gt0ajwrZm4VRFx3SmQskSFdJSeIKZyNhxu0lQc7mvvgvL7wqkLhNmQ 6jeILDp3WEyHOOeXXI0sFe+hAm7/6DmJQe0Eqjdu2+QrtlJJcRVcsUGHJae+eMNLwxQn W0L3+uLZVPsWWwimpk1uz4CRCJsx1MmphxFrRxfSH8KqeBer2a2iU5VTSSRHuqXOlH81 Nxh78PWznEUO3hMRHj9/QTGni/PdFEabLdY43WQMpyD49wvP088Cc+z5lYEBfaO8PA6J NWjQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="N/bTgqvL"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a5d4dcc000000b002c556a4f1casm2049107wru.42.2023.02.16.09.11.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 09:11:37 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/30] arm/virt: don't try to spell out the accelerator Date: Thu, 16 Feb 2023 17:11:08 +0000 Message-Id: <20230216171123.2518285-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216171123.2518285-1-peter.maydell@linaro.org> References: <20230216171123.2518285-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Cornelia Huck Just use current_accel_name() directly. Signed-off-by: Cornelia Huck Reviewed-by: Eric Auger Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- hw/arm/virt.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 75f28947de0..8d13e4486b1 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2133,21 +2133,21 @@ static void machvirt_init(MachineState *machine) if (vms->secure && (kvm_enabled() || hvf_enabled())) { error_report("mach-virt: %s does not support providing " "Security extensions (TrustZone) to the guest CPU", - kvm_enabled() ? "KVM" : "HVF"); + current_accel_name()); exit(1); } if (vms->virt && (kvm_enabled() || hvf_enabled())) { error_report("mach-virt: %s does not support providing " "Virtualization extensions to the guest CPU", - kvm_enabled() ? "KVM" : "HVF"); + current_accel_name()); exit(1); } if (vms->mte && (kvm_enabled() || hvf_enabled())) { error_report("mach-virt: %s does not support providing " "MTE to the guest CPU", - kvm_enabled() ? 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a5d4dcc000000b002c556a4f1casm2049107wru.42.2023.02.16.09.11.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 09:11:38 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/30] MAINTAINERS: Add myself to maintainers and remove Havard Date: Thu, 16 Feb 2023 17:11:09 +0000 Message-Id: <20230216171123.2518285-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216171123.2518285-1-peter.maydell@linaro.org> References: <20230216171123.2518285-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Hao Wu Havard is no longer working on the Nuvoton systems for a while and won't be able to do any work on it in the future. So I'll take over maintaining the Nuvoton system from him. Signed-off-by: Hao Wu Acked-by: Havard Skinnemoen Reviewed-by: Philippe Mathieu-Daude Message-id: 20230208235433.3989937-2-wuhaotsh@google.com Signed-off-by: Peter Maydell --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index fd54c1f1401..94659e42c2c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -807,8 +807,8 @@ F: include/hw/net/mv88w8618_eth.h F: docs/system/arm/musicpal.rst Nuvoton NPCM7xx -M: Havard Skinnemoen M: Tyrone Ting +M: Hao Wu L: qemu-arm@nongnu.org S: Supported F: hw/*/npcm7xx* From patchwork Thu Feb 16 17:11:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 654072 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp86685wrc; Thu, 16 Feb 2023 09:15:53 -0800 (PST) X-Google-Smtp-Source: AK7set8mUBA3AGmDARnjjtUMRpakB5jKAH8dIqSvBTlFCTh68CFcMzsH0v8lBPHfYgWgfB5Y7Nza X-Received: by 2002:ac8:7fcc:0:b0:3ba:138f:7b46 with SMTP id b12-20020ac87fcc000000b003ba138f7b46mr10308696qtk.42.1676567752893; Thu, 16 Feb 2023 09:15:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676567752; cv=none; d=google.com; s=arc-20160816; b=fbPBkUQuXeElosJ0AZa3gO9U8aMbq3CQI0kgAre5XKE1swSOyufKoViyYUi0q3UlGH fzO0j+WePhIe1GbopmgkCv/AEG+1g1qp7R7BcnDFWwAr5ZIjq5F5L0EkesAJS8O7stDc sFLFFp8CLDA2aeBcgtV3pwImTY6pYhg2ktM2dqbSznSNPo7AG0vS+BTZARl0j2I+UI3/ ItHnz4cz2pMsheDyrpnC8luKpizVCw8OhzlWXVteTnXXN5SrmQkrY8q7t546cikkXjHr 1tAjzwgZg/XbQMJF2lhCj8UW7tznMhw4c5yi2VmqWDmDfHb1Huo153twhYAJuxtD3MZ8 54cA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WJGiFDdYVNEAwNHmoXQCKuWGS/DxAbFTps8rYNvQTJ0=; b=qDUO5mLZiJ4tRu+sB6tx/XpU6HZCQhxBt7zGd7ufFI8/unmnzADXItZXKo7HyUMaSt 5YCZp0bu9xTgrG8yFqdJbu4z2Bv8b4H+B31pNMc1QxaTv+ehnqmV+bv6bGURiyKDu1Cn Bv567z/TTpiNhJSgf3W2VV+QJu06cL4T80bKf2lksrOm/b8BeQd9zonATKpnZZ2XoqJC c2nLL50UOD5ugg+UUTpCHDe2KD/X7nFeh7gvCzeWyeL1+6pqRRZM32ZEEfOHUHqQtaf9 TRh0Drrtlmonuqarcr7gEieMA9FfpSdn6miywzELhzfd2HULYPQ/HJssFbsZLNfIzew2 vbHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="konmaSU/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a5d4dcc000000b002c556a4f1casm2049107wru.42.2023.02.16.09.11.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 09:11:39 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/30] hw/ssi: Add Nuvoton PSPI Module Date: Thu, 16 Feb 2023 17:11:10 +0000 Message-Id: <20230216171123.2518285-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216171123.2518285-1-peter.maydell@linaro.org> References: <20230216171123.2518285-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Hao Wu Nuvoton's PSPI is a general purpose SPI module which enables connections to SPI-based peripheral devices. Signed-off-by: Hao Wu Reviewed-by: Chris Rauer Reviewed-by: Philippe Mathieu-Daude Message-id: 20230208235433.3989937-3-wuhaotsh@google.com Signed-off-by: Peter Maydell --- MAINTAINERS | 6 +- include/hw/ssi/npcm_pspi.h | 53 +++++++++ hw/ssi/npcm_pspi.c | 221 +++++++++++++++++++++++++++++++++++++ hw/ssi/meson.build | 2 +- hw/ssi/trace-events | 5 + 5 files changed, 283 insertions(+), 4 deletions(-) create mode 100644 include/hw/ssi/npcm_pspi.h create mode 100644 hw/ssi/npcm_pspi.c diff --git a/MAINTAINERS b/MAINTAINERS index 94659e42c2c..21595f0aadd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -811,9 +811,9 @@ M: Tyrone Ting M: Hao Wu L: qemu-arm@nongnu.org S: Supported -F: hw/*/npcm7xx* -F: include/hw/*/npcm7xx* -F: tests/qtest/npcm7xx* +F: hw/*/npcm* +F: include/hw/*/npcm* +F: tests/qtest/npcm* F: pc-bios/npcm7xx_bootrom.bin F: roms/vbootrom F: docs/system/arm/nuvoton.rst diff --git a/include/hw/ssi/npcm_pspi.h b/include/hw/ssi/npcm_pspi.h new file mode 100644 index 00000000000..37cc784d962 --- /dev/null +++ b/include/hw/ssi/npcm_pspi.h @@ -0,0 +1,53 @@ +/* + * Nuvoton Peripheral SPI Module + * + * Copyright 2023 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ +#ifndef NPCM_PSPI_H +#define NPCM_PSPI_H + +#include "hw/ssi/ssi.h" +#include "hw/sysbus.h" + +/* + * Number of registers in our device state structure. Don't change this without + * incrementing the version_id in the vmstate. + */ +#define NPCM_PSPI_NR_REGS 3 + +/** + * NPCMPSPIState - Device state for one Flash Interface Unit. + * @parent: System bus device. + * @mmio: Memory region for register access. + * @spi: The SPI bus mastered by this controller. + * @regs: Register contents. + * @irq: The interrupt request queue for this module. + * + * Each PSPI has a shared bank of registers, and controls up to four chip + * selects. Each chip select has a dedicated memory region which may be used to + * read and write the flash connected to that chip select as if it were memory. + */ +typedef struct NPCMPSPIState { + SysBusDevice parent; + + MemoryRegion mmio; + + SSIBus *spi; + uint16_t regs[NPCM_PSPI_NR_REGS]; + qemu_irq irq; +} NPCMPSPIState; + +#define TYPE_NPCM_PSPI "npcm-pspi" +OBJECT_DECLARE_SIMPLE_TYPE(NPCMPSPIState, NPCM_PSPI) + +#endif /* NPCM_PSPI_H */ diff --git a/hw/ssi/npcm_pspi.c b/hw/ssi/npcm_pspi.c new file mode 100644 index 00000000000..3fb935043ab --- /dev/null +++ b/hw/ssi/npcm_pspi.c @@ -0,0 +1,221 @@ +/* + * Nuvoton NPCM Peripheral SPI Module (PSPI) + * + * Copyright 2023 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" + +#include "hw/irq.h" +#include "hw/registerfields.h" +#include "hw/ssi/npcm_pspi.h" +#include "migration/vmstate.h" +#include "qapi/error.h" +#include "qemu/error-report.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/units.h" + +#include "trace.h" + +REG16(PSPI_DATA, 0x0) +REG16(PSPI_CTL1, 0x2) + FIELD(PSPI_CTL1, SPIEN, 0, 1) + FIELD(PSPI_CTL1, MOD, 2, 1) + FIELD(PSPI_CTL1, EIR, 5, 1) + FIELD(PSPI_CTL1, EIW, 6, 1) + FIELD(PSPI_CTL1, SCM, 7, 1) + FIELD(PSPI_CTL1, SCIDL, 8, 1) + FIELD(PSPI_CTL1, SCDV, 9, 7) +REG16(PSPI_STAT, 0x4) + FIELD(PSPI_STAT, BSY, 0, 1) + FIELD(PSPI_STAT, RBF, 1, 1) + +static void npcm_pspi_update_irq(NPCMPSPIState *s) +{ + int level = 0; + + /* Only fire IRQ when the module is enabled. */ + if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, SPIEN)) { + /* Update interrupt as BSY is cleared. */ + if ((!FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, BSY)) && + FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIW)) { + level = 1; + } + + /* Update interrupt as RBF is set. */ + if (FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, RBF) && + FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIR)) { + level = 1; + } + } + qemu_set_irq(s->irq, level); +} + +static uint16_t npcm_pspi_read_data(NPCMPSPIState *s) +{ + uint16_t value = s->regs[R_PSPI_DATA]; + + /* Clear stat bits as the value are read out. */ + s->regs[R_PSPI_STAT] = 0; + + return value; +} + +static void npcm_pspi_write_data(NPCMPSPIState *s, uint16_t data) +{ + uint16_t value = 0; + + if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, MOD)) { + value = ssi_transfer(s->spi, extract16(data, 8, 8)) << 8; + } + value |= ssi_transfer(s->spi, extract16(data, 0, 8)); + s->regs[R_PSPI_DATA] = value; + + /* Mark data as available */ + s->regs[R_PSPI_STAT] = R_PSPI_STAT_BSY_MASK | R_PSPI_STAT_RBF_MASK; +} + +/* Control register read handler. */ +static uint64_t npcm_pspi_ctrl_read(void *opaque, hwaddr addr, + unsigned int size) +{ + NPCMPSPIState *s = opaque; + uint16_t value; + + switch (addr) { + case A_PSPI_DATA: + value = npcm_pspi_read_data(s); + break; + + case A_PSPI_CTL1: + value = s->regs[R_PSPI_CTL1]; + break; + + case A_PSPI_STAT: + value = s->regs[R_PSPI_STAT]; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to invalid offset 0x%" PRIx64 "\n", + DEVICE(s)->canonical_path, addr); + return 0; + } + trace_npcm_pspi_ctrl_read(DEVICE(s)->canonical_path, addr, value); + npcm_pspi_update_irq(s); + + return value; +} + +/* Control register write handler. */ +static void npcm_pspi_ctrl_write(void *opaque, hwaddr addr, uint64_t v, + unsigned int size) +{ + NPCMPSPIState *s = opaque; + uint16_t value = v; + + trace_npcm_pspi_ctrl_write(DEVICE(s)->canonical_path, addr, value); + + switch (addr) { + case A_PSPI_DATA: + npcm_pspi_write_data(s, value); + break; + + case A_PSPI_CTL1: + s->regs[R_PSPI_CTL1] = value; + break; + + case A_PSPI_STAT: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to read-only register PSPI_STAT: 0x%08" + PRIx64 "\n", DEVICE(s)->canonical_path, v); + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to invalid offset 0x%" PRIx64 "\n", + DEVICE(s)->canonical_path, addr); + return; + } + npcm_pspi_update_irq(s); +} + +static const MemoryRegionOps npcm_pspi_ctrl_ops = { + .read = npcm_pspi_ctrl_read, + .write = npcm_pspi_ctrl_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 1, + .max_access_size = 2, + .unaligned = false, + }, + .impl = { + .min_access_size = 2, + .max_access_size = 2, + .unaligned = false, + }, +}; + +static void npcm_pspi_enter_reset(Object *obj, ResetType type) +{ + NPCMPSPIState *s = NPCM_PSPI(obj); + + trace_npcm_pspi_enter_reset(DEVICE(obj)->canonical_path, type); + memset(s->regs, 0, sizeof(s->regs)); +} + +static void npcm_pspi_realize(DeviceState *dev, Error **errp) +{ + NPCMPSPIState *s = NPCM_PSPI(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + Object *obj = OBJECT(dev); + + s->spi = ssi_create_bus(dev, "pspi"); + memory_region_init_io(&s->mmio, obj, &npcm_pspi_ctrl_ops, s, + "mmio", 4 * KiB); + sysbus_init_mmio(sbd, &s->mmio); + sysbus_init_irq(sbd, &s->irq); +} + +static const VMStateDescription vmstate_npcm_pspi = { + .name = "npcm-pspi", + .version_id = 0, + .minimum_version_id = 0, + .fields = (VMStateField[]) { + VMSTATE_UINT16_ARRAY(regs, NPCMPSPIState, NPCM_PSPI_NR_REGS), + VMSTATE_END_OF_LIST(), + }, +}; + + +static void npcm_pspi_class_init(ObjectClass *klass, void *data) +{ + ResettableClass *rc = RESETTABLE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->desc = "NPCM Peripheral SPI Module"; + dc->realize = npcm_pspi_realize; + dc->vmsd = &vmstate_npcm_pspi; + rc->phases.enter = npcm_pspi_enter_reset; +} + +static const TypeInfo npcm_pspi_types[] = { + { + .name = TYPE_NPCM_PSPI, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(NPCMPSPIState), + .class_init = npcm_pspi_class_init, + }, +}; +DEFINE_TYPES(npcm_pspi_types); diff --git a/hw/ssi/meson.build b/hw/ssi/meson.build index 702aa5e4dfe..904a47161a4 100644 --- a/hw/ssi/meson.build +++ b/hw/ssi/meson.build @@ -1,6 +1,6 @@ softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_smc.c')) softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('mss-spi.c')) -softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c')) +softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c', 'npcm_pspi.c')) softmmu_ss.add(when: 'CONFIG_PL022', if_true: files('pl022.c')) softmmu_ss.add(when: 'CONFIG_SIFIVE_SPI', if_true: files('sifive_spi.c')) softmmu_ss.add(when: 'CONFIG_SSI', if_true: files('ssi.c')) diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events index c707d4aabaf..2d5bd2b83d0 100644 --- a/hw/ssi/trace-events +++ b/hw/ssi/trace-events @@ -21,6 +21,11 @@ npcm7xx_fiu_ctrl_write(const char *id, uint64_t addr, uint32_t data) "%s offset: npcm7xx_fiu_flash_read(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64 npcm7xx_fiu_flash_write(const char *id, unsigned cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64 +# npcm_pspi.c +npcm_pspi_enter_reset(const char *id, int reset_type) "%s reset type: %d" +npcm_pspi_ctrl_read(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16 +npcm_pspi_ctrl_write(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16 + # ibex_spi_host.c ibex_spi_host_reset(const char *msg) "%s" From patchwork Thu Feb 16 17:11:11 2023 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a5d4dcc000000b002c556a4f1casm2049107wru.42.2023.02.16.09.11.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 09:11:39 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/30] hw/arm: Attach PSPI module to NPCM7XX SoC Date: Thu, 16 Feb 2023 17:11:11 +0000 Message-Id: <20230216171123.2518285-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216171123.2518285-1-peter.maydell@linaro.org> References: <20230216171123.2518285-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Hao Wu Signed-off-by: Hao Wu Reviewed-by: Titus Rwantare Reviewed-by: Philippe Mathieu-Daude Message-id: 20230208235433.3989937-4-wuhaotsh@google.com Signed-off-by: Peter Maydell --- docs/system/arm/nuvoton.rst | 2 +- include/hw/arm/npcm7xx.h | 2 ++ hw/arm/npcm7xx.c | 25 +++++++++++++++++++++++-- 3 files changed, 26 insertions(+), 3 deletions(-) diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst index c38df32bde0..0424cae4b01 100644 --- a/docs/system/arm/nuvoton.rst +++ b/docs/system/arm/nuvoton.rst @@ -49,6 +49,7 @@ Supported devices * SMBus controller (SMBF) * Ethernet controller (EMC) * Tachometer + * Peripheral SPI controller (PSPI) Missing devices --------------- @@ -64,7 +65,6 @@ Missing devices * Ethernet controller (GMAC) * USB device (USBD) - * Peripheral SPI controller (PSPI) * SD/MMC host * PECI interface * PCI and PCIe root complex and bridges diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index f1b7e4a48d3..72c77220964 100644 --- a/include/hw/arm/npcm7xx.h +++ b/include/hw/arm/npcm7xx.h @@ -32,6 +32,7 @@ #include "hw/nvram/npcm7xx_otp.h" #include "hw/timer/npcm7xx_timer.h" #include "hw/ssi/npcm7xx_fiu.h" +#include "hw/ssi/npcm_pspi.h" #include "hw/usb/hcd-ehci.h" #include "hw/usb/hcd-ohci.h" #include "target/arm/cpu.h" @@ -104,6 +105,7 @@ struct NPCM7xxState { NPCM7xxFIUState fiu[2]; NPCM7xxEMCState emc[2]; NPCM7xxSDHCIState mmc; + NPCMPSPIState pspi[2]; }; #define TYPE_NPCM7XX "npcm7xx" diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index d85cc027651..15ff21d0472 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -86,6 +86,8 @@ enum NPCM7xxInterrupt { NPCM7XX_EMC1RX_IRQ = 15, NPCM7XX_EMC1TX_IRQ, NPCM7XX_MMC_IRQ = 26, + NPCM7XX_PSPI2_IRQ = 28, + NPCM7XX_PSPI1_IRQ = 31, NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */ NPCM7XX_TIMER1_IRQ, NPCM7XX_TIMER2_IRQ, @@ -220,6 +222,12 @@ static const hwaddr npcm7xx_emc_addr[] = { 0xf0826000, }; +/* Register base address for each PSPI Module */ +static const hwaddr npcm7xx_pspi_addr[] = { + 0xf0200000, + 0xf0201000, +}; + static const struct { hwaddr regs_addr; uint32_t unconnected_pins; @@ -444,6 +452,10 @@ static void npcm7xx_init(Object *obj) object_initialize_child(obj, "emc[*]", &s->emc[i], TYPE_NPCM7XX_EMC); } + for (i = 0; i < ARRAY_SIZE(s->pspi); i++) { + object_initialize_child(obj, "pspi[*]", &s->pspi[i], TYPE_NPCM_PSPI); + } + object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI); } @@ -715,6 +727,17 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0, npcm7xx_irq(s, NPCM7XX_MMC_IRQ)); + /* PSPI */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pspi_addr) != ARRAY_SIZE(s->pspi)); + for (i = 0; i < ARRAY_SIZE(s->pspi); i++) { + SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pspi[i]); + int irq = (i == 0) ? NPCM7XX_PSPI1_IRQ : NPCM7XX_PSPI2_IRQ; + + sysbus_realize(sbd, &error_abort); + sysbus_mmio_map(sbd, 0, npcm7xx_pspi_addr[i]); + sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, irq)); + } + create_unimplemented_device("npcm7xx.shm", 0xc0001000, 4 * KiB); create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB); create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB); @@ -724,8 +747,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB); create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB); create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB); - create_unimplemented_device("npcm7xx.pspi1", 0xf0200000, 4 * KiB); - create_unimplemented_device("npcm7xx.pspi2", 0xf0201000, 4 * KiB); create_unimplemented_device("npcm7xx.ahbpci", 0xf0400000, 1 * MiB); create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * KiB); create_unimplemented_device("npcm7xx.gmac1", 0xf0802000, 8 * KiB); From patchwork Thu Feb 16 17:11:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 654065 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp86400wrc; Thu, 16 Feb 2023 09:15:21 -0800 (PST) X-Google-Smtp-Source: AK7set9OBeMEf3F/MjBjlsGVQOkv2oSb3bvzIpsG9h65vf8n0WVejwsWQaj9OVj7y20gXKRedF/A X-Received: by 2002:ac8:5983:0:b0:3b9:b43e:5733 with SMTP id e3-20020ac85983000000b003b9b43e5733mr10527815qte.61.1676567720882; Thu, 16 Feb 2023 09:15:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676567720; cv=none; d=google.com; s=arc-20160816; b=qC8hx1ALF+l1ocUkKOQgLY1KEo9mlu1Tq0FtVNCEQntreJAtE9tDtVeqhzO46zhpjf c8DrdV2wU9YEQXi8l8KhhJx5Y8f6uCnwRqflq9PF3zUiEmgIwrI32rBJ14yH0PVeRGVN GxxV0J14cCriLbpYHixwNcqoMN3+7wI26arSi1id8zG/q+ZzT+w+hxJ1AYGO9LpCqjVy vgK4P2PStJdhsk12QQpEDMumReAG86922Sdl0MSRNf96CgbtfYkH/Z3zzogP9mlQCCic LWaVi84GiusIsq/kg5X1Y4VUqBE+jdZbz6UAtu/CnYwLTKMuDrxXzoyaGi75LiyrJcoz 7tMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=zD+gZe3NwGNlSfMSq90UNcL0FHuG48xEwAB0qrl/tCo=; b=b4wVLcQ0qNoaret/I5N8iKM0l8m/O4ZswFfdxJUr5OxgTLkc2H4vaKVqkqN/Ryngly t3V8ufN5oWkyJzFOK8/mvD6eRq9n9CxnJBr+r7END5W7PqpmZOxO7XxaQuH86doLpf8L qUcgJaL7EoXAK5Mi+djl0w5gg0ukttkkTOl4gGG/eFmjARWvtQ5Cv/IvEJ/0OYcs6P3/ tMIMR3xc1iHAwsGkk63L7bwXeCNU3wfPAWgDh7VCUeCVi7UXC34o3gph4FVH+UvywKSR Ztm7HpUB/eMlfQY//b8d4LzDSJd/f9v5cJS6zA/l1HOwcMro6R79JTpslJhMmF2Y25mv iylg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cLsqx9Dn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a5d4dcc000000b002c556a4f1casm2049107wru.42.2023.02.16.09.11.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 09:11:40 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/30] hw/arm/smmu-common: Support 64-bit addresses Date: Thu, 16 Feb 2023 17:11:12 +0000 Message-Id: <20230216171123.2518285-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216171123.2518285-1-peter.maydell@linaro.org> References: <20230216171123.2518285-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Jean-Philippe Brucker Addresses targeting the second translation table (TTB1) in the SMMU have all upper bits set. Ensure the IOMMU region covers all 64 bits. Reviewed-by: Richard Henderson Signed-off-by: Jean-Philippe Brucker Reviewed-by: Eric Auger Message-id: 20230214171921.1917916-2-jean-philippe@linaro.org Signed-off-by: Peter Maydell --- include/hw/arm/smmu-common.h | 2 -- hw/arm/smmu-common.c | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index c5683af07d6..9fcff26357f 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -27,8 +27,6 @@ #define SMMU_PCI_DEVFN_MAX 256 #define SMMU_PCI_DEVFN(sid) (sid & 0xFF) -#define SMMU_MAX_VA_BITS 48 - /* * Page table walk error types */ diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 733c9647784..2b8c67b9a1d 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -439,7 +439,7 @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn) memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu), s->mrtypename, - OBJECT(s), name, 1ULL << SMMU_MAX_VA_BITS); + OBJECT(s), name, UINT64_MAX); address_space_init(&sdev->as, MEMORY_REGION(&sdev->iommu), name); trace_smmu_add_mr(name); From patchwork Thu Feb 16 17:11:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 654063 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp86396wrc; Thu, 16 Feb 2023 09:15:20 -0800 (PST) X-Google-Smtp-Source: AK7set/B/iZCVo23qjo4rT948/mkKVK08wNzZGPIrx1uj5c5hpq4/1QKv/MSY+WzAclW70gXDY6S X-Received: by 2002:a05:6214:2402:b0:56e:fb1b:3c7b with SMTP id fv2-20020a056214240200b0056efb1b3c7bmr5047765qvb.38.1676567720572; Thu, 16 Feb 2023 09:15:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676567720; cv=none; d=google.com; s=arc-20160816; b=UeIOww1C2fljpaWYovCalgPq3uBAYNqPWYy+qaJ3hAlolt7wqCppiK+BHBlnOryyFM VeIPj1mR2LQ14xWDsGRyd2CBTbSAVxdkjwympboXfxlqKCF7/ylVAXx2FvdGJ5cTJN0m IygDXiFVAzQkvY0i63wwxWFuYd923C7wHsC7H9c1hpf+ALRFQfKb6LoQa7r13MpTBKx6 fJwyc730hgV9KUWJkNjClvUCs1LpQScQ4KIfX1teDiRRp/e+/zjeuXYSw9FZ3NDPaIFs DgfQH6bwy/ussY02hE1odv9mfWsVBolc4Ujc0vEEFRbyHJwGk506PckAWCQSwXQyUeHf 9GFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=nb5AAn5zyFKHHN1q+dOOj2I4towk0anX1Vqm7ObRW+M=; b=jn6PxOdhQ6Uhml3Z4ucrybSvQg1wT4FV7JpIO5/QJZda69LltSxPEkuQ23RlRDy3mV JWaZljV8sC23QYssprAam1EdIs8EM8i/rALovV4wtrZw2bWMWM2pyRDaam5yHdVpAwRi fxnB26vsBBDvvYoBBWb4sWhnx6jlsW2RIAImCe1Z0bRVvQ7LuR5bfsZNk/EbeGSpr3qR mHAdFdFzOJchnYwAlbtH7jGKUf+qR+EIqop5JtaPOdG7Otebpppx60NaZmX3Opyq27+C KC6G/+pWw0VUlESFKH7ZFBmBy11/XbuwAN/M0z512f1beJOhmC1ZwWoBqwpyIlUl9Y+x cLqQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=O0SuPXKp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a5d4dcc000000b002c556a4f1casm2049107wru.42.2023.02.16.09.11.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 09:11:41 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/30] hw/arm/smmu-common: Fix TTB1 handling Date: Thu, 16 Feb 2023 17:11:13 +0000 Message-Id: <20230216171123.2518285-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216171123.2518285-1-peter.maydell@linaro.org> References: <20230216171123.2518285-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Jean-Philippe Brucker Addresses targeting the second translation table (TTB1) in the SMMU have all upper bits set (except for the top byte when TBI is enabled). Fix the TTB1 check. Reported-by: Ola Hugosson Reviewed-by: Eric Auger Reviewed-by: Richard Henderson Signed-off-by: Jean-Philippe Brucker Message-id: 20230214171921.1917916-3-jean-philippe@linaro.org Signed-off-by: Peter Maydell --- hw/arm/smmu-common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 2b8c67b9a1d..0a5a60ca1e9 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -249,7 +249,7 @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova) /* there is a ttbr0 region and we are in it (high bits all zero) */ return &cfg->tt[0]; } else if (cfg->tt[1].tsz && - !extract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte)) { + sextract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte) == -1) { /* there is a ttbr1 region and we are in it (high bits all one) */ return &cfg->tt[1]; } else if (!cfg->tt[0].tsz) { From patchwork Thu Feb 16 17:11:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 654066 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp86563wrc; Thu, 16 Feb 2023 09:15:41 -0800 (PST) X-Google-Smtp-Source: AK7set9IE+OYbcboU+OsRktpMZQSwESoMaRC9sOjwm7r1uatpWYePczcnIveD6CvjQ3FaUrtgjg7 X-Received: by 2002:a05:622a:311:b0:3b9:a441:37ed with SMTP id q17-20020a05622a031100b003b9a44137edmr10845721qtw.32.1676567741104; Thu, 16 Feb 2023 09:15:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676567741; cv=none; d=google.com; s=arc-20160816; b=PHRwKFWQ+UoYJ7FfUcS0Ez507JwMXEJZ2Eh62zQebUHRPfbYzVE9Ps226Dfq0dB+Y2 vkUItJ+w9L3Zm9ReXTcW2oVF+z1ZO7KAUIDtxUyNzl2+yE4pbtLrBITdhud9+Wi2DP7+ Y+J4pKbsgBKZ917A/c8NvDnrIxy43vYT/6WuM7Sg+sU72D3uTN3cuLKuX4E6X43K26AC EppWHghNr/OHW766be2YaEGhJfyNQSl4vki/DssLQsr+Rbt0LqwofqueLDJly5EdVUY8 fBaj3yRWxS+w7sEdaUy1KG/LMvgG70VEGpWiErBYOYmb4Wve2jrRFPA7xtUlF3LX30Ao vkiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=RdFlF/b3VYR2fecwChpgN5HOR7iNVGAod5mHzESL9uI=; b=aoodgLxJCDTy7ui1Jr2q5077bHKvlTWyOwNJQOXEdJ1MJ2KtfyWmTpQRMDO2Bwg4u2 Jm9chaEAMgwXjnqzWXoJPJe6IONbkC0ZIbShilmImUjSCoA6H6HMq2zfEofejg4+xB4i /35XIzYkreXAa5RokSpYEDPKicm2rAT1zl3yJf19uEW3Gu0Nys/+9fiFRuAKPaL2fqgT ulHRO+aj5ow3KnzH3iTPj0w+e+k8wT96T99aIZaj2CkGnaR8z0pb68MjHLHyGVsOWyy+ oDwmj3vF1BI7S3HFxuIrafK6FrMj9DKHqmfVl1eb8Ew3cF3krKlRs9Cs4ZgR6pw4FQxB x1Qg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=znvZml3Z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a5d4dcc000000b002c556a4f1casm2049107wru.42.2023.02.16.09.11.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 09:11:42 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/30] target/arm: rename handle_semihosting to tcg_handle_semihosting Date: Thu, 16 Feb 2023 17:11:14 +0000 Message-Id: <20230216171123.2518285-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216171123.2518285-1-peter.maydell@linaro.org> References: <20230216171123.2518285-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Claudio Fontana make it clearer from the name that this is a tcg-only function. Signed-off-by: Claudio Fontana Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 22670c20c00..509e674b0f0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11014,7 +11014,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) * trapped to the hypervisor in KVM. */ #ifdef CONFIG_TCG -static void handle_semihosting(CPUState *cs) +static void tcg_handle_semihosting(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; @@ -11076,7 +11076,7 @@ void arm_cpu_do_interrupt(CPUState *cs) */ #ifdef CONFIG_TCG if (cs->exception_index == EXCP_SEMIHOST) { - handle_semihosting(cs); + tcg_handle_semihosting(cs); return; } #endif From patchwork Thu Feb 16 17:11:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 654067 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp86564wrc; Thu, 16 Feb 2023 09:15:41 -0800 (PST) X-Google-Smtp-Source: AK7set8qSCSsI7ejcKfPpZ7boQnMjI3viDmKvNi5LwbQzfoNuvDv1AqOVyFeBZo3nEyCmy4IMX7V X-Received: by 2002:a05:6214:242d:b0:56e:c0df:8492 with SMTP id gy13-20020a056214242d00b0056ec0df8492mr12946221qvb.31.1676567741044; Thu, 16 Feb 2023 09:15:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676567741; cv=none; d=google.com; s=arc-20160816; b=RyUAf1C3J99c7jpB98jfv4W1JfS14B334ioRsFFwW7JEla38JSFTBzKxxiCYuWIrsN doMCI5nWb6IggMCDdaW5zM3CGfczCezSaLdQUM38XVL1UDnYv7K+ERl6iqm/XlSOFMdg nrxZ8AleauFKLn4LylPsFggcubwjunwxO9ryID5iaP7jAx0z7lcsDSvHFyN62YfGZpgz qpQ/aV1R32P9e2cvvVL6hd1c/pOkpgAnru1F1geVdrIk6rxF1B/KzjXtOgHwAGsCGsWe mgMO92k0DVYmpGU+FKAEjiEIbaiXza4msTuz9dE0PWbEfOmkvKWoWsMDu3RxRTNgvma8 KSkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=MLAn5GKevaRJXltRfdrt51PNhBydmEzcr/VkvxtQ/eA=; b=WOhUznwP3Dz+OrOLFyDQ2MZaB+i+hcT2bk/DNFN7O0OdUT9elxoQfWjJ9Kd6B7SNbG 1uFoTmHxIN1/ZNLMvaCFcTT87rWFgWmRV9P2X1vIX4Frg4omj4SDuc/KOLJYrd1xsFQK 2LK6CSrxcwvNPDtiUAznhd6DY73qgQbM1A/2v10x7KES+1P04NI7Jvj5OW5PmMO/aPTN rypYB6HbBYeEVLAmNYoO5sWK+yHhUJ+Atv8oAgGiAtlXwitXxBBy3BG324FhSIaQ9Ry6 htXQIt9k8bR6AkuH2+0ak6Ur0Y64Qi0UY6jQJC4ivL6BEsJMK5KHP0BeaI6nxDcu7Rw8 yxCQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RbrEQ+Am; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a5d4dcc000000b002c556a4f1casm2049107wru.42.2023.02.16.09.11.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 09:11:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/30] target/arm: wrap psci call with tcg_enabled Date: Thu, 16 Feb 2023 17:11:15 +0000 Message-Id: <20230216171123.2518285-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216171123.2518285-1-peter.maydell@linaro.org> References: <20230216171123.2518285-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Claudio Fontana for "all" builds (tcg + kvm), we want to avoid doing the psci check if tcg is built-in, but not enabled. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Fabiano Rosas Tested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- target/arm/helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 509e674b0f0..2d38c3ed7aa 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -22,6 +22,7 @@ #include "hw/irq.h" #include "sysemu/cpu-timers.h" #include "sysemu/kvm.h" +#include "sysemu/tcg.h" #include "qapi/qapi-commands-machine-target.h" #include "qapi/error.h" #include "qemu/guest-random.h" @@ -11063,7 +11064,7 @@ void arm_cpu_do_interrupt(CPUState *cs) env->exception.syndrome); } - if (arm_is_psci_call(cpu, cs->exception_index)) { + if (tcg_enabled() && arm_is_psci_call(cpu, cs->exception_index)) { arm_handle_psci_call(cpu); qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); return; From patchwork Thu Feb 16 17:11:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 654056 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp85875wrc; Thu, 16 Feb 2023 09:14:19 -0800 (PST) X-Google-Smtp-Source: AK7set+ZZzL8VQONWsU+pJ9YYlS3BzEqPnnutPcQiwcRlmE74GNUAliafSernzI4olCD/Cqza8a2 X-Received: by 2002:a05:622a:412:b0:3b8:525f:f0a7 with SMTP id n18-20020a05622a041200b003b8525ff0a7mr10286583qtx.56.1676567658942; Thu, 16 Feb 2023 09:14:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676567658; cv=none; d=google.com; s=arc-20160816; b=GaVVxYrx2ZMHOO40FPUyTHD1rLvWSwFrbXQRbkTL5FgLrck1BJXRuPlC3cLsZFF1K0 O6Ti7ARY8KSz7/agq891OSykHB4dK8XB6RL8hztOarSnRp4w7x+zzyBVN7GI0nG4vQXb mH0i/ycVPAZatO2mD5SCqSmAauVZICNvrGc4cb4EhtIO8nIj8sw4wP/tCyIWe6aejd68 n63NMZwLhneMwnS41qr2hErs5zrKjjA3cUGNCa/10vcm+yRPIqvEL8gOMwb+Bn1qw/n5 qBf3ePXlg+tQ8mX7GloXAept3i7fLZeaK9M/b//P/oDhdVZfqTkveeRjCLVBaopmIflE ndWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=X3rMKJZAHSn2N53RNjbN11WgeDbh222tQ0PpdvQC108=; b=gHgsu4U8S2fN55aEtQItK2T26Zr9R0ocEbk9imGJh2eboHNnOEiUAFuL+4oTbBEboN aVOBzYll3ZKjGGsjiCKydSbCXexpYuf32l4bLgWjklzQYr+/B3F087TUTwvBqE8ba+mS IL/WAxhO7lmp4gKSRh6nKjTNrUaEi0p8ikzVhypsUn8jwktBDETQZdbsdtH1oTRUj+lZ XjsV1tO/iAG9Kk86dzNgPNNy3vRKnuUgTIvyi9DGH/dL8JJV7NOwMbBKCFDxv93ceXaX 2/iky0jk6GukWW1aLrqEMWNeQUBiWFB4vmm5iyOKiWdgW2x7yCIqoxGnWkblKKMUoxaa Vptg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RPl6tlOE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a5d4dcc000000b002c556a4f1casm2049107wru.42.2023.02.16.09.11.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 09:11:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/30] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() Date: Thu, 16 Feb 2023 17:11:16 +0000 Message-Id: <20230216171123.2518285-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216171123.2518285-1-peter.maydell@linaro.org> References: <20230216171123.2518285-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Claudio Fontana Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Fabiano Rosas Tested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- target/arm/helper.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 2d38c3ed7aa..07d41003654 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10827,11 +10827,13 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) unsigned int cur_el = arm_current_el(env); int rt; - /* - * Note that new_el can never be 0. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a5d4dcc000000b002c556a4f1casm2049107wru.42.2023.02.16.09.11.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 09:11:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/30] target/arm: Move PC alignment check Date: Thu, 16 Feb 2023 17:11:17 +0000 Message-Id: <20230216171123.2518285-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216171123.2518285-1-peter.maydell@linaro.org> References: <20230216171123.2518285-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Fabiano Rosas Move this earlier to make the next patch diff cleaner. While here update the comment slightly to not give the impression that the misalignment affects only TCG. Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Fabiano Rosas Tested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- target/arm/machine.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/arm/machine.c b/target/arm/machine.c index 5f261526525..b4c3850570c 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -839,6 +839,15 @@ static int cpu_post_load(void *opaque, int version_id) } } + /* + * Misaligned thumb pc is architecturally impossible. Fail the + * incoming migration. For TCG it would trigger the assert in + * thumb_tr_translate_insn(). + */ + if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { + return -1; + } + hw_breakpoint_update_all(cpu); hw_watchpoint_update_all(cpu); @@ -856,15 +865,6 @@ static int cpu_post_load(void *opaque, int version_id) } } - /* - * Misaligned thumb pc is architecturally impossible. - * We have an assert in thumb_tr_translate_insn to verify this. - * Fail an incoming migrate to avoid this assert. - */ - if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { - return -1; - } - if (!kvm_enabled()) { pmu_op_finish(&cpu->env); } From patchwork Thu Feb 16 17:11:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 654055 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp85739wrc; Thu, 16 Feb 2023 09:14:04 -0800 (PST) X-Google-Smtp-Source: AK7set/zN32R1arDVKyIZP+fdlUDu/jUpGu9EVOkCnkE4e2XGDF5G/hX31gRKVWQtPILHWV+DDfN X-Received: by 2002:ad4:4eef:0:b0:537:7d76:ea7c with SMTP id dv15-20020ad44eef000000b005377d76ea7cmr13218164qvb.25.1676567644702; Thu, 16 Feb 2023 09:14:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676567644; cv=none; d=google.com; s=arc-20160816; b=gAWhE77Myqs85/Rlbf3WJIvxJ7buFbcDK+5qaAaTVlucFtsGl5cq0QxjaGlicaKzmD IA7r7+9dwRg8M4i10RDjqF+Fsqzh/cxyOqA7jh/cfvGUUUdaiB+TgpFqkJWbefsFkfdB SnMNHodfRfzW88jxDRdE3SqFm7+9rQ2xXaHdjp8DisI33GnQf+ysKAvallpVkakCq4Ls 0XyQWhLskdFh5A23VfYBNe7jPFlCSgCWQmir9itK5wGNLmOkUuD06WONexOxJZ3MQpVJ 4v5hK+WAAp5wTlNelYToBJ0UnrTSzIJu7CS/tWZ5nYkSvRCxHOmsO3HY8Os51lpNaoTJ dtRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rLdLg7FVc+e5cTbBnKEvOZt66LpMMYrauCjY8XnM1eg=; b=etvMhoquQGDeMWzfHhXm+1f1+8Y7umK2TX5sBDONiFS6S1B8nrnjlJ95OXs1ICr+hf 3WPosAOZBDeC62miW0Z1JtZWqiVdn6eNRBv8UO2We8a9bQ8jpiklioco4DLLrAaJGK5+ YOOS+s4t7Pmn407AGSw8HBE69AGL4cd3wHETx06288QKIyY0UE8wPfNLVW71mW6MlwSS PpmeGWL5zPhfKGm2zix87XtKShKydm+eY0PM3rQl1yM+p2wzsC1bLAd/OVlzWHXUlNCc l6eRjSMJWcei1IsELNhye8pT8EQlY4a5hi2+BYAsfJf/CFNo7WcolFIM4Y4MBWXPlFUw uNRQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DVMkLF61; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a5d4dcc000000b002c556a4f1casm2049107wru.42.2023.02.16.09.11.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 09:11:46 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/30] target/arm: Move cpregs code out of cpu.h Date: Thu, 16 Feb 2023 17:11:18 +0000 Message-Id: <20230216171123.2518285-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216171123.2518285-1-peter.maydell@linaro.org> References: <20230216171123.2518285-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Fabiano Rosas Since commit cf7c6d1004 ("target/arm: Split out cpregs.h") we now have a cpregs.h header which is more suitable for this code. Code moved verbatim. Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 98 +++++++++++++++++++++++++++++++++++++++++++++ target/arm/cpu.h | 91 ----------------------------------------- 2 files changed, 98 insertions(+), 91 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index efcf9181b97..1ee64e99de8 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -120,6 +120,104 @@ enum { ARM_CP_SME = 1 << 19, }; +/* + * Interface for defining coprocessor registers. + * Registers are defined in tables of arm_cp_reginfo structs + * which are passed to define_arm_cp_regs(). + */ + +/* + * When looking up a coprocessor register we look for it + * via an integer which encodes all of: + * coprocessor number + * Crn, Crm, opc1, opc2 fields + * 32 or 64 bit register (ie is it accessed via MRC/MCR + * or via MRRC/MCRR?) + * non-secure/secure bank (AArch32 only) + * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. + * (In this case crn and opc2 should be zero.) + * For AArch64, there is no 32/64 bit size distinction; + * instead all registers have a 2 bit op0, 3 bit op1 and op2, + * and 4 bit CRn and CRm. The encoding patterns are chosen + * to be easy to convert to and from the KVM encodings, and also + * so that the hashtable can contain both AArch32 and AArch64 + * registers (to allow for interprocessing where we might run + * 32 bit code on a 64 bit core). + */ +/* + * This bit is private to our hashtable cpreg; in KVM register + * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 + * in the upper bits of the 64 bit ID. + */ +#define CP_REG_AA64_SHIFT 28 +#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) + +/* + * To enable banking of coprocessor registers depending on ns-bit we + * add a bit to distinguish between secure and non-secure cpregs in the + * hashtable. + */ +#define CP_REG_NS_SHIFT 29 +#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) + +#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ + ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ + ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) + +#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ + (CP_REG_AA64_MASK | \ + ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ + ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ + ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ + ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ + ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ + ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) + +/* + * Convert a full 64 bit KVM register ID to the truncated 32 bit + * version used as a key for the coprocessor register hashtable + */ +static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) +{ + uint32_t cpregid = kvmid; + if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { + cpregid |= CP_REG_AA64_MASK; + } else { + if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { + cpregid |= (1 << 15); + } + + /* + * KVM is always non-secure so add the NS flag on AArch32 register + * entries. + */ + cpregid |= 1 << CP_REG_NS_SHIFT; + } + return cpregid; +} + +/* + * Convert a truncated 32 bit hashtable key into the full + * 64 bit KVM register ID. + */ +static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) +{ + uint64_t kvmid; + + if (cpregid & CP_REG_AA64_MASK) { + kvmid = cpregid & ~CP_REG_AA64_MASK; + kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; + } else { + kvmid = cpregid & ~(1 << 15); + if (cpregid & (1 << 15)) { + kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; + } else { + kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; + } + } + return kvmid; +} + /* * Valid values for ARMCPRegInfo state field, indicating which of * the AArch32 and AArch64 execution states this register is visible in. diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d623afe84af..12b1082537c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2559,97 +2559,6 @@ void arm_cpu_list(void); uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, uint32_t cur_el, bool secure); -/* Interface for defining coprocessor registers. - * Registers are defined in tables of arm_cp_reginfo structs - * which are passed to define_arm_cp_regs(). - */ - -/* When looking up a coprocessor register we look for it - * via an integer which encodes all of: - * coprocessor number - * Crn, Crm, opc1, opc2 fields - * 32 or 64 bit register (ie is it accessed via MRC/MCR - * or via MRRC/MCRR?) - * non-secure/secure bank (AArch32 only) - * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. - * (In this case crn and opc2 should be zero.) - * For AArch64, there is no 32/64 bit size distinction; - * instead all registers have a 2 bit op0, 3 bit op1 and op2, - * and 4 bit CRn and CRm. The encoding patterns are chosen - * to be easy to convert to and from the KVM encodings, and also - * so that the hashtable can contain both AArch32 and AArch64 - * registers (to allow for interprocessing where we might run - * 32 bit code on a 64 bit core). - */ -/* This bit is private to our hashtable cpreg; in KVM register - * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 - * in the upper bits of the 64 bit ID. - */ -#define CP_REG_AA64_SHIFT 28 -#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) - -/* To enable banking of coprocessor registers depending on ns-bit we - * add a bit to distinguish between secure and non-secure cpregs in the - * hashtable. - */ -#define CP_REG_NS_SHIFT 29 -#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) - -#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ - ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ - ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) - -#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ - (CP_REG_AA64_MASK | \ - ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ - ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ - ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ - ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ - ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ - ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) - -/* Convert a full 64 bit KVM register ID to the truncated 32 bit - * version used as a key for the coprocessor register hashtable - */ -static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) -{ - uint32_t cpregid = kvmid; - if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { - cpregid |= CP_REG_AA64_MASK; - } else { - if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { - cpregid |= (1 << 15); - } - - /* KVM is always non-secure so add the NS flag on AArch32 register - * entries. - */ - cpregid |= 1 << CP_REG_NS_SHIFT; - } - return cpregid; -} - -/* Convert a truncated 32 bit hashtable key into the full - * 64 bit KVM register ID. - */ -static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) -{ - uint64_t kvmid; - - if (cpregid & CP_REG_AA64_MASK) { - kvmid = cpregid & ~CP_REG_AA64_MASK; - kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; - } else { - kvmid = cpregid & ~(1 << 15); - if (cpregid & (1 << 15)) { - kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; - } else { - kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; - } - } - return kvmid; -} - /* Return the highest implemented Exception Level */ static inline int arm_highest_el(CPUARMState *env) { From patchwork Thu Feb 16 17:11:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 654053 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp85429wrc; Thu, 16 Feb 2023 09:13:28 -0800 (PST) X-Google-Smtp-Source: AK7set9tV/kM/WJ3mIqDtPtGQXSmhYd/p5i+C2uRlxifeKIaXswxFGG7uUpAqtVjWucPfvF/VcOr X-Received: by 2002:a05:6214:2aa2:b0:56e:9c74:74b7 with SMTP id js2-20020a0562142aa200b0056e9c7474b7mr10615483qvb.23.1676567608544; Thu, 16 Feb 2023 09:13:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676567608; cv=none; d=google.com; s=arc-20160816; b=pfYURP0yMkkgyqDyi74fyA2E6i9xXViUuBBkE8YoOnQUSGq4gPOhm8XSsbV/+xT1rP zh+TS9NJGy93/LNMkChMPG4hnZOWSGZXgYUhXed8N3cspTnS2X+dImm3OVtN8ofMsm1l PI1TxasQ0bx+BjvFha+VCmqAyKGHMsAdtV0IGybGz5rrNqdEzvyL9Aw34KtZNlIvgGxB dxPo7MGZiVweRncy2NptC1yCjwVKmwXEcCxA8US6xxFhtr6T5SsW0G+bRKMCYJ7viOKd GJ/1OM0tutUw4uvkOAqqSiIU3P+JsObZtZmraC4eOHbemILjzQ7JhbRInVl1S3NwHP4e NCKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=fKaIoyL82f1ne64Qgj6g8dHFUQLBIO6UYjkBABaWKfo=; b=pIs4fuVa10o6NclUebtVD1SGWawDkbjWBKvt750EqYOnpgiEMINBdKAMpzMa1cktg+ UkZZg9x0aq6s14aaxxDaob1+c2rV0QmjmzR7yXncRMeX/m4JOg60gZsyPd7rVlAOAM+Z 501aJWhwhmclNTHGYgWcJ8F6oQkOFwO1MWxgCQkqO1rUBRh96V4B93v5yOVMJjGLn/xS Hm4ihEL9CGDO/GPkziV2ezMqpeqR3xTzDg1WKglhOKDiszTaO5ja1ThXhzQbSdcuHeeP Ab26KlbaTWMvqC9Zy9tLXOMAKN0KBk1LSx5uZ63pbWILzC2rVoigfXwBaB8XWWdka9pE gsQw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DgMZthnn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a5d4dcc000000b002c556a4f1casm2049107wru.42.2023.02.16.09.11.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 09:11:47 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/30] tests/avocado: Skip tests that require a missing accelerator Date: Thu, 16 Feb 2023 17:11:19 +0000 Message-Id: <20230216171123.2518285-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216171123.2518285-1-peter.maydell@linaro.org> References: <20230216171123.2518285-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Fabiano Rosas If a test was tagged with the "accel" tag and the specified accelerator it not present in the qemu binary, cancel the test. We can now write tests without explicit calls to require_accelerator, just the tag is enough. Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- tests/avocado/avocado_qemu/__init__.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tests/avocado/avocado_qemu/__init__.py b/tests/avocado/avocado_qemu/__init__.py index 25a546842fa..a313e88c07e 100644 --- a/tests/avocado/avocado_qemu/__init__.py +++ b/tests/avocado/avocado_qemu/__init__.py @@ -274,6 +274,10 @@ def setUp(self): super().setUp('qemu-system-') + accel_required = self._get_unique_tag_val('accel') + if accel_required: + self.require_accelerator(accel_required) + self.machine = self.params.get('machine', default=self._get_unique_tag_val('machine')) From patchwork Thu Feb 16 17:11:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 654073 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp86761wrc; Thu, 16 Feb 2023 09:16:02 -0800 (PST) X-Google-Smtp-Source: AK7set/gHpMbseMdELtAK979RFBO+Fjcoipch05oykpPawDVua0u2WOW4vtTkHed0HLzVjOF72r5 X-Received: by 2002:a05:622a:1983:b0:3b6:2bb3:fb53 with SMTP id u3-20020a05622a198300b003b62bb3fb53mr12287845qtc.16.1676567762613; Thu, 16 Feb 2023 09:16:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676567762; cv=none; d=google.com; s=arc-20160816; b=zhuqCTevuq4VetRVybjdUa8RsNNlWtk7MA+SkI9VFPSKG5cE8J3g1u8XBu8JobTQyx JP6FeU+p8egRMo8YI/fKxE6UmxZ/Q9dRZ1Rt7o7s4Zmdkx8/rdUEXbYm8/qHSXJjtNO+ aknTXYuTZTLSCVflm32mGNPoRYhgdGRd+c2OvjpItyByXjZDVKuufrykS5g0ZlN5BvwK UUVB8LIbwugfU3cpjkKLPxaXkfT8Ljyf7+OdoKyv7z3tLETyn4W2GsjD1iwmvpFlnGVH xshEaw7CW5JJA5GVMFpZgdiOBEJfCSYqFXC91S6J4RVSm69YKWYSVf7bXmdscWmJTgWx Ovcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=tgMbUsRHeiMP1zN6oNigLk88zA1/eZdSv72d9GFz8HA=; b=efPU60oDB/NAy9TtyU+T/HeHuegGtrgpduNOshcpiKyDTT0lrfsJU2cYMljLRJz+Xs ef+b3aV3hoAcI63AuaDT+fcGPPWSD86cvgPJFdcV+npwxXmnpepkHmI1qRyC41hyKBwK mM5fDqdnYAUlMs9lHodzwi3vt6f9MqRrhPzb9fBYib3GphPHGUVLtrmwKUL9+dMUanio waTwHNubySM2MlJ279S7h+rbjKIozlMspeQ7oArcYanNCZONm7NrAsJe5NvdcKLFr6or Wq7iE/r5YB9tL9Dc2geD1GBSVwO/fI/BI03Ibmz6nNYJFmqlGPkx9X/onNX4xM6bYDdR DRUw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xzGzqmUf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a5d4dcc000000b002c556a4f1casm2049107wru.42.2023.02.16.09.11.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 09:11:47 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/30] tests/avocado: Tag TCG tests with accel:tcg Date: Thu, 16 Feb 2023 17:11:20 +0000 Message-Id: <20230216171123.2518285-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216171123.2518285-1-peter.maydell@linaro.org> References: <20230216171123.2518285-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Fabiano Rosas This allows the test to be skipped when TCG is not present in the QEMU binary. Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- tests/avocado/boot_linux_console.py | 1 + tests/avocado/reverse_debugging.py | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py index be60f8cda9a..574609bf43b 100644 --- a/tests/avocado/boot_linux_console.py +++ b/tests/avocado/boot_linux_console.py @@ -997,6 +997,7 @@ def test_arm_orangepi_uboot_netbsd9(self): def test_aarch64_raspi3_atf(self): """ + :avocado: tags=accel:tcg :avocado: tags=arch:aarch64 :avocado: tags=machine:raspi3b :avocado: tags=cpu:cortex-a53 diff --git a/tests/avocado/reverse_debugging.py b/tests/avocado/reverse_debugging.py index d2921e70c3b..680c314cfcc 100644 --- a/tests/avocado/reverse_debugging.py +++ b/tests/avocado/reverse_debugging.py @@ -173,6 +173,10 @@ def reverse_debugging(self, shift=7, args=None): vm.shutdown() class ReverseDebugging_X86_64(ReverseDebugging): + """ + :avocado: tags=accel:tcg + """ + REG_PC = 0x10 REG_CS = 0x12 def get_pc(self, g): @@ -190,6 +194,10 @@ def test_x86_64_pc(self): self.reverse_debugging() class ReverseDebugging_AArch64(ReverseDebugging): + """ + :avocado: tags=accel:tcg + """ + REG_PC = 32 # unidentified gitlab timeout problem From patchwork Thu Feb 16 17:11:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 654059 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp86143wrc; Thu, 16 Feb 2023 09:14:52 -0800 (PST) X-Google-Smtp-Source: AK7set9bHlf+OWxMAnoTB5PnngzOK7xMDOc+gFLZFaHGzNMr+uvy7fblNvCf/lnHSInzErjUPvS4 X-Received: by 2002:ac8:7f07:0:b0:3bd:1081:b939 with SMTP id f7-20020ac87f07000000b003bd1081b939mr1898219qtk.0.1676567691821; Thu, 16 Feb 2023 09:14:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676567691; cv=none; d=google.com; s=arc-20160816; b=Jca+RYdDmVaoNrT+zk+CrvIhmGoCbgrWQk51JjGGI/bDlzeM3r+RPABInZohpD6UfE QGsBP1mcse/gJ+z8VhtfxkpKADINfwt8thJ3u67n2hAJHv+A+nN+72ZWhnWJQxR3Wpwb hthiVCPPr0XCdgx0xduEdxHvStCh0tqfvRwUx5oWIB15NMQZKQA5dtiTk+6+WHpJJgaE 74DY6VuhKJ5U8ipO+Um+geTPsu9RV2bahoJUKKIvMjqpKj9rRUHErWDeWvkjWh6TM4dX hQ5E5vmVZBDAff8Sdou8PAPqpQbgQaIs2OCfPtLUoqqoCdvvqxHnjmYFZtMKg70wQuim RQzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=XVRtdPWy6SO/+ib4dr2eJvk7NAPUzEubpNbchybnbuU=; b=XeANeUAAFjy5QIPT6i7V+NgcjhQES9km9xawbclFlSdEpPLzA4xG6VArIL2HKdIhEq b8RsBoBBSBxQI1uboCr7MJEO7Hb1fxdBXdxhHuo0wrmxzSFnJxjkiogfeSzf8A9eYoVm EGrsxkvhyO3gxbbskjNLfWBvspcWGTUflUsWHsYoQNFG38fxFAhPRNf2n0NokOoT5x90 WuXeWNsIlqfVQV2uZScePkDC1qR3XexrYWr4k3TMqybZ2BwW0eB52dBjUcbM42rKxydX NzXC2TAj9g83s0Q/zeCRSsbn9UTKmNZx9jAoF+vDVmhaJiDX1L2nKh6a/AI9XvdD1bnp QITg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=P2VxbLao; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a5d4dcc000000b002c556a4f1casm2049107wru.42.2023.02.16.09.11.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 09:11:49 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/30] target/arm: Use "max" as default cpu for the virt machine with KVM Date: Thu, 16 Feb 2023 17:11:21 +0000 Message-Id: <20230216171123.2518285-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216171123.2518285-1-peter.maydell@linaro.org> References: <20230216171123.2518285-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Fabiano Rosas Now that the cortex-a15 is under CONFIG_TCG, use as default CPU for a KVM-only build the 'max' cpu. Note that we cannot use 'host' here because the qtests can run without any other accelerator (than qtest) and 'host' depends on KVM being enabled. Signed-off-by: Fabiano Rosas Acked-by: Richard Henderson Reviewed-by: Thomas Huth Signed-off-by: Peter Maydell --- hw/arm/virt.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 8d13e4486b1..ac626b3bef7 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3013,7 +3013,11 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) mc->minimum_page_bits = 12; mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; mc->cpu_index_to_instance_props = virt_cpu_index_to_props; +#ifdef CONFIG_TCG mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); +#else + mc->default_cpu_type = ARM_CPU_TYPE_NAME("max"); +#endif mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; mc->kvm_type = virt_kvm_type; assert(!mc->get_hotplug_handler); From patchwork Thu Feb 16 17:11:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 654060 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp86186wrc; Thu, 16 Feb 2023 09:14:57 -0800 (PST) X-Google-Smtp-Source: AK7set/adLtxKB1fqZeRP6zCcHDuim3jNsIZeImNPeDOx9MhVfI9AxKNQ2ogwEBk9yuLA5yDNjtb X-Received: by 2002:a05:6214:627:b0:56e:a6bb:47ac with SMTP id a7-20020a056214062700b0056ea6bb47acmr11586920qvx.31.1676567697699; Thu, 16 Feb 2023 09:14:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676567697; cv=none; d=google.com; s=arc-20160816; b=mxzsSTLfqvfOGjV0wJ8aLoMVUlpohWLapdRhYJHKkczLF7wYUzVvBRlVuXmOCRFl1f OT8RCzpZVMD30GFiBoFFXUAYMMCwGid3zxD1mr2xcPYhVFjDokaSdDiy6JmJROT8VjP7 5h8g6bqAoFftfEumlUqRiWpdJ9dOzWp3KzBE8QchxmCNlRLsgI72+FiSWsoOeCgsr4Pb Pm+KTptzlN4UrYyDD7dm35Gx4QT0amo3KXTF8j3Qr3pAJJ8RndhdHbJeGjvmGNSHL4HP EQjW3j7Yb2OprTqFky80jp+q2xMiq0S4+nxivXo5w/NsvhgEB4q7PJCETue3sukOHlHf +Ecw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=VvgfuLUSNrvN4aahIRpGRRD0M1CGU3JQCC4h/XD559w=; b=wNjbIgLsjY+caOTHI+sYwU6yiDkyFfVSEAn/RXBQwcXwOXBocQJMftzuyMpDnkIesk wl9s4lwb+Vo+2Jenj7Mli9e1DhC0aeMeg6fITOzuRCeXq/j89JzakLaauBtcpj0hB+ou 06mMJtPfrxV6ux4RsuAbFACtf+sjIBYBMFGLMno0FKadEgoqhUu3jLCcDhDZDnpsbOy4 lsksuCw3LjT5O8YPwoGr6Cwog3/NYsXIGgWk1zVJWIkuVRsKodsZF51Sozuos7LRyDjs t4m/MSgIvMVBI2thXOuCmnzwEjl9G7Ghh6figfJ3kzhB0Q0eudp31OP2LQn2rEKVlyxu 6GVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=J8c8hg6z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a5d4dcc000000b002c556a4f1casm2049107wru.42.2023.02.16.09.11.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 09:11:50 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/30] tests/qtest: arm-cpu-features: Match tests to required accelerators Date: Thu, 16 Feb 2023 17:11:22 +0000 Message-Id: <20230216171123.2518285-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216171123.2518285-1-peter.maydell@linaro.org> References: <20230216171123.2518285-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Fabiano Rosas Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson Acked-by: Thomas Huth Signed-off-by: Peter Maydell --- tests/qtest/arm-cpu-features.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index 8691802950c..1cb08138ad1 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -21,7 +21,7 @@ #define SVE_MAX_VQ 16 #define MACHINE "-machine virt,gic-version=max -accel tcg " -#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm -accel tcg " +#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm " #define QUERY_HEAD "{ 'execute': 'query-cpu-model-expansion', " \ " 'arguments': { 'type': 'full', " #define QUERY_TAIL "}}" @@ -607,31 +607,39 @@ int main(int argc, char **argv) { g_test_init(&argc, &argv, NULL); - qtest_add_data_func("/arm/query-cpu-model-expansion", - NULL, test_query_cpu_model_expansion); + if (qtest_has_accel("tcg")) { + qtest_add_data_func("/arm/query-cpu-model-expansion", + NULL, test_query_cpu_model_expansion); + } + + if (!g_str_equal(qtest_get_arch(), "aarch64")) { + goto out; + } /* * For now we only run KVM specific tests with AArch64 QEMU in * order avoid attempting to run an AArch32 QEMU with KVM on * AArch64 hosts. That won't work and isn't easy to detect. */ - if (g_str_equal(qtest_get_arch(), "aarch64") && qtest_has_accel("kvm")) { + if (qtest_has_accel("kvm")) { /* * This tests target the 'host' CPU type, so register it only if * KVM is available. */ qtest_add_data_func("/arm/kvm/query-cpu-model-expansion", NULL, test_query_cpu_model_expansion_kvm); - } - if (g_str_equal(qtest_get_arch(), "aarch64")) { - qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8", - NULL, sve_tests_sve_max_vq_8); - qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off", - NULL, sve_tests_sve_off); qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off", NULL, sve_tests_sve_off_kvm); } + if (qtest_has_accel("tcg")) { + qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8", + NULL, sve_tests_sve_max_vq_8); + qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off", + NULL, sve_tests_sve_off); + } + +out: return g_test_run(); } From patchwork Thu Feb 16 17:11:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 654046 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp84719wrc; Thu, 16 Feb 2023 09:12:18 -0800 (PST) X-Google-Smtp-Source: AK7set8noSsvV5o5BDm3lDWgux7/xd5F7DwJw63wx5m7T9FvXxdAkrI+fGyqL1sfPU+iyWY2symW X-Received: by 2002:ac8:4e89:0:b0:3b9:bc8c:c1fa with SMTP id 9-20020ac84e89000000b003b9bc8cc1famr5215683qtp.5.1676567538238; Thu, 16 Feb 2023 09:12:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676567538; cv=none; d=google.com; s=arc-20160816; b=RiiKWiRR9wf3FHXdLcHDBitzFRAMAdB3ulYFX+F3Zo6PFQscl8OU2Ehiz+/Bkgfd1x gCoGtKFFbDzvFKz+Qx0ijIJ9ZAUiGJbZDA62zXEWlFc9RnRYFnSI+41MBv7rSI9/LPtE tJ3kSxdCZe1pQcPwyE9mKbw28ii9R7cCJpeXLKQz/MFQxOJNHgOFBDFWMP2pmlm77WFo EVOL9TGetEo46VtnI5gMDGIdJycpiaBXCHI9kahXHBdqiVZpvrQlduuoLo30GNeFNZSG kQonZsi+fGZw/aqK7865+I4gNyTJSDT9hAYo63ExyZuBq+aM471aMax5PMgdeHehMg9D Rr9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=evm0X8KpwexdZmoAXGBwk/4u+Ox8rhWrbCkUwekUiFs=; b=PtWNt0zH2kyL9ddHR/h4bVpRlrXd6EPGxr20hjppaox5Rx21TiJYqSFoNViMjV6hnL iCR42XPHPvNVoNcN3Jya3n8iBwPHMCWLuTi7N0BlsLSBhw1r6S0SatVhBzvjh+SvMrhe oQhiuWrYLfBtwBU8T80u0lgT8IrXbXoi5nN7eNGh46tefcSPQBTeoO3XTs8Iv0U3Vx/E 3h8BdlGzoYdk1VIeCdL2CR4uJKCEurEfywYIOxWg25lGvBLvrB1kZcpphOvTfMIUELTH GNSFqBs/DGjsKOcMiFHzKrSLYrSWfSXw5B2wuAnx6O0z4sBXeNMitGEpwuW2BZ6snk2G F4mA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=o8Nk+uCC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a5d4dcc000000b002c556a4f1casm2049107wru.42.2023.02.16.09.11.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 09:11:51 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/30] tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG Date: Thu, 16 Feb 2023 17:11:23 +0000 Message-Id: <20230216171123.2518285-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216171123.2518285-1-peter.maydell@linaro.org> References: <20230216171123.2518285-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Fabiano Rosas These tests set -accel tcg, so restrict them to when TCG is present. Signed-off-by: Fabiano Rosas Acked-by: Richard Henderson Reviewed-by: Thomas Huth Signed-off-by: Peter Maydell --- tests/qtest/meson.build | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 222e1892fb5..29a4efb4c24 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -208,8 +208,8 @@ qtests_arm = \ # TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-test unconditional qtests_aarch64 = \ (cpu != 'arm' and unpack_edk2_blobs ? ['bios-tables-test'] : []) + \ - (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-test'] : []) + \ - (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) + \ + (config_all.has_key('CONFIG_TCG') and config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? \ + ['tpm-tis-device-test', 'tpm-tis-device-swtpm-test'] : []) + \ (config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test', 'fuzz-xlnx-dp-test'] : []) + \ (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \ ['arm-cpu-features',