From patchwork Tue May 7 11:59:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 163515 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:81:0:0:0:0 with SMTP id l1csp1250054ilm; Tue, 7 May 2019 05:01:03 -0700 (PDT) X-Google-Smtp-Source: APXvYqw9QcDkpScs0Zmc/awHGjVZ/HuFg3sdEqdqy6z4son7+87h0hOGkUmTKJzwIXx1pFgvouzX X-Received: by 2002:a1c:dcc2:: with SMTP id t185mr21960409wmg.143.1557230463179; Tue, 07 May 2019 05:01:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557230463; cv=none; d=google.com; s=arc-20160816; b=swNu0SXB6r59hZuXtekXygOUCoBWalw20T5JgaRU5QFcL20rSHn4wnYOxcrUR7cCAh jwIqlaqp/+Q6VniX/5KtyAvT/xc9lc/6csw/S8xFoCf9vx3JWiZ+mHvbAG0svo5pmdcg u5pgCcJdfLgq7PuthwjYC4yYWgxTrtTxKL4prx1m37RfKY6aRyrWEgMH/b3L0aA4T9OM vStISE1QJPcMnDg1nk1hEEiPM8BFOQV8VzRaVDPL8Lw6FHw2/hiAlKPAHsc9+bN2HChA 35j0jlJABbj92d5CzKKHaM+zLanYZ3CYYdk/8H3yTNpO3KEggEt6afReueo1RkiuRvKH mtDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=kMoTHcm1UDtivn+Jb4RW2U3g3XSUPQ7nsrsWmhvbMsU=; b=LQ4C6+ci5P4pwg1gVSBOPacYqGPEQpTQiwLf47Qp6yMQv0OCJy7ziAh5rn8fz7qEHu XsHLsBqGcAUxdDF0l4mxLUE8J+URkcRCPgc61CCRxyyB5a8QithRXTO7fuSZQ4TU1UOR MNdH4J3g1vSWOPHxPifNH44yLh4JI9E3KXIMhYb/iatujMyZ+KQrbx9MPUI/3YbC2DG2 3cMv9MNKflXcH6h3QymqbQadgDAHCQjRUhBsh2gz0kTbcDStIHyKzoQQEESE5/aXTI9u FAJSAyoW3Ty1fsr6jwbOrAg6Q4sVf5IWTfObhmdCBgcsk1PX2vKd51c3MBeyQgfw8/a/ g3CQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="r/qPJ2mv"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g3sm12348596wmf.9.2019.05.07.05.00.14 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 May 2019 05:00:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 7 May 2019 12:59:57 +0100 Message-Id: <20190507120011.18100-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190507120011.18100-1-peter.maydell@linaro.org> References: <20190507120011.18100-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::329 Subject: [Qemu-devel] [PULL 01/15] pc: Rearrange pc_system_firmware_init()'s legacy -drive loop X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Markus Armbruster The loop does two things: map legacy -drive to properties, and collect all the backends for use after the loop. The next patch will factor out the former for reuse in hw/arm/virt.c. To make that easier, rearrange the loop so it does the first thing first, and the second thing second. Signed-off-by: Markus Armbruster Reviewed-by: Laszlo Ersek Reviewed-by: Philippe Mathieu-Daudé Message-id: 20190416091348.26075-2-armbru@redhat.com Signed-off-by: Peter Maydell --- hw/i386/pc_sysfw.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) -- 2.20.1 diff --git a/hw/i386/pc_sysfw.c b/hw/i386/pc_sysfw.c index c6285407748..75925f5d3f7 100644 --- a/hw/i386/pc_sysfw.c +++ b/hw/i386/pc_sysfw.c @@ -280,21 +280,19 @@ void pc_system_firmware_init(PCMachineState *pcms, /* Map legacy -drive if=pflash to machine properties */ for (i = 0; i < ARRAY_SIZE(pcms->flash); i++) { - pflash_blk[i] = pflash_cfi01_get_blk(pcms->flash[i]); pflash_drv = drive_get(IF_PFLASH, 0, i); - if (!pflash_drv) { - continue; + if (pflash_drv) { + loc_push_none(&loc); + qemu_opts_loc_restore(pflash_drv->opts); + if (pflash_cfi01_get_blk(pcms->flash[i])) { + error_report("clashes with -machine"); + exit(1); + } + qdev_prop_set_drive(DEVICE(pcms->flash[i]), "drive", + blk_by_legacy_dinfo(pflash_drv), &error_fatal); + loc_pop(&loc); } - loc_push_none(&loc); - qemu_opts_loc_restore(pflash_drv->opts); - if (pflash_blk[i]) { - error_report("clashes with -machine"); - exit(1); - } - pflash_blk[i] = blk_by_legacy_dinfo(pflash_drv); - qdev_prop_set_drive(DEVICE(pcms->flash[i]), - "drive", pflash_blk[i], &error_fatal); - loc_pop(&loc); + pflash_blk[i] = pflash_cfi01_get_blk(pcms->flash[i]); } /* Reject gaps */ From patchwork Tue May 7 11:59:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 163522 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:81:0:0:0:0 with SMTP id l1csp1257968ilm; Tue, 7 May 2019 05:06:59 -0700 (PDT) X-Google-Smtp-Source: APXvYqwsxMid7jTAjwjmFUBTMQcEOMs4+vKrUVVQ3UjoavMiqz5eIl8TcgUaXLPM4pmJYu/d2KJQ X-Received: by 2002:a1c:4e0b:: with SMTP id g11mr2929486wmh.38.1557230818900; Tue, 07 May 2019 05:06:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557230818; cv=none; d=google.com; s=arc-20160816; b=AxcQ6eL+dlAvwcR70vcf4I6aHduO0eaAjLHGbcSN39aY6dCRHSDQtE0fjMBkVeBECn nQ3xlPfJfFQnLSh2L9DTLz6BFxqFZPf5dxpzLyro8F4fIbGmGzoWy1o+8g7EzmVbQyFn H7YxSU4/i19jMcbUcIqTVLpCAyRM62/clyrifr1U5P/ExQ18dsKDmb+tJty6EoCJQQc2 ivUoS4yi8CsKnWmNHWP55deDCYp6eTU4aoxS+VD7TBeATpT8AV64lsVQBWsCxBVL6acG 8HHAdaEcWfXbAT0ZlDQ5ktjO2L8h1J2sJeSYcMUY6YvGvRXgduyKElCNS5anqvSCnlWs lzvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=cukpgcV1j7F/Z6mZritMbWeaif27ugZHIZtYyXsN4A8=; b=fkNeZho+m7cAjl+YnqrLluDqnhXDcSJMHBVkKPllxnrmlhxn6O+zlkiMmUySwZAG32 gN4TiblwVywK7whNdKUVASBjb1VeuzdQl7A9D7E8ZSlQSYJnHI6aEZg/J6eYpKlmRA0Z zgX46hFsIU/+NDJSJMLZiySdHDVxm5YzdYfeQ+l7x4GzhfgelMuuWjbHmpxIWiU0jR8y 8g9XB4jiO7Z6VJ5GF7Oho06YvBHX77JNhk4pgwLwm5J6wCHLfgyNHvywi8mL31ytt09M jzsXrO35pf+qvz259QjctbN5zBHO3tCKQyamEX4paoqdcH7MmPBK72LHwoZOe/3WG+l5 vt1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Bi2HNjMP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g3sm12348596wmf.9.2019.05.07.05.00.15 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 May 2019 05:00:16 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 7 May 2019 12:59:58 +0100 Message-Id: <20190507120011.18100-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190507120011.18100-1-peter.maydell@linaro.org> References: <20190507120011.18100-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::432 Subject: [Qemu-devel] [PULL 02/15] pflash_cfi01: New pflash_cfi01_legacy_drive() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Markus Armbruster Factored out of pc_system_firmware_init() so the next commit can reuse it in hw/arm/virt.c. Signed-off-by: Markus Armbruster Reviewed-by: Laszlo Ersek Reviewed-by: Philippe Mathieu-Daudé Message-id: 20190416091348.26075-3-armbru@redhat.com Signed-off-by: Peter Maydell --- include/hw/block/flash.h | 1 + hw/block/pflash_cfi01.c | 28 ++++++++++++++++++++++++++++ hw/i386/pc_sysfw.c | 16 ++-------------- 3 files changed, 31 insertions(+), 14 deletions(-) -- 2.20.1 diff --git a/include/hw/block/flash.h b/include/hw/block/flash.h index a0f488732af..1acaf7de802 100644 --- a/include/hw/block/flash.h +++ b/include/hw/block/flash.h @@ -24,6 +24,7 @@ PFlashCFI01 *pflash_cfi01_register(hwaddr base, int be); BlockBackend *pflash_cfi01_get_blk(PFlashCFI01 *fl); MemoryRegion *pflash_cfi01_get_memory(PFlashCFI01 *fl); +void pflash_cfi01_legacy_drive(PFlashCFI01 *dev, DriveInfo *dinfo); /* pflash_cfi02.c */ diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index 16dfae14b80..333b7362771 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -44,9 +44,12 @@ #include "qapi/error.h" #include "qemu/timer.h" #include "qemu/bitops.h" +#include "qemu/error-report.h" #include "qemu/host-utils.h" #include "qemu/log.h" +#include "qemu/option.h" #include "hw/sysbus.h" +#include "sysemu/blockdev.h" #include "sysemu/sysemu.h" #include "trace.h" @@ -968,6 +971,31 @@ MemoryRegion *pflash_cfi01_get_memory(PFlashCFI01 *fl) return &fl->mem; } +/* + * Handle -drive if=pflash for machines that use properties. + * If @dinfo is null, do nothing. + * Else if @fl's property "drive" is already set, fatal error. + * Else set it to the BlockBackend with @dinfo. + */ +void pflash_cfi01_legacy_drive(PFlashCFI01 *fl, DriveInfo *dinfo) +{ + Location loc; + + if (!dinfo) { + return; + } + + loc_push_none(&loc); + qemu_opts_loc_restore(dinfo->opts); + if (fl->blk) { + error_report("clashes with -machine"); + exit(1); + } + qdev_prop_set_drive(DEVICE(fl), "drive", + blk_by_legacy_dinfo(dinfo), &error_fatal); + loc_pop(&loc); +} + static void postload_update_cb(void *opaque, int running, RunState state) { PFlashCFI01 *pfl = opaque; diff --git a/hw/i386/pc_sysfw.c b/hw/i386/pc_sysfw.c index 75925f5d3f7..751fcafa121 100644 --- a/hw/i386/pc_sysfw.c +++ b/hw/i386/pc_sysfw.c @@ -269,9 +269,7 @@ void pc_system_firmware_init(PCMachineState *pcms, { PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); int i; - DriveInfo *pflash_drv; BlockBackend *pflash_blk[ARRAY_SIZE(pcms->flash)]; - Location loc; if (!pcmc->pci_enabled) { old_pc_system_rom_init(rom_memory, true); @@ -280,18 +278,8 @@ void pc_system_firmware_init(PCMachineState *pcms, /* Map legacy -drive if=pflash to machine properties */ for (i = 0; i < ARRAY_SIZE(pcms->flash); i++) { - pflash_drv = drive_get(IF_PFLASH, 0, i); - if (pflash_drv) { - loc_push_none(&loc); - qemu_opts_loc_restore(pflash_drv->opts); - if (pflash_cfi01_get_blk(pcms->flash[i])) { - error_report("clashes with -machine"); - exit(1); - } - qdev_prop_set_drive(DEVICE(pcms->flash[i]), "drive", - blk_by_legacy_dinfo(pflash_drv), &error_fatal); - loc_pop(&loc); - } + pflash_cfi01_legacy_drive(pcms->flash[i], + drive_get(IF_PFLASH, 0, i)); pflash_blk[i] = pflash_cfi01_get_blk(pcms->flash[i]); } From patchwork Tue May 7 11:59:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 163526 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:81:0:0:0:0 with SMTP id l1csp1262156ilm; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g3sm12348596wmf.9.2019.05.07.05.00.17 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 May 2019 05:00:18 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 7 May 2019 12:59:59 +0100 Message-Id: <20190507120011.18100-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190507120011.18100-1-peter.maydell@linaro.org> References: <20190507120011.18100-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::429 Subject: [Qemu-devel] [PULL 03/15] hw/arm/virt: Support firmware configuration with -blockdev X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Markus Armbruster The ARM virt machines put firmware in flash memory. To configure it, you use -drive if=pflash,unit=0,... and optionally -drive if=pflash,unit=1,... Why two -drive? This permits setting up one part of the flash memory read-only, and the other part read/write. It also makes upgrading firmware on the host easier. Below the hood, we get two separate flash devices, because we were too lazy to improve our flash device models to support sector protection. The problem at hand is to do the same with -blockdev somehow, as one more step towards deprecating -drive. We recently solved this problem for x86 PC machines, in commit ebc29e1beab. See the commit message for design rationale. This commit solves it for ARM virt basically the same way: new machine properties pflash0, pflash1 forward to the onboard flash devices' properties. Requires creating the onboard devices in the .instance_init() method virt_instance_init(). The existing code to pick up drives defined with -drive if=pflash is replaced by code to desugar into the machine properties. There are a few behavioral differences, though: * The flash devices are always present (x86: only present if configured) * Flash base addresses and sizes are fixed (x86: sizes depend on images, mapped back to back below a fixed address) * -bios configures contents of first pflash (x86: -bios configures ROM contents) * -bios is rejected when first pflash is also configured with -machine pflash0=... (x86: bios is silently ignored then) * -machine pflash1=... does not require -machine pflash0=... (x86: it does). The actual code is a bit simpler than for x86 mostly due to the first two differences. Before the patch, all the action is in create_flash(), called from the machine's .init() method machvirt_init(): main() machine_run_board_init() machvirt_init() create_flash() create_one_flash() for flash[0] create configure includes obeying -drive if=pflash,unit=0 realize map fall back to -bios create_one_flash() for flash[1] create configure includes obeying -drive if=pflash,unit=1 realize map update FDT To make the machine properties work, we need to move device creation to its .instance_init() method virt_instance_init(). Another complication is machvirt_init()'s computation of @firmware_loaded: it predicts what create_flash() will do. Instead of predicting what create_flash()'s replacement virt_firmware_init() will do, I decided to have virt_firmware_init() return what it did. Requires calling it a bit earlier. Resulting call tree: main() current_machine = object_new() ... virt_instance_init() virt_flash_create() virt_flash_create1() for flash[0] create configure: set defaults become child of machine [NEW] add machine prop pflash0 as alias for drive [NEW] virt_flash_create1() for flash[1] create configure: set defaults become child of machine [NEW] add machine prop pflash1 as alias for drive [NEW] for all machine props from the command line: machine_set_property() ... property_set_alias() for machine props pflash0, pflash1 ... set_drive() for cfi.pflash01 prop drive this is how -machine pflash0=... etc set machine_run_board_init(current_machine); virt_firmware_init() pflash_cfi01_legacy_drive() legacy -drive if=pflash,unit=0 and =1 [NEW] virt_flash_map() virt_flash_map1() for flash[0] configure: num-blocks realize map virt_flash_map1() for flash[1] configure: num-blocks realize map fall back to -bios virt_flash_fdt() update FDT You have László to thank for making me explain this in detail. Signed-off-by: Markus Armbruster Acked-by: Laszlo Ersek Message-id: 20190416091348.26075-4-armbru@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/virt.h | 2 + hw/arm/virt.c | 202 +++++++++++++++++++++++++++--------------- 2 files changed, 132 insertions(+), 72 deletions(-) -- 2.20.1 diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 507517c603b..424070924ed 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -35,6 +35,7 @@ #include "qemu/notify.h" #include "hw/boards.h" #include "hw/arm/arm.h" +#include "hw/block/flash.h" #include "sysemu/kvm.h" #include "hw/intc/arm_gicv3_common.h" @@ -113,6 +114,7 @@ typedef struct { Notifier machine_done; DeviceState *platform_bus_dev; FWCfgState *fw_cfg; + PFlashCFI01 *flash[2]; bool secure; bool highmem; bool highmem_ecam; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 16ba67f7a76..5331ab71e22 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -30,6 +30,7 @@ #include "qemu/osdep.h" #include "qemu/units.h" +#include "qemu/option.h" #include "qapi/error.h" #include "hw/sysbus.h" #include "hw/arm/arm.h" @@ -871,25 +872,19 @@ static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic) } } -static void create_one_flash(const char *name, hwaddr flashbase, - hwaddr flashsize, const char *file, - MemoryRegion *sysmem) +#define VIRT_FLASH_SECTOR_SIZE (256 * KiB) + +static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, + const char *name, + const char *alias_prop_name) { - /* Create and map a single flash device. We use the same - * parameters as the flash devices on the Versatile Express board. + /* + * Create a single flash device. We use the same parameters as + * the flash devices on the Versatile Express board. */ - DriveInfo *dinfo = drive_get_next(IF_PFLASH); DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01); - SysBusDevice *sbd = SYS_BUS_DEVICE(dev); - const uint64_t sectorlength = 256 * 1024; - if (dinfo) { - qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), - &error_abort); - } - - qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength); - qdev_prop_set_uint64(dev, "sector-length", sectorlength); + qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); qdev_prop_set_uint8(dev, "width", 4); qdev_prop_set_uint8(dev, "device-width", 2); qdev_prop_set_bit(dev, "big-endian", false); @@ -898,41 +893,41 @@ static void create_one_flash(const char *name, hwaddr flashbase, qdev_prop_set_uint16(dev, "id2", 0x00); qdev_prop_set_uint16(dev, "id3", 0x00); qdev_prop_set_string(dev, "name", name); - qdev_init_nofail(dev); - - memory_region_add_subregion(sysmem, flashbase, - sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); - - if (file) { - char *fn; - int image_size; - - if (drive_get(IF_PFLASH, 0, 0)) { - error_report("The contents of the first flash device may be " - "specified with -bios or with -drive if=pflash... " - "but you cannot use both options at once"); - exit(1); - } - fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, file); - if (!fn) { - error_report("Could not find ROM image '%s'", file); - exit(1); - } - image_size = load_image_mr(fn, sysbus_mmio_get_region(sbd, 0)); - g_free(fn); - if (image_size < 0) { - error_report("Could not load ROM image '%s'", file); - exit(1); - } - } + object_property_add_child(OBJECT(vms), name, OBJECT(dev), + &error_abort); + object_property_add_alias(OBJECT(vms), alias_prop_name, + OBJECT(dev), "drive", &error_abort); + return PFLASH_CFI01(dev); } -static void create_flash(const VirtMachineState *vms, - MemoryRegion *sysmem, - MemoryRegion *secure_sysmem) +static void virt_flash_create(VirtMachineState *vms) { - /* Create two flash devices to fill the VIRT_FLASH space in the memmap. - * Any file passed via -bios goes in the first of these. + vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); + vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); +} + +static void virt_flash_map1(PFlashCFI01 *flash, + hwaddr base, hwaddr size, + MemoryRegion *sysmem) +{ + DeviceState *dev = DEVICE(flash); + + assert(size % VIRT_FLASH_SECTOR_SIZE == 0); + assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); + qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); + qdev_init_nofail(dev); + + memory_region_add_subregion(sysmem, base, + sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), + 0)); +} + +static void virt_flash_map(VirtMachineState *vms, + MemoryRegion *sysmem, + MemoryRegion *secure_sysmem) +{ + /* + * Map two flash devices to fill the VIRT_FLASH space in the memmap. * sysmem is the system memory space. secure_sysmem is the secure view * of the system, and the first flash device should be made visible only * there. The second flash device is visible to both secure and nonsecure. @@ -941,12 +936,20 @@ static void create_flash(const VirtMachineState *vms, */ hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; hwaddr flashbase = vms->memmap[VIRT_FLASH].base; - char *nodename; - create_one_flash("virt.flash0", flashbase, flashsize, - bios_name, secure_sysmem); - create_one_flash("virt.flash1", flashbase + flashsize, flashsize, - NULL, sysmem); + virt_flash_map1(vms->flash[0], flashbase, flashsize, + secure_sysmem); + virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, + sysmem); +} + +static void virt_flash_fdt(VirtMachineState *vms, + MemoryRegion *sysmem, + MemoryRegion *secure_sysmem) +{ + hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; + hwaddr flashbase = vms->memmap[VIRT_FLASH].base; + char *nodename; if (sysmem == secure_sysmem) { /* Report both flash devices as a single node in the DT */ @@ -959,7 +962,8 @@ static void create_flash(const VirtMachineState *vms, qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); g_free(nodename); } else { - /* Report the devices as separate nodes so we can mark one as + /* + * Report the devices as separate nodes so we can mark one as * only visible to the secure world. */ nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); @@ -982,6 +986,54 @@ static void create_flash(const VirtMachineState *vms, } } +static bool virt_firmware_init(VirtMachineState *vms, + MemoryRegion *sysmem, + MemoryRegion *secure_sysmem) +{ + int i; + BlockBackend *pflash_blk0; + + /* Map legacy -drive if=pflash to machine properties */ + for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { + pflash_cfi01_legacy_drive(vms->flash[i], + drive_get(IF_PFLASH, 0, i)); + } + + virt_flash_map(vms, sysmem, secure_sysmem); + + pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); + + if (bios_name) { + char *fname; + MemoryRegion *mr; + int image_size; + + if (pflash_blk0) { + error_report("The contents of the first flash device may be " + "specified with -bios or with -drive if=pflash... " + "but you cannot use both options at once"); + exit(1); + } + + /* Fall back to -bios */ + + fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); + if (!fname) { + error_report("Could not find ROM image '%s'", bios_name); + exit(1); + } + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); + image_size = load_image_mr(fname, mr); + g_free(fname); + if (image_size < 0) { + error_report("Could not load ROM image '%s'", bios_name); + exit(1); + } + } + + return pflash_blk0 || bios_name; +} + static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) { hwaddr base = vms->memmap[VIRT_FW_CFG].base; @@ -1421,7 +1473,7 @@ static void machvirt_init(MachineState *machine) MemoryRegion *secure_sysmem = NULL; int n, virt_max_cpus; MemoryRegion *ram = g_new(MemoryRegion, 1); - bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0); + bool firmware_loaded; bool aarch64 = true; /* @@ -1460,6 +1512,27 @@ static void machvirt_init(MachineState *machine) exit(1); } + if (vms->secure) { + if (kvm_enabled()) { + error_report("mach-virt: KVM does not support Security extensions"); + exit(1); + } + + /* + * The Secure view of the world is the same as the NonSecure, + * but with a few extra devices. Create it as a container region + * containing the system memory at low priority; any secure-only + * devices go in at higher priority and take precedence. + */ + secure_sysmem = g_new(MemoryRegion, 1); + memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", + UINT64_MAX); + memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); + } + + firmware_loaded = virt_firmware_init(vms, sysmem, + secure_sysmem ?: sysmem); + /* If we have an EL3 boot ROM then the assumption is that it will * implement PSCI itself, so disable QEMU's internal implementation * so it doesn't get in the way. Instead of starting secondary @@ -1505,23 +1578,6 @@ static void machvirt_init(MachineState *machine) exit(1); } - if (vms->secure) { - if (kvm_enabled()) { - error_report("mach-virt: KVM does not support Security extensions"); - exit(1); - } - - /* The Secure view of the world is the same as the NonSecure, - * but with a few extra devices. Create it as a container region - * containing the system memory at low priority; any secure-only - * devices go in at higher priority and take precedence. - */ - secure_sysmem = g_new(MemoryRegion, 1); - memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", - UINT64_MAX); - memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); - } - create_fdt(vms); possible_cpus = mc->possible_cpu_arch_ids(machine); @@ -1610,7 +1666,7 @@ static void machvirt_init(MachineState *machine) &machine->device_memory->mr); } - create_flash(vms, sysmem, secure_sysmem ? secure_sysmem : sysmem); + virt_flash_fdt(vms, sysmem, secure_sysmem); create_gic(vms, pic); @@ -1956,6 +2012,8 @@ static void virt_instance_init(Object *obj) NULL); vms->irqmap = a15irqmap; + + virt_flash_create(vms); } static const TypeInfo virt_machine_info = { From patchwork Tue May 7 12:00:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 163520 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:81:0:0:0:0 with SMTP id l1csp1257852ilm; Tue, 7 May 2019 05:06:53 -0700 (PDT) X-Google-Smtp-Source: APXvYqxHwlT/7rMNJOu2/YJSP8kU86m9Uz1+kOMbGN5HnUDZhqlACsXUTNvABFaD4awz3ZFYZy38 X-Received: by 2002:a1c:1c8:: with SMTP id 191mr12794819wmb.101.1557230813522; Tue, 07 May 2019 05:06:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557230813; cv=none; d=google.com; s=arc-20160816; b=VQAUQTD5tRYrRXg9xvKtAWg+joiroCeJ59lpb3uBmroVYczA7q8sqDeYUeuiBwZuLK fyGiMCxOesPrhuRrZJur2YfmmPxKzvwzPeGIKS/VK6wt9erB1Urjn0pev3vqqyhnq3kO SrlCN6l3Vi8qOU5+NXfP3vmUphCiPvP6WUKN3kKRvfXfLgo3JpNS7ywPE173JJt3TdjF +4o+AyTWca/Ds66TaY10PL9qyYwho1S3PDU5tZjSni7Vx7Y/TgFNyFit9TLWWgDp1w8s Mqc6ZbQjhx6O9IAkOJ4Z6ZVZMh+mrVK1c+o6sGZJMd4zm/hvpN8a7fufYcdOAd5VlXKr Ha8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=rDd8j3zLrg/PkW3/m3AjSO85H/8lBtQfTCQzKKkNESw=; b=srxLa0dy14kKvWEBolxdMi78k3iRBSNbPcPYKd4BdBSW7Ec4OrhFkfOUNmLrMQmd0e nf2M7lsXJ1vcBTeIpb0JpIuOwOJ2R2xI7sJY7N7Xmju2WXVgeYvQVjpo0vVhH0KAbGhR dkfztnUbJYSisb9ij1Sk3pvfIt00gTnLRm9CtPDHVDtYuRW5JXbn8F6kpmCIIZX4rEt+ M8ozFgWL0hhDf8zKAWB6LxsseMhpE+91FqmIDBtmM4/ZE+XI9Nc0M/4Lqz0k9gTl5HeJ 5p4RjWkeTmowSAZDR1OAlnB4BRDnqOgL50sWeaX7yzcc/9YQ/I7M46U13/2XvUh3qMPz AMsw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=JgJcs7K6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g3sm12348596wmf.9.2019.05.07.05.00.18 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 May 2019 05:00:19 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 7 May 2019 13:00:00 +0100 Message-Id: <20190507120011.18100-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190507120011.18100-1-peter.maydell@linaro.org> References: <20190507120011.18100-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PULL 04/15] hw/arm/raspi: Diagnose requests for too much RAM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The Raspberry Pi boards have a physical memory map which does not allow for more than 1GB of RAM. Currently if the user tries to ask for more then we fail in a confusing way: $ qemu-system-aarch64 --machine raspi3 -m 8G Unexpected error in visit_type_uintN() at qapi/qapi-visit-core.c:164: qemu-system-aarch64: Parameter 'vcram-base' expects uint32_t Aborted (core dumped) Catch this earlier and diagnose it with a more friendly message: $ qemu-system-aarch64 --machine raspi3 -m 8G qemu-system-aarch64: Requested ram size is too large for this machine: maximum is 1GB Fixes: https://bugs.launchpad.net/qemu/+bug/1794187 Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Wainer dos Santos Moschetta --- hw/arm/raspi.c | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.20.1 diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 66899c28dc1..fe2bb511b98 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -12,6 +12,7 @@ */ #include "qemu/osdep.h" +#include "qemu/units.h" #include "qapi/error.h" #include "qemu-common.h" #include "cpu.h" @@ -175,6 +176,12 @@ static void raspi_init(MachineState *machine, int version) BusState *bus; DeviceState *carddev; + if (machine->ram_size > 1 * GiB) { + error_report("Requested ram size is too large for this machine: " + "maximum is 1GB"); + exit(1); + } + object_initialize(&s->soc, sizeof(s->soc), version == 3 ? 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g3sm12348596wmf.9.2019.05.07.05.00.20 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 May 2019 05:00:20 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 7 May 2019 13:00:01 +0100 Message-Id: <20190507120011.18100-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190507120011.18100-1-peter.maydell@linaro.org> References: <20190507120011.18100-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PULL 05/15] arm: Allow system registers for KVM guests to be changed by QEMU code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" At the moment the Arm implementations of kvm_arch_{get,put}_registers() don't support having QEMU change the values of system registers (aka coprocessor registers for AArch32). This is because although kvm_arch_get_registers() calls write_list_to_cpustate() to update the CPU state struct fields (so QEMU code can read the values in the usual way), kvm_arch_put_registers() does not call write_cpustate_to_list(), meaning that any changes to the CPU state struct fields will not be passed back to KVM. The rationale for this design is documented in a comment in the AArch32 kvm_arch_put_registers() -- writing the values in the cpregs list into the CPU state struct is "lossy" because the write of a register might not succeed, and so if we blindly copy the CPU state values back again we will incorrectly change register values for the guest. The assumption was that no QEMU code would need to write to the registers. However, when we implemented debug support for KVM guests, we broke that assumption: the code to handle "set the guest up to take a breakpoint exception" does so by updating various guest registers including ESR_EL1. Support this by making kvm_arch_put_registers() synchronize CPU state back into the list. We sync only those registers where the initial write succeeds, which should be sufficient. This commit is the same as commit 823e1b3818f9b10b824ddc which we had to revert in commit 942f99c825fc94c8b1a4, except that the bug which was preventing EDK2 guest firmware running has been fixed: kvm_arm_reset_vcpu() now calls write_list_to_cpustate(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Eric Auger --- target/arm/cpu.h | 9 ++++++++- target/arm/helper.c | 27 +++++++++++++++++++++++++-- target/arm/kvm.c | 8 ++++++++ target/arm/kvm32.c | 20 ++------------------ target/arm/kvm64.c | 2 ++ target/arm/machine.c | 2 +- 6 files changed, 46 insertions(+), 22 deletions(-) -- 2.20.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 22bc6e00ab9..0304ddd9f11 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2610,18 +2610,25 @@ bool write_list_to_cpustate(ARMCPU *cpu); /** * write_cpustate_to_list: * @cpu: ARMCPU + * @kvm_sync: true if this is for syncing back to KVM * * For each register listed in the ARMCPU cpreg_indexes list, write * its value from the ARMCPUState structure into the cpreg_values list. * This is used to copy info from TCG's working data structures into * KVM or for outbound migration. * + * @kvm_sync is true if we are doing this in order to sync the + * register state back to KVM. In this case we will only update + * values in the list if the previous list->cpustate sync actually + * successfully wrote the CPU state. Otherwise we will keep the value + * that is in the list. + * * Returns: true if all register values were read correctly, * false if some register was unknown or could not be read. * Note that we do not stop early on failure -- we will attempt * reading all registers in the list. */ -bool write_cpustate_to_list(ARMCPU *cpu); +bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); #define ARM_CPUID_TI915T 0x54029152 #define ARM_CPUID_TI925T 0x54029252 diff --git a/target/arm/helper.c b/target/arm/helper.c index 81a92ab4911..9b805d0e6bd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -266,7 +266,7 @@ static bool raw_accessors_invalid(const ARMCPRegInfo *ri) return true; } -bool write_cpustate_to_list(ARMCPU *cpu) +bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync) { /* Write the coprocessor state from cpu->env to the (index,value) list. */ int i; @@ -275,6 +275,7 @@ bool write_cpustate_to_list(ARMCPU *cpu) for (i = 0; i < cpu->cpreg_array_len; i++) { uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); const ARMCPRegInfo *ri; + uint64_t newval; ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); if (!ri) { @@ -284,7 +285,29 @@ bool write_cpustate_to_list(ARMCPU *cpu) if (ri->type & ARM_CP_NO_RAW) { continue; } - cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri); + + newval = read_raw_cp_reg(&cpu->env, ri); + if (kvm_sync) { + /* + * Only sync if the previous list->cpustate sync succeeded. + * Rather than tracking the success/failure state for every + * item in the list, we just recheck "does the raw write we must + * have made in write_list_to_cpustate() read back OK" here. + */ + uint64_t oldval = cpu->cpreg_values[i]; + + if (oldval == newval) { + continue; + } + + write_raw_cp_reg(&cpu->env, ri, oldval); + if (read_raw_cp_reg(&cpu->env, ri) != oldval) { + continue; + } + + write_raw_cp_reg(&cpu->env, ri, newval); + } + cpu->cpreg_values[i] = newval; } return ok; } diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 79a79f01905..59956346126 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -497,6 +497,14 @@ void kvm_arm_reset_vcpu(ARMCPU *cpu) fprintf(stderr, "write_kvmstate_to_list failed\n"); abort(); } + /* + * Sync the reset values also into the CPUState. This is necessary + * because the next thing we do will be a kvm_arch_put_registers() + * which will update the list values from the CPUState before copying + * the list values back to KVM. It's OK to ignore failure returns here + * for the same reason we do so in kvm_arch_get_registers(). + */ + write_list_to_cpustate(cpu); } /* diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index 50327989dcc..327375f6252 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -384,24 +384,8 @@ int kvm_arch_put_registers(CPUState *cs, int level) return ret; } - /* Note that we do not call write_cpustate_to_list() - * here, so we are only writing the tuple list back to - * KVM. This is safe because nothing can change the - * CPUARMState cp15 fields (in particular gdb accesses cannot) - * and so there are no changes to sync. In fact syncing would - * be wrong at this point: for a constant register where TCG and - * KVM disagree about its value, the preceding write_list_to_cpustate() - * would not have had any effect on the CPUARMState value (since the - * register is read-only), and a write_cpustate_to_list() here would - * then try to write the TCG value back into KVM -- this would either - * fail or incorrectly change the value the guest sees. - * - * If we ever want to allow the user to modify cp15 registers via - * the gdb stub, we would need to be more clever here (for instance - * tracking the set of registers kvm_arch_get_registers() successfully - * managed to update the CPUARMState with, and only allowing those - * to be written back up into the kernel). - */ + write_cpustate_to_list(cpu, true); + if (!write_list_to_kvmstate(cpu, level)) { return EINVAL; } diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 089af9c5f02..e3ba1492482 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -838,6 +838,8 @@ int kvm_arch_put_registers(CPUState *cs, int level) return ret; } + write_cpustate_to_list(cpu, true); + if (!write_list_to_kvmstate(cpu, level)) { return EINVAL; } diff --git a/target/arm/machine.c b/target/arm/machine.c index 09567d4fc66..96d032f2a7e 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -646,7 +646,7 @@ static int cpu_pre_save(void *opaque) abort(); } } else { - if (!write_cpustate_to_list(cpu)) { + if (!write_cpustate_to_list(cpu, false)) { /* This should never fail. */ abort(); } From patchwork Tue May 7 12:00:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 163527 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:81:0:0:0:0 with SMTP id l1csp1262222ilm; Tue, 7 May 2019 05:10:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqwNxyzrPWXQ8b+PL6s6yfGWkaY8w9TAYQlrGbbWEnIz52wY22vr9EAJl+R3BlaW00r949sG X-Received: by 2002:adf:9cc8:: with SMTP id h8mr16599773wre.308.1557231038663; Tue, 07 May 2019 05:10:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557231038; cv=none; d=google.com; s=arc-20160816; b=FNUQThjKGXAQW5WL0EXLMXErU6D8Vkd18VAs0YotzXhhiKVr9N8sr4TPyHr8mIvItJ mf7KQ48ZWD3R0phJM36hE168FYGIcY3SzwhhuS9H8UfP540cNc6+BEkIJMk+Po7rz9W7 hwfB2ZbG9vEnYV14WAf8MJigEbBlv7jjbEyWACz+TvborV62B/nO+IWePjcLcs28cli0 AVcPRs7oSYRhxcfasa7PWzjj11CSljYkGnSrY3fmb2L6jOcvSiNJuWK5zxixDRlVnI/F X2cGm3vlvzeDuNbq2DbSWi4jbmjv1k4O6bt/coJ3BdEwtbmi7lDkYTAO0goAwAOgwRYv nMKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=PrRjWEvXDJOpA+k1xEwYJM/zCv1rnAwRsRuPQ3BARac=; b=ZWcgJxUYrYjmSObIXeTYy2tIGZll5imOuiQedP+ACKAygWvA5CaL5XXn068rdQuYum H0YrMFm3aVq5CqTKuTimXeynmY+p8gpwG4MoLuWXVh/cGqfAN7fM2I042m0WVNWOeb2H D/JgqgB3kxjGdpTdb6tS2HbdkrH+c2rho0vSCE6Tw/eVA6olhkW1mC/n4mblXfoO2XkQ WYYyY146BXshNDU9PrHOpaXzXBzuY7KNSGLXdsrC/GmYOhXXoN03GoHxW9zeWlUaHbPB 21PeRuOyG1PouHWFolR8/vSWpsJDg+YKtOcqFWN9MmFG3Q10aKNubFi44YGb+UIhG+tw yk3g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SEFkh4Ts; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g3sm12348596wmf.9.2019.05.07.05.00.21 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 May 2019 05:00:22 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 7 May 2019 13:00:02 +0100 Message-Id: <20190507120011.18100-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190507120011.18100-1-peter.maydell@linaro.org> References: <20190507120011.18100-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::330 Subject: [Qemu-devel] [PULL 06/15] arm: aspeed: Set SDRAM size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Joel Stanley We currently use Qemu's default of 128MB. As we know how much ram each machine ships with, make it easier on users by setting a default. It can still be overridden with -m on the command line. Signed-off-by: Joel Stanley Reviewed-by: Andrew Jeffery Reviewed-by: Richard Henderson Message-id: 20190503022958.1394-1-joel@jms.id.au Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- include/hw/arm/aspeed.h | 1 + hw/arm/aspeed.c | 8 ++++++++ 2 files changed, 9 insertions(+) -- 2.20.1 diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h index 325c091d09e..02073a6b4d6 100644 --- a/include/hw/arm/aspeed.h +++ b/include/hw/arm/aspeed.h @@ -22,6 +22,7 @@ typedef struct AspeedBoardConfig { const char *spi_model; uint32_t num_cs; void (*i2c_init)(AspeedBoardState *bmc); + uint32_t ram; } AspeedBoardConfig; #define TYPE_ASPEED_MACHINE MACHINE_TYPE_NAME("aspeed") diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 1c23ebd9925..29d225ed140 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -25,6 +25,7 @@ #include "sysemu/block-backend.h" #include "hw/loader.h" #include "qemu/error-report.h" +#include "qemu/units.h" static struct arm_boot_info aspeed_board_binfo = { .board_id = -1, /* device-tree-only board */ @@ -331,6 +332,9 @@ static void aspeed_machine_class_init(ObjectClass *oc, void *data) mc->no_floppy = 1; mc->no_cdrom = 1; mc->no_parallel = 1; + if (board->ram) { + mc->default_ram_size = board->ram; + } amc->board = board; } @@ -352,6 +356,7 @@ static const AspeedBoardConfig aspeed_boards[] = { .spi_model = "mx25l25635e", .num_cs = 1, .i2c_init = palmetto_bmc_i2c_init, + .ram = 256 * MiB, }, { .name = MACHINE_TYPE_NAME("ast2500-evb"), .desc = "Aspeed AST2500 EVB (ARM1176)", @@ -361,6 +366,7 @@ static const AspeedBoardConfig aspeed_boards[] = { .spi_model = "mx25l25635e", .num_cs = 1, .i2c_init = ast2500_evb_i2c_init, + .ram = 512 * MiB, }, { .name = MACHINE_TYPE_NAME("romulus-bmc"), .desc = "OpenPOWER Romulus BMC (ARM1176)", @@ -370,6 +376,7 @@ static const AspeedBoardConfig aspeed_boards[] = { .spi_model = "mx66l1g45g", .num_cs = 2, .i2c_init = romulus_bmc_i2c_init, + .ram = 512 * MiB, }, { .name = MACHINE_TYPE_NAME("witherspoon-bmc"), .desc = "OpenPOWER Witherspoon BMC (ARM1176)", @@ -379,6 +386,7 @@ static const AspeedBoardConfig aspeed_boards[] = { .spi_model = "mx66l1g45g", .num_cs = 2, .i2c_init = witherspoon_bmc_i2c_init, + .ram = 512 * MiB, }, }; From patchwork Tue May 7 12:00:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 163517 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:81:0:0:0:0 with SMTP id l1csp1250202ilm; Tue, 7 May 2019 05:01:10 -0700 (PDT) X-Google-Smtp-Source: APXvYqwaJCKU0EjSIgN7/V6CsEi/JxM1/7hUmQ9f0PpFj95bfMiHKi3r8s9Otf6yu70M3auO9Gq0 X-Received: by 2002:a1c:6502:: with SMTP id z2mr19897218wmb.119.1557230470701; Tue, 07 May 2019 05:01:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557230470; cv=none; d=google.com; s=arc-20160816; b=QBeeNNkb5x6jSfATB74jSh5FmsMW1qFOaK/VkwlvUsXCqm61Fe9OD32/PmpY7IqmGE AQIF7MltCcYAQxCtYV5mMqDU1A+Junp28AkD/m9zxbPwsWyrmRL/35Tt3hS4VUAI088h MMqjYfN0dmCdeXqrG4fTlgiUMvI9E8Bo48Umf96Pr5/iaxlaOQYLvMx8UPCVprP/hLJV ppMxVcA3XlV3razo2vguRuDjcoNf5tVb2b2mbB1vmylFb3byLMUzcK2sTlhiBmew/gEt 7ix2bqQhkdxO91ROZF6+YyOLhwgWAWSQChKtWVwiYBqysgJoayss8FLIUHfHojSMFLSV F/Hw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=Am1J2dJAVo3jcOoloT8MAdmJNelCyLiGsCZp2pMysc4=; b=UbBYWmPIiwn17PZAuqndf5wWi9jWw4hLayhq9iacu7CmtNYCa1B3eGtjqGiZ8Ex5gy eWh1twTJugWBTipGB6Wum0EYgWg4ws6jUxNNncBuCe41KmOU6Hj90yW0aaHf65kqg3xe 2fPt4lwdK3GwSNoqB9BwXvcMSQUHkJLT1cquK0NMby84v1lxxEAuI5Ur3X+nSz0Td4fJ YQnYnCjoA/ldd2uBWwi45D9GiXvlK/2XAywnnfOaq6LxILf3r8RywHUEyVJZfNC5nClf bCfl6djfUWjg0vI0ZalHwVRWgXZ8h/dDGlvcvO5n4eO4g6D9TV1l4Pd/tHRbYlswCU0R gOjg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gos9+dXd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g3sm12348596wmf.9.2019.05.07.05.00.23 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 May 2019 05:00:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 7 May 2019 13:00:03 +0100 Message-Id: <20190507120011.18100-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190507120011.18100-1-peter.maydell@linaro.org> References: <20190507120011.18100-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32f Subject: [Qemu-devel] [PULL 07/15] QEMU_PACKED: Remove gcc_struct attribute in Windows non x86 targets X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Cao Jiaxi gcc_struct is for x86 only, and it generates an warning on ARM64 Clang/MinGW targets. Signed-off-by: Cao Jiaxi Reviewed-by: Thomas Huth Message-id: 20190503003618.10089-1-driver1998@foxmail.com [PMM: dropped the slirp change as slirp is now a submodule] Signed-off-by: Peter Maydell --- contrib/libvhost-user/libvhost-user.h | 2 +- include/qemu/compiler.h | 2 +- scripts/cocci-macro-file.h | 7 ++++++- 3 files changed, 8 insertions(+), 3 deletions(-) -- 2.20.1 diff --git a/contrib/libvhost-user/libvhost-user.h b/contrib/libvhost-user/libvhost-user.h index 414ceb0a2f9..78b33306e81 100644 --- a/contrib/libvhost-user/libvhost-user.h +++ b/contrib/libvhost-user/libvhost-user.h @@ -148,7 +148,7 @@ typedef struct VhostUserInflight { uint16_t queue_size; } VhostUserInflight; -#if defined(_WIN32) +#if defined(_WIN32) && (defined(__x86_64__) || defined(__i386__)) # define VU_PACKED __attribute__((gcc_struct, packed)) #else # define VU_PACKED __attribute__((packed)) diff --git a/include/qemu/compiler.h b/include/qemu/compiler.h index 296b2fd5727..09fc44cca45 100644 --- a/include/qemu/compiler.h +++ b/include/qemu/compiler.h @@ -28,7 +28,7 @@ #define QEMU_SENTINEL __attribute__((sentinel)) -#if defined(_WIN32) +#if defined(_WIN32) && (defined(__x86_64__) || defined(__i386__)) # define QEMU_PACKED __attribute__((gcc_struct, packed)) #else # define QEMU_PACKED __attribute__((packed)) diff --git a/scripts/cocci-macro-file.h b/scripts/cocci-macro-file.h index e485cdccae8..c6bbc05ba3e 100644 --- a/scripts/cocci-macro-file.h +++ b/scripts/cocci-macro-file.h @@ -23,7 +23,12 @@ #define QEMU_NORETURN __attribute__ ((__noreturn__)) #define QEMU_WARN_UNUSED_RESULT __attribute__((warn_unused_result)) #define QEMU_SENTINEL __attribute__((sentinel)) -#define QEMU_PACKED __attribute__((gcc_struct, packed)) + +#if defined(_WIN32) && (defined(__x86_64__) || defined(__i386__)) +# define QEMU_PACKED __attribute__((gcc_struct, packed)) +#else +# define QEMU_PACKED __attribute__((packed)) +#endif #define cat(x,y) x ## y #define cat2(x,y) cat(x,y) From patchwork Tue May 7 12:00:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 163529 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:81:0:0:0:0 with SMTP id l1csp1264250ilm; Tue, 7 May 2019 05:12:21 -0700 (PDT) X-Google-Smtp-Source: APXvYqze44wlDvFLqncLrE1xCE/LUQUBigR9BXPRwIY0bB1rPK2/viVGjFP81YzKEOBtlaoGwt7p X-Received: by 2002:a7b:ca42:: with SMTP id m2mr20820390wml.35.1557231141131; Tue, 07 May 2019 05:12:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557231141; cv=none; d=google.com; s=arc-20160816; b=rT18ULkpDl43Raqa0rbRwYK33LUlhK7wWuqNkIpyfpJRQfNz8+IAf/Cwtqc1EYkaK1 0JWDmNXlqPH2KG12GKmX5h6d8XONBm5HIlFldCJfduibkQuQUe/7cBtxWWkeGVXXCzgD 15Tu8F+/qDXSF0L3rBA5uqwFGKJWct2E0RUmmAVeFY9E1xJ9f1JpZcUL8ciVg/W8r7mx csExNychSjG2kIgD5nR9pSbri0Q5SbEzNcoTurhjs0OrGXB4qgKT1r+S/Qmh7c7NLNzE llvnHfvGPBZa+YgG+rnKVvWJKrHooa84qQIkGGBUt0NIe3jTZlf+VXCvoqoJePT7TlGu DPMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=X9+rr2bCSDZG/nCniXr98w168+IzhYcZne15QwzLe+E=; b=ORR4Iv0NIGO3BuuI0C7LB6I3+zTMRspT9uTJp1i0/DDfACWNNpb3vwuRYRNcutcTFS yTt5swJQoDsbxlrg+pQ1ogJYllY9/Lqq40/XwL8PGhF+tvZiiPGuhCCfbX7GOaC0Kvfa AUpLGVGRTP1QatI9BT6tDnbWn6KSbhjnWp0XJjeJXNyWgcgv1soCLcVyfm2OmBcC5bEK 12/v6WuYIY+8XWGmNJu5H/wnDoNpgbje8OD4sDcd619mvsb8udnXqrNcFOwWrOWufR0Z LCwyMM76yPpVnBwCg0MS8AJphmrHEc7oEaLug0dk6P66i28CbYD6fWbeD8qM5L7eX1WA upPQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=P1TFtT+v; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o15si9615595wrv.97.2019.05.07.05.12.20 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 07 May 2019 05:12:21 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=P1TFtT+v; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:45787 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hNyxI-0000e6-5L for patch@linaro.org; Tue, 07 May 2019 08:12:20 -0400 Received: from eggs.gnu.org ([209.51.188.92]:44925) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hNyls-0007fM-Pv for qemu-devel@nongnu.org; Tue, 07 May 2019 08:00:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hNyln-0003hq-DL for qemu-devel@nongnu.org; Tue, 07 May 2019 08:00:32 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:39864) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hNyln-0003cx-3k for qemu-devel@nongnu.org; Tue, 07 May 2019 08:00:27 -0400 Received: by mail-wr1-x432.google.com with SMTP id v10so9675843wrt.6 for ; Tue, 07 May 2019 05:00:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=X9+rr2bCSDZG/nCniXr98w168+IzhYcZne15QwzLe+E=; b=P1TFtT+vueqVZhZXCKNUxnc8miDmySU0De8UEeP5b0fw1nOenYECcV96822hNpHXK1 QW25QBo0695Xp17ywA/Ud5TOz4ER0TnTx/btTItSZt94Zg/mNRtNbeVavkDHHIYUgRau 0neMhiOqyFdc1wJRwpT1G8qDtlvGNb8hWbrqiCHWDlaZYVEm/YQSyUuKkMYz6rl9s2AM Cjif2gaMiBv1nJJbXzYyTYggX1H6IQwcMD29eLLi3dtbDZ8x7wJ+uPIG9PiUqbDLETwg bXibwpkitSOSoKZztwgMI4o+yUQKNGssedPdSiYjgpJsHv4pg522Vd2Q7iGO6clFqm04 O+tA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X9+rr2bCSDZG/nCniXr98w168+IzhYcZne15QwzLe+E=; b=OxNyg56vQ0DtNhN6v5kTNKodRTKcjZ7TNnWch1iZMoxO2OxOG3YTVcV62XxWB39ugD w04PpxCjAJTQQfxTcPyR402qdnk/zHH4skWTwgQHZE82Lm9ivGQtcQFU5wGeFhxQynGl xmWRoZkzanilGY6E+Hd+tJnRFOwnMp50x8t781FiLHzRLm8ME2rkMNCJlQggsufkrMO3 MNJgAyfYBUiAsfOvluEwjE4YNAaSYX64hy+cxp0zD6aoeGdK2Dq32Foq3ygBkD3uNFNs du3d40VN771A4cr7FO6a4nyYI+ptPnnPhRds+5X8y4pmuXy8ZX653SYHnxTeIxgsJMSv gRXA== X-Gm-Message-State: APjAAAVBaU/mpsIOZUSlSCjYDuRi96veSmgsUWRAWoyUPVU2efLUtxEL LI9OQN5J7IKHaD8TD9Pae+33LDKN6pc= X-Received: by 2002:adf:bc86:: with SMTP id g6mr14397539wrh.60.1557230425949; Tue, 07 May 2019 05:00:25 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g3sm12348596wmf.9.2019.05.07.05.00.24 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 May 2019 05:00:24 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 7 May 2019 13:00:04 +0100 Message-Id: <20190507120011.18100-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190507120011.18100-1-peter.maydell@linaro.org> References: <20190507120011.18100-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::432 Subject: [Qemu-devel] [PULL 08/15] qga: Fix mingw compilation warnings on enum conversion X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Cao Jiaxi The win2qemu[] is supposed to be the conversion table to convert between STORAGE_BUS_TYPE in Windows SDK and GuestDiskBusType in qga. But it was incorrectly written that it forces to set a GuestDiskBusType value to STORAGE_BUS_TYPE, which generates an enum conversion warning in clang. Suggested-by: Eric Blake Signed-off-by: Cao Jiaxi Reviewed-by: Richard Henderson Reviewed-by: Thomas Huth Message-id: 20190503003650.10137-1-driver1998@foxmail.com Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- qga/commands-win32.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.20.1 diff --git a/qga/commands-win32.c b/qga/commands-win32.c index d40d61f605c..6b67f16faf1 100644 --- a/qga/commands-win32.c +++ b/qga/commands-win32.c @@ -457,7 +457,7 @@ void qmp_guest_file_flush(int64_t handle, Error **errp) #ifdef CONFIG_QGA_NTDDSCSI -static STORAGE_BUS_TYPE win2qemu[] = { +static GuestDiskBusType win2qemu[] = { [BusTypeUnknown] = GUEST_DISK_BUS_TYPE_UNKNOWN, [BusTypeScsi] = GUEST_DISK_BUS_TYPE_SCSI, [BusTypeAtapi] = GUEST_DISK_BUS_TYPE_IDE, From patchwork Tue May 7 12:00:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 163516 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:81:0:0:0:0 with SMTP id l1csp1250135ilm; Tue, 7 May 2019 05:01:08 -0700 (PDT) X-Google-Smtp-Source: APXvYqz0V/g4BujUKgTJhpuBphmQ/A47Xau4CeGi/lHgblkOwYIHvcfIVqbFG1w/LdMQ4wGPljqY X-Received: by 2002:a5d:440e:: with SMTP id z14mr1602379wrq.70.1557230468387; Tue, 07 May 2019 05:01:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557230468; cv=none; d=google.com; s=arc-20160816; b=EVB6FMUjU2r9Mx4vlMpncRCn/MkBYXbnuj1oIUv4XceWh8Ir1DHzM9vq+XDNceByJS jUbqwyUA/0Em6q+7iWT1iPXbRxprMYONdaqi0fm7Ua/yrNJ91MuAFtcpApnFQDDqmK8C fOAc8c+UjzG8xcRCJwmOR8VmWXPSmpT3fjldHlrHOUbboVt29s5GdESjbUaD/O385L2Z 66Melk/aQ2I5WCDo+zKLbhbmk+3tVIChxpHhRy7AX29NExqyL8Cl6xUiti273x7j2BWs A74XaRhpttl9Sx9b2wMPSjkjM2Hs/fGdkziDD1xxBCo3/P3nb0837z5DE6fXdkNwyiyv m8xg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=QJnsO/e2aUvBsiJ7AzOUR4tR/12UDD/kLgyFI8NTW1o=; b=GeOWzzwluoNpQJT32gu/ZnL62nRyFPqy2+YxwgLQsalgsLuFT7LVi9tnxTxL5pHGcC zUcwNqcr8kWWvwKG7fICL43OLb3yGvyMyKAnQTJfjZX25ENM9/3uxydcraMbNuU2GobX 5yrnrOsehS+6A0wPUhbXol1tnzqZxTt+7sZcitQPPCqos8hHEa4tZ88WDNOzhn4La7Ld gupgzmPwcl3LPy23GqxdDw8SmP/vleEzG/03QSOYM2F6nDfwDUKagUA/mG1zCDwoxP90 9dcyJSfl7DM9a9T/6T3kpgTe0NdjcltkY/0+G18XAKJFCO6TwxjkAl1OVfyHd7jsvv8t Z8lA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=BnAEaXTF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g3sm12348596wmf.9.2019.05.07.05.00.26 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 May 2019 05:00:26 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 7 May 2019 13:00:05 +0100 Message-Id: <20190507120011.18100-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190507120011.18100-1-peter.maydell@linaro.org> References: <20190507120011.18100-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PULL 09/15] util/cacheinfo: Use uint64_t on LLP64 model to satisfy Windows ARM64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Cao Jiaxi Windows ARM64 uses LLP64 model, which breaks current assumptions. Signed-off-by: Cao Jiaxi Reviewed-by: Richard Henderson Reviewed-by: Thomas Huth Message-id: 20190503003707.10185-1-driver1998@foxmail.com Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- util/cacheinfo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.20.1 diff --git a/util/cacheinfo.c b/util/cacheinfo.c index 3cd080b83d1..eebe1ce9c5d 100644 --- a/util/cacheinfo.c +++ b/util/cacheinfo.c @@ -107,7 +107,7 @@ static void sys_cache_info(int *isize, int *dsize) static void arch_cache_info(int *isize, int *dsize) { if (*isize == 0 || *dsize == 0) { - unsigned long ctr; + uint64_t ctr; /* The real cache geometry is in CCSIDR_EL1/CLIDR_EL1/CSSELR_EL1, but (at least under Linux) these are marked protected by the From patchwork Tue May 7 12:00:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 163521 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:81:0:0:0:0 with SMTP id l1csp1257920ilm; Tue, 7 May 2019 05:06:56 -0700 (PDT) X-Google-Smtp-Source: APXvYqy8MkTRp1cq6e/Ickf3VZR8hJZz9ismE4V33K3asC6+DoXAderlv219AEsR0vmtYCVkXwmM X-Received: by 2002:a5d:4a81:: with SMTP id o1mr2265597wrq.183.1557230815982; Tue, 07 May 2019 05:06:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557230815; cv=none; d=google.com; s=arc-20160816; b=XqVQ8RM5SfvyxuMLTRSt1P5qfWrhhPxVg/WoObL3LyJhPh5hZ2IwKlIEgkVv1gdeED g1a5zxfTmCwz8x2A9AHNlvIOzQ1UsdI6KS1erg+WRKuREIouWg5cmmwFUQvBPlU4lVmF o/Z9EyNfq2YfXy/nNjh9AXZSuQ0a0QcP4HgvYFXfWKwDuw0X8XQ6U/ryNfetk4qiA8Le srEcjm191dAsu1AXoCEGHdqz0qsDJlpnNeeREwyYIkcSYeNKBqg2r23YSaqFx7zmrTgK KMP78flfftM1gWnqGDb6TaM5jg7DBJYrL5inPm31pv+hPqJ29rYldNEd1sseTo2BiAF6 +pcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=2H24j/ivxKhpWMoNZRyFm5/WUhhAwlHuP6YRtZPABdg=; b=OTCD4wZbhBu3t/EaY4KCS3cLzTqJ9HL0MmivFLqviER0RDQelBwXloEh4yqSrqBNBM lwhVbkvu0N19L3/K2wLcnN+S6TVnmsDYc2BmwEqwo/V9vmFW79t/0L2cfHYPsOhYhWwZ 1E6npfz7Q+cc2jcqXr+UsSTkYOqJxEz4T7mDoF76bwPt2rg2/B86nVQQG8eWXfSkZl3c PXhhtx2VFN0ZEokr8FrzNvjz1qElQnlz2EFAzKH5OpIyATKqetgr8AbUP6+7IUPm4mE5 odI8yalzoXEuYJhjpxzBVOXdx2/lnDkr0U6WxY0U4V7Z3SYk44NoxIvbYhMRLyiIGXvG hAWQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Po9GDH7G; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g3sm12348596wmf.9.2019.05.07.05.00.27 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 May 2019 05:00:27 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 7 May 2019 13:00:06 +0100 Message-Id: <20190507120011.18100-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190507120011.18100-1-peter.maydell@linaro.org> References: <20190507120011.18100-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::334 Subject: [Qemu-devel] [PULL 10/15] osdep: Fix mingw compilation regarding stdio formats X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Cao Jiaxi I encountered the following compilation error on mingw: /mnt/d/qemu/include/qemu/osdep.h:97:9: error: '__USE_MINGW_ANSI_STDIO' macro redefined [-Werror,-Wmacro-redefined] #define __USE_MINGW_ANSI_STDIO 1 ^ /mnt/d/llvm-mingw/aarch64-w64-mingw32/include/_mingw.h:433:9: note: previous definition is here #define __USE_MINGW_ANSI_STDIO 0 /* was not defined so it should be 0 */ It turns out that __USE_MINGW_ANSI_STDIO must be set before any system headers are included, not just before stdio.h. Signed-off-by: Cao Jiaxi Reviewed-by: Thomas Huth Reviewed-by: Stefan Weil Message-id: 20190503003719.10233-1-driver1998@foxmail.com Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- include/qemu/osdep.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) -- 2.20.1 diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index 303d315c5d4..af2b91f0b87 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -85,17 +85,17 @@ extern int daemon(int, int); #endif #endif +/* enable C99/POSIX format strings (needs mingw32-runtime 3.15 or later) */ +#ifdef __MINGW32__ +#define __USE_MINGW_ANSI_STDIO 1 +#endif + #include #include #include #include #include #include - -/* enable C99/POSIX format strings (needs mingw32-runtime 3.15 or later) */ -#ifdef __MINGW32__ -#define __USE_MINGW_ANSI_STDIO 1 -#endif #include #include From patchwork Tue May 7 12:00:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 163523 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:81:0:0:0:0 with SMTP id l1csp1258407ilm; Tue, 7 May 2019 05:07:18 -0700 (PDT) X-Google-Smtp-Source: APXvYqxoDhygi6+EnRhegX7gOoaJfu3evsgxCMQXxlOLPMUycbOJAUOwTrKPeyTRnzSgWCKTmWq9 X-Received: by 2002:adf:db8a:: with SMTP id u10mr23349310wri.82.1557230838890; Tue, 07 May 2019 05:07:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557230838; cv=none; d=google.com; s=arc-20160816; b=i+Osw33+NhP7odHB6Y6rwWVFCVH00gV/0Ccbo8YktD6v9XlP97Ppc382u4ICsPFLzd Q0IV6UndFjG8nEILyBJQiHBtUoArr11pirKJmLvmborEP3mPdW9giJHAmuW9SC48NJCV Xgu7xp674EWB7LfV0xzjGIY6AIAoLzatwwz+N83vwHfx5i0/3HaxApGpGwx6ltNW/0Uk YH13906nsRNCwId8X9sUWd0PagikEDHuuebHm5HKhzVq7vMDX/8+7iC3iOjW/cn+ya9H 1FewE5yQjIi0IkkafkuSUMwyM423BbVsYhRUFHL8ItzK1AUHERUF5Z5GP+fzMkgOXxyM 8UpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=4X9sIu0YHhUgKH1JkMRhAu/b2BTcREHijf9rjBQvr1M=; b=gxvOzfMk7SMisjlXaydd9oBe5eZWi1gYI4ExjvkNAjUZA70T0Ds01dx5HemiRqb3V0 IBdhIwlKpmx+VFOPZSXZuBvDjLXOap0+MzfBtmbHwTZL7wpGJOvg299SNu9JABMEbOjV i9SSh5+Jbb5VqOy+4Na9kyiCoX8JRNPYdkXHK+r9senVZ39jAxCQyHngSHucGabPq84C jEuIcC8/iwQXCIGKVsNIteqqQmhkPkIwYUsjgkF1+JptZWg+3QJOp+flAK+AqtAeBvNu hCiSh23mAIOE1fQMsct8ykJATWjjQJHib0XaB3lCia0Mb5EmyNljvSl36Ga+UgEGun6N U5IA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yHqgs6Gi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g3sm12348596wmf.9.2019.05.07.05.00.28 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 May 2019 05:00:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 7 May 2019 13:00:07 +0100 Message-Id: <20190507120011.18100-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190507120011.18100-1-peter.maydell@linaro.org> References: <20190507120011.18100-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::335 Subject: [Qemu-devel] [PULL 11/15] hw/arm/armv7m_nvic: Check subpriority in nvic_recompute_state_secure() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rule R_CQRV says that if two pending interrupts have the same group priority then ties are broken by looking at the subpriority. We had a comment describing this but had forgotten to actually implement the subpriority comparison. Correct the omission. (The further tie break rules of "lowest exception number" and "secure before non-secure" are handled implicitly by the order in which we iterate through the exceptions in the loops.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20190430131439.25251-2-peter.maydell@linaro.org --- hw/intc/armv7m_nvic.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) -- 2.20.1 diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index fff6e694e60..131b5938b9a 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -213,6 +213,7 @@ static void nvic_recompute_state_secure(NVICState *s) int active_prio = NVIC_NOEXC_PRIO; int pend_irq = 0; bool pending_is_s_banked = false; + int pend_subprio = 0; /* R_CQRV: precedence is by: * - lowest group priority; if both the same then @@ -226,7 +227,7 @@ static void nvic_recompute_state_secure(NVICState *s) for (i = 1; i < s->num_irq; i++) { for (bank = M_REG_S; bank >= M_REG_NS; bank--) { VecInfo *vec; - int prio; + int prio, subprio; bool targets_secure; if (bank == M_REG_S) { @@ -241,8 +242,12 @@ static void nvic_recompute_state_secure(NVICState *s) } prio = exc_group_prio(s, vec->prio, targets_secure); - if (vec->enabled && vec->pending && prio < pend_prio) { + subprio = vec->prio & ~nvic_gprio_mask(s, targets_secure); + if (vec->enabled && vec->pending && + ((prio < pend_prio) || + (prio == pend_prio && prio >= 0 && subprio < pend_subprio))) { pend_prio = prio; + pend_subprio = subprio; pend_irq = i; pending_is_s_banked = (bank == M_REG_S); } From patchwork Tue May 7 12:00:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 163530 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:81:0:0:0:0 with SMTP id l1csp1266236ilm; Tue, 7 May 2019 05:14:07 -0700 (PDT) X-Google-Smtp-Source: APXvYqz1J72cCSC+11UwiCf3SK+DALPRMG6LnkqgG0AykpQzvHTWK5nYHReiYG06lwX0wD66lN6Q X-Received: by 2002:adf:e911:: with SMTP id f17mr11862268wrm.105.1557231246994; Tue, 07 May 2019 05:14:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557231246; cv=none; d=google.com; s=arc-20160816; b=S0R9/TaIFbbPjsEM7JVurIWmKQkzAIl50nYdsxNKP8525qAdQxwC1irCskNtDXRGY8 gPUjqmO50Jj5QLQAH9odHSjnC+TnjYKT5xJxI7B4NV2MYRmSnAbfNWycYjL1sBRlFBVK oQgiZGPGtFqlVO26EFwlAoqynYJLv7lEuhPidMKknhmIU+aXxrZX2aIYV2Fnl88RPjlp bcTJ8GVVHfHBJJL3V/orGeOzcA7ZW5iUvCxugFFgO2mOhCty009nzTvTBdO9sr/38kMt Rc6K8Wl+eKkfAUME+JO/fansPBG7vGmugXX2eah9CuQet4CsMck7k045ECPJUIvsWnHS +6RA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=z9A+d6NR/272WHXylxaqVz5VB4YHQmOPLGtdfveFKqg=; b=wWiNFKOcyofQ8xt7DPL7huXiqa1ImJxzwhdkwaJflsq93KxIykwSZxdK+6Z6S+qsQK Z5/hX40TyvYUfwKquOBQ/pSmcbATGFYxoNVS6e1OBB/dv05apzIYnqcR3XeLinxkj0fE CqyBMWDd4CmxyCIdNbMkQUUrai+D6b3OsF4nAHHxk17qDjs1M0wOV/k60w0AbaX4pVs/ Ctl1rcQIrea+EgdezA4W4F7jM0xhjrFGTtfKk8hbIZCbix3lXQGiDHW5ePUns73vcTUn f7HmZWynQ6bF2QFN/WvHFYPUVanHVogFpoW5LADJ+VJz3XfeCTcgNoiqko68ZSPn6tU4 RS8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UxldnRDP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g3sm12348596wmf.9.2019.05.07.05.00.29 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 May 2019 05:00:30 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 7 May 2019 13:00:08 +0100 Message-Id: <20190507120011.18100-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190507120011.18100-1-peter.maydell@linaro.org> References: <20190507120011.18100-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::334 Subject: [Qemu-devel] [PULL 12/15] hw/intc/armv7m_nvic: NS BFAR and BFSR are RAZ/WI if BFHFNMINS == 0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The non-secure versions of the BFAR and BFSR registers are supposed to be RAZ/WI if AICR.BFHFNMINS == 0; we were incorrectly allowing NS code to access the real values. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20190430131439.25251-3-peter.maydell@linaro.org --- hw/intc/armv7m_nvic.c | 27 ++++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) -- 2.20.1 diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 131b5938b9a..15cba63c964 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1167,6 +1167,10 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } + if (!attrs.secure && + !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { + return 0; + } return cpu->env.v7m.bfar; case 0xd3c: /* Aux Fault Status. */ /* TODO: Implement fault status registers. */ @@ -1646,6 +1650,10 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } + if (!attrs.secure && + !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { + return; + } cpu->env.v7m.bfar = value; return; case 0xd3c: /* Aux Fault Status. */ @@ -2130,11 +2138,18 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, val = 0; break; }; - /* The BFSR bits [15:8] are shared between security states - * and we store them in the NS copy + /* + * The BFSR bits [15:8] are shared between security states + * and we store them in the NS copy. They are RAZ/WI for + * NS code if AIRCR.BFHFNMINS is 0. */ val = s->cpu->env.v7m.cfsr[attrs.secure]; - val |= s->cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK; + if (!attrs.secure && + !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { + val &= ~R_V7M_CFSR_BFSR_MASK; + } else { + val |= s->cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK; + } val = extract32(val, (offset - 0xd28) * 8, size * 8); break; case 0xfe0 ... 0xfff: /* ID. */ @@ -2249,6 +2264,12 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, */ value <<= ((offset - 0xd28) * 8); + if (!attrs.secure && + !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { + /* BFSR bits are RAZ/WI for NS if BFHFNMINS is set */ + value &= ~R_V7M_CFSR_BFSR_MASK; + } + s->cpu->env.v7m.cfsr[attrs.secure] &= ~value; if (attrs.secure) { /* The BFSR bits [15:8] are shared between security states From patchwork Tue May 7 12:00:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 163528 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:81:0:0:0:0 with SMTP id l1csp1263310ilm; Tue, 7 May 2019 05:11:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqx0BeWkGiEuzsjUK+5/zH7jNhkRxw+shrwdvn8ivE6Q0Bv8YuwerOvF0WOMX4BVdeXjdQCQ X-Received: by 2002:adf:80c4:: with SMTP id 62mr3414365wrl.234.1557231092930; Tue, 07 May 2019 05:11:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557231092; cv=none; d=google.com; s=arc-20160816; b=X9HkjJJJEnobHkjzREgAiqmSDVgBofXAqMSApQ6OdNsWpahBHYxw4xvf8BDxgBXCjf kaye0lG6LP2YHoGcQVGDSym4Tz24OPQBwloyl4qSwBpvZ+MFLXazp3exQlHkorVrCNLI roU9O9Fk9nPmRIcys6MVfLru0UD9l9Em1fYKLTu35woEcPlyBFuH+kFXYnU7KxH9D420 8zWLgypeqaXo8HTexJM8atHMamNZFP9SKMi33wljrd5js0PWLYLDh/+637B2SEw1LEM7 9MAyzXixfno+FV8IyyGhGAU8PYY0g065QGnAGofkK6NlM+TOdM0diAVtLj7fkvspX9pl aMTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=0E/GB8BOaQHYgNe4bA1uWRBqwj8g9GMMZpj2tYiWP00=; b=DUtfoEa6vWT/a8RZ4lZcWDQ39uHonsnau2ZyD56P6fdvOeOfMkh4FxR336/2LGWtt+ iVTuTL7jTxqG3tMu97YWxDXWZze1XmGpBK7Qj/o1TYO6kM1z9UsTiiKOHYTCjoy3kQhr 4W3L+Z8khdM3LLDvmV/caZaHgQUlunYvMM8ga1P86as+9P/6X9xAbg9lcYV1hr5BXsT2 HhCiPsR61eFRB5iWGpm9NRlzvYPP1iqjwCdY9+NwXbsLWYUf07On22ZiJMrkK0ADsCyY SMrNYFSbeJSe3+McpHC1Ro0nkRUQ1jOs0vN6cuH6gGgeGBP5RNoqQR2/6PBU/aAFhcsA nkSQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=MjrPnYyC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g3sm12348596wmf.9.2019.05.07.05.00.31 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 May 2019 05:00:31 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 7 May 2019 13:00:09 +0100 Message-Id: <20190507120011.18100-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190507120011.18100-1-peter.maydell@linaro.org> References: <20190507120011.18100-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42c Subject: [Qemu-devel] [PULL 13/15] hw/intc/armv7m_nvic: Don't enable ARMV7M_EXCP_DEBUG from reset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The M-profile architecture specifies that the DebugMonitor exception should be initially disabled, not enabled. It should be controlled by the DEMCR register's MON_EN bit, but we don't implement that register yet (like most of the debug architecture for M-profile). Note that BKPT instructions will still work, because they will be escalated to HardFault. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20190430131439.25251-4-peter.maydell@linaro.org --- hw/intc/armv7m_nvic.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.20.1 diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 15cba63c964..3a346a682a3 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2491,10 +2491,12 @@ static void armv7m_nvic_reset(DeviceState *dev) * the System Handler Control register */ s->vectors[ARMV7M_EXCP_SVC].enabled = 1; - s->vectors[ARMV7M_EXCP_DEBUG].enabled = 1; s->vectors[ARMV7M_EXCP_PENDSV].enabled = 1; s->vectors[ARMV7M_EXCP_SYSTICK].enabled = 1; + /* DebugMonitor is enabled via DEMCR.MON_EN */ + s->vectors[ARMV7M_EXCP_DEBUG].enabled = 0; + resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3; s->vectors[ARMV7M_EXCP_RESET].prio = resetprio; s->vectors[ARMV7M_EXCP_NMI].prio = -2; From patchwork Tue May 7 12:00:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 163519 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:81:0:0:0:0 with SMTP id l1csp1254667ilm; Tue, 7 May 2019 05:04:28 -0700 (PDT) X-Google-Smtp-Source: APXvYqw+GDdnmbE2y2J1nVqmDVl1QW6D4EfDS5NvEap6YD2oFbidfOjxPaZ0ZdY7fj6vMlmPxM+W X-Received: by 2002:a05:600c:2051:: with SMTP id p17mr9798963wmg.125.1557230668786; Tue, 07 May 2019 05:04:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557230668; cv=none; d=google.com; s=arc-20160816; b=vm4E03VgtSUbHuZeKTSeJKtzA4skXXLsQgZSbIa7XLsPpXmOoEr+BXU6wULTYFfQEK GGeHwA/CsUN7mmnhqIG4TzZlm5IftRMvqLEK2ZiviAVP6HOBMcS93crrbenloOgCXcsP 8wxMGGDTlFsvWWfw4snWW8SyXoboeAWpQvYt6lpuEFjVVIFiW98eC522rsOlHta/Ayjx dau9JBMOV73dFcENTr0SNZZGzxdchy5wymnWxb1ATxFl4deMOVzkrcq05PzL/txmnC/1 Vnz/xhU0LpgRf4MiFMHELJHAtU5FtkifClDZyBaxvcVJXPszGBnjb4JkvL3bLKjZjcse dEHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=upDb/oCermKTFkACDchj8gTFhCiWSrAdwy8aQAIaTNU=; b=Y2j9xkU8vZxSUiK1XPd4fdp9NlzJ+GvvK4Db5iXogUEtssT0EZ5FsPpzHHqsZfHA2u LXJ+byK58SNmDdRS2dkdwddxflOU/Tv08Pf4LCLGSEZctxA+bBkYSidLPCTamEFi+6cg n2RQzoexbheKprl2Nx2ZtyfKAtFOo1475Klpx2du2t9/a7F5lHxEmDeu8c1qBFvlAnSs ohsBHZo3AFsM0JTC+3Y8Y0U5GExQOfTLplMWCIwM6Mk9zi3ZYWryVA9qwTiSsucDeKML arkRc+byGLzWaBvwNDBliffoYEhcbJt/HzfJpEqLR4Y2DRxiuSBm6oGv/pRR2WBjbp0M 0X7A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RFkTd4+H; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g3sm12348596wmf.9.2019.05.07.05.00.32 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 May 2019 05:00:32 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 7 May 2019 13:00:10 +0100 Message-Id: <20190507120011.18100-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190507120011.18100-1-peter.maydell@linaro.org> References: <20190507120011.18100-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32b Subject: [Qemu-devel] [PULL 14/15] target/arm: Implement XPSR GE bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In the M-profile architecture, if the CPU implements the DSP extension then the XPSR has GE bits, in the same way as the A-profile CPSR. When we added DSP extension support we forgot to add support for reading and writing the GE bits, which are stored in env->GE. We did put in the code to add XPSR_GE to the mask of bits to update in the v7m_msr helper, but forgot it in v7m_mrs. We also must not allow the XPSR we pull off the stack on exception return to set the nonexistent GE bits. Correct these errors: * read and write env->GE in xpsr_read() and xpsr_write() * only set GE bits on exception return if DSP present * read GE bits for MRS if DSP present Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20190430131439.25251-5-peter.maydell@linaro.org --- target/arm/cpu.h | 4 ++++ target/arm/helper.c | 12 ++++++++++-- 2 files changed, 14 insertions(+), 2 deletions(-) -- 2.20.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0304ddd9f11..733b840a712 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1285,6 +1285,7 @@ static inline uint32_t xpsr_read(CPUARMState *env) | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) | ((env->condexec_bits & 0xfc) << 8) + | (env->GE << 16) | env->v7m.exception; } @@ -1300,6 +1301,9 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) if (mask & XPSR_Q) { env->QF = ((val & XPSR_Q) != 0); } + if (mask & XPSR_GE) { + env->GE = (val & XPSR_GE) >> 16; + } if (mask & XPSR_T) { env->thumb = ((val & XPSR_T) != 0); } diff --git a/target/arm/helper.c b/target/arm/helper.c index 9b805d0e6bd..b9745a42bab 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8727,7 +8727,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) { CPUARMState *env = &cpu->env; uint32_t excret; - uint32_t xpsr; + uint32_t xpsr, xpsr_mask; bool ufault = false; bool sfault = false; bool return_to_sp_process; @@ -9179,8 +9179,13 @@ static void do_v7m_exception_exit(ARMCPU *cpu) } *frame_sp_p = frameptr; } + + xpsr_mask = ~(XPSR_SPREALIGN | XPSR_SFPA); + if (!arm_feature(env, ARM_FEATURE_THUMB_DSP)) { + xpsr_mask &= ~XPSR_GE; + } /* This xpsr_write() will invalidate frame_sp_p as it may switch stack */ - xpsr_write(env, xpsr, ~(XPSR_SPREALIGN | XPSR_SFPA)); + xpsr_write(env, xpsr, xpsr_mask); if (env->v7m.secure) { bool sfpa = xpsr & XPSR_SFPA; @@ -12665,6 +12670,9 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) } if (!(reg & 4)) { mask |= XPSR_NZCV | XPSR_Q; /* APSR */ + if (arm_feature(env, ARM_FEATURE_THUMB_DSP)) { + mask |= XPSR_GE; + } } /* EPSR reads as zero */ return xpsr_read(env) & mask; From patchwork Tue May 7 12:00:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 163531 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:81:0:0:0:0 with SMTP id l1csp1267100ilm; Tue, 7 May 2019 05:14:54 -0700 (PDT) X-Google-Smtp-Source: APXvYqwkROXwORxwlV5Z1+uVVhoGVXunBrHRujkUgw6fscxJIIdrIHreNkgbH2qVzXcoOsKIXapr X-Received: by 2002:adf:da51:: with SMTP id r17mr11802458wrl.118.1557231293905; Tue, 07 May 2019 05:14:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557231293; cv=none; d=google.com; s=arc-20160816; b=OTLuc1NW+/QCGDD2i/k8vNOG++djLoFsn0L9AyCsASRZfUA53pq3bf6RKd2JQg6wlb QDYrnov+mYWuZjKA+YkbKLssCmPcDKJIZO5Hrj0AiwTiJnuZJXP55Blbz76oSO/qyjig MR/0ug1nzaNzYrDtFle8TV0b1llWlMJONAHQPnr+QdgFrOU7s2W5yPUKgG3NpPAZ8/Cz X6ginj79w1R4OuWY6KE6Nv0dd8XDHdhKKr+gN2VW8Gmwbwyo4E02D4JjgFWSewTJ8MAs 9iZc91JJaXj8gEv6FBi7MWs2Auq9yPeAkADfPIwPXi007CrjuhZjmnFAnLmI4fl3rpRP Qhyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=NJGpq0OAxWQIci6soRm4qOcyKSMv9zMfLaUKqYHLGrI=; b=Sm5AwMCydMNN/uV3+wXb48CzwFshtTeJCJWW/AIbTGKH+MB1UWGSCFclyPZ8Zg96nU SiShh+ATUPkE6rN5P9wxlhxZDlg/BV8wTkKwIoURYUr9o0HtwmovjSAcDEm5C64sp2v8 joGeFAnmCCrZ/rrr+wI5kSYdxU4FuX4emUIWRNJqPbo7gWX9O/EDZlccOHjg/LUeDgZF TvPY6W4hU2BgbQliiY47cPfd8fvn+bPaEPPHbu8Fd0Oi2FbpK47I9Bt/mrJEZrfc5hGo to/PrkQkbTCf7UOyVAH8jahjeYDDk52NfXfrlxvqgOwg2crtMKr/rGQkVyrJSwTTbkXq 76wg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Ypd5zaHX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g3sm12348596wmf.9.2019.05.07.05.00.33 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 May 2019 05:00:33 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 7 May 2019 13:00:11 +0100 Message-Id: <20190507120011.18100-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190507120011.18100-1-peter.maydell@linaro.org> References: <20190507120011.18100-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PULL 15/15] target/arm: Stop using variable length array in dc_zva X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Currently the dc_zva helper function uses a variable length array. In fact we know (as the comment above remarks) that the length of this array is bounded because the architecture limits the block size and QEMU limits the target page size. Use a fixed array size and assert that we don't run off it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Message-id: 20190503120448.13385-1-peter.maydell@linaro.org --- target/arm/helper.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index b9745a42bab..1e6eb0d0f36 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1,4 +1,5 @@ #include "qemu/osdep.h" +#include "qemu/units.h" #include "target/arm/idau.h" #include "trace.h" #include "cpu.h" @@ -13130,14 +13131,17 @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) * We know that in fact for any v8 CPU the page size is at least 4K * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only * 1K as an artefact of legacy v5 subpage support being present in the - * same QEMU executable. + * same QEMU executable. So in practice the hostaddr[] array has + * two entries, given the current setting of TARGET_PAGE_BITS_MIN. */ int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE); - void *hostaddr[maxidx]; + void *hostaddr[DIV_ROUND_UP(2 * KiB, 1 << TARGET_PAGE_BITS_MIN)]; int try, i; unsigned mmu_idx = cpu_mmu_index(env, false); TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx); + assert(maxidx <= ARRAY_SIZE(hostaddr)); + for (try = 0; try < 2; try++) { for (i = 0; i < maxidx; i++) {