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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id 25sm320494pfo.145.2019.05.08.15.43.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 08 May 2019 15:43:13 -0700 (PDT) From: Bjorn Andersson To: Andy Gross , David Brown Cc: Rob Herring , Mark Rutland , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/3] arm64: dts: qcom: qcs404: Make gcc as reset-controller Date: Wed, 8 May 2019 15:43:07 -0700 Message-Id: <20190508224309.5744-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190508224309.5744-1-bjorn.andersson@linaro.org> References: <20190508224309.5744-1-bjorn.andersson@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org GCC is a reset-controller, so define #reset-cells. Signed-off-by: Bjorn Andersson --- Changes since v3: - Split single patch, no functional change arch/arm64/boot/dts/qcom/qcs404.dtsi | 1 + 1 file changed, 1 insertion(+) -- 2.18.0 diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index ffedf9640af7..65a2cbeb28be 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -383,6 +383,7 @@ compatible = "qcom,gcc-qcs404"; reg = <0x01800000 0x80000>; #clock-cells = <1>; + #reset-cells = <1>; assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; assigned-clock-rates = <19200000>; From patchwork Wed May 8 22:43:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 163651 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:142:0:0:0:0 with SMTP id j2csp167363ilr; Wed, 8 May 2019 15:43:18 -0700 (PDT) X-Google-Smtp-Source: APXvYqyYPBP2yDHu/rQ9AYF+2h0x0ittAybtz5Jh+k01dZJ2QtSI/zzDHw+0Uvqy6eH0jw5LuI3p X-Received: by 2002:a62:75d8:: with SMTP id q207mr84323pfc.35.1557355398659; Wed, 08 May 2019 15:43:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557355398; cv=none; d=google.com; s=arc-20160816; b=ik4nMuLDo62MnfLHy4lxiIo3Snn/c4S+5iBuXf3ehDqyp2r8wz0vDcct6gMZnPI/ho 8C6Kzaq1aa3HNWqrWbNcyOyPTdGIxX63q0BeOXAkuRaG7aXXFgKDkFBA8eEihPDFWF3W qDPwAJPf48ZNvbpP4KxNU1fryXJE6gRdOZB69lIswBm3eYgWcCPnCj6Jc8KSgVLWcLby g7a9mIk04eXeim8EdrRUcJ758JqZJ1HMeQGpFwX3xbB/8qSKqUCJWXAlTGgaFd1mqTaD LQWb63rdg2kUd7GIQ59QBT2FjAPvxekIVmpGLZh5Z7J00oeM4FFndPGiDOeXurPPtW1r uBEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=ZRWOAg/RyHnGg26N15yptA5VgOFfFjkzmzqD1kcfUOw=; b=hRfN2trymQ04V8EhbEuDrvyGEqTH8bwnGAxkxhmhVGTuxfz6P6tYoCjQn1wZaG7Q0b /cjMGipL+r7LQVA6NDUCNkpunc4mlU2mPbjXKJYq3aGQDQx0JDHZJygGzJIA8xwUDJR0 kyNiuW/ZQdSRsyukLP1n5EGuHJS5GIzGuQ7ioZUPhqYGbF+3+is6emJM4QbnZB6iZiUy ReiqmGfweLSiBwVESA9rISAFlr9QOnna8FE/x3qNUzsb7XtWGBD0YStbEFxd2pTBK8+F HWPE7RHLgoIyQ7uMyoxbinibbUuwuevTRzQdS6YFZ1Y4Ut3ch4Ql0ciFQSnGPmVEmzOJ v0EQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RdT8BY5t; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id 25sm320494pfo.145.2019.05.08.15.43.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 08 May 2019 15:43:14 -0700 (PDT) From: Bjorn Andersson To: Andy Gross , David Brown Cc: Rob Herring , Mark Rutland , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/3] arm64: dts: qcom: qcs404: Add PCIe related nodes Date: Wed, 8 May 2019 15:43:08 -0700 Message-Id: <20190508224309.5744-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190508224309.5744-1-bjorn.andersson@linaro.org> References: <20190508224309.5744-1-bjorn.andersson@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The QCS404 has a PCIe2 PHY and a Qualcomm PCIe controller, define these to for the platform. Reviewed-by: Niklas Cassel Signed-off-by: Bjorn Andersson --- Changes since v3: - Split single patch, no functional change arch/arm64/boot/dts/qcom/qcs404.dtsi | 65 ++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) -- 2.18.0 diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 65a2cbeb28be..f97e9c96b7f7 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -412,6 +412,21 @@ #interrupt-cells = <4>; }; + pcie_phy: phy@7786000 { + compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; + reg = <0x07786000 0xb8>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, + <&gcc GCC_PCIE_0_PIPE_ARES>; + reset-names = "phy", "pipe"; + + clock-output-names = "pcie_0_pipe_clk"; + #phy-cells = <0>; + + status = "disabled"; + }; + sdcc1: sdcc@7804000 { compatible = "qcom,sdhci-msm-v5"; reg = <0x07804000 0x1000>, <0x7805000 0x1000>; @@ -797,6 +812,56 @@ status = "disabled"; }; }; + + pcie: pci@10000000 { + compatible = "qcom,pcie-qcs404", "snps,dw-pcie"; + reg = <0x10000000 0xf1d>, + <0x10000f20 0xa8>, + <0x07780000 0x2000>, + <0x10001000 0x2000>; + reg-names = "dbi", "elbi", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x81000000 0 0 0x10003000 0 0x00010000>, /* I/O */ + <0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */ + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>; + clock-names = "iface", "aux", "master_bus", "slave_bus"; + + resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>, + <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>, + <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>, + <&gcc GCC_PCIE_0_CORE_STICKY_ARES>, + <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_AHB_ARES>; + reset-names = "axi_m", + "axi_s", + "axi_m_sticky", + "pipe_sticky", + "pwr", + "ahb"; + + phys = <&pcie_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; }; timer {