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([2602:ae:154a:9f01:87cc:49bb:2900:c08b]) by smtp.gmail.com with ESMTPSA id g23-20020aa78197000000b0061949fe3beasm2921056pfi.22.2023.03.05.17.57.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Mar 2023 17:57:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com Subject: [PATCH v2 1/5] tcg: Do not elide memory barriers for !CF_PARALLEL Date: Sun, 5 Mar 2023 17:57:06 -0800 Message-Id: <20230306015710.1868853-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230306015710.1868853-1-richard.henderson@linaro.org> References: <20230306015710.1868853-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The virtio devices require proper memory ordering between the vcpus and the iothreads. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- tcg/tcg-op.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 77658a88f0..75fdcdaac7 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -102,9 +102,13 @@ void tcg_gen_br(TCGLabel *l) void tcg_gen_mb(TCGBar mb_type) { - if (tcg_ctx->gen_tb->cflags & CF_PARALLEL) { - tcg_gen_op1(INDEX_op_mb, mb_type); - } + /* + * It is tempting to elide the barrier in a single-threaded context + * (i.e. !(cflags & CF_PARALLEL)), however, even with a single cpu + * we have i/o threads running in parallel, and lack of memory order + * can result in e.g. virtio queue entries being read incorrectly. + */ + tcg_gen_op1(INDEX_op_mb, mb_type); } /* 32 bit ops */ From patchwork Mon Mar 6 01:57:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 659220 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp1593921wrb; Sun, 5 Mar 2023 17:58:35 -0800 (PST) X-Google-Smtp-Source: AK7set/6NDroMSi6qh32sNdB1wFjyz8vV93VZtC/wVewGpAhYZSmLG7NCZNVzNNzqJkT9DFe7geE X-Received: by 2002:ac8:7f01:0:b0:3ae:189c:7455 with SMTP id f1-20020ac87f01000000b003ae189c7455mr12935278qtk.47.1678067915258; Sun, 05 Mar 2023 17:58:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678067915; cv=none; d=google.com; s=arc-20160816; b=kbcoCz+c4KqUJpdRflm761n8RzmAnQyo7gv3bsGFFUlyaOPo0dTgDRkxGoxq+mK5AX copUdHsdC5i5bRQ0IW2gEx0Hz4ildw8bjHvUZlu939JuLa9uoTEgcuSd8dJaezp8hrW8 8QdsjwpDUCgGbPXClJeRNkyM0CBXz+CdM41SSLb/Pg3jdH9HNIdqGhrA/pkK40la/0XG ZUG6fvjRJKOEAea9p7gCeCLoO/U30C42WawrVxjiLsp6hTpb1JGlgRvwAmRl5/hGa4gw yNlAhAnW7I3Y6J6bB7XXM/ZSvJbD/E58i3Gtltsq8WQdxazAdkllFotSjBouMmudDNLg 8I/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=+/1/w+4tCdZdhSP9X+tt6DrDGtiinyr2Hzdz5vlpulU=; b=H6Uac5hPp5m/FoG1dpZ/C6xwxUv6Ac2ne3VdxCHG3xJDFxidyvrW+hyvM7xWgkwOmW vmg4+SeyoZEpxFehwXcOsZQKXsGXNr823FKn3J5hBks2TtnHtJ+JLMWcuVsJfNctlQv/ QEq0RbYcsjjthlIWSKrCNTm/rBoV11aYPz4KKce0nmFY4Ia0/bKg4VjVtAfh73yaLfPN pzNsoa6hQwC4EquLKmtggReb1lb9EbpjIxy3wR0mtiUH821idRKAmOHt2aWqKFSO7Y7t v3idQWbPQa5/IOPnaWShyspCVEe0GPvSD/UnWj+jqJpXuZXWODiGnaglebDTTHDGZIpV TgGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mcF5GPkM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:154a:9f01:87cc:49bb:2900:c08b]) by smtp.gmail.com with ESMTPSA id g23-20020aa78197000000b0061949fe3beasm2921056pfi.22.2023.03.05.17.57.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Mar 2023 17:57:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com Subject: [PATCH v2 2/5] tcg: Elide memory barriers implied by the host memory model Date: Sun, 5 Mar 2023 17:57:07 -0800 Message-Id: <20230306015710.1868853-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230306015710.1868853-1-richard.henderson@linaro.org> References: <20230306015710.1868853-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reduce the set of required barriers to those needed by the host right from the beginning. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- tcg/tcg-op.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 75fdcdaac7..2721c1cab9 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -107,8 +107,13 @@ void tcg_gen_mb(TCGBar mb_type) * (i.e. !(cflags & CF_PARALLEL)), however, even with a single cpu * we have i/o threads running in parallel, and lack of memory order * can result in e.g. virtio queue entries being read incorrectly. + * + * That said, we can elide anything which the host provides for free. */ - tcg_gen_op1(INDEX_op_mb, mb_type); + mb_type &= ~TCG_TARGET_DEFAULT_MO; + if (mb_type & TCG_MO_ALL) { + tcg_gen_op1(INDEX_op_mb, mb_type); + } } /* 32 bit ops */ From patchwork Mon Mar 6 01:57:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 659222 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp1593915wrb; Sun, 5 Mar 2023 17:58:35 -0800 (PST) X-Google-Smtp-Source: AK7set+S6VHdlrm5LCWfpqdbb7sqrf6dcvj1h+va0H+9WRrQ9mDavkLhCURyJ1GpAdo25zX7Qvi5 X-Received: by 2002:a05:622a:5c9:b0:3bf:cae4:296c with SMTP id d9-20020a05622a05c900b003bfcae4296cmr12876287qtb.65.1678067914916; Sun, 05 Mar 2023 17:58:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678067914; cv=none; d=google.com; s=arc-20160816; b=ObSWkVwqwEHTkyFpqQjMAidhjkscA/UHEz118VLWM33NvSeOB9+B45ttEDhtnAGh2e gzulpcrbF+pOCilYguK2ky0vICaVqTSdQfN1BL1pET3nRNe7J7c/FQW99flknfdg3/Cd 4drkYlMU7+FSCOY6W/yJGB+Ia0EGVGoXHDktcXHXnIFggrtxv2XJBcx8E9X7WupfgBkW jcKsFvDcfecUyPgCVqU3EhiUtgQhioi5PyqtwYM/YZ4sc+xoaVmG8zuDkp9rI2KR+mfo ZJebYw6eSNrwN3DiZ512GMPbiLrSAFtUpDquZLFhnThawMQlitZEuf4NATPaIUZ2FnrE q/Vw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=L77qkOSs51Hv1VBgnoUhwAR0MTuD2MxK8XGop9z/E6E=; b=dFX+99qW/3mrJ+vUM535Z0/7Z9ZPKXYAFwE7q2wSpZt4T9ZKz+dLK7xAVfa4KaMEfy AHqHGp5rfE78W6QIgr3BlU9SgIB2vI8gW/+FkyBIuQee/mQUtgfmWlmh9ir8t9dRsca+ KOP2e+ioI7AMjgDN3FL6FPVihkZjRFYCLnQD4fgIjwALiY7/jEr7eVuoi4iXVErT14Hd uIO1mtCUoAsYZ7mvN8nAQw1F5ShGbzDt+jxzrAaEKp9TKwDDFdrqjsZR5hggk+9uMsBP suP3yrGv5mDapRAX8784K6UZYOcFn9ZyRfCSPIoEAtiHjwBEQu02Bq9gqssoMADCZF8i 90zQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="to/MfcvR"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:154a:9f01:87cc:49bb:2900:c08b]) by smtp.gmail.com with ESMTPSA id g23-20020aa78197000000b0061949fe3beasm2921056pfi.22.2023.03.05.17.57.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Mar 2023 17:57:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com Subject: [PATCH v2 3/5] tcg: Create tcg_req_mo Date: Sun, 5 Mar 2023 17:57:08 -0800 Message-Id: <20230306015710.1868853-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230306015710.1868853-1-richard.henderson@linaro.org> References: <20230306015710.1868853-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Split out the logic to emit a host memory barrier in response to a guest memory operation. Do not provide a true default for TCG_GUEST_DEFAULT_MO because the defined() check will still be useful for determining if a guest has been updated for MTTCG. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- include/tcg/tcg.h | 20 ++++++++++++++++++++ accel/tcg/tcg-all.c | 6 +----- tcg/tcg-op.c | 8 +------- 3 files changed, 22 insertions(+), 12 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index a5cf21be83..b76b597878 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -1171,6 +1171,26 @@ static inline size_t tcg_current_code_size(TCGContext *s) return tcg_ptr_byte_diff(s->code_ptr, s->code_buf); } +/** + * tcg_req_mo: + * @type: TCGBar + * + * Filter @type to the barrier that is required for the guest + * memory ordering vs the host memory ordering. A non-zero + * result indicates that some barrier is required. + * + * If TCG_GUEST_DEFAULT_MO is not defined, assume that the + * guest requires strict alignment. + * + * This is a macro so that it's constant even without optimization. + */ +#ifdef TCG_GUEST_DEFAULT_MO +# define tcg_req_mo(type) \ + ((type) & TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO) +#else +# define tcg_req_mo(type) ((type) & ~TCG_TARGET_DEFAULT_MO) +#endif + /** * tcg_qemu_tb_exec: * @env: pointer to CPUArchState for the CPU diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 5dab1ae9dd..604efd1b18 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -74,11 +74,7 @@ DECLARE_INSTANCE_CHECKER(TCGState, TCG_STATE, static bool check_tcg_memory_orders_compatible(void) { -#if defined(TCG_GUEST_DEFAULT_MO) && defined(TCG_TARGET_DEFAULT_MO) - return (TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO) == 0; -#else - return false; -#endif + return tcg_req_mo(TCG_MO_ALL) == 0; } static bool default_mttcg_enabled(void) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 2721c1cab9..d6faf30c52 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2930,13 +2930,7 @@ static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr, static void tcg_gen_req_mo(TCGBar type) { -#ifdef TCG_GUEST_DEFAULT_MO - type &= TCG_GUEST_DEFAULT_MO; -#endif - type &= ~TCG_TARGET_DEFAULT_MO; - if (type) { - tcg_gen_mb(type | TCG_BAR_SC); - } + tcg_gen_mb(tcg_req_mo(type) | TCG_BAR_SC); } static inline TCGv plugin_prep_mem_callbacks(TCGv vaddr) From patchwork Mon Mar 6 01:57:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 659223 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp1593917wrb; Sun, 5 Mar 2023 17:58:35 -0800 (PST) X-Google-Smtp-Source: AK7set8bRYjfT0CgXDPqJkGQlK9inSMcXo8KKsFLLXp4h6Ufrgi6LqUVXBrz1L9b0Juo4A289ZJq X-Received: by 2002:ad4:5f49:0:b0:56e:9551:196a with SMTP id p9-20020ad45f49000000b0056e9551196amr17108828qvg.1.1678067915093; Sun, 05 Mar 2023 17:58:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678067915; cv=none; d=google.com; s=arc-20160816; b=MY04M9PqtW76Lq3yBCTm62FmDjJGVHB1nHPRYg7q+6p8euzQxyLQZ+Cc5akbx5HoP0 8kO3V6WXmNkrZeD6bDHexF4M0VxiOpE35n2/TPSgxYYlHaIVylNS8/kcxg66xmUIZomD uY07q4RbcUOxlppaoppodgeqvVyU19eBb0y5HKHJznz0L48hL6fcuZHwTU10wLe2dJIX S0jnEBi6Rs1FNg3EzOAvz2+PT7inGxDoB9jg2H6TEycSxL5rCwtOrszSn4H2qSksQA93 mB5rZtpwxE+JFhiln/i/yosF3R+Jd559c36oMOJM0XSqpfErBcKrtVPHjJneYej4jyeb vVyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=qW4Tcwf/FnMqp0denRrnXohqRV8qgaCk0t1OXd3WVbQ=; b=0bhgrNMrCJl3FADpMk0gXHFsXql8ydurRLaJDyqrWfGFfabuSkh+paMvb7GZuUvShU eCbIhWUDvCigRgAX2qttaskixPW3xSE5gIBDc7jc1mw7DJoPAx7KjhLqFwhl7BxAWvtz 2mw6bYJhgBvxS+8+m6V3QYy/oZeVRVmGmRMzyHKC4mFkAo2d9H11ZE3H2QEJHiBv2xaY u8ncLYOW9zQhIIAiifL+RNPEI75ohwStqfIrZJ2Yu7px27u8CDYeWS1XIhBYQhkmGJbZ NaK7kxort2Eq4H7FPExTEpRkSco3hIlqIOSaAv0cjm3pHqV7zs17jyzJNLum4X5wxWic cRGA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iYGWw6yX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:154a:9f01:87cc:49bb:2900:c08b]) by smtp.gmail.com with ESMTPSA id g23-20020aa78197000000b0061949fe3beasm2921056pfi.22.2023.03.05.17.57.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Mar 2023 17:57:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com Subject: [PATCH v2 4/5] tcg: Add host memory barriers to cpu_ldst.h interfaces Date: Sun, 5 Mar 2023 17:57:09 -0800 Message-Id: <20230306015710.1868853-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230306015710.1868853-1-richard.henderson@linaro.org> References: <20230306015710.1868853-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Bring the majority of helpers into line with the rest of tcg in respecting guest memory ordering. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 14 ++++++++++++++ accel/tcg/cputlb.c | 2 ++ accel/tcg/user-exec.c | 14 ++++++++++++++ 3 files changed, 30 insertions(+) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index b76b597878..0edda5f89f 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -1191,6 +1191,20 @@ static inline size_t tcg_current_code_size(TCGContext *s) # define tcg_req_mo(type) ((type) & ~TCG_TARGET_DEFAULT_MO) #endif +/** + * tcg_req_mo: + * @type: TCGBar + * + * If tcg_req_mo indicates a barrier for @type is required for the + * guest memory model, issue a host memory barrier. + */ +#define cpu_req_mo(type) \ + do { \ + if (tcg_req_mo(type)) { \ + smp_mb(); \ + } \ + } while (0) + /** * tcg_qemu_tb_exec: * @env: pointer to CPUArchState for the CPU diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index e984a98dc4..6a04514427 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2174,6 +2174,7 @@ static inline uint64_t cpu_load_helper(CPUArchState *env, abi_ptr addr, { uint64_t ret; + cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); ret = full_load(env, addr, oi, retaddr); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); return ret; @@ -2586,6 +2587,7 @@ static inline void cpu_store_helper(CPUArchState *env, target_ulong addr, uint64_t val, MemOpIdx oi, uintptr_t ra, FullStoreHelper *full_store) { + cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); full_store(env, addr, val, oi, ra); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 7b37fd229e..489459ae17 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -942,6 +942,7 @@ uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr addr, validate_memop(oi, MO_UB); haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); ret = ldub_p(haddr); clear_helper_retaddr(); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); @@ -956,6 +957,7 @@ uint16_t cpu_ldw_be_mmu(CPUArchState *env, abi_ptr addr, validate_memop(oi, MO_BEUW); haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); ret = lduw_be_p(haddr); clear_helper_retaddr(); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); @@ -970,6 +972,7 @@ uint32_t cpu_ldl_be_mmu(CPUArchState *env, abi_ptr addr, validate_memop(oi, MO_BEUL); haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); ret = ldl_be_p(haddr); clear_helper_retaddr(); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); @@ -984,6 +987,7 @@ uint64_t cpu_ldq_be_mmu(CPUArchState *env, abi_ptr addr, validate_memop(oi, MO_BEUQ); haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); ret = ldq_be_p(haddr); clear_helper_retaddr(); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); @@ -998,6 +1002,7 @@ uint16_t cpu_ldw_le_mmu(CPUArchState *env, abi_ptr addr, validate_memop(oi, MO_LEUW); haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); ret = lduw_le_p(haddr); clear_helper_retaddr(); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); @@ -1012,6 +1017,7 @@ uint32_t cpu_ldl_le_mmu(CPUArchState *env, abi_ptr addr, validate_memop(oi, MO_LEUL); haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); ret = ldl_le_p(haddr); clear_helper_retaddr(); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); @@ -1026,6 +1032,7 @@ uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr addr, validate_memop(oi, MO_LEUQ); haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); ret = ldq_le_p(haddr); clear_helper_retaddr(); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); @@ -1075,6 +1082,7 @@ void cpu_stb_mmu(CPUArchState *env, abi_ptr addr, uint8_t val, validate_memop(oi, MO_UB); haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); stb_p(haddr, val); clear_helper_retaddr(); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); @@ -1087,6 +1095,7 @@ void cpu_stw_be_mmu(CPUArchState *env, abi_ptr addr, uint16_t val, validate_memop(oi, MO_BEUW); haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); stw_be_p(haddr, val); clear_helper_retaddr(); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); @@ -1099,6 +1108,7 @@ void cpu_stl_be_mmu(CPUArchState *env, abi_ptr addr, uint32_t val, validate_memop(oi, MO_BEUL); haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); stl_be_p(haddr, val); clear_helper_retaddr(); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); @@ -1111,6 +1121,7 @@ void cpu_stq_be_mmu(CPUArchState *env, abi_ptr addr, uint64_t val, validate_memop(oi, MO_BEUQ); haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); stq_be_p(haddr, val); clear_helper_retaddr(); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); @@ -1123,6 +1134,7 @@ void cpu_stw_le_mmu(CPUArchState *env, abi_ptr addr, uint16_t val, validate_memop(oi, MO_LEUW); haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); stw_le_p(haddr, val); clear_helper_retaddr(); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); @@ -1135,6 +1147,7 @@ void cpu_stl_le_mmu(CPUArchState *env, abi_ptr addr, uint32_t val, validate_memop(oi, MO_LEUL); haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); stl_le_p(haddr, val); clear_helper_retaddr(); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); @@ -1147,6 +1160,7 @@ void cpu_stq_le_mmu(CPUArchState *env, abi_ptr addr, uint64_t val, validate_memop(oi, MO_LEUQ); haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); stq_le_p(haddr, val); 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([2602:ae:154a:9f01:87cc:49bb:2900:c08b]) by smtp.gmail.com with ESMTPSA id g23-20020aa78197000000b0061949fe3beasm2921056pfi.22.2023.03.05.17.57.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Mar 2023 17:57:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com Subject: [PATCH v2 5/5] accel/tcg: Remove check_tcg_memory_orders_compatible Date: Sun, 5 Mar 2023 17:57:10 -0800 Message-Id: <20230306015710.1868853-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230306015710.1868853-1-richard.henderson@linaro.org> References: <20230306015710.1868853-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We now issue host memory barriers to match the guest memory order. Continue to disable MTTCG only if the guest has not been ported. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- accel/tcg/tcg-all.c | 34 ++++++++-------------------------- 1 file changed, 8 insertions(+), 26 deletions(-) diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 604efd1b18..f6b44548cc 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -61,33 +61,20 @@ DECLARE_INSTANCE_CHECKER(TCGState, TCG_STATE, * they can set the appropriate CONFIG flags in ${target}-softmmu.mak * * Once a guest architecture has been converted to the new primitives - * there are two remaining limitations to check. - * - * - The guest can't be oversized (e.g. 64 bit guest on 32 bit host) - * - The host must have a stronger memory order than the guest - * - * It may be possible in future to support strong guests on weak hosts - * but that will require tagging all load/stores in a guest with their - * implicit memory order requirements which would likely slow things - * down a lot. + * there is one remaining limitation to check: + * - The guest can't be oversized (e.g. 64 bit guest on 32 bit host) */ -static bool check_tcg_memory_orders_compatible(void) -{ - return tcg_req_mo(TCG_MO_ALL) == 0; -} - static bool default_mttcg_enabled(void) { if (icount_enabled() || TCG_OVERSIZED_GUEST) { return false; - } else { -#ifdef TARGET_SUPPORTS_MTTCG - return check_tcg_memory_orders_compatible(); -#else - return false; -#endif } +#if defined(TARGET_SUPPORTS_MTTCG) && defined(TCG_GUEST_DEFAULT_MO) + return true; +#else + return false; +#endif } static void tcg_accel_instance_init(Object *obj) @@ -150,15 +137,10 @@ static void tcg_set_thread(Object *obj, const char *value, Error **errp) } else if (icount_enabled()) { error_setg(errp, "No MTTCG when icount is enabled"); } else { -#ifndef TARGET_SUPPORTS_MTTCG +#if !(defined(TARGET_SUPPORTS_MTTCG) && defined(TCG_GUEST_DEFAULT_MO)) warn_report("Guest not yet converted to MTTCG - " "you may get unexpected results"); #endif - if (!check_tcg_memory_orders_compatible()) { - warn_report("Guest expects a stronger memory ordering " - "than the host provides"); - error_printf("This may cause strange/hard to debug errors\n"); - } s->mttcg_enabled = true; } } else if (strcmp(value, "single") == 0) {