From patchwork Wed Mar 8 15:58:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 660947 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3A21C64EC4 for ; Wed, 8 Mar 2023 16:00:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232340AbjCHQAS (ORCPT ); Wed, 8 Mar 2023 11:00:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231949AbjCHP7o (ORCPT ); Wed, 8 Mar 2023 10:59:44 -0500 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20FD8C889F for ; Wed, 8 Mar 2023 07:59:14 -0800 (PST) Received: by mail-wm1-x336.google.com with SMTP id j19-20020a05600c191300b003eb3e1eb0caso1654396wmq.1 for ; Wed, 08 Mar 2023 07:59:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678291152; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zC3rBAyogCXIAD1VsZOmG00wbKNgTNIw5+yFA7bQttI=; b=Vdv6DOIg4BCC8wPi5HScxqeJh2mHSjYO6LTl1gfFti6HfFGuWves0nNIH6Wr4OVfk9 8JyccT7YLSjOjWhQz/VcyUijhmSx95Y+x+9Xodw0+tZwz795HGocqjAY5tk+Q9jW7eig OLAMi8o7PJU1MFJ24/H80dIvCB8IY859MFJTnDTjrzqMizgpAm2iHiqxl1RQjl6u7nQ0 pirP59iG32qyfdrSEo5z2myvjvLe2l6dTa8wXACP6t5q1+AeaKhsqbcCfr8LdZKzSiLm Djw0no64M3dIvkc3sReHWXNNcdcUC979LD5dMVj7VvSizVQHBf7WrPdWyBACepoICkve 1RhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678291152; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zC3rBAyogCXIAD1VsZOmG00wbKNgTNIw5+yFA7bQttI=; b=U4uZ6GQfz3xvvX1ky1gLo1wrGYLg0EsosbAXqQur90yh/SP4hXWx2OJCReAsIDW3eE sRnvoNkf6V+/+cQsTxfJil2mIyXizobx7BjNiW7EEg9CxRZ90g4jDYp3HAvrhkAE7QSk BGvg7y39rEuew05rTOsbMwLQzowBqKPP/1IWLKKNn7UIRiWKXHPalpej0fK4TDonwW26 YYNHCdhI699b4HfOTJVVfavLcaa2U9DakoySfY6cSFlPsifIANWZt2QActn+XES9WN5W HX2dxNSqCs2cXi8cc6rA28qHdwWKdtAPD5SMf7qfkVDCdRw7dl+l2om/JJDiHnWTJXQX XSbQ== X-Gm-Message-State: AO0yUKXoZoIH4JWFSJDfMm71sNvvH785zVN1o/7ANUakseenBZuHwO5f t0b5uBtws+1HUddOlRSxn2ewVw== X-Google-Smtp-Source: AK7set8YzgMdlIr1cG8BAb8BjyprBjLL4QKMG7It5oJ3gTMQegtLOQwap83fQBD9YQDZcR2AwHDluA== X-Received: by 2002:a05:600c:4447:b0:3ea:c110:55ba with SMTP id v7-20020a05600c444700b003eac11055bamr16585291wmn.18.1678291152568; Wed, 08 Mar 2023 07:59:12 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id 16-20020a05600c229000b003eb2e33f327sm2548430wmf.2.2023.03.08.07.59.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 07:59:12 -0800 (PST) From: Abel Vesa To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , Alim Akhtar , Avri Altman , Bart Van Assche , Adrian Hunter , "James E . J . Bottomley" , "Martin K . Petersen" Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org Subject: [RFC PATCH v2 3/7] dt-bindings: mmc: sdhci-msm: Add ICE phandle and drop core clock Date: Wed, 8 Mar 2023 17:58:34 +0200 Message-Id: <20230308155838.1094920-4-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230308155838.1094920-1-abel.vesa@linaro.org> References: <20230308155838.1094920-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org The ICE will have its own devicetree node, so drop the ICE core clock and add the qcom,ice property instead. Signed-off-by: Abel Vesa --- This patch was not part of the v1. Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml index 64df6919abaf..92f6316c423f 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -80,7 +80,6 @@ properties: - const: iface - const: core - const: xo - - const: ice - const: bus - const: cal - const: sleep @@ -120,6 +119,10 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 description: platform specific settings for DLL_CONFIG reg. + qcom,ice: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the Inline Crypto Engine node + iommus: minItems: 1 maxItems: 8 @@ -180,14 +183,12 @@ allOf: - description: Host controller register map - description: SD Core register map - description: CQE register map - - description: Inline Crypto Engine register map reg-names: minItems: 2 items: - const: hc - const: core - const: cqhci - - const: ice else: properties: reg: @@ -195,13 +196,11 @@ allOf: items: - description: Host controller register map - description: CQE register map - - description: Inline Crypto Engine register map reg-names: minItems: 1 items: - const: hc - const: cqhci - - const: ice unevaluatedProperties: false From patchwork Wed Mar 8 15:58:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 660948 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0F20C7618A for ; Wed, 8 Mar 2023 16:00:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232300AbjCHQAP (ORCPT ); Wed, 8 Mar 2023 11:00:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48050 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232217AbjCHP7o (ORCPT ); Wed, 8 Mar 2023 10:59:44 -0500 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B1D9C88A5 for ; Wed, 8 Mar 2023 07:59:16 -0800 (PST) Received: by mail-wm1-x331.google.com with SMTP id j3so10128948wms.2 for ; Wed, 08 Mar 2023 07:59:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678291154; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DXkNvl7yoyLGSBX8GHeyAqUxbD+ph/7MJHHxxyUtNzE=; b=VozZyfyp/5Kd6Pv/VzwPgj4NxWN9fi7BpA03g1mgWhrFwZWPGp7osUHmK5dEcnGWR7 /SnMRybuD1jyzQwQ8VaBjnTjd1qky48eDG/2GfHUGipCQU19HechBonoyiNkjhD23ps5 lPem13f3rxXCGuxdq9ejvWK6n1ELjvc0mFuc92UvSThw6OhqLL7JDCTVwn2oeJhW/uST zl39eaUTR1eVhAzlz0E0Otq1MMdV7EIfAFAWaypTsb8AKZHVjIlCZi6WsmAyWXY8jVCL za0DnFI1MiPNqmW5CJc/UbD7T1WjxhpyfD7wvoVBCDUdi84aA2D9Hm0J4dKMEQkrS3Im cK/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678291154; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DXkNvl7yoyLGSBX8GHeyAqUxbD+ph/7MJHHxxyUtNzE=; b=CfFxhU1+ibpQvufMFmInOzzQACIc1N5kz+yWZJcLbfcB5HlTMDOgthb8x1MS+/tweR mamGbpY9sttpoRMR4hAmgG4nvdVDEKDOK8at0TDjv1/6fPqPRCQpL9sNvCTx+9qOUEwZ cki827dlkiQWkXn62XFFYdwIp00B/kbBr1yXR1X1X5FiPiV9K/ep/s1m3LCSrZK4CkgE HeVqL7bjcER0vynbcCx4dp4du88EB28hyZClnw5weFnIlDMEZUPSpFsLxCtfbaK7O/Nw MEp7aWELWj4cRfcp8K/hQEHzb+1l5SSUUeTPjrVWq3F5w1gRTPIZWI4ceLcYOsXpRKRv MBvQ== X-Gm-Message-State: AO0yUKXRVZasEtChSpot1fNTjJIKGrLcFRUqGVvSzrztYhyNNgmipf32 7QrBKzP1ZudsWVMYYDXOzpDyBg== X-Google-Smtp-Source: AK7set9AIJEIR/NEKHAQYOwuWYYdYzhjzq5RvXvxjfgt+QemaTy2ofielIk0PZ39oUs5ydam6uGA7A== X-Received: by 2002:a05:600c:3b07:b0:3ea:ea3e:2d36 with SMTP id m7-20020a05600c3b0700b003eaea3e2d36mr17450404wms.24.1678291154429; Wed, 08 Mar 2023 07:59:14 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id 16-20020a05600c229000b003eb2e33f327sm2548430wmf.2.2023.03.08.07.59.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 07:59:13 -0800 (PST) From: Abel Vesa To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , Alim Akhtar , Avri Altman , Bart Van Assche , Adrian Hunter , "James E . J . Bottomley" , "Martin K . Petersen" Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org Subject: [RFC PATCH v2 4/7] soc: qcom: Make the Qualcomm UFS/SDCC ICE a dedicated driver Date: Wed, 8 Mar 2023 17:58:35 +0200 Message-Id: <20230308155838.1094920-5-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230308155838.1094920-1-abel.vesa@linaro.org> References: <20230308155838.1094920-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org This takes the already existing duplicated support in both ufs-qcom and sdhci-msm drivers and makes it a dedicated driver that can be used by both mentioned drivers. The reason for this is because, staring with SM8550, the ICE IP block is shared between UFS and SDCC, which means we need to probe a dedicated device and share it between those two consumers. So let's add the ICE dedicated driver as a soc driver. Signed-off-by: Abel Vesa --- Changes since v1: * renamed filename to simply ice.c * kept all the copyrights from UFS and SDHC drivers * Used GENMASK like Konrad suggested * Fixed the comment about "ICE instance is supported currently", like Konrad suggested * Used FIELD_GET * Dropped extra comment from qcom_ice_low_power_mode_enable * Used lowercase in hex values * Dropped double space from comment above the qcom_ice_program_key function * Changed the dev_info about engine being registered to dev_dbg * Made the compatible entry in the match table a single line * Made the qcom_ice_driver definition consistent with respect to spaces/tabs * Switched QCOM_INLINE_CRYPTO_ENGINE to tristate and made it built-in if any of the UFS or the SDHC drivers are built-in. This is to allow the API to be available even if the built-in driver doesn't have crypto enabled. * Dropped the engine container state. The of_qcom_ice_get will look up the ICE device based on the phandle and get the ICE data from dev data. * Dropped the supported field from qcom_ice definition. * Marked all funtions that are local as static. * Replaced qcom_ice_wait_bist_status function implementation with the one dropped from sdhci-msm.c * Added a separate function for key eviction drivers/soc/qcom/Kconfig | 6 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/ice.c | 301 ++++++++++++++++++++++++++++++++++++++ include/soc/qcom/ice.h | 65 ++++++++ 4 files changed, 373 insertions(+) create mode 100644 drivers/soc/qcom/ice.c create mode 100644 include/soc/qcom/ice.h diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index a8f283086a21..c584369e9810 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -275,4 +275,10 @@ config QCOM_ICC_BWMON the fixed bandwidth votes from cpufreq (CPU nodes) thus achieve high memory throughput even with lower CPU frequencies. +config QCOM_INLINE_CRYPTO_ENGINE + tristate + depends on SCSI_UFS_CRYPTO || MMC_CRYPTO + default y if SCSI_UFS_QCOM=y || MMC_SDHCI_MSM=y + select QCOM_SCM + endmenu diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index 6e88da899f60..0f43a88b4894 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -32,3 +32,4 @@ obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) += kryo-l2-accessors.o obj-$(CONFIG_QCOM_ICC_BWMON) += icc-bwmon.o +obj-$(CONFIG_QCOM_INLINE_CRYPTO_ENGINE) += ice.o diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c new file mode 100644 index 000000000000..ae354e110dc0 --- /dev/null +++ b/drivers/soc/qcom/ice.c @@ -0,0 +1,301 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Qualcomm ICE (Inline Crypto Engine) support. + * + * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019, Google LLC + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include + +#include + +#include + +#define AES_256_XTS_KEY_SIZE 64 + +/* QCOM ICE registers */ +#define QCOM_ICE_REG_VERSION 0x0008 +#define QCOM_ICE_REG_FUSE_SETTING 0x0010 + +/* QCOM ICE v2.X only */ + +#define QCOM_ICE_REG_BIST_STATUS 0x0070 +#define QCOM_ICE_REG_ADVANCED_CONTROL 0x1000 + +/* BIST ("built-in self-test"?) status flags */ +#define QCOM_ICE_BIST_STATUS_MASK GENMASK(31, 28) + +#define QCOM_ICE_FUSE_SETTING_MASK 0x1 +#define QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK 0x2 +#define QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK 0x4 + +#define qcom_ice_writel(engine, val, reg) \ + writel((val), (engine)->base + (reg)) + +#define qcom_ice_readl(engine, reg) \ + readl((engine)->base + (reg)) + +/* Only one ICE instance is currently supported by HW */ +static bool qcom_ice_check_supported(struct qcom_ice *ice) +{ + u32 regval = qcom_ice_readl(ice, QCOM_ICE_REG_VERSION); + struct device *dev = ice->dev; + int major = FIELD_GET(GENMASK(31, 24), regval); + int minor = FIELD_GET(GENMASK(23, 16), regval); + int step = FIELD_GET(GENMASK(15, 0), regval); + + /* For now this driver only supports ICE version 3. */ + if (major != 3) { + dev_warn(dev, "Unsupported ICE version: v%d.%d.%d\n", + major, minor, step); + return false; + } + + dev_info(dev, "Found QC Inline Crypto Engine (ICE) v%d.%d.%d\n", + major, minor, step); + + /* If fuses are blown, ICE might not work in the standard way. */ + regval = qcom_ice_readl(ice, QCOM_ICE_REG_FUSE_SETTING); + if (regval & (QCOM_ICE_FUSE_SETTING_MASK | + QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK | + QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK)) { + dev_warn(dev, "Fuses are blown; ICE is unusable!\n"); + return false; + } + + return true; +} + +static void qcom_ice_low_power_mode_enable(struct qcom_ice *ice) +{ + u32 regval; + + regval = qcom_ice_readl(ice, QCOM_ICE_REG_ADVANCED_CONTROL); + + /* Enable low power mode sequence */ + regval |= 0x7000; + qcom_ice_writel(ice, regval, QCOM_ICE_REG_ADVANCED_CONTROL); +} + +static void qcom_ice_optimization_enable(struct qcom_ice *ice) +{ + u32 regval; + + /* ICE Optimizations Enable Sequence */ + regval = qcom_ice_readl(ice, QCOM_ICE_REG_ADVANCED_CONTROL); + regval |= 0xd807100; + /* ICE HPG requires delay before writing */ + udelay(5); + qcom_ice_writel(ice, regval, QCOM_ICE_REG_ADVANCED_CONTROL); + udelay(5); +} + +/* + * Wait until the ICE BIST (built-in self-test) has completed. + * + * This may be necessary before ICE can be used. + * Note that we don't really care whether the BIST passed or failed; + * we really just want to make sure that it isn't still running. This is + * because (a) the BIST is a FIPS compliance thing that never fails in + * practice, (b) ICE is documented to reject crypto requests if the BIST + * fails, so we needn't do it in software too, and (c) properly testing + * storage encryption requires testing the full storage stack anyway, + * and not relying on hardware-level self-tests. + */ +static int qcom_ice_wait_bist_status(struct qcom_ice *ice) +{ + u32 regval; + int err; + + err = readl_poll_timeout(ice->base + QCOM_ICE_REG_BIST_STATUS, + regval, !(regval & QCOM_ICE_BIST_STATUS_MASK), + 50, 5000); + if (err) + dev_err(ice->dev, + "Timed out waiting for ICE self-test to complete\n"); + return err; +} + +int qcom_ice_resume(struct qcom_ice *ice) +{ + struct device *dev = ice->dev; + int err; + + if (!ice) + return 0; + + err = qcom_ice_wait_bist_status(ice); + if (err) { + dev_err(dev, "BIST status error (%d)\n", err); + return err; + } + + return 0; +} +EXPORT_SYMBOL_GPL(qcom_ice_resume); + +int qcom_ice_enable(struct qcom_ice *ice) +{ + if (!ice) + return 0; + + qcom_ice_low_power_mode_enable(ice); + qcom_ice_optimization_enable(ice); + + return qcom_ice_resume(ice); +} +EXPORT_SYMBOL_GPL(qcom_ice_enable); + +int qcom_ice_program_key(struct qcom_ice *ice, u8 crypto_cap_idx, + u8 algorithm_id, u8 key_size, + const u8 crypto_key[], u8 data_unit_size, + int slot) +{ + struct device *dev; + union { + u8 bytes[AES_256_XTS_KEY_SIZE]; + u32 words[AES_256_XTS_KEY_SIZE / sizeof(u32)]; + } key; + int i; + int err; + + if (!ice) + return 0; + + dev = ice->dev; + + /* Only AES-256-XTS has been tested so far. */ + if (algorithm_id != QCOM_ICE_CRYPTO_ALG_AES_XTS || + key_size != QCOM_ICE_CRYPTO_KEY_SIZE_256) { + dev_err_ratelimited(dev, + "Unhandled crypto capability; algorithm_id=%d, key_size=%d\n", + algorithm_id, key_size); + return -EINVAL; + } + + memcpy(key.bytes, crypto_key, AES_256_XTS_KEY_SIZE); + + /* + * The SCM call byte-swaps the 32-bit words of the key. + * So we have to do the same, in order for the final key be correct. + */ + for (i = 0; i < ARRAY_SIZE(key.words); i++) + __cpu_to_be32s(&key.words[i]); + + err = qcom_scm_ice_set_key(slot, key.bytes, AES_256_XTS_KEY_SIZE, + QCOM_SCM_ICE_CIPHER_AES_256_XTS, + data_unit_size); + + memzero_explicit(&key, sizeof(key)); + + return err; +} +EXPORT_SYMBOL_GPL(qcom_ice_program_key); + +int qcom_ice_evict_key(struct qcom_ice *ice, int slot) +{ + if (!ice) + return 0; + + return qcom_scm_ice_invalidate_key(slot); +} +EXPORT_SYMBOL_GPL(qcom_ice_evict_key); + +struct qcom_ice *of_qcom_ice_get(struct device *dev) +{ + struct platform_device *pdev; + struct qcom_ice *ice = ERR_PTR(-EPROBE_DEFER); + struct device_node *node; + + if (!dev || !dev->of_node) + return ERR_PTR(-ENODEV); + + node = of_parse_phandle(dev->of_node, "qcom,ice", 0); + if (!node) { + ice = NULL; + goto out; + } + + pdev = of_find_device_by_node(node); + if (!pdev) { + dev_err(dev, "Cannot find device node %s\n", node->name); + goto out; + } + + ice = platform_get_drvdata(pdev); + if (!ice) { + dev_err(dev, "Cannot get ice\n"); + put_device(&pdev->dev); + return ERR_PTR(-ENODEV); + } + +out: + of_node_put(node); + + return ice; +} +EXPORT_SYMBOL_GPL(of_qcom_ice_get); + +static int qcom_ice_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct qcom_ice *engine; + + if (!qcom_scm_is_available()) + return -EPROBE_DEFER; + + if (!qcom_scm_ice_available()) { + dev_warn(dev, "ICE SCM interface not found\n"); + return 0; + } + + engine = devm_kzalloc(dev, sizeof(*engine), GFP_KERNEL); + if (!engine) + return -ENOMEM; + + engine->dev = dev; + engine->np = np; + + engine->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(engine->base)) + return PTR_ERR(engine->base); + + engine->core_clk = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(engine->core_clk)) + return dev_err_probe(dev, PTR_ERR(engine->core_clk), + "failed to get and enable core clk\n"); + + if (!qcom_ice_check_supported(engine)) + return -EOPNOTSUPP; + + platform_set_drvdata(pdev, engine); + + dev_dbg(dev, "Registered Qualcomm Inline Crypto Engine\n"); + + return 0; +} + +static const struct of_device_id qcom_ice_of_match_table[] = { + { .compatible = "qcom,inline-crypto-engine" }, + { }, +}; +MODULE_DEVICE_TABLE(of, qcom_ice_of_match_table); + +static struct platform_driver qcom_ice_driver = { + .probe = qcom_ice_probe, + .driver = { + .name = "qcom-ice", + .of_match_table = qcom_ice_of_match_table, + }, +}; + +module_platform_driver(qcom_ice_driver); + +MODULE_DESCRIPTION("Qualcomm Inline Crypto Engine driver"); +MODULE_LICENSE("GPL"); diff --git a/include/soc/qcom/ice.h b/include/soc/qcom/ice.h new file mode 100644 index 000000000000..57062dc97e5d --- /dev/null +++ b/include/soc/qcom/ice.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef __QCOM_ICE_H__ +#define __QCOM_ICE_H__ + +#include + +struct qcom_ice { + struct device *dev; + struct device_node *np; + void __iomem *base; + + struct clk *core_clk; +}; + +enum qcom_ice_crypto_key_size { + QCOM_ICE_CRYPTO_KEY_SIZE_INVALID = 0x0, + QCOM_ICE_CRYPTO_KEY_SIZE_128 = 0x1, + QCOM_ICE_CRYPTO_KEY_SIZE_192 = 0x2, + QCOM_ICE_CRYPTO_KEY_SIZE_256 = 0x3, + QCOM_ICE_CRYPTO_KEY_SIZE_512 = 0x4, +}; + +enum qcom_ice_crypto_alg { + QCOM_ICE_CRYPTO_ALG_AES_XTS = 0x0, + QCOM_ICE_CRYPTO_ALG_BITLOCKER_AES_CBC = 0x1, + QCOM_ICE_CRYPTO_ALG_AES_ECB = 0x2, + QCOM_ICE_CRYPTO_ALG_ESSIV_AES_CBC = 0x3, +}; + +#if IS_ENABLED(CONFIG_QCOM_INLINE_CRYPTO_ENGINE) +int qcom_ice_enable(struct qcom_ice *ice); +int qcom_ice_resume(struct qcom_ice *ice); +struct qcom_ice *of_qcom_ice_get(struct device *dev); +int qcom_ice_program_key(struct qcom_ice *ice, u8 crypto_cap_idx, + u8 algorithm_id, u8 key_size, + const u8 crypto_key[], u8 data_unit_size, + int slot); +int qcom_ice_evict_key(struct qcom_ice *ice, int slot); +#else +static inline int qcom_ice_enable(struct qcom_ice *ice) { return 0; } +static inline int qcom_ice_resume(struct qcom_ice *ice) { return 0; } + +static inline struct qcom_ice *of_qcom_ice_get(struct device *dev) +{ + return NULL; +} + +static inline int qcom_ice_program_key(struct qcom_ice *ice, u8 crypto_cap_idx, + u8 algorithm_id, u8 key_size, + const u8 crypto_key[], u8 data_unit_size, + int slot) +{ + return 0; +} + +static inline int qcom_ice_evict_key(struct qcom_ice *ice, int slot) +{ + return 0; +} +#endif /* CONFIG_QCOM_INLINE_CRYPTO_ENGINE */ +#endif /* __QCOM_ICE_H__ */ From patchwork Wed Mar 8 15:58:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 660946 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6EF0C74A4B for ; Wed, 8 Mar 2023 16:00:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232361AbjCHQAX (ORCPT ); Wed, 8 Mar 2023 11:00:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48148 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232385AbjCHP7r (ORCPT ); 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Wed, 08 Mar 2023 07:59:15 -0800 (PST) From: Abel Vesa To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , Alim Akhtar , Avri Altman , Bart Van Assche , Adrian Hunter , "James E . J . Bottomley" , "Martin K . Petersen" Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org Subject: [RFC PATCH v2 5/7] scsi: ufs: ufs-qcom: Switch to the new ICE API Date: Wed, 8 Mar 2023 17:58:36 +0200 Message-Id: <20230308155838.1094920-6-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230308155838.1094920-1-abel.vesa@linaro.org> References: <20230308155838.1094920-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Now that there is a new dedicated ICE driver, drop the ufs-qcom-ice and use the new ICE api provided by the Qualcomm soc driver qcom-ice. Signed-off-by: Abel Vesa --- Changes since v1: * Added a check for supported algorithm and key size and passed the ICE defined values for algorithm and key size * Added call to evict function drivers/ufs/host/Kconfig | 2 +- drivers/ufs/host/Makefile | 1 - drivers/ufs/host/ufs-qcom-ice.c | 244 -------------------------------- drivers/ufs/host/ufs-qcom.c | 50 +++++-- drivers/ufs/host/ufs-qcom.h | 30 +--- 5 files changed, 46 insertions(+), 281 deletions(-) delete mode 100644 drivers/ufs/host/ufs-qcom-ice.c diff --git a/drivers/ufs/host/Kconfig b/drivers/ufs/host/Kconfig index 8793e3433580..16624ba08050 100644 --- a/drivers/ufs/host/Kconfig +++ b/drivers/ufs/host/Kconfig @@ -59,7 +59,7 @@ config SCSI_UFS_QCOM depends on SCSI_UFSHCD_PLATFORM && ARCH_QCOM depends on GENERIC_MSI_IRQ depends on RESET_CONTROLLER - select QCOM_SCM if SCSI_UFS_CRYPTO + select QCOM_INLINE_CRYPTO_ENGINE if SCSI_UFS_CRYPTO help This selects the QCOM specific additions to UFSHCD platform driver. UFS host on QCOM needs some vendor specific configuration before diff --git a/drivers/ufs/host/Makefile b/drivers/ufs/host/Makefile index d7c5bf7fa512..081b332fe7ce 100644 --- a/drivers/ufs/host/Makefile +++ b/drivers/ufs/host/Makefile @@ -5,7 +5,6 @@ obj-$(CONFIG_SCSI_UFS_DWC_TC_PLATFORM) += tc-dwc-g210-pltfrm.o ufshcd-dwc.o tc-d obj-$(CONFIG_SCSI_UFS_CDNS_PLATFORM) += cdns-pltfrm.o obj-$(CONFIG_SCSI_UFS_QCOM) += ufs_qcom.o ufs_qcom-y += ufs-qcom.o -ufs_qcom-$(CONFIG_SCSI_UFS_CRYPTO) += ufs-qcom-ice.o obj-$(CONFIG_SCSI_UFS_EXYNOS) += ufs-exynos.o obj-$(CONFIG_SCSI_UFSHCD_PCI) += ufshcd-pci.o obj-$(CONFIG_SCSI_UFSHCD_PLATFORM) += ufshcd-pltfrm.o diff --git a/drivers/ufs/host/ufs-qcom-ice.c b/drivers/ufs/host/ufs-qcom-ice.c deleted file mode 100644 index 453978877ae9..000000000000 --- a/drivers/ufs/host/ufs-qcom-ice.c +++ /dev/null @@ -1,244 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Qualcomm ICE (Inline Crypto Engine) support. - * - * Copyright (c) 2014-2019, The Linux Foundation. All rights reserved. - * Copyright 2019 Google LLC - */ - -#include -#include -#include - -#include "ufs-qcom.h" - -#define AES_256_XTS_KEY_SIZE 64 - -/* QCOM ICE registers */ - -#define QCOM_ICE_REG_CONTROL 0x0000 -#define QCOM_ICE_REG_RESET 0x0004 -#define QCOM_ICE_REG_VERSION 0x0008 -#define QCOM_ICE_REG_FUSE_SETTING 0x0010 -#define QCOM_ICE_REG_PARAMETERS_1 0x0014 -#define QCOM_ICE_REG_PARAMETERS_2 0x0018 -#define QCOM_ICE_REG_PARAMETERS_3 0x001C -#define QCOM_ICE_REG_PARAMETERS_4 0x0020 -#define QCOM_ICE_REG_PARAMETERS_5 0x0024 - -/* QCOM ICE v3.X only */ -#define QCOM_ICE_GENERAL_ERR_STTS 0x0040 -#define QCOM_ICE_INVALID_CCFG_ERR_STTS 0x0030 -#define QCOM_ICE_GENERAL_ERR_MASK 0x0044 - -/* QCOM ICE v2.X only */ -#define QCOM_ICE_REG_NON_SEC_IRQ_STTS 0x0040 -#define QCOM_ICE_REG_NON_SEC_IRQ_MASK 0x0044 - -#define QCOM_ICE_REG_NON_SEC_IRQ_CLR 0x0048 -#define QCOM_ICE_REG_STREAM1_ERROR_SYNDROME1 0x0050 -#define QCOM_ICE_REG_STREAM1_ERROR_SYNDROME2 0x0054 -#define QCOM_ICE_REG_STREAM2_ERROR_SYNDROME1 0x0058 -#define QCOM_ICE_REG_STREAM2_ERROR_SYNDROME2 0x005C -#define QCOM_ICE_REG_STREAM1_BIST_ERROR_VEC 0x0060 -#define QCOM_ICE_REG_STREAM2_BIST_ERROR_VEC 0x0064 -#define QCOM_ICE_REG_STREAM1_BIST_FINISH_VEC 0x0068 -#define QCOM_ICE_REG_STREAM2_BIST_FINISH_VEC 0x006C -#define QCOM_ICE_REG_BIST_STATUS 0x0070 -#define QCOM_ICE_REG_BYPASS_STATUS 0x0074 -#define QCOM_ICE_REG_ADVANCED_CONTROL 0x1000 -#define QCOM_ICE_REG_ENDIAN_SWAP 0x1004 -#define QCOM_ICE_REG_TEST_BUS_CONTROL 0x1010 -#define QCOM_ICE_REG_TEST_BUS_REG 0x1014 - -/* BIST ("built-in self-test"?) status flags */ -#define QCOM_ICE_BIST_STATUS_MASK 0xF0000000 - -#define QCOM_ICE_FUSE_SETTING_MASK 0x1 -#define QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK 0x2 -#define QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK 0x4 - -#define qcom_ice_writel(host, val, reg) \ - writel((val), (host)->ice_mmio + (reg)) -#define qcom_ice_readl(host, reg) \ - readl((host)->ice_mmio + (reg)) - -static bool qcom_ice_supported(struct ufs_qcom_host *host) -{ - struct device *dev = host->hba->dev; - u32 regval = qcom_ice_readl(host, QCOM_ICE_REG_VERSION); - int major = regval >> 24; - int minor = (regval >> 16) & 0xFF; - int step = regval & 0xFFFF; - - /* For now this driver only supports ICE version 3. */ - if (major != 3) { - dev_warn(dev, "Unsupported ICE version: v%d.%d.%d\n", - major, minor, step); - return false; - } - - dev_info(dev, "Found QC Inline Crypto Engine (ICE) v%d.%d.%d\n", - major, minor, step); - - /* If fuses are blown, ICE might not work in the standard way. */ - regval = qcom_ice_readl(host, QCOM_ICE_REG_FUSE_SETTING); - if (regval & (QCOM_ICE_FUSE_SETTING_MASK | - QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK | - QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK)) { - dev_warn(dev, "Fuses are blown; ICE is unusable!\n"); - return false; - } - return true; -} - -int ufs_qcom_ice_init(struct ufs_qcom_host *host) -{ - struct ufs_hba *hba = host->hba; - struct device *dev = hba->dev; - struct platform_device *pdev = to_platform_device(dev); - struct resource *res; - int err; - - if (!(ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES) & - MASK_CRYPTO_SUPPORT)) - return 0; - - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ice"); - if (!res) { - dev_warn(dev, "ICE registers not found\n"); - goto disable; - } - - if (!qcom_scm_ice_available()) { - dev_warn(dev, "ICE SCM interface not found\n"); - goto disable; - } - - host->ice_mmio = devm_ioremap_resource(dev, res); - if (IS_ERR(host->ice_mmio)) { - err = PTR_ERR(host->ice_mmio); - return err; - } - - if (!qcom_ice_supported(host)) - goto disable; - - return 0; - -disable: - dev_warn(dev, "Disabling inline encryption support\n"); - hba->caps &= ~UFSHCD_CAP_CRYPTO; - return 0; -} - -static void qcom_ice_low_power_mode_enable(struct ufs_qcom_host *host) -{ - u32 regval; - - regval = qcom_ice_readl(host, QCOM_ICE_REG_ADVANCED_CONTROL); - /* - * Enable low power mode sequence - * [0]-0, [1]-0, [2]-0, [3]-E, [4]-0, [5]-0, [6]-0, [7]-0 - */ - regval |= 0x7000; - qcom_ice_writel(host, regval, QCOM_ICE_REG_ADVANCED_CONTROL); -} - -static void qcom_ice_optimization_enable(struct ufs_qcom_host *host) -{ - u32 regval; - - /* ICE Optimizations Enable Sequence */ - regval = qcom_ice_readl(host, QCOM_ICE_REG_ADVANCED_CONTROL); - regval |= 0xD807100; - /* ICE HPG requires delay before writing */ - udelay(5); - qcom_ice_writel(host, regval, QCOM_ICE_REG_ADVANCED_CONTROL); - udelay(5); -} - -int ufs_qcom_ice_enable(struct ufs_qcom_host *host) -{ - if (!(host->hba->caps & UFSHCD_CAP_CRYPTO)) - return 0; - qcom_ice_low_power_mode_enable(host); - qcom_ice_optimization_enable(host); - return ufs_qcom_ice_resume(host); -} - -/* Poll until all BIST bits are reset */ -static int qcom_ice_wait_bist_status(struct ufs_qcom_host *host) -{ - int count; - u32 reg; - - for (count = 0; count < 100; count++) { - reg = qcom_ice_readl(host, QCOM_ICE_REG_BIST_STATUS); - if (!(reg & QCOM_ICE_BIST_STATUS_MASK)) - break; - udelay(50); - } - if (reg) - return -ETIMEDOUT; - return 0; -} - -int ufs_qcom_ice_resume(struct ufs_qcom_host *host) -{ - int err; - - if (!(host->hba->caps & UFSHCD_CAP_CRYPTO)) - return 0; - - err = qcom_ice_wait_bist_status(host); - if (err) { - dev_err(host->hba->dev, "BIST status error (%d)\n", err); - return err; - } - return 0; -} - -/* - * Program a key into a QC ICE keyslot, or evict a keyslot. QC ICE requires - * vendor-specific SCM calls for this; it doesn't support the standard way. - */ -int ufs_qcom_ice_program_key(struct ufs_hba *hba, - const union ufs_crypto_cfg_entry *cfg, int slot) -{ - union ufs_crypto_cap_entry cap; - union { - u8 bytes[AES_256_XTS_KEY_SIZE]; - u32 words[AES_256_XTS_KEY_SIZE / sizeof(u32)]; - } key; - int i; - int err; - - if (!(cfg->config_enable & UFS_CRYPTO_CONFIGURATION_ENABLE)) - return qcom_scm_ice_invalidate_key(slot); - - /* Only AES-256-XTS has been tested so far. */ - cap = hba->crypto_cap_array[cfg->crypto_cap_idx]; - if (cap.algorithm_id != UFS_CRYPTO_ALG_AES_XTS || - cap.key_size != UFS_CRYPTO_KEY_SIZE_256) { - dev_err_ratelimited(hba->dev, - "Unhandled crypto capability; algorithm_id=%d, key_size=%d\n", - cap.algorithm_id, cap.key_size); - return -EINVAL; - } - - memcpy(key.bytes, cfg->crypto_key, AES_256_XTS_KEY_SIZE); - - /* - * The SCM call byte-swaps the 32-bit words of the key. So we have to - * do the same, in order for the final key be correct. - */ - for (i = 0; i < ARRAY_SIZE(key.words); i++) - __cpu_to_be32s(&key.words[i]); - - err = qcom_scm_ice_set_key(slot, key.bytes, AES_256_XTS_KEY_SIZE, - QCOM_SCM_ICE_CIPHER_AES_256_XTS, - cfg->data_unit_size); - memzero_explicit(&key, sizeof(key)); - return err; -} diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 34fc453f3eb1..f61f957e6d32 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -15,6 +15,8 @@ #include #include +#include + #include #include "ufshcd-pltfrm.h" #include @@ -378,7 +380,7 @@ static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, /* check if UFS PHY moved from DISABLED to HIBERN8 */ err = ufs_qcom_check_hibern8(hba); ufs_qcom_enable_hw_clk_gating(hba); - ufs_qcom_ice_enable(host); + qcom_ice_enable(host->ice); break; default: dev_err(hba->dev, "%s: invalid status %d\n", __func__, status); @@ -634,7 +636,10 @@ static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) return err; } - return ufs_qcom_ice_resume(host); + if (!(host->hba->caps & UFSHCD_CAP_CRYPTO)) + return 0; + + return qcom_ice_resume(host->ice); } static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable) @@ -1034,9 +1039,9 @@ static int ufs_qcom_init(struct ufs_hba *hba) ufs_qcom_set_caps(hba); ufs_qcom_advertise_quirks(hba); - err = ufs_qcom_ice_init(host); - if (err) - goto out_variant_clear; + host->ice = of_qcom_ice_get(dev); + if (IS_ERR(host->ice)) + return PTR_ERR(host->ice); ufs_qcom_setup_clocks(hba, true, POST_CHANGE); @@ -1384,8 +1389,8 @@ static int ufs_qcom_device_reset(struct ufs_hba *hba) #if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND) static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, - struct devfreq_dev_profile *p, - struct devfreq_simple_ondemand_data *d) + struct devfreq_dev_profile *p, + struct devfreq_simple_ondemand_data *d) { p->polling_ms = 60; d->upthreshold = 70; @@ -1399,6 +1404,33 @@ static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, } #endif +#ifdef CONFIG_SCSI_UFS_CRYPTO +int ufs_qcom_program_key(struct ufs_hba *hba, + const union ufs_crypto_cfg_entry *cfg, int slot) +{ + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + union ufs_crypto_cap_entry cap; + bool config_enable = + cfg->config_enable & UFS_CRYPTO_CONFIGURATION_ENABLE; + + /* Only AES-256-XTS has been tested so far. */ + cap = hba->crypto_cap_array[cfg->crypto_cap_idx]; + if (cap.algorithm_id != UFS_CRYPTO_ALG_AES_XTS || + cap.key_size != UFS_CRYPTO_KEY_SIZE_256) + return -EINVAL; + + if (config_enable) + return qcom_ice_program_key(host->ice, + cfg->crypto_cap_idx, + QCOM_ICE_CRYPTO_ALG_AES_XTS, + QCOM_ICE_CRYPTO_KEY_SIZE_256, + cfg->crypto_key, + cfg->data_unit_size, slot); + else + return qcom_ice_evict_key(host->ice, slot); +} +#endif + static void ufs_qcom_reinit_notify(struct ufs_hba *hba) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); @@ -1651,7 +1683,9 @@ static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = { .dbg_register_dump = ufs_qcom_dump_dbg_regs, .device_reset = ufs_qcom_device_reset, .config_scaling_param = ufs_qcom_config_scaling_param, - .program_key = ufs_qcom_ice_program_key, +#ifdef CONFIG_SCSI_UFS_CRYPTO + .program_key = ufs_qcom_program_key, +#endif .reinit_notify = ufs_qcom_reinit_notify, .mcq_config_resource = ufs_qcom_mcq_config_resource, .get_hba_mac = ufs_qcom_get_hba_mac, diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 39e774254fb2..fea39ccd90fc 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -7,6 +7,7 @@ #include #include +#include #include #define MAX_UFS_QCOM_HOSTS 1 @@ -205,12 +206,11 @@ struct ufs_qcom_host { struct clk *tx_l1_sync_clk; bool is_lane_clks_enabled; + struct qcom_ice *ice; + void __iomem *dev_ref_clk_ctrl_mmio; bool is_dev_ref_clk_enabled; struct ufs_hw_version hw_ver; -#ifdef CONFIG_SCSI_UFS_CRYPTO - void __iomem *ice_mmio; -#endif u32 dev_ref_clk_en_mask; @@ -248,28 +248,4 @@ static inline bool ufs_qcom_cap_qunipro(struct ufs_qcom_host *host) return host->caps & UFS_QCOM_CAP_QUNIPRO; } -/* ufs-qcom-ice.c */ - -#ifdef CONFIG_SCSI_UFS_CRYPTO -int ufs_qcom_ice_init(struct ufs_qcom_host *host); -int ufs_qcom_ice_enable(struct ufs_qcom_host *host); -int ufs_qcom_ice_resume(struct ufs_qcom_host *host); -int ufs_qcom_ice_program_key(struct ufs_hba *hba, - const union ufs_crypto_cfg_entry *cfg, int slot); -#else -static inline int ufs_qcom_ice_init(struct ufs_qcom_host *host) -{ - return 0; -} -static inline int ufs_qcom_ice_enable(struct ufs_qcom_host *host) -{ - return 0; -} -static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host) -{ - return 0; -} -#define ufs_qcom_ice_program_key NULL -#endif /* !CONFIG_SCSI_UFS_CRYPTO */ - #endif /* UFS_QCOM_H_ */ From patchwork Wed Mar 8 15:58:38 2023 Content-Type: text/plain; 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Wed, 08 Mar 2023 07:59:20 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id 16-20020a05600c229000b003eb2e33f327sm2548430wmf.2.2023.03.08.07.59.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 07:59:19 -0800 (PST) From: Abel Vesa To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , Alim Akhtar , Avri Altman , Bart Van Assche , Adrian Hunter , "James E . J . Bottomley" , "Martin K . Petersen" Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org Subject: [RFC PATCH v2 7/7] arm64: dts: qcom: Add the Inline Crypto Engine nodes Date: Wed, 8 Mar 2023 17:58:38 +0200 Message-Id: <20230308155838.1094920-8-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230308155838.1094920-1-abel.vesa@linaro.org> References: <20230308155838.1094920-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Drop all properties related to ICE from every UFS and SDCC node, for all platforms, and add dedicated ICE nodes for each platform. On most platforms, there is only one ICE instance, used by either UFS or SDCC, but there are some platforms that have two separate instances and, therefore, two separate nodes are added. Signed-off-by: Abel Vesa --- Changes since v1: * Made changes for all platforms that use ICE, as a single patch since most changes look really similar. arch/arm64/boot/dts/qcom/sdm630.dtsi | 18 +++++++++----- arch/arm64/boot/dts/qcom/sdm670.dtsi | 15 +++++++---- arch/arm64/boot/dts/qcom/sdm845.dtsi | 21 +++++++++------- arch/arm64/boot/dts/qcom/sm6115.dtsi | 37 +++++++++++++++++----------- arch/arm64/boot/dts/qcom/sm6350.dtsi | 31 ++++++++++++++--------- arch/arm64/boot/dts/qcom/sm8150.dtsi | 21 +++++++++------- arch/arm64/boot/dts/qcom/sm8450.dtsi | 22 ++++++++++------- 7 files changed, 102 insertions(+), 63 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 5827cda270a0..2aed49104d9d 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1330,9 +1330,8 @@ opp-200000000 { sdhc_1: mmc@c0c4000 { compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; reg = <0x0c0c4000 0x1000>, - <0x0c0c5000 0x1000>, - <0x0c0c8000 0x8000>; - reg-names = "hc", "cqhci", "ice"; + <0x0c0c5000 0x1000>; + reg-names = "hc", "cqhci"; interrupts = , ; @@ -1340,9 +1339,8 @@ sdhc_1: mmc@c0c4000 { clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, - <&xo_board>, - <&gcc GCC_SDCC1_ICE_CORE_CLK>; - clock-names = "iface", "core", "xo", "ice"; + <&xo_board>; + clock-names = "iface", "core", "xo"; interconnects = <&a2noc 2 &a2noc 10>, <&gnoc 0 &cnoc 27>; @@ -1353,6 +1351,8 @@ sdhc_1: mmc@c0c4000 { pinctrl-1 = <&sdc1_state_off>; power-domains = <&rpmpd SDM660_VDDCX>; + qcom,ice = <&ice>; + bus-width = <8>; non-removable; @@ -1382,6 +1382,12 @@ opp-384000000 { }; }; + ice: inline-crypto-engine@c0c8000 { + compatible = "qcom,inline-crypto-engine"; + reg = <0x0c0c8000 0x8000>; + clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>; + }; + usb2: usb@c2f8800 { compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; reg = <0x0c2f8800 0x400>; diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index 02f14692dd9d..7c1c01a8fdae 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -416,9 +416,8 @@ qusb2_hstx_trim: hstx-trim@1eb { sdhc_1: mmc@7c4000 { compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x007c4000 0 0x1000>, - <0 0x007c5000 0 0x1000>, - <0 0x007c8000 0 0x8000>; - reg-names = "hc", "cqhci", "ice"; + <0 0x007c5000 0 0x1000>; + reg-names = "hc", "cqhci"; interrupts = , ; @@ -427,9 +426,8 @@ sdhc_1: mmc@7c4000 { clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_SDCC1_ICE_CORE_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; - clock-names = "iface", "core", "xo", "ice", "bus"; + clock-names = "iface", "core", "xo", "bus"; iommus = <&apps_smmu 0x140 0xf>; @@ -440,10 +438,17 @@ sdhc_1: mmc@7c4000 { bus-width = <8>; non-removable; + qcom,ice = <&ice>; status = "disabled"; }; + ice: inline-crypto-engine@7c8000 { + compatible = "qcom,inline-crypto-engine"; + reg = <0 0x007c8000 0 0x8000>; + clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>; + }; + gpi_dma0: dma-controller@800000 { #dma-cells = <3>; compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma"; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 479859bd8ab3..80cf76dc612c 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2543,9 +2543,8 @@ mmss_noc: interconnect@1740000 { ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x2500>, - <0 0x01d90000 0 0x8000>; - reg-names = "std", "ice"; + reg = <0 0x01d84000 0 0x2500>; + reg-names = "std"; interrupts = ; phys = <&ufs_mem_phy_lanes>; phy-names = "ufsphy"; @@ -2565,8 +2564,7 @@ ufs_mem_hc: ufshc@1d84000 { "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", - "rx_lane1_sync_clk", - "ice_core_clk"; + "rx_lane1_sync_clk"; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, @@ -2575,8 +2573,7 @@ ufs_mem_hc: ufshc@1d84000 { <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, - <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; freq-table-hz = <50000000 200000000>, <0 0>, @@ -2585,12 +2582,18 @@ ufs_mem_hc: ufshc@1d84000 { <0 0>, <0 0>, <0 0>, - <0 0>, - <0 300000000>; + <0 0>; + qcom,ice = <&ice>; status = "disabled"; }; + ice: inline-crypto-engine@1d90000 { + compatible = "qcom,inline-crypto-engine"; + reg = <0 0x01d90000 0 0x8000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + ufs_mem_phy: phy@1d87000 { compatible = "qcom,sdm845-qmp-ufs-phy"; reg = <0 0x01d87000 0 0x18c>; diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 4d6ec815b78b..0ac12c839bc1 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -717,9 +717,8 @@ sram@4690000 { sdhc_1: mmc@4744000 { compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; reg = <0x0 0x04744000 0x0 0x1000>, - <0x0 0x04745000 0x0 0x1000>, - <0x0 0x04748000 0x0 0x8000>; - reg-names = "hc", "cqhci", "ice"; + <0x0 0x04745000 0x0 0x1000>; + reg-names = "hc", "cqhci"; interrupts = , ; @@ -727,18 +726,24 @@ sdhc_1: mmc@4744000 { clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, - <&rpmcc RPM_SMD_XO_CLK_SRC>, - <&gcc GCC_SDCC1_ICE_CORE_CLK>; - clock-names = "iface", "core", "xo", "ice"; + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "core", "xo"; pinctrl-0 = <&sdc1_state_on>; pinctrl-1 = <&sdc1_state_off>; pinctrl-names = "default", "sleep"; bus-width = <8>; + qcom,ice = <&sdhc_ice>; status = "disabled"; }; + sdhc_ice: inline-crypto-engine@4748000 { + compatible = "qcom,inline-crypto-engine"; + reg = <0 0x04748000 0 0x8000>; + clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>; + }; + sdhc_2: mmc@4784000 { compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; reg = <0x0 0x04784000 0x0 0x1000>; @@ -784,8 +789,8 @@ opp-202000000 { ufs_mem_hc: ufs@4804000 { compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>; - reg-names = "std", "ice"; + reg = <0x0 0x04804000 0x0 0x3000>; + reg-names = "std"; interrupts = ; phys = <&ufs_mem_phy_lanes>; phy-names = "ufsphy"; @@ -803,16 +808,14 @@ ufs_mem_hc: ufs@4804000 { <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; clock-names = "core_clk", "bus_aggr_clk", "iface_clk", "core_clk_unipro", "ref_clk", "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "ice_core_clk"; + "rx_lane0_sync_clk"; freq-table-hz = <50000000 200000000>, <0 0>, @@ -820,12 +823,18 @@ ufs_mem_hc: ufs@4804000 { <37500000 150000000>, <0 0>, <0 0>, - <0 0>, - <75000000 300000000>; + <0 0>; + qcom,ice = <&ufs_ice>; status = "disabled"; }; + ufs_ice: inline-crypto-engine@4810000 { + compatible = "qcom,inline-crypto-engine"; + reg = <0 0x04810000 0 0x8000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + ufs_mem_phy: phy@4807000 { compatible = "qcom,sm6115-qmp-ufs-phy"; reg = <0x0 0x04807000 0x0 0x1c4>; diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 1e1d366c92c1..ed28f8e3626b 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -638,9 +638,8 @@ rng: rng@793000 { sdhc_1: mmc@7c4000 { compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x007c4000 0 0x1000>, - <0 0x007c5000 0 0x1000>, - <0 0x007c8000 0 0x8000>; - reg-names = "hc", "cqhci", "ice"; + <0 0x007c5000 0 0x1000>; + reg-names = "hc", "cqhci"; interrupts = , ; @@ -659,6 +658,7 @@ sdhc_1: mmc@7c4000 { bus-width = <8>; non-removable; supports-cqe; + qcom,ice = <&sdhc_ice>; status = "disabled"; @@ -682,6 +682,12 @@ opp-384000000 { }; }; + sdhc_ice: inline-crypto-engine@c0c8000 { + compatible = "qcom,inline-crypto-engine"; + reg = <0 0x007c8000 0 0x8000>; + clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>; + }; + gpi_dma0: dma-controller@800000 { compatible = "qcom,sm6350-gpi-dma"; reg = <0 0x00800000 0 0x60000>; @@ -933,9 +939,8 @@ mmss_noc: interconnect@1740000 { ufs_mem_hc: ufs@1d84000 { compatible = "qcom,sm6350-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x3000>, - <0 0x01d90000 0 0x8000>; - reg-names = "std", "ice"; + reg = <0 0x01d84000 0 0x3000>; + reg-names = "std"; interrupts = ; phys = <&ufs_mem_phy_lanes>; phy-names = "ufsphy"; @@ -955,8 +960,7 @@ ufs_mem_hc: ufs@1d84000 { "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", - "rx_lane1_sync_clk", - "ice_core_clk"; + "rx_lane1_sync_clk"; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>, @@ -964,8 +968,7 @@ ufs_mem_hc: ufs@1d84000 { <&rpmhcc RPMH_QLINK_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, - <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; freq-table-hz = <50000000 200000000>, <0 0>, @@ -974,8 +977,8 @@ ufs_mem_hc: ufs@1d84000 { <75000000 300000000>, <0 0>, <0 0>, - <0 0>, <0 0>; + qcom,ice = <&ufs_ice>; status = "disabled"; }; @@ -1007,6 +1010,12 @@ ufs_mem_phy_lanes: phy@1d87400 { }; }; + ufs_ice: inline-crypto-engine@1d90000 { + compatible = "qcom,inline-crypto-engine"; + reg = <0 0x01d90000 0 0x8000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + ipa: ipa@1e40000 { compatible = "qcom,sm6350-ipa"; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index fd20096cfc6e..844c7b80d205 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1983,9 +1983,8 @@ pcie1_lane: phy@1c0e200 { ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x2500>, - <0 0x01d90000 0 0x8000>; - reg-names = "std", "ice"; + reg = <0 0x01d84000 0 0x2500>; + reg-names = "std"; interrupts = ; phys = <&ufs_mem_phy_lanes>; phy-names = "ufsphy"; @@ -2004,8 +2003,7 @@ ufs_mem_hc: ufshc@1d84000 { "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", - "rx_lane1_sync_clk", - "ice_core_clk"; + "rx_lane1_sync_clk"; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, @@ -2014,8 +2012,7 @@ ufs_mem_hc: ufshc@1d84000 { <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, - <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; freq-table-hz = <37500000 300000000>, <0 0>, @@ -2024,8 +2021,8 @@ ufs_mem_hc: ufshc@1d84000 { <0 0>, <0 0>, <0 0>, - <0 0>, - <0 300000000>; + <0 0>; + qcom,ice = <&ice>; status = "disabled"; }; @@ -2057,6 +2054,12 @@ ufs_mem_phy_lanes: phy@1d87400 { }; }; + ice: inline-crypto-engine@1d90000 { + compatible = "qcom,inline-crypto-engine"; + reg = <0 0x01d90000 0 0x8000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>; diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 1a744a33bcf4..8ebe6184a9c3 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3989,9 +3989,8 @@ system-cache-controller@19200000 { ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8450-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x3000>, - <0 0x01d88000 0 0x8000>; - reg-names = "std", "ice"; + reg = <0 0x01d84000 0 0x3000>; + reg-names = "std"; interrupts = ; phys = <&ufs_mem_phy_lanes>; phy-names = "ufsphy"; @@ -4015,8 +4014,7 @@ ufs_mem_hc: ufshc@1d84000 { "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", - "rx_lane1_sync_clk", - "ice_core_clk"; + "rx_lane1_sync_clk"; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, @@ -4025,8 +4023,7 @@ ufs_mem_hc: ufshc@1d84000 { <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, - <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; freq-table-hz = <75000000 300000000>, <0 0>, @@ -4035,8 +4032,9 @@ ufs_mem_hc: ufshc@1d84000 { <75000000 300000000>, <0 0>, <0 0>, - <0 0>, - <75000000 300000000>; + <0 0>; + qcom,ice = <&ice>; + status = "disabled"; }; @@ -4066,6 +4064,12 @@ ufs_mem_phy_lanes: phy@1d87400 { }; }; + ice: inline-crypto-engine@1d88000 { + compatible = "qcom,inline-crypto-engine"; + reg = <0 0x01d88000 0 0x8000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + sdhc_2: mmc@8804000 { compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>;