From patchwork Fri Mar 17 21:29:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 664651 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE51BC74A5B for ; Fri, 17 Mar 2023 21:30:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230241AbjCQVac (ORCPT ); Fri, 17 Mar 2023 17:30:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230116AbjCQVa3 (ORCPT ); Fri, 17 Mar 2023 17:30:29 -0400 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B83C547838; Fri, 17 Mar 2023 14:30:20 -0700 (PDT) Received: by mail-ed1-x52d.google.com with SMTP id h8so25391049ede.8; Fri, 17 Mar 2023 14:30:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679088619; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MnURxZI1suPSaEDTpxd+ifaQ2eMQxg73RycWrn38PLc=; b=Jj5cHoXuo5vzuSHuaVZbpDptwdnrQJOqG+lrz4fpGuSjXLn511bCvc6l8wzjYv/GF6 u1TlV+M9HKoSnT4HMg6PS5ZxqLlxUFNZKU7utAqqRzKzOXCqzDj3U5t02bIc6mb3VidN pBW+3W+37SarmpO6Qxe6gcwthXBTP6jUQQCDNfCOONMh8AaaQ2//fQ+Bdf1ktP2zhLhd dOTNWt5E6g/GnJrVTkvtAhqni2yaeijzNzWNYs3/HqUMY6kyABLhbHhDVuTonjK3RVoz i/wTryiWHA/rysxTvmicxdS/hcEu3vw375vYj00x/rarTD7vseoHWikl2Zpkwj+LRzZ/ pZxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679088619; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MnURxZI1suPSaEDTpxd+ifaQ2eMQxg73RycWrn38PLc=; b=2B3r+UJggSgL4csRjmnNn3rO6Zq+vYA9H54zMvRUdxTLlAe63vI4okXX84eDoJZtpH ybGyHO/DyLEl/tD5eeuPJWVK/ORzcCWh4kJ5AR+/ke3LpWPgWtmNoq8LglbzN3wImSDg W8jMSotsIbwLDZQgVmonf17Ngb/4ZrRD7K6tYmeZI8nxCHU7UotRix7DYpFemAY+Y6do Wp0NIwjq+PJ5Gpjw3E0XBOL/1jxuIQI24Ez8gkZ0MigfkPMLmUOWgBMvrXimycH2vthy kIwiJi4b5fvRs5GlzYCc+qrn/j3tPfX0lVViTFfJFC85vesBe5n5HZc8wRFd0kK8UVqu y+sw== X-Gm-Message-State: AO0yUKWVWnJmSOs1RRn0VPdtqYvlsc+gPN75CT2PaD9n4rgidN3fMeq9 qwlrb4x7pIPqCTiBYQKv4jw= X-Google-Smtp-Source: AK7set8RLsaF8wDQPtds1b75SoWVe0h8Xb0S/esh2wCPRjjFFANgtzOE/9FwEcwd2mV/vp5opNVNpg== X-Received: by 2002:a17:906:2dd3:b0:931:52d4:1b7c with SMTP id h19-20020a1709062dd300b0093152d41b7cmr725214eji.62.1679088619024; Fri, 17 Mar 2023 14:30:19 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.30.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:30:18 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Sergio Paracuellos , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?utf-8?q?Bernhard_Rosenkr=C3=A4nze?= =?utf-8?q?r?= , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 01/21] pinctrl: ralink: reintroduce ralink,rt2880-pinmux compatible string Date: Sat, 18 Mar 2023 00:29:51 +0300 Message-Id: <20230317213011.13656-2-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Arınç ÜNAL There have been stable releases with the ralink,rt2880-pinmux compatible string included. Having it removed breaks the ABI. Reintroduce it. Fixes: e5981cd46183 ("pinctrl: ralink: add new compatible strings for each pinctrl subdriver") Signed-off-by: Arınç ÜNAL Reviewed-by: Sergio Paracuellos --- drivers/pinctrl/ralink/pinctrl-mt7620.c | 1 + drivers/pinctrl/ralink/pinctrl-mt7621.c | 1 + drivers/pinctrl/ralink/pinctrl-rt2880.c | 1 + drivers/pinctrl/ralink/pinctrl-rt305x.c | 1 + drivers/pinctrl/ralink/pinctrl-rt3883.c | 1 + 5 files changed, 5 insertions(+) diff --git a/drivers/pinctrl/ralink/pinctrl-mt7620.c b/drivers/pinctrl/ralink/pinctrl-mt7620.c index 4e8d26bb3430..06b86c726839 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7620.c +++ b/drivers/pinctrl/ralink/pinctrl-mt7620.c @@ -372,6 +372,7 @@ static int mt7620_pinctrl_probe(struct platform_device *pdev) static const struct of_device_id mt7620_pinctrl_match[] = { { .compatible = "ralink,mt7620-pinctrl" }, + { .compatible = "ralink,rt2880-pinmux" }, {} }; MODULE_DEVICE_TABLE(of, mt7620_pinctrl_match); diff --git a/drivers/pinctrl/ralink/pinctrl-mt7621.c b/drivers/pinctrl/ralink/pinctrl-mt7621.c index eddc0ba6d468..fb5824922e78 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7621.c +++ b/drivers/pinctrl/ralink/pinctrl-mt7621.c @@ -97,6 +97,7 @@ static int mt7621_pinctrl_probe(struct platform_device *pdev) static const struct of_device_id mt7621_pinctrl_match[] = { { .compatible = "ralink,mt7621-pinctrl" }, + { .compatible = "ralink,rt2880-pinmux" }, {} }; MODULE_DEVICE_TABLE(of, mt7621_pinctrl_match); diff --git a/drivers/pinctrl/ralink/pinctrl-rt2880.c b/drivers/pinctrl/ralink/pinctrl-rt2880.c index 3e2f1aaaf095..d7a65fcc7755 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt2880.c +++ b/drivers/pinctrl/ralink/pinctrl-rt2880.c @@ -41,6 +41,7 @@ static int rt2880_pinctrl_probe(struct platform_device *pdev) static const struct of_device_id rt2880_pinctrl_match[] = { { .compatible = "ralink,rt2880-pinctrl" }, + { .compatible = "ralink,rt2880-pinmux" }, {} }; MODULE_DEVICE_TABLE(of, rt2880_pinctrl_match); diff --git a/drivers/pinctrl/ralink/pinctrl-rt305x.c b/drivers/pinctrl/ralink/pinctrl-rt305x.c index bdaee5ce1ee0..f6092c64383e 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt305x.c +++ b/drivers/pinctrl/ralink/pinctrl-rt305x.c @@ -118,6 +118,7 @@ static int rt305x_pinctrl_probe(struct platform_device *pdev) static const struct of_device_id rt305x_pinctrl_match[] = { { .compatible = "ralink,rt305x-pinctrl" }, + { .compatible = "ralink,rt2880-pinmux" }, {} }; MODULE_DEVICE_TABLE(of, rt305x_pinctrl_match); diff --git a/drivers/pinctrl/ralink/pinctrl-rt3883.c b/drivers/pinctrl/ralink/pinctrl-rt3883.c index 392208662355..5f766d76bafa 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt3883.c +++ b/drivers/pinctrl/ralink/pinctrl-rt3883.c @@ -88,6 +88,7 @@ static int rt3883_pinctrl_probe(struct platform_device *pdev) static const struct of_device_id rt3883_pinctrl_match[] = { { .compatible = "ralink,rt3883-pinctrl" }, + { .compatible = "ralink,rt2880-pinmux" }, {} }; MODULE_DEVICE_TABLE(of, rt3883_pinctrl_match); From patchwork Fri Mar 17 21:29:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 665086 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C19CC6FD1D for ; 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Fri, 17 Mar 2023 14:30:21 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Sergio Paracuellos , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?utf-8?q?Bernhard_Rosenkr=C3=A4nze?= =?utf-8?q?r?= , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 02/21] pinctrl: ralink: rt305x: add new compatible string for every SoC Date: Sat, 18 Mar 2023 00:29:52 +0300 Message-Id: <20230317213011.13656-3-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Arınç ÜNAL Add new compatible strings to make every SoC, or SoCs that use the same pinmux data have a unique compatible string. This ensures that the pin muxing information of every SoC, or a set of SoCs that use the same pinmux data can be properly documented. Signed-off-by: Arınç ÜNAL Reviewed-by: Sergio Paracuellos --- drivers/pinctrl/ralink/pinctrl-rt305x.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pinctrl/ralink/pinctrl-rt305x.c b/drivers/pinctrl/ralink/pinctrl-rt305x.c index f6092c64383e..fa3743c7680f 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt305x.c +++ b/drivers/pinctrl/ralink/pinctrl-rt305x.c @@ -118,6 +118,8 @@ static int rt305x_pinctrl_probe(struct platform_device *pdev) static const struct of_device_id rt305x_pinctrl_match[] = { { .compatible = "ralink,rt305x-pinctrl" }, + { .compatible = "ralink,rt3352-pinctrl" }, + { .compatible = "ralink,rt5350-pinctrl" }, { .compatible = "ralink,rt2880-pinmux" }, {} }; From patchwork Fri Mar 17 21:29:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 664650 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6DD79C6FD1D for ; Fri, 17 Mar 2023 21:30:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230366AbjCQVaf (ORCPT ); Fri, 17 Mar 2023 17:30:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41568 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230326AbjCQVad (ORCPT ); Fri, 17 Mar 2023 17:30:33 -0400 Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DCFFFEC74; Fri, 17 Mar 2023 14:30:25 -0700 (PDT) Received: by mail-ed1-x535.google.com with SMTP id fd5so25398016edb.7; Fri, 17 Mar 2023 14:30:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679088624; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eZtcbxuenv5Hgd7He4MoaSBQyHio/C6M7ta0+avs8ds=; b=WSrV0fU2m5Wh2diMnpwUZhBdMSnmoYqbGIs54XQGgoWlnmvkJ2cX92tfz3O56F/nhQ 0qRtyTeJNF2AxGKwb/Eu9JQlB81bz1eOBJ0gKeEEPfDJuuBxGt/FZ7JWJEn768BIYYU9 rVhH9A2L753/4X/90Wgm17ZQUz5yEjjKkKenwrWa4CPZN+4SjggMPWZiqCECKXt4Mqa2 lGUJnzWog8MHFH/++4NEA3fjk3591g8imDpjSiLekbonj0ROx1VQcIO71dl92MT9p1aJ p/+10PYgiibNPEKmY1XRseE2jVJcjHBT7jA/4B6xAdh65i1tlDgZ0SaTFzQwCqBwx+8g J0UQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679088624; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eZtcbxuenv5Hgd7He4MoaSBQyHio/C6M7ta0+avs8ds=; b=SSKz9hDJZ4hiSslQ+N1wJ0QyDoaTgYK2s3p0kro1ruXyNTEviXJPvxCx2ZO+B+mxBx iIbHeMKCVTpXJ/NyP8NNIGyxsYdmXCwPmUYtIlPAOn0w0fjHAB+kxoX/jp34BDeWsHBx zWs/bjVzoesbWOkQzCaNltwa4kFe5S4pAdI8gMX0S6P4PCG/URaygEYUmsGLetVhzOp4 RNzMKyp3kBYRSVZA4bERjPxyOlRMFS3yhGpG1YfyararaT3EsedTuStHNEWtABejuuP2 jL/Qax9fMRHHonaB+Fm1NcvXdNsNq4kLMdSV8sYJIiX46rLV/TC9Wu5EEfiJ3p0JJ5K7 zkOw== X-Gm-Message-State: AO0yUKW8ZMOy/HBNg5jJnkktwYqVgpfmuCdjcSEIdS93aMmWaPQ38mPi J6oxJ7damKMH96beDTHTjeo= X-Google-Smtp-Source: AK7set+G4AmnAACcS2WO8v3IH0Z01X8prMZl4wEN2qCqWv+fKNTfOjF0G3frWV05Z7c3GhxRrVQj1Q== X-Received: by 2002:a17:907:381:b0:88f:9c29:d232 with SMTP id ss1-20020a170907038100b0088f9c29d232mr768885ejb.57.1679088624077; Fri, 17 Mar 2023 14:30:24 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.30.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:30:23 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Sergio Paracuellos , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?utf-8?q?Bernhard_Rosenkr=C3=A4nze?= =?utf-8?q?r?= , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 03/21] pinctrl: ralink: mt7620: split out to mt76x8 Date: Sat, 18 Mar 2023 00:29:53 +0300 Message-Id: <20230317213011.13656-4-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Arınç ÜNAL Split the driver out to pinctrl-mt76x8.c. Remove including the unnecessary headers since is_mt76x8() is not being used anymore. Introduce a new compatible string to be able to document the pin muxing information properly. Signed-off-by: Arınç ÜNAL Reviewed-by: Sergio Paracuellos --- drivers/pinctrl/ralink/Kconfig | 5 + drivers/pinctrl/ralink/Makefile | 1 + drivers/pinctrl/ralink/pinctrl-mt7620.c | 257 +-------------------- drivers/pinctrl/ralink/pinctrl-mt76x8.c | 283 ++++++++++++++++++++++++ 4 files changed, 290 insertions(+), 256 deletions(-) create mode 100644 drivers/pinctrl/ralink/pinctrl-mt76x8.c diff --git a/drivers/pinctrl/ralink/Kconfig b/drivers/pinctrl/ralink/Kconfig index 1e4c5e43d69b..c5fe4c31aaea 100644 --- a/drivers/pinctrl/ralink/Kconfig +++ b/drivers/pinctrl/ralink/Kconfig @@ -17,6 +17,11 @@ config PINCTRL_MT7621 depends on RALINK && SOC_MT7621 select PINCTRL_RALINK +config PINCTRL_MT76X8 + bool "MT76X8 pinctrl subdriver" + depends on RALINK && SOC_MT7620 + select PINCTRL_RALINK + config PINCTRL_RT2880 bool "RT2880 pinctrl subdriver" depends on RALINK && SOC_RT288X diff --git a/drivers/pinctrl/ralink/Makefile b/drivers/pinctrl/ralink/Makefile index 0ebbe552526d..be9acf2e27fd 100644 --- a/drivers/pinctrl/ralink/Makefile +++ b/drivers/pinctrl/ralink/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_PINCTRL_RALINK) += pinctrl-ralink.o obj-$(CONFIG_PINCTRL_MT7620) += pinctrl-mt7620.o obj-$(CONFIG_PINCTRL_MT7621) += pinctrl-mt7621.o +obj-$(CONFIG_PINCTRL_MT76X8) += pinctrl-mt76x8.o obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o obj-$(CONFIG_PINCTRL_RT305X) += pinctrl-rt305x.o obj-$(CONFIG_PINCTRL_RT3883) += pinctrl-rt3883.o diff --git a/drivers/pinctrl/ralink/pinctrl-mt7620.c b/drivers/pinctrl/ralink/pinctrl-mt7620.c index 06b86c726839..3f6ffccc6882 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7620.c +++ b/drivers/pinctrl/ralink/pinctrl-mt7620.c @@ -1,7 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -#include -#include #include #include #include @@ -112,262 +110,9 @@ static struct ralink_pmx_group mt7620a_pinmux_data[] = { { 0 } }; -static struct ralink_pmx_func pwm1_grp_mt76x8[] = { - FUNC("sdxc d6", 3, 19, 1), - FUNC("utif", 2, 19, 1), - FUNC("gpio", 1, 19, 1), - FUNC("pwm1", 0, 19, 1), -}; - -static struct ralink_pmx_func pwm0_grp_mt76x8[] = { - FUNC("sdxc d7", 3, 18, 1), - FUNC("utif", 2, 18, 1), - FUNC("gpio", 1, 18, 1), - FUNC("pwm0", 0, 18, 1), -}; - -static struct ralink_pmx_func uart2_grp_mt76x8[] = { - FUNC("sdxc d5 d4", 3, 20, 2), - FUNC("pwm", 2, 20, 2), - FUNC("gpio", 1, 20, 2), - FUNC("uart2", 0, 20, 2), -}; - -static struct ralink_pmx_func uart1_grp_mt76x8[] = { - FUNC("sw_r", 3, 45, 2), - FUNC("pwm", 2, 45, 2), - FUNC("gpio", 1, 45, 2), - FUNC("uart1", 0, 45, 2), -}; - -static struct ralink_pmx_func i2c_grp_mt76x8[] = { - FUNC("-", 3, 4, 2), - FUNC("debug", 2, 4, 2), - FUNC("gpio", 1, 4, 2), - FUNC("i2c", 0, 4, 2), -}; - -static struct ralink_pmx_func refclk_grp_mt76x8[] = { FUNC("refclk", 0, 37, 1) }; -static struct ralink_pmx_func perst_grp_mt76x8[] = { FUNC("perst", 0, 36, 1) }; -static struct ralink_pmx_func wdt_grp_mt76x8[] = { FUNC("wdt", 0, 38, 1) }; -static struct ralink_pmx_func spi_grp_mt76x8[] = { FUNC("spi", 0, 7, 4) }; - -static struct ralink_pmx_func sd_mode_grp_mt76x8[] = { - FUNC("jtag", 3, 22, 8), - FUNC("utif", 2, 22, 8), - FUNC("gpio", 1, 22, 8), - FUNC("sdxc", 0, 22, 8), -}; - -static struct ralink_pmx_func uart0_grp_mt76x8[] = { - FUNC("-", 3, 12, 2), - FUNC("-", 2, 12, 2), - FUNC("gpio", 1, 12, 2), - FUNC("uart0", 0, 12, 2), -}; - -static struct ralink_pmx_func i2s_grp_mt76x8[] = { - FUNC("antenna", 3, 0, 4), - FUNC("pcm", 2, 0, 4), - FUNC("gpio", 1, 0, 4), - FUNC("i2s", 0, 0, 4), -}; - -static struct ralink_pmx_func spi_cs1_grp_mt76x8[] = { - FUNC("-", 3, 6, 1), - FUNC("refclk", 2, 6, 1), - FUNC("gpio", 1, 6, 1), - FUNC("spi cs1", 0, 6, 1), -}; - -static struct ralink_pmx_func spis_grp_mt76x8[] = { - FUNC("pwm_uart2", 3, 14, 4), - FUNC("utif", 2, 14, 4), - FUNC("gpio", 1, 14, 4), - FUNC("spis", 0, 14, 4), -}; - -static struct ralink_pmx_func gpio_grp_mt76x8[] = { - FUNC("pcie", 3, 11, 1), - FUNC("refclk", 2, 11, 1), - FUNC("gpio", 1, 11, 1), - FUNC("gpio", 0, 11, 1), -}; - -static struct ralink_pmx_func p4led_kn_grp_mt76x8[] = { - FUNC("jtag", 3, 30, 1), - FUNC("utif", 2, 30, 1), - FUNC("gpio", 1, 30, 1), - FUNC("p4led_kn", 0, 30, 1), -}; - -static struct ralink_pmx_func p3led_kn_grp_mt76x8[] = { - FUNC("jtag", 3, 31, 1), - FUNC("utif", 2, 31, 1), - FUNC("gpio", 1, 31, 1), - FUNC("p3led_kn", 0, 31, 1), -}; - -static struct ralink_pmx_func p2led_kn_grp_mt76x8[] = { - FUNC("jtag", 3, 32, 1), - FUNC("utif", 2, 32, 1), - FUNC("gpio", 1, 32, 1), - FUNC("p2led_kn", 0, 32, 1), -}; - -static struct ralink_pmx_func p1led_kn_grp_mt76x8[] = { - FUNC("jtag", 3, 33, 1), - FUNC("utif", 2, 33, 1), - FUNC("gpio", 1, 33, 1), - FUNC("p1led_kn", 0, 33, 1), -}; - -static struct ralink_pmx_func p0led_kn_grp_mt76x8[] = { - FUNC("jtag", 3, 34, 1), - FUNC("rsvd", 2, 34, 1), - FUNC("gpio", 1, 34, 1), - FUNC("p0led_kn", 0, 34, 1), -}; - -static struct ralink_pmx_func wled_kn_grp_mt76x8[] = { - FUNC("rsvd", 3, 35, 1), - FUNC("rsvd", 2, 35, 1), - FUNC("gpio", 1, 35, 1), - FUNC("wled_kn", 0, 35, 1), -}; - -static struct ralink_pmx_func p4led_an_grp_mt76x8[] = { - FUNC("jtag", 3, 39, 1), - FUNC("utif", 2, 39, 1), - FUNC("gpio", 1, 39, 1), - FUNC("p4led_an", 0, 39, 1), -}; - -static struct ralink_pmx_func p3led_an_grp_mt76x8[] = { - FUNC("jtag", 3, 40, 1), - FUNC("utif", 2, 40, 1), - FUNC("gpio", 1, 40, 1), - FUNC("p3led_an", 0, 40, 1), -}; - -static struct ralink_pmx_func p2led_an_grp_mt76x8[] = { - FUNC("jtag", 3, 41, 1), - FUNC("utif", 2, 41, 1), - FUNC("gpio", 1, 41, 1), - FUNC("p2led_an", 0, 41, 1), -}; - -static struct ralink_pmx_func p1led_an_grp_mt76x8[] = { - FUNC("jtag", 3, 42, 1), - FUNC("utif", 2, 42, 1), - FUNC("gpio", 1, 42, 1), - FUNC("p1led_an", 0, 42, 1), -}; - -static struct ralink_pmx_func p0led_an_grp_mt76x8[] = { - FUNC("jtag", 3, 43, 1), - FUNC("rsvd", 2, 43, 1), - FUNC("gpio", 1, 43, 1), - FUNC("p0led_an", 0, 43, 1), -}; - -static struct ralink_pmx_func wled_an_grp_mt76x8[] = { - FUNC("rsvd", 3, 44, 1), - FUNC("rsvd", 2, 44, 1), - FUNC("gpio", 1, 44, 1), - FUNC("wled_an", 0, 44, 1), -}; - -#define MT76X8_GPIO_MODE_MASK 0x3 - -#define MT76X8_GPIO_MODE_P4LED_KN 58 -#define MT76X8_GPIO_MODE_P3LED_KN 56 -#define MT76X8_GPIO_MODE_P2LED_KN 54 -#define MT76X8_GPIO_MODE_P1LED_KN 52 -#define MT76X8_GPIO_MODE_P0LED_KN 50 -#define MT76X8_GPIO_MODE_WLED_KN 48 -#define MT76X8_GPIO_MODE_P4LED_AN 42 -#define MT76X8_GPIO_MODE_P3LED_AN 40 -#define MT76X8_GPIO_MODE_P2LED_AN 38 -#define MT76X8_GPIO_MODE_P1LED_AN 36 -#define MT76X8_GPIO_MODE_P0LED_AN 34 -#define MT76X8_GPIO_MODE_WLED_AN 32 -#define MT76X8_GPIO_MODE_PWM1 30 -#define MT76X8_GPIO_MODE_PWM0 28 -#define MT76X8_GPIO_MODE_UART2 26 -#define MT76X8_GPIO_MODE_UART1 24 -#define MT76X8_GPIO_MODE_I2C 20 -#define MT76X8_GPIO_MODE_REFCLK 18 -#define MT76X8_GPIO_MODE_PERST 16 -#define MT76X8_GPIO_MODE_WDT 14 -#define MT76X8_GPIO_MODE_SPI 12 -#define MT76X8_GPIO_MODE_SDMODE 10 -#define MT76X8_GPIO_MODE_UART0 8 -#define MT76X8_GPIO_MODE_I2S 6 -#define MT76X8_GPIO_MODE_CS1 4 -#define MT76X8_GPIO_MODE_SPIS 2 -#define MT76X8_GPIO_MODE_GPIO 0 - -static struct ralink_pmx_group mt76x8_pinmux_data[] = { - GRP_G("pwm1", pwm1_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_PWM1), - GRP_G("pwm0", pwm0_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_PWM0), - GRP_G("uart2", uart2_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_UART2), - GRP_G("uart1", uart1_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_UART1), - GRP_G("i2c", i2c_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_I2C), - GRP("refclk", refclk_grp_mt76x8, 1, MT76X8_GPIO_MODE_REFCLK), - GRP("perst", perst_grp_mt76x8, 1, MT76X8_GPIO_MODE_PERST), - GRP("wdt", wdt_grp_mt76x8, 1, MT76X8_GPIO_MODE_WDT), - GRP("spi", spi_grp_mt76x8, 1, MT76X8_GPIO_MODE_SPI), - GRP_G("sdmode", sd_mode_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_SDMODE), - GRP_G("uart0", uart0_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_UART0), - GRP_G("i2s", i2s_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_I2S), - GRP_G("spi cs1", spi_cs1_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_CS1), - GRP_G("spis", spis_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_SPIS), - GRP_G("gpio", gpio_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_GPIO), - GRP_G("wled_an", wled_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_WLED_AN), - GRP_G("p0led_an", p0led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P0LED_AN), - GRP_G("p1led_an", p1led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P1LED_AN), - GRP_G("p2led_an", p2led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P2LED_AN), - GRP_G("p3led_an", p3led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P3LED_AN), - GRP_G("p4led_an", p4led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P4LED_AN), - GRP_G("wled_kn", wled_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_WLED_KN), - GRP_G("p0led_kn", p0led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P0LED_KN), - GRP_G("p1led_kn", p1led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P1LED_KN), - GRP_G("p2led_kn", p2led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P2LED_KN), - GRP_G("p3led_kn", p3led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P3LED_KN), - GRP_G("p4led_kn", p4led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P4LED_KN), - { 0 } -}; - static int mt7620_pinctrl_probe(struct platform_device *pdev) { - if (is_mt76x8()) - return ralink_pinctrl_init(pdev, mt76x8_pinmux_data); - else - return ralink_pinctrl_init(pdev, mt7620a_pinmux_data); + return ralink_pinctrl_init(pdev, mt7620a_pinmux_data); } static const struct of_device_id mt7620_pinctrl_match[] = { diff --git a/drivers/pinctrl/ralink/pinctrl-mt76x8.c b/drivers/pinctrl/ralink/pinctrl-mt76x8.c new file mode 100644 index 000000000000..4283a54d2db0 --- /dev/null +++ b/drivers/pinctrl/ralink/pinctrl-mt76x8.c @@ -0,0 +1,283 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include "pinctrl-ralink.h" + +#define MT76X8_GPIO_MODE_MASK 0x3 + +#define MT76X8_GPIO_MODE_P4LED_KN 58 +#define MT76X8_GPIO_MODE_P3LED_KN 56 +#define MT76X8_GPIO_MODE_P2LED_KN 54 +#define MT76X8_GPIO_MODE_P1LED_KN 52 +#define MT76X8_GPIO_MODE_P0LED_KN 50 +#define MT76X8_GPIO_MODE_WLED_KN 48 +#define MT76X8_GPIO_MODE_P4LED_AN 42 +#define MT76X8_GPIO_MODE_P3LED_AN 40 +#define MT76X8_GPIO_MODE_P2LED_AN 38 +#define MT76X8_GPIO_MODE_P1LED_AN 36 +#define MT76X8_GPIO_MODE_P0LED_AN 34 +#define MT76X8_GPIO_MODE_WLED_AN 32 +#define MT76X8_GPIO_MODE_PWM1 30 +#define MT76X8_GPIO_MODE_PWM0 28 +#define MT76X8_GPIO_MODE_UART2 26 +#define MT76X8_GPIO_MODE_UART1 24 +#define MT76X8_GPIO_MODE_I2C 20 +#define MT76X8_GPIO_MODE_REFCLK 18 +#define MT76X8_GPIO_MODE_PERST 16 +#define MT76X8_GPIO_MODE_WDT 14 +#define MT76X8_GPIO_MODE_SPI 12 +#define MT76X8_GPIO_MODE_SDMODE 10 +#define MT76X8_GPIO_MODE_UART0 8 +#define MT76X8_GPIO_MODE_I2S 6 +#define MT76X8_GPIO_MODE_CS1 4 +#define MT76X8_GPIO_MODE_SPIS 2 +#define MT76X8_GPIO_MODE_GPIO 0 + +static struct ralink_pmx_func pwm1_grp[] = { + FUNC("sdxc d6", 3, 19, 1), + FUNC("utif", 2, 19, 1), + FUNC("gpio", 1, 19, 1), + FUNC("pwm1", 0, 19, 1), +}; + +static struct ralink_pmx_func pwm0_grp[] = { + FUNC("sdxc d7", 3, 18, 1), + FUNC("utif", 2, 18, 1), + FUNC("gpio", 1, 18, 1), + FUNC("pwm0", 0, 18, 1), +}; + +static struct ralink_pmx_func uart2_grp[] = { + FUNC("sdxc d5 d4", 3, 20, 2), + FUNC("pwm", 2, 20, 2), + FUNC("gpio", 1, 20, 2), + FUNC("uart2", 0, 20, 2), +}; + +static struct ralink_pmx_func uart1_grp[] = { + FUNC("sw_r", 3, 45, 2), + FUNC("pwm", 2, 45, 2), + FUNC("gpio", 1, 45, 2), + FUNC("uart1", 0, 45, 2), +}; + +static struct ralink_pmx_func i2c_grp[] = { + FUNC("-", 3, 4, 2), + FUNC("debug", 2, 4, 2), + FUNC("gpio", 1, 4, 2), + FUNC("i2c", 0, 4, 2), +}; + +static struct ralink_pmx_func refclk_grp[] = { FUNC("refclk", 0, 37, 1) }; +static struct ralink_pmx_func perst_grp[] = { FUNC("perst", 0, 36, 1) }; +static struct ralink_pmx_func wdt_grp[] = { FUNC("wdt", 0, 38, 1) }; +static struct ralink_pmx_func spi_grp[] = { FUNC("spi", 0, 7, 4) }; + +static struct ralink_pmx_func sd_mode_grp[] = { + FUNC("jtag", 3, 22, 8), + FUNC("utif", 2, 22, 8), + FUNC("gpio", 1, 22, 8), + FUNC("sdxc", 0, 22, 8), +}; + +static struct ralink_pmx_func uart0_grp[] = { + FUNC("-", 3, 12, 2), + FUNC("-", 2, 12, 2), + FUNC("gpio", 1, 12, 2), + FUNC("uart0", 0, 12, 2), +}; + +static struct ralink_pmx_func i2s_grp[] = { + FUNC("antenna", 3, 0, 4), + FUNC("pcm", 2, 0, 4), + FUNC("gpio", 1, 0, 4), + FUNC("i2s", 0, 0, 4), +}; + +static struct ralink_pmx_func spi_cs1_grp[] = { + FUNC("-", 3, 6, 1), + FUNC("refclk", 2, 6, 1), + FUNC("gpio", 1, 6, 1), + FUNC("spi cs1", 0, 6, 1), +}; + +static struct ralink_pmx_func spis_grp[] = { + FUNC("pwm_uart2", 3, 14, 4), + FUNC("utif", 2, 14, 4), + FUNC("gpio", 1, 14, 4), + FUNC("spis", 0, 14, 4), +}; + +static struct ralink_pmx_func gpio_grp[] = { + FUNC("pcie", 3, 11, 1), + FUNC("refclk", 2, 11, 1), + FUNC("gpio", 1, 11, 1), + FUNC("gpio", 0, 11, 1), +}; + +static struct ralink_pmx_func p4led_kn_grp[] = { + FUNC("jtag", 3, 30, 1), + FUNC("utif", 2, 30, 1), + FUNC("gpio", 1, 30, 1), + FUNC("p4led_kn", 0, 30, 1), +}; + +static struct ralink_pmx_func p3led_kn_grp[] = { + FUNC("jtag", 3, 31, 1), + FUNC("utif", 2, 31, 1), + FUNC("gpio", 1, 31, 1), + FUNC("p3led_kn", 0, 31, 1), +}; + +static struct ralink_pmx_func p2led_kn_grp[] = { + FUNC("jtag", 3, 32, 1), + FUNC("utif", 2, 32, 1), + FUNC("gpio", 1, 32, 1), + FUNC("p2led_kn", 0, 32, 1), +}; + +static struct ralink_pmx_func p1led_kn_grp[] = { + FUNC("jtag", 3, 33, 1), + FUNC("utif", 2, 33, 1), + FUNC("gpio", 1, 33, 1), + FUNC("p1led_kn", 0, 33, 1), +}; + +static struct ralink_pmx_func p0led_kn_grp[] = { + FUNC("jtag", 3, 34, 1), + FUNC("rsvd", 2, 34, 1), + FUNC("gpio", 1, 34, 1), + FUNC("p0led_kn", 0, 34, 1), +}; + +static struct ralink_pmx_func wled_kn_grp[] = { + FUNC("rsvd", 3, 35, 1), + FUNC("rsvd", 2, 35, 1), + FUNC("gpio", 1, 35, 1), + FUNC("wled_kn", 0, 35, 1), +}; + +static struct ralink_pmx_func p4led_an_grp[] = { + FUNC("jtag", 3, 39, 1), + FUNC("utif", 2, 39, 1), + FUNC("gpio", 1, 39, 1), + FUNC("p4led_an", 0, 39, 1), +}; + +static struct ralink_pmx_func p3led_an_grp[] = { + FUNC("jtag", 3, 40, 1), + FUNC("utif", 2, 40, 1), + FUNC("gpio", 1, 40, 1), + FUNC("p3led_an", 0, 40, 1), +}; + +static struct ralink_pmx_func p2led_an_grp[] = { + FUNC("jtag", 3, 41, 1), + FUNC("utif", 2, 41, 1), + FUNC("gpio", 1, 41, 1), + FUNC("p2led_an", 0, 41, 1), +}; + +static struct ralink_pmx_func p1led_an_grp[] = { + FUNC("jtag", 3, 42, 1), + FUNC("utif", 2, 42, 1), + FUNC("gpio", 1, 42, 1), + FUNC("p1led_an", 0, 42, 1), +}; + +static struct ralink_pmx_func p0led_an_grp[] = { + FUNC("jtag", 3, 43, 1), + FUNC("rsvd", 2, 43, 1), + FUNC("gpio", 1, 43, 1), + FUNC("p0led_an", 0, 43, 1), +}; + +static struct ralink_pmx_func wled_an_grp[] = { + FUNC("rsvd", 3, 44, 1), + FUNC("rsvd", 2, 44, 1), + FUNC("gpio", 1, 44, 1), + FUNC("wled_an", 0, 44, 1), +}; + +static struct ralink_pmx_group mt76x8_pinmux_data[] = { + GRP_G("pwm1", pwm1_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_PWM1), + GRP_G("pwm0", pwm0_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_PWM0), + GRP_G("uart2", uart2_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_UART2), + GRP_G("uart1", uart1_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_UART1), + GRP_G("i2c", i2c_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_I2C), + GRP("refclk", refclk_grp, 1, MT76X8_GPIO_MODE_REFCLK), + GRP("perst", perst_grp, 1, MT76X8_GPIO_MODE_PERST), + GRP("wdt", wdt_grp, 1, MT76X8_GPIO_MODE_WDT), + GRP("spi", spi_grp, 1, MT76X8_GPIO_MODE_SPI), + GRP_G("sdmode", sd_mode_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_SDMODE), + GRP_G("uart0", uart0_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_UART0), + GRP_G("i2s", i2s_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_I2S), + GRP_G("spi cs1", spi_cs1_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_CS1), + GRP_G("spis", spis_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_SPIS), + GRP_G("gpio", gpio_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_GPIO), + GRP_G("wled_an", wled_an_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_WLED_AN), + GRP_G("p0led_an", p0led_an_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P0LED_AN), + GRP_G("p1led_an", p1led_an_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P1LED_AN), + GRP_G("p2led_an", p2led_an_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P2LED_AN), + GRP_G("p3led_an", p3led_an_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P3LED_AN), + GRP_G("p4led_an", p4led_an_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P4LED_AN), + GRP_G("wled_kn", wled_kn_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_WLED_KN), + GRP_G("p0led_kn", p0led_kn_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P0LED_KN), + GRP_G("p1led_kn", p1led_kn_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P1LED_KN), + GRP_G("p2led_kn", p2led_kn_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P2LED_KN), + GRP_G("p3led_kn", p3led_kn_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P3LED_KN), + GRP_G("p4led_kn", p4led_kn_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P4LED_KN), + { 0 } +}; + +static int mt76x8_pinctrl_probe(struct platform_device *pdev) +{ + return ralink_pinctrl_init(pdev, mt76x8_pinmux_data); +} + +static const struct of_device_id mt76x8_pinctrl_match[] = { + { .compatible = "ralink,mt76x8-pinctrl" }, + { .compatible = "ralink,mt7620-pinctrl" }, + { .compatible = "ralink,rt2880-pinmux" }, + {} +}; +MODULE_DEVICE_TABLE(of, mt76x8_pinctrl_match); + +static struct platform_driver mt76x8_pinctrl_driver = { + .probe = mt76x8_pinctrl_probe, + .driver = { + .name = "mt76x8-pinctrl", + .of_match_table = mt76x8_pinctrl_match, + }, +}; + +static int __init mt76x8_pinctrl_init(void) +{ + return platform_driver_register(&mt76x8_pinctrl_driver); +} +core_initcall_sync(mt76x8_pinctrl_init); From patchwork Fri Mar 17 21:29:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 664649 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32A31C6FD1D for ; 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Fri, 17 Mar 2023 14:30:26 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?utf-8?q?Bernhard_Rosenkr=C3=A4nze?= =?utf-8?q?r?= , Sergio Paracuellos , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 04/21] pinctrl: ralink: move to mediatek as mtmips Date: Sat, 18 Mar 2023 00:29:54 +0300 Message-Id: <20230317213011.13656-5-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Arınç ÜNAL This platform from Ralink was acquired by MediaTek in 2011. Then, MediaTek introduced new SoCs which utilise this platform. Move the driver to mediatek pinctrl directory. Rename the ralink core driver to mtmips. Signed-off-by: Arınç ÜNAL --- drivers/pinctrl/Kconfig | 1 - drivers/pinctrl/Makefile | 1 - drivers/pinctrl/mediatek/Kconfig | 51 ++++++++++- drivers/pinctrl/mediatek/Makefile | 63 +++++++------ .../{ralink => mediatek}/pinctrl-mt7620.c | 34 +++---- .../{ralink => mediatek}/pinctrl-mt7621.c | 30 +++---- .../{ralink => mediatek}/pinctrl-mt76x8.c | 60 ++++++------- .../pinctrl-mtmips.c} | 90 +++++++++---------- .../pinctrl-mtmips.h} | 16 ++-- .../{ralink => mediatek}/pinctrl-rt2880.c | 20 ++--- .../{ralink => mediatek}/pinctrl-rt305x.c | 44 ++++----- .../{ralink => mediatek}/pinctrl-rt3883.c | 28 +++--- drivers/pinctrl/ralink/Kconfig | 40 --------- drivers/pinctrl/ralink/Makefile | 9 -- 14 files changed, 246 insertions(+), 241 deletions(-) rename drivers/pinctrl/{ralink => mediatek}/pinctrl-mt7620.c (81%) rename drivers/pinctrl/{ralink => mediatek}/pinctrl-mt7621.c (80%) rename drivers/pinctrl/{ralink => mediatek}/pinctrl-mt76x8.c (81%) rename drivers/pinctrl/{ralink/pinctrl-ralink.c => mediatek/pinctrl-mtmips.c} (74%) rename drivers/pinctrl/{ralink/pinctrl-ralink.h => mediatek/pinctrl-mtmips.h} (75%) rename drivers/pinctrl/{ralink => mediatek}/pinctrl-rt2880.c (71%) rename drivers/pinctrl/{ralink => mediatek}/pinctrl-rt305x.c (75%) rename drivers/pinctrl/{ralink => mediatek}/pinctrl-rt3883.c (80%) delete mode 100644 drivers/pinctrl/ralink/Kconfig delete mode 100644 drivers/pinctrl/ralink/Makefile diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 694f47fe6d11..e2a24d668e41 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -538,7 +538,6 @@ source "drivers/pinctrl/nuvoton/Kconfig" source "drivers/pinctrl/nxp/Kconfig" source "drivers/pinctrl/pxa/Kconfig" source "drivers/pinctrl/qcom/Kconfig" -source "drivers/pinctrl/ralink/Kconfig" source "drivers/pinctrl/renesas/Kconfig" source "drivers/pinctrl/samsung/Kconfig" source "drivers/pinctrl/spear/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index c40397af024b..413b1e6b6933 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -67,7 +67,6 @@ obj-y += nuvoton/ obj-y += nxp/ obj-$(CONFIG_PINCTRL_PXA) += pxa/ obj-$(CONFIG_ARCH_QCOM) += qcom/ -obj-$(CONFIG_PINCTRL_RALINK) += ralink/ obj-$(CONFIG_PINCTRL_RENESAS) += renesas/ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ obj-$(CONFIG_PINCTRL_SPEAR) += spear/ diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index f20c28334bcb..ba21a599953c 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only menu "MediaTek pinctrl drivers" - depends on ARCH_MEDIATEK || COMPILE_TEST + depends on ARCH_MEDIATEK || RALINK || COMPILE_TEST config EINT_MTK tristate "MediaTek External Interrupt Support" @@ -22,6 +22,12 @@ config PINCTRL_MTK config PINCTRL_MTK_V2 tristate +config PINCTRL_MTK_MTMIPS + bool + depends on RALINK + select PINMUX + select GENERIC_PINCONF + config PINCTRL_MTK_MOORE bool depends on OF @@ -43,6 +49,49 @@ config PINCTRL_MTK_PARIS select OF_GPIO select PINCTRL_MTK_V2 +# For MIPS SoCs +config PINCTRL_MT7620 + bool "MediaTek MT7620 pin control" + depends on SOC_MT7620 || COMPILE_TEST + depends on RALINK + default SOC_MT7620 + select PINCTRL_MTK_MTMIPS + +config PINCTRL_MT7621 + bool "MediaTek MT7621 pin control" + depends on SOC_MT7621 || COMPILE_TEST + depends on RALINK + default SOC_MT7621 + select PINCTRL_MTK_MTMIPS + +config PINCTRL_MT76X8 + bool "MediaTek MT76X8 pin control" + depends on SOC_MT7620 || COMPILE_TEST + depends on RALINK + default SOC_MT7620 + select PINCTRL_MTK_MTMIPS + +config PINCTRL_RT2880 + bool "Ralink RT2880 pin control" + depends on SOC_RT288X || COMPILE_TEST + depends on RALINK + default SOC_RT288X + select PINCTRL_MTK_MTMIPS + +config PINCTRL_RT305X + bool "Ralink RT305X pin control" + depends on SOC_RT305X || COMPILE_TEST + depends on RALINK + default SOC_RT305X + select PINCTRL_MTK_MTMIPS + +config PINCTRL_RT3883 + bool "Ralink RT3883 pin control" + depends on SOC_RT3883 || COMPILE_TEST + depends on RALINK + default SOC_RT3883 + select PINCTRL_MTK_MTMIPS + # For ARMv7 SoCs config PINCTRL_MT2701 bool "Mediatek MT2701 pin control" diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index 44d197af516a..680f7e8526e0 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -1,32 +1,39 @@ # SPDX-License-Identifier: GPL-2.0 # Core -obj-$(CONFIG_EINT_MTK) += mtk-eint.o -obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o -obj-$(CONFIG_PINCTRL_MTK_V2) += pinctrl-mtk-common-v2.o -obj-$(CONFIG_PINCTRL_MTK_MOORE) += pinctrl-moore.o -obj-$(CONFIG_PINCTRL_MTK_PARIS) += pinctrl-paris.o +obj-$(CONFIG_EINT_MTK) += mtk-eint.o +obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o +obj-$(CONFIG_PINCTRL_MTK_V2) += pinctrl-mtk-common-v2.o +obj-$(CONFIG_PINCTRL_MTK_MTMIPS) += pinctrl-mtmips.o +obj-$(CONFIG_PINCTRL_MTK_MOORE) += pinctrl-moore.o +obj-$(CONFIG_PINCTRL_MTK_PARIS) += pinctrl-paris.o # SoC Drivers -obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o -obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o -obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o -obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o -obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o -obj-$(CONFIG_PINCTRL_MT6779) += pinctrl-mt6779.o -obj-$(CONFIG_PINCTRL_MT6795) += pinctrl-mt6795.o -obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o -obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o -obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o -obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o -obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o -obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o -obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o -obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o -obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o -obj-$(CONFIG_PINCTRL_MT8186) += pinctrl-mt8186.o -obj-$(CONFIG_PINCTRL_MT8188) += pinctrl-mt8188.o -obj-$(CONFIG_PINCTRL_MT8192) += pinctrl-mt8192.o -obj-$(CONFIG_PINCTRL_MT8195) += pinctrl-mt8195.o -obj-$(CONFIG_PINCTRL_MT8365) += pinctrl-mt8365.o -obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o -obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o +obj-$(CONFIG_PINCTRL_MT7620) += pinctrl-mt7620.o +obj-$(CONFIG_PINCTRL_MT7621) += pinctrl-mt7621.o +obj-$(CONFIG_PINCTRL_MT76X8) += pinctrl-mt76x8.o +obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o +obj-$(CONFIG_PINCTRL_RT305X) += pinctrl-rt305x.o +obj-$(CONFIG_PINCTRL_RT3883) += pinctrl-rt3883.o +obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o +obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o +obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o +obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o +obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o +obj-$(CONFIG_PINCTRL_MT6779) += pinctrl-mt6779.o +obj-$(CONFIG_PINCTRL_MT6795) += pinctrl-mt6795.o +obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o +obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o +obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o +obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o +obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o +obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o +obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o +obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o +obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o +obj-$(CONFIG_PINCTRL_MT8186) += pinctrl-mt8186.o +obj-$(CONFIG_PINCTRL_MT8188) += pinctrl-mt8188.o +obj-$(CONFIG_PINCTRL_MT8192) += pinctrl-mt8192.o +obj-$(CONFIG_PINCTRL_MT8195) += pinctrl-mt8195.o +obj-$(CONFIG_PINCTRL_MT8365) += pinctrl-mt8365.o +obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o +obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o diff --git a/drivers/pinctrl/ralink/pinctrl-mt7620.c b/drivers/pinctrl/mediatek/pinctrl-mt7620.c similarity index 81% rename from drivers/pinctrl/ralink/pinctrl-mt7620.c rename to drivers/pinctrl/mediatek/pinctrl-mt7620.c index 3f6ffccc6882..d2624b9b5bc4 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7620.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7620.c @@ -3,7 +3,7 @@ #include #include #include -#include "pinctrl-ralink.h" +#include "pinctrl-mtmips.h" #define MT7620_GPIO_MODE_UART0_SHIFT 2 #define MT7620_GPIO_MODE_UART0_MASK 0x7 @@ -52,20 +52,20 @@ #define MT7620_GPIO_MODE_EPHY 15 #define MT7620_GPIO_MODE_PA 20 -static struct ralink_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; -static struct ralink_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; -static struct ralink_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) }; -static struct ralink_pmx_func mdio_grp[] = { +static struct mtmips_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; +static struct mtmips_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; +static struct mtmips_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) }; +static struct mtmips_pmx_func mdio_grp[] = { FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2), FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2), }; -static struct ralink_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) }; -static struct ralink_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) }; -static struct ralink_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) }; -static struct ralink_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) }; -static struct ralink_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) }; -static struct ralink_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) }; -static struct ralink_pmx_func uartf_grp[] = { +static struct mtmips_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) }; +static struct mtmips_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) }; +static struct mtmips_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) }; +static struct mtmips_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) }; +static struct mtmips_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) }; +static struct mtmips_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) }; +static struct mtmips_pmx_func uartf_grp[] = { FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8), FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8), FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8), @@ -74,20 +74,20 @@ static struct ralink_pmx_func uartf_grp[] = { FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4), FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4), }; -static struct ralink_pmx_func wdt_grp[] = { +static struct mtmips_pmx_func wdt_grp[] = { FUNC("wdt rst", 0, 17, 1), FUNC("wdt refclk", 0, 17, 1), }; -static struct ralink_pmx_func pcie_rst_grp[] = { +static struct mtmips_pmx_func pcie_rst_grp[] = { FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1), FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1) }; -static struct ralink_pmx_func nd_sd_grp[] = { +static struct mtmips_pmx_func nd_sd_grp[] = { FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15), FUNC("sd", MT7620_GPIO_MODE_SD, 47, 13) }; -static struct ralink_pmx_group mt7620a_pinmux_data[] = { +static struct mtmips_pmx_group mt7620a_pinmux_data[] = { GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C), GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK, MT7620_GPIO_MODE_UART0_SHIFT), @@ -112,7 +112,7 @@ static struct ralink_pmx_group mt7620a_pinmux_data[] = { static int mt7620_pinctrl_probe(struct platform_device *pdev) { - return ralink_pinctrl_init(pdev, mt7620a_pinmux_data); + return mtmips_pinctrl_init(pdev, mt7620a_pinmux_data); } static const struct of_device_id mt7620_pinctrl_match[] = { diff --git a/drivers/pinctrl/ralink/pinctrl-mt7621.c b/drivers/pinctrl/mediatek/pinctrl-mt7621.c similarity index 80% rename from drivers/pinctrl/ralink/pinctrl-mt7621.c rename to drivers/pinctrl/mediatek/pinctrl-mt7621.c index fb5824922e78..b18c1a47bbeb 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7621.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7621.c @@ -3,7 +3,7 @@ #include #include #include -#include "pinctrl-ralink.h" +#include "pinctrl-mtmips.h" #define MT7621_GPIO_MODE_UART1 1 #define MT7621_GPIO_MODE_I2C 2 @@ -34,40 +34,40 @@ #define MT7621_GPIO_MODE_SDHCI_SHIFT 18 #define MT7621_GPIO_MODE_SDHCI_GPIO 1 -static struct ralink_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) }; -static struct ralink_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) }; -static struct ralink_pmx_func uart3_grp[] = { +static struct mtmips_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) }; +static struct mtmips_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) }; +static struct mtmips_pmx_func uart3_grp[] = { FUNC("uart3", 0, 5, 4), FUNC("i2s", 2, 5, 4), FUNC("spdif3", 3, 5, 4), }; -static struct ralink_pmx_func uart2_grp[] = { +static struct mtmips_pmx_func uart2_grp[] = { FUNC("uart2", 0, 9, 4), FUNC("pcm", 2, 9, 4), FUNC("spdif2", 3, 9, 4), }; -static struct ralink_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) }; -static struct ralink_pmx_func wdt_grp[] = { +static struct mtmips_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) }; +static struct mtmips_pmx_func wdt_grp[] = { FUNC("wdt rst", 0, 18, 1), FUNC("wdt refclk", 2, 18, 1), }; -static struct ralink_pmx_func pcie_rst_grp[] = { +static struct mtmips_pmx_func pcie_rst_grp[] = { FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1), FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1) }; -static struct ralink_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) }; -static struct ralink_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) }; -static struct ralink_pmx_func spi_grp[] = { +static struct mtmips_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) }; +static struct mtmips_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) }; +static struct mtmips_pmx_func spi_grp[] = { FUNC("spi", 0, 34, 7), FUNC("nand1", 2, 34, 7), }; -static struct ralink_pmx_func sdhci_grp[] = { +static struct mtmips_pmx_func sdhci_grp[] = { FUNC("sdhci", 0, 41, 8), FUNC("nand2", 2, 41, 8), }; -static struct ralink_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) }; +static struct mtmips_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) }; -static struct ralink_pmx_group mt7621_pinmux_data[] = { +static struct mtmips_pmx_group mt7621_pinmux_data[] = { GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1), GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C), GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK, @@ -92,7 +92,7 @@ static struct ralink_pmx_group mt7621_pinmux_data[] = { static int mt7621_pinctrl_probe(struct platform_device *pdev) { - return ralink_pinctrl_init(pdev, mt7621_pinmux_data); + return mtmips_pinctrl_init(pdev, mt7621_pinmux_data); } static const struct of_device_id mt7621_pinctrl_match[] = { diff --git a/drivers/pinctrl/ralink/pinctrl-mt76x8.c b/drivers/pinctrl/mediatek/pinctrl-mt76x8.c similarity index 81% rename from drivers/pinctrl/ralink/pinctrl-mt76x8.c rename to drivers/pinctrl/mediatek/pinctrl-mt76x8.c index 4283a54d2db0..e7d6ad2f62e4 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt76x8.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt76x8.c @@ -3,7 +3,7 @@ #include #include #include -#include "pinctrl-ralink.h" +#include "pinctrl-mtmips.h" #define MT76X8_GPIO_MODE_MASK 0x3 @@ -35,173 +35,173 @@ #define MT76X8_GPIO_MODE_SPIS 2 #define MT76X8_GPIO_MODE_GPIO 0 -static struct ralink_pmx_func pwm1_grp[] = { +static struct mtmips_pmx_func pwm1_grp[] = { FUNC("sdxc d6", 3, 19, 1), FUNC("utif", 2, 19, 1), FUNC("gpio", 1, 19, 1), FUNC("pwm1", 0, 19, 1), }; -static struct ralink_pmx_func pwm0_grp[] = { +static struct mtmips_pmx_func pwm0_grp[] = { FUNC("sdxc d7", 3, 18, 1), FUNC("utif", 2, 18, 1), FUNC("gpio", 1, 18, 1), FUNC("pwm0", 0, 18, 1), }; -static struct ralink_pmx_func uart2_grp[] = { +static struct mtmips_pmx_func uart2_grp[] = { FUNC("sdxc d5 d4", 3, 20, 2), FUNC("pwm", 2, 20, 2), FUNC("gpio", 1, 20, 2), FUNC("uart2", 0, 20, 2), }; -static struct ralink_pmx_func uart1_grp[] = { +static struct mtmips_pmx_func uart1_grp[] = { FUNC("sw_r", 3, 45, 2), FUNC("pwm", 2, 45, 2), FUNC("gpio", 1, 45, 2), FUNC("uart1", 0, 45, 2), }; -static struct ralink_pmx_func i2c_grp[] = { +static struct mtmips_pmx_func i2c_grp[] = { FUNC("-", 3, 4, 2), FUNC("debug", 2, 4, 2), FUNC("gpio", 1, 4, 2), FUNC("i2c", 0, 4, 2), }; -static struct ralink_pmx_func refclk_grp[] = { FUNC("refclk", 0, 37, 1) }; -static struct ralink_pmx_func perst_grp[] = { FUNC("perst", 0, 36, 1) }; -static struct ralink_pmx_func wdt_grp[] = { FUNC("wdt", 0, 38, 1) }; -static struct ralink_pmx_func spi_grp[] = { FUNC("spi", 0, 7, 4) }; +static struct mtmips_pmx_func refclk_grp[] = { FUNC("refclk", 0, 37, 1) }; +static struct mtmips_pmx_func perst_grp[] = { FUNC("perst", 0, 36, 1) }; +static struct mtmips_pmx_func wdt_grp[] = { FUNC("wdt", 0, 38, 1) }; +static struct mtmips_pmx_func spi_grp[] = { FUNC("spi", 0, 7, 4) }; -static struct ralink_pmx_func sd_mode_grp[] = { +static struct mtmips_pmx_func sd_mode_grp[] = { FUNC("jtag", 3, 22, 8), FUNC("utif", 2, 22, 8), FUNC("gpio", 1, 22, 8), FUNC("sdxc", 0, 22, 8), }; -static struct ralink_pmx_func uart0_grp[] = { +static struct mtmips_pmx_func uart0_grp[] = { FUNC("-", 3, 12, 2), FUNC("-", 2, 12, 2), FUNC("gpio", 1, 12, 2), FUNC("uart0", 0, 12, 2), }; -static struct ralink_pmx_func i2s_grp[] = { +static struct mtmips_pmx_func i2s_grp[] = { FUNC("antenna", 3, 0, 4), FUNC("pcm", 2, 0, 4), FUNC("gpio", 1, 0, 4), FUNC("i2s", 0, 0, 4), }; -static struct ralink_pmx_func spi_cs1_grp[] = { +static struct mtmips_pmx_func spi_cs1_grp[] = { FUNC("-", 3, 6, 1), FUNC("refclk", 2, 6, 1), FUNC("gpio", 1, 6, 1), FUNC("spi cs1", 0, 6, 1), }; -static struct ralink_pmx_func spis_grp[] = { +static struct mtmips_pmx_func spis_grp[] = { FUNC("pwm_uart2", 3, 14, 4), FUNC("utif", 2, 14, 4), FUNC("gpio", 1, 14, 4), FUNC("spis", 0, 14, 4), }; -static struct ralink_pmx_func gpio_grp[] = { +static struct mtmips_pmx_func gpio_grp[] = { FUNC("pcie", 3, 11, 1), FUNC("refclk", 2, 11, 1), FUNC("gpio", 1, 11, 1), FUNC("gpio", 0, 11, 1), }; -static struct ralink_pmx_func p4led_kn_grp[] = { +static struct mtmips_pmx_func p4led_kn_grp[] = { FUNC("jtag", 3, 30, 1), FUNC("utif", 2, 30, 1), FUNC("gpio", 1, 30, 1), FUNC("p4led_kn", 0, 30, 1), }; -static struct ralink_pmx_func p3led_kn_grp[] = { +static struct mtmips_pmx_func p3led_kn_grp[] = { FUNC("jtag", 3, 31, 1), FUNC("utif", 2, 31, 1), FUNC("gpio", 1, 31, 1), FUNC("p3led_kn", 0, 31, 1), }; -static struct ralink_pmx_func p2led_kn_grp[] = { +static struct mtmips_pmx_func p2led_kn_grp[] = { FUNC("jtag", 3, 32, 1), FUNC("utif", 2, 32, 1), FUNC("gpio", 1, 32, 1), FUNC("p2led_kn", 0, 32, 1), }; -static struct ralink_pmx_func p1led_kn_grp[] = { +static struct mtmips_pmx_func p1led_kn_grp[] = { FUNC("jtag", 3, 33, 1), FUNC("utif", 2, 33, 1), FUNC("gpio", 1, 33, 1), FUNC("p1led_kn", 0, 33, 1), }; -static struct ralink_pmx_func p0led_kn_grp[] = { +static struct mtmips_pmx_func p0led_kn_grp[] = { FUNC("jtag", 3, 34, 1), FUNC("rsvd", 2, 34, 1), FUNC("gpio", 1, 34, 1), FUNC("p0led_kn", 0, 34, 1), }; -static struct ralink_pmx_func wled_kn_grp[] = { +static struct mtmips_pmx_func wled_kn_grp[] = { FUNC("rsvd", 3, 35, 1), FUNC("rsvd", 2, 35, 1), FUNC("gpio", 1, 35, 1), FUNC("wled_kn", 0, 35, 1), }; -static struct ralink_pmx_func p4led_an_grp[] = { +static struct mtmips_pmx_func p4led_an_grp[] = { FUNC("jtag", 3, 39, 1), FUNC("utif", 2, 39, 1), FUNC("gpio", 1, 39, 1), FUNC("p4led_an", 0, 39, 1), }; -static struct ralink_pmx_func p3led_an_grp[] = { +static struct mtmips_pmx_func p3led_an_grp[] = { FUNC("jtag", 3, 40, 1), FUNC("utif", 2, 40, 1), FUNC("gpio", 1, 40, 1), FUNC("p3led_an", 0, 40, 1), }; -static struct ralink_pmx_func p2led_an_grp[] = { +static struct mtmips_pmx_func p2led_an_grp[] = { FUNC("jtag", 3, 41, 1), FUNC("utif", 2, 41, 1), FUNC("gpio", 1, 41, 1), FUNC("p2led_an", 0, 41, 1), }; -static struct ralink_pmx_func p1led_an_grp[] = { +static struct mtmips_pmx_func p1led_an_grp[] = { FUNC("jtag", 3, 42, 1), FUNC("utif", 2, 42, 1), FUNC("gpio", 1, 42, 1), FUNC("p1led_an", 0, 42, 1), }; -static struct ralink_pmx_func p0led_an_grp[] = { +static struct mtmips_pmx_func p0led_an_grp[] = { FUNC("jtag", 3, 43, 1), FUNC("rsvd", 2, 43, 1), FUNC("gpio", 1, 43, 1), FUNC("p0led_an", 0, 43, 1), }; -static struct ralink_pmx_func wled_an_grp[] = { +static struct mtmips_pmx_func wled_an_grp[] = { FUNC("rsvd", 3, 44, 1), FUNC("rsvd", 2, 44, 1), FUNC("gpio", 1, 44, 1), FUNC("wled_an", 0, 44, 1), }; -static struct ralink_pmx_group mt76x8_pinmux_data[] = { +static struct mtmips_pmx_group mt76x8_pinmux_data[] = { GRP_G("pwm1", pwm1_grp, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_PWM1), GRP_G("pwm0", pwm0_grp, MT76X8_GPIO_MODE_MASK, @@ -257,7 +257,7 @@ static struct ralink_pmx_group mt76x8_pinmux_data[] = { static int mt76x8_pinctrl_probe(struct platform_device *pdev) { - return ralink_pinctrl_init(pdev, mt76x8_pinmux_data); + return mtmips_pinctrl_init(pdev, mt76x8_pinmux_data); } static const struct of_device_id mt76x8_pinctrl_match[] = { diff --git a/drivers/pinctrl/ralink/pinctrl-ralink.c b/drivers/pinctrl/mediatek/pinctrl-mtmips.c similarity index 74% rename from drivers/pinctrl/ralink/pinctrl-ralink.c rename to drivers/pinctrl/mediatek/pinctrl-mtmips.c index 770862f45b3f..efd77b6c56a1 100644 --- a/drivers/pinctrl/ralink/pinctrl-ralink.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtmips.c @@ -19,23 +19,23 @@ #include #include -#include "pinctrl-ralink.h" +#include "pinctrl-mtmips.h" #include "../core.h" #include "../pinctrl-utils.h" #define SYSC_REG_GPIO_MODE 0x60 #define SYSC_REG_GPIO_MODE2 0x64 -struct ralink_priv { +struct mtmips_priv { struct device *dev; struct pinctrl_pin_desc *pads; struct pinctrl_desc *desc; - struct ralink_pmx_func **func; + struct mtmips_pmx_func **func; int func_count; - struct ralink_pmx_group *groups; + struct mtmips_pmx_group *groups; const char **group_names; int group_count; @@ -43,27 +43,27 @@ struct ralink_priv { int max_pins; }; -static int ralink_get_group_count(struct pinctrl_dev *pctrldev) +static int mtmips_get_group_count(struct pinctrl_dev *pctrldev) { - struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p = pinctrl_dev_get_drvdata(pctrldev); return p->group_count; } -static const char *ralink_get_group_name(struct pinctrl_dev *pctrldev, +static const char *mtmips_get_group_name(struct pinctrl_dev *pctrldev, unsigned int group) { - struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p = pinctrl_dev_get_drvdata(pctrldev); return (group >= p->group_count) ? NULL : p->group_names[group]; } -static int ralink_get_group_pins(struct pinctrl_dev *pctrldev, +static int mtmips_get_group_pins(struct pinctrl_dev *pctrldev, unsigned int group, const unsigned int **pins, unsigned int *num_pins) { - struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p = pinctrl_dev_get_drvdata(pctrldev); if (group >= p->group_count) return -EINVAL; @@ -74,35 +74,35 @@ static int ralink_get_group_pins(struct pinctrl_dev *pctrldev, return 0; } -static const struct pinctrl_ops ralink_pctrl_ops = { - .get_groups_count = ralink_get_group_count, - .get_group_name = ralink_get_group_name, - .get_group_pins = ralink_get_group_pins, +static const struct pinctrl_ops mtmips_pctrl_ops = { + .get_groups_count = mtmips_get_group_count, + .get_group_name = mtmips_get_group_name, + .get_group_pins = mtmips_get_group_pins, .dt_node_to_map = pinconf_generic_dt_node_to_map_all, .dt_free_map = pinconf_generic_dt_free_map, }; -static int ralink_pmx_func_count(struct pinctrl_dev *pctrldev) +static int mtmips_pmx_func_count(struct pinctrl_dev *pctrldev) { - struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p = pinctrl_dev_get_drvdata(pctrldev); return p->func_count; } -static const char *ralink_pmx_func_name(struct pinctrl_dev *pctrldev, +static const char *mtmips_pmx_func_name(struct pinctrl_dev *pctrldev, unsigned int func) { - struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p = pinctrl_dev_get_drvdata(pctrldev); return p->func[func]->name; } -static int ralink_pmx_group_get_groups(struct pinctrl_dev *pctrldev, +static int mtmips_pmx_group_get_groups(struct pinctrl_dev *pctrldev, unsigned int func, const char * const **groups, unsigned int * const num_groups) { - struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p = pinctrl_dev_get_drvdata(pctrldev); if (p->func[func]->group_count == 1) *groups = &p->group_names[p->func[func]->groups[0]]; @@ -114,10 +114,10 @@ static int ralink_pmx_group_get_groups(struct pinctrl_dev *pctrldev, return 0; } -static int ralink_pmx_group_enable(struct pinctrl_dev *pctrldev, +static int mtmips_pmx_group_enable(struct pinctrl_dev *pctrldev, unsigned int func, unsigned int group) { - struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p = pinctrl_dev_get_drvdata(pctrldev); u32 mode = 0; u32 reg = SYSC_REG_GPIO_MODE; int i; @@ -158,11 +158,11 @@ static int ralink_pmx_group_enable(struct pinctrl_dev *pctrldev, return 0; } -static int ralink_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrldev, +static int mtmips_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrldev, struct pinctrl_gpio_range *range, unsigned int pin) { - struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p = pinctrl_dev_get_drvdata(pctrldev); if (!p->gpio[pin]) { dev_err(p->dev, "pin %d is not set to gpio mux\n", pin); @@ -172,28 +172,28 @@ static int ralink_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrldev, return 0; } -static const struct pinmux_ops ralink_pmx_group_ops = { - .get_functions_count = ralink_pmx_func_count, - .get_function_name = ralink_pmx_func_name, - .get_function_groups = ralink_pmx_group_get_groups, - .set_mux = ralink_pmx_group_enable, - .gpio_request_enable = ralink_pmx_group_gpio_request_enable, +static const struct pinmux_ops mtmips_pmx_group_ops = { + .get_functions_count = mtmips_pmx_func_count, + .get_function_name = mtmips_pmx_func_name, + .get_function_groups = mtmips_pmx_group_get_groups, + .set_mux = mtmips_pmx_group_enable, + .gpio_request_enable = mtmips_pmx_group_gpio_request_enable, }; -static struct pinctrl_desc ralink_pctrl_desc = { +static struct pinctrl_desc mtmips_pctrl_desc = { .owner = THIS_MODULE, - .name = "ralink-pinctrl", - .pctlops = &ralink_pctrl_ops, - .pmxops = &ralink_pmx_group_ops, + .name = "mtmips-pinctrl", + .pctlops = &mtmips_pctrl_ops, + .pmxops = &mtmips_pmx_group_ops, }; -static struct ralink_pmx_func gpio_func = { +static struct mtmips_pmx_func gpio_func = { .name = "gpio", }; -static int ralink_pinctrl_index(struct ralink_priv *p) +static int mtmips_pinctrl_index(struct mtmips_priv *p) { - struct ralink_pmx_group *mux = p->groups; + struct mtmips_pmx_group *mux = p->groups; int i, j, c = 0; /* count the mux functions */ @@ -248,7 +248,7 @@ static int ralink_pinctrl_index(struct ralink_priv *p) return 0; } -static int ralink_pinctrl_pins(struct ralink_priv *p) +static int mtmips_pinctrl_pins(struct mtmips_priv *p) { int i, j; @@ -313,10 +313,10 @@ static int ralink_pinctrl_pins(struct ralink_priv *p) return 0; } -int ralink_pinctrl_init(struct platform_device *pdev, - struct ralink_pmx_group *data) +int mtmips_pinctrl_init(struct platform_device *pdev, + struct mtmips_pmx_group *data) { - struct ralink_priv *p; + struct mtmips_priv *p; struct pinctrl_dev *dev; int err; @@ -324,23 +324,23 @@ int ralink_pinctrl_init(struct platform_device *pdev, return -ENOTSUPP; /* setup the private data */ - p = devm_kzalloc(&pdev->dev, sizeof(struct ralink_priv), GFP_KERNEL); + p = devm_kzalloc(&pdev->dev, sizeof(struct mtmips_priv), GFP_KERNEL); if (!p) return -ENOMEM; p->dev = &pdev->dev; - p->desc = &ralink_pctrl_desc; + p->desc = &mtmips_pctrl_desc; p->groups = data; platform_set_drvdata(pdev, p); /* init the device */ - err = ralink_pinctrl_index(p); + err = mtmips_pinctrl_index(p); if (err) { dev_err(&pdev->dev, "failed to load index\n"); return err; } - err = ralink_pinctrl_pins(p); + err = mtmips_pinctrl_pins(p); if (err) { dev_err(&pdev->dev, "failed to load pins\n"); return err; diff --git a/drivers/pinctrl/ralink/pinctrl-ralink.h b/drivers/pinctrl/mediatek/pinctrl-mtmips.h similarity index 75% rename from drivers/pinctrl/ralink/pinctrl-ralink.h rename to drivers/pinctrl/mediatek/pinctrl-mtmips.h index e6037be1e153..a7c3dd724431 100644 --- a/drivers/pinctrl/ralink/pinctrl-ralink.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtmips.h @@ -3,8 +3,8 @@ * Copyright (C) 2012 John Crispin */ -#ifndef _PINCTRL_RALINK_H__ -#define _PINCTRL_RALINK_H__ +#ifndef _PINCTRL_MTMIPS_H__ +#define _PINCTRL_MTMIPS_H__ #define FUNC(name, value, pin_first, pin_count) \ { name, value, pin_first, pin_count } @@ -19,9 +19,9 @@ .func = _func, .gpio = _gpio, \ .func_count = ARRAY_SIZE(_func) } -struct ralink_pmx_group; +struct mtmips_pmx_group; -struct ralink_pmx_func { +struct mtmips_pmx_func { const char *name; const char value; @@ -35,7 +35,7 @@ struct ralink_pmx_func { int enabled; }; -struct ralink_pmx_group { +struct mtmips_pmx_group { const char *name; int enabled; @@ -43,11 +43,11 @@ struct ralink_pmx_group { const char mask; const char gpio; - struct ralink_pmx_func *func; + struct mtmips_pmx_func *func; int func_count; }; -int ralink_pinctrl_init(struct platform_device *pdev, - struct ralink_pmx_group *data); +int mtmips_pinctrl_init(struct platform_device *pdev, + struct mtmips_pmx_group *data); #endif diff --git a/drivers/pinctrl/ralink/pinctrl-rt2880.c b/drivers/pinctrl/mediatek/pinctrl-rt2880.c similarity index 71% rename from drivers/pinctrl/ralink/pinctrl-rt2880.c rename to drivers/pinctrl/mediatek/pinctrl-rt2880.c index d7a65fcc7755..e0366721a515 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt2880.c +++ b/drivers/pinctrl/mediatek/pinctrl-rt2880.c @@ -4,7 +4,7 @@ #include #include #include -#include "pinctrl-ralink.h" +#include "pinctrl-mtmips.h" #define RT2880_GPIO_MODE_I2C BIT(0) #define RT2880_GPIO_MODE_UART0 BIT(1) @@ -15,15 +15,15 @@ #define RT2880_GPIO_MODE_SDRAM BIT(6) #define RT2880_GPIO_MODE_PCI BIT(7) -static struct ralink_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; -static struct ralink_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; -static struct ralink_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 7, 8) }; -static struct ralink_pmx_func jtag_grp[] = { FUNC("jtag", 0, 17, 5) }; -static struct ralink_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) }; -static struct ralink_pmx_func sdram_grp[] = { FUNC("sdram", 0, 24, 16) }; -static struct ralink_pmx_func pci_grp[] = { FUNC("pci", 0, 40, 32) }; +static struct mtmips_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; +static struct mtmips_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; +static struct mtmips_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 7, 8) }; +static struct mtmips_pmx_func jtag_grp[] = { FUNC("jtag", 0, 17, 5) }; +static struct mtmips_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) }; +static struct mtmips_pmx_func sdram_grp[] = { FUNC("sdram", 0, 24, 16) }; +static struct mtmips_pmx_func pci_grp[] = { FUNC("pci", 0, 40, 32) }; -static struct ralink_pmx_group rt2880_pinmux_data_act[] = { +static struct mtmips_pmx_group rt2880_pinmux_data_act[] = { GRP("i2c", i2c_grp, 1, RT2880_GPIO_MODE_I2C), GRP("spi", spi_grp, 1, RT2880_GPIO_MODE_SPI), GRP("uartlite", uartlite_grp, 1, RT2880_GPIO_MODE_UART0), @@ -36,7 +36,7 @@ static struct ralink_pmx_group rt2880_pinmux_data_act[] = { static int rt2880_pinctrl_probe(struct platform_device *pdev) { - return ralink_pinctrl_init(pdev, rt2880_pinmux_data_act); + return mtmips_pinctrl_init(pdev, rt2880_pinmux_data_act); } static const struct of_device_id rt2880_pinctrl_match[] = { diff --git a/drivers/pinctrl/ralink/pinctrl-rt305x.c b/drivers/pinctrl/mediatek/pinctrl-rt305x.c similarity index 75% rename from drivers/pinctrl/ralink/pinctrl-rt305x.c rename to drivers/pinctrl/mediatek/pinctrl-rt305x.c index fa3743c7680f..77bd4d1f6122 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt305x.c +++ b/drivers/pinctrl/mediatek/pinctrl-rt305x.c @@ -5,7 +5,7 @@ #include #include #include -#include "pinctrl-ralink.h" +#include "pinctrl-mtmips.h" #define RT305X_GPIO_MODE_UART0_SHIFT 2 #define RT305X_GPIO_MODE_UART0_MASK 0x7 @@ -31,9 +31,9 @@ #define RT3352_GPIO_MODE_LNA 18 #define RT3352_GPIO_MODE_PA 20 -static struct ralink_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; -static struct ralink_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; -static struct ralink_pmx_func uartf_grp[] = { +static struct mtmips_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; +static struct mtmips_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; +static struct mtmips_pmx_func uartf_grp[] = { FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8), FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8), FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8), @@ -42,28 +42,28 @@ static struct ralink_pmx_func uartf_grp[] = { FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4), FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4), }; -static struct ralink_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) }; -static struct ralink_pmx_func jtag_grp[] = { FUNC("jtag", 0, 17, 5) }; -static struct ralink_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) }; -static struct ralink_pmx_func rt5350_led_grp[] = { FUNC("led", 0, 22, 5) }; -static struct ralink_pmx_func rt5350_cs1_grp[] = { +static struct mtmips_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) }; +static struct mtmips_pmx_func jtag_grp[] = { FUNC("jtag", 0, 17, 5) }; +static struct mtmips_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) }; +static struct mtmips_pmx_func rt5350_led_grp[] = { FUNC("led", 0, 22, 5) }; +static struct mtmips_pmx_func rt5350_cs1_grp[] = { FUNC("spi_cs1", 0, 27, 1), FUNC("wdg_cs1", 1, 27, 1), }; -static struct ralink_pmx_func sdram_grp[] = { FUNC("sdram", 0, 24, 16) }; -static struct ralink_pmx_func rt3352_rgmii_grp[] = { +static struct mtmips_pmx_func sdram_grp[] = { FUNC("sdram", 0, 24, 16) }; +static struct mtmips_pmx_func rt3352_rgmii_grp[] = { FUNC("rgmii", 0, 24, 12) }; -static struct ralink_pmx_func rgmii_grp[] = { FUNC("rgmii", 0, 40, 12) }; -static struct ralink_pmx_func rt3352_lna_grp[] = { FUNC("lna", 0, 36, 2) }; -static struct ralink_pmx_func rt3352_pa_grp[] = { FUNC("pa", 0, 38, 2) }; -static struct ralink_pmx_func rt3352_led_grp[] = { FUNC("led", 0, 40, 5) }; -static struct ralink_pmx_func rt3352_cs1_grp[] = { +static struct mtmips_pmx_func rgmii_grp[] = { FUNC("rgmii", 0, 40, 12) }; +static struct mtmips_pmx_func rt3352_lna_grp[] = { FUNC("lna", 0, 36, 2) }; +static struct mtmips_pmx_func rt3352_pa_grp[] = { FUNC("pa", 0, 38, 2) }; +static struct mtmips_pmx_func rt3352_led_grp[] = { FUNC("led", 0, 40, 5) }; +static struct mtmips_pmx_func rt3352_cs1_grp[] = { FUNC("spi_cs1", 0, 45, 1), FUNC("wdg_cs1", 1, 45, 1), }; -static struct ralink_pmx_group rt3050_pinmux_data[] = { +static struct mtmips_pmx_group rt3050_pinmux_data[] = { GRP("i2c", i2c_grp, 1, RT305X_GPIO_MODE_I2C), GRP("spi", spi_grp, 1, RT305X_GPIO_MODE_SPI), GRP("uartf", uartf_grp, RT305X_GPIO_MODE_UART0_MASK, @@ -76,7 +76,7 @@ static struct ralink_pmx_group rt3050_pinmux_data[] = { { 0 } }; -static struct ralink_pmx_group rt3352_pinmux_data[] = { +static struct mtmips_pmx_group rt3352_pinmux_data[] = { GRP("i2c", i2c_grp, 1, RT305X_GPIO_MODE_I2C), GRP("spi", spi_grp, 1, RT305X_GPIO_MODE_SPI), GRP("uartf", uartf_grp, RT305X_GPIO_MODE_UART0_MASK, @@ -92,7 +92,7 @@ static struct ralink_pmx_group rt3352_pinmux_data[] = { { 0 } }; -static struct ralink_pmx_group rt5350_pinmux_data[] = { +static struct mtmips_pmx_group rt5350_pinmux_data[] = { GRP("i2c", i2c_grp, 1, RT305X_GPIO_MODE_I2C), GRP("spi", spi_grp, 1, RT305X_GPIO_MODE_SPI), GRP("uartf", uartf_grp, RT305X_GPIO_MODE_UART0_MASK, @@ -107,11 +107,11 @@ static struct ralink_pmx_group rt5350_pinmux_data[] = { static int rt305x_pinctrl_probe(struct platform_device *pdev) { if (soc_is_rt5350()) - return ralink_pinctrl_init(pdev, rt5350_pinmux_data); + return mtmips_pinctrl_init(pdev, rt5350_pinmux_data); else if (soc_is_rt305x() || soc_is_rt3350()) - return ralink_pinctrl_init(pdev, rt3050_pinmux_data); + return mtmips_pinctrl_init(pdev, rt3050_pinmux_data); else if (soc_is_rt3352()) - return ralink_pinctrl_init(pdev, rt3352_pinmux_data); + return mtmips_pinctrl_init(pdev, rt3352_pinmux_data); else return -EINVAL; } diff --git a/drivers/pinctrl/ralink/pinctrl-rt3883.c b/drivers/pinctrl/mediatek/pinctrl-rt3883.c similarity index 80% rename from drivers/pinctrl/ralink/pinctrl-rt3883.c rename to drivers/pinctrl/mediatek/pinctrl-rt3883.c index 5f766d76bafa..eeaf344c3647 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt3883.c +++ b/drivers/pinctrl/mediatek/pinctrl-rt3883.c @@ -3,7 +3,7 @@ #include #include #include -#include "pinctrl-ralink.h" +#include "pinctrl-mtmips.h" #define RT3883_GPIO_MODE_UART0_SHIFT 2 #define RT3883_GPIO_MODE_UART0_MASK 0x7 @@ -39,9 +39,9 @@ #define RT3883_GPIO_MODE_LNA_G_GPIO 0x3 #define RT3883_GPIO_MODE_LNA_G _RT3883_GPIO_MODE_LNA_G(RT3883_GPIO_MODE_LNA_G_MASK) -static struct ralink_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; -static struct ralink_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; -static struct ralink_pmx_func uartf_grp[] = { +static struct mtmips_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; +static struct mtmips_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; +static struct mtmips_pmx_func uartf_grp[] = { FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8), FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8), FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8), @@ -50,21 +50,21 @@ static struct ralink_pmx_func uartf_grp[] = { FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4), FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4), }; -static struct ralink_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) }; -static struct ralink_pmx_func jtag_grp[] = { FUNC("jtag", 0, 17, 5) }; -static struct ralink_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) }; -static struct ralink_pmx_func lna_a_grp[] = { FUNC("lna a", 0, 32, 3) }; -static struct ralink_pmx_func lna_g_grp[] = { FUNC("lna g", 0, 35, 3) }; -static struct ralink_pmx_func pci_grp[] = { +static struct mtmips_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) }; +static struct mtmips_pmx_func jtag_grp[] = { FUNC("jtag", 0, 17, 5) }; +static struct mtmips_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) }; +static struct mtmips_pmx_func lna_a_grp[] = { FUNC("lna a", 0, 32, 3) }; +static struct mtmips_pmx_func lna_g_grp[] = { FUNC("lna g", 0, 35, 3) }; +static struct mtmips_pmx_func pci_grp[] = { FUNC("pci-dev", 0, 40, 32), FUNC("pci-host2", 1, 40, 32), FUNC("pci-host1", 2, 40, 32), FUNC("pci-fnc", 3, 40, 32) }; -static struct ralink_pmx_func ge1_grp[] = { FUNC("ge1", 0, 72, 12) }; -static struct ralink_pmx_func ge2_grp[] = { FUNC("ge2", 0, 84, 12) }; +static struct mtmips_pmx_func ge1_grp[] = { FUNC("ge1", 0, 72, 12) }; +static struct mtmips_pmx_func ge2_grp[] = { FUNC("ge2", 0, 84, 12) }; -static struct ralink_pmx_group rt3883_pinmux_data[] = { +static struct mtmips_pmx_group rt3883_pinmux_data[] = { GRP("i2c", i2c_grp, 1, RT3883_GPIO_MODE_I2C), GRP("spi", spi_grp, 1, RT3883_GPIO_MODE_SPI), GRP("uartf", uartf_grp, RT3883_GPIO_MODE_UART0_MASK, @@ -83,7 +83,7 @@ static struct ralink_pmx_group rt3883_pinmux_data[] = { static int rt3883_pinctrl_probe(struct platform_device *pdev) { - return ralink_pinctrl_init(pdev, rt3883_pinmux_data); + return mtmips_pinctrl_init(pdev, rt3883_pinmux_data); } static const struct of_device_id rt3883_pinctrl_match[] = { diff --git a/drivers/pinctrl/ralink/Kconfig b/drivers/pinctrl/ralink/Kconfig deleted file mode 100644 index c5fe4c31aaea..000000000000 --- a/drivers/pinctrl/ralink/Kconfig +++ /dev/null @@ -1,40 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -menu "Ralink pinctrl drivers" - depends on RALINK - -config PINCTRL_RALINK - bool "Ralink pinctrl driver" - select PINMUX - select GENERIC_PINCONF - -config PINCTRL_MT7620 - bool "MT7620 pinctrl subdriver" - depends on RALINK && SOC_MT7620 - select PINCTRL_RALINK - -config PINCTRL_MT7621 - bool "MT7621 pinctrl subdriver" - depends on RALINK && SOC_MT7621 - select PINCTRL_RALINK - -config PINCTRL_MT76X8 - bool "MT76X8 pinctrl subdriver" - depends on RALINK && SOC_MT7620 - select PINCTRL_RALINK - -config PINCTRL_RT2880 - bool "RT2880 pinctrl subdriver" - depends on RALINK && SOC_RT288X - select PINCTRL_RALINK - -config PINCTRL_RT305X - bool "RT305X pinctrl subdriver" - depends on RALINK && SOC_RT305X - select PINCTRL_RALINK - -config PINCTRL_RT3883 - bool "RT3883 pinctrl subdriver" - depends on RALINK && SOC_RT3883 - select PINCTRL_RALINK - -endmenu diff --git a/drivers/pinctrl/ralink/Makefile b/drivers/pinctrl/ralink/Makefile deleted file mode 100644 index be9acf2e27fd..000000000000 --- a/drivers/pinctrl/ralink/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_PINCTRL_RALINK) += pinctrl-ralink.o - -obj-$(CONFIG_PINCTRL_MT7620) += pinctrl-mt7620.o -obj-$(CONFIG_PINCTRL_MT7621) += pinctrl-mt7621.o -obj-$(CONFIG_PINCTRL_MT76X8) += pinctrl-mt76x8.o -obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o -obj-$(CONFIG_PINCTRL_RT305X) += pinctrl-rt305x.o -obj-$(CONFIG_PINCTRL_RT3883) += pinctrl-rt3883.o From patchwork Fri Mar 17 21:29:55 2023 Content-Type: text/plain; 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Fri, 17 Mar 2023 14:30:29 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.30.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:30:28 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Sergio Paracuellos , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?utf-8?q?Bernhard_Rosenkr=C3=A4nze?= =?utf-8?q?r?= , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 05/21] pinctrl: mediatek: remove OF_GPIO as reverse dependency Date: Sat, 18 Mar 2023 00:29:55 +0300 Message-Id: <20230317213011.13656-6-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Arınç ÜNAL The OF_GPIO option is enabled by default when GPIOLIB is enabled, and cannot be disabled. Remove it as a reverse dependency where GPIOLIB is also set as a reverse dependency. Signed-off-by: Arınç ÜNAL Reviewed-by: Sergio Paracuellos Reviewed-by: AngeloGioacchino Del Regno --- drivers/pinctrl/mediatek/Kconfig | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index ba21a599953c..ee04b1af36dd 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -17,7 +17,6 @@ config PINCTRL_MTK select GENERIC_PINCONF select GPIOLIB select EINT_MTK - select OF_GPIO config PINCTRL_MTK_V2 tristate @@ -35,7 +34,6 @@ config PINCTRL_MTK_MOORE select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS select GPIOLIB - select OF_GPIO select EINT_MTK select PINCTRL_MTK_V2 @@ -46,7 +44,6 @@ config PINCTRL_MTK_PARIS select GENERIC_PINCONF select GPIOLIB select EINT_MTK - select OF_GPIO select PINCTRL_MTK_V2 # For MIPS SoCs From patchwork Fri Mar 17 21:29:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 664648 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28C5FC7618B for ; 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Fri, 17 Mar 2023 14:30:31 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Rob Herring , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?utf-8?q?Bernhard_Rosenkr=C3=A4nze?= =?utf-8?q?r?= , Sergio Paracuellos , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 06/21] dt-bindings: pinctrl: ralink: move additionalProperties to top Date: Sat, 18 Mar 2023 00:29:56 +0300 Message-Id: <20230317213011.13656-7-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Arınç ÜNAL Move additionalProperties to the top. It's easier to read than after a long indented section. Signed-off-by: Arınç ÜNAL Reviewed-by: Rob Herring --- .../devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml | 7 +++---- .../devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml | 7 +++---- .../devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml | 7 +++---- .../devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml | 7 +++---- .../devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml | 7 +++---- 5 files changed, 15 insertions(+), 20 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml index 1e63ea34146a..b25e0db77cb3 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml @@ -22,11 +22,14 @@ properties: patternProperties: '-pins$': type: object + additionalProperties: false + patternProperties: '^(.*-)?pinmux$': type: object description: node for pinctrl. $ref: pinmux-node.yaml# + additionalProperties: false properties: function: @@ -632,10 +635,6 @@ patternProperties: groups: enum: [i2c, spi cs1, uart0] - additionalProperties: false - - additionalProperties: false - allOf: - $ref: "pinctrl.yaml#" diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml index 1b1d37b981d9..60f6273930f5 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml @@ -22,11 +22,14 @@ properties: patternProperties: '-pins$': type: object + additionalProperties: false + patternProperties: '^(.*-)?pinmux$': type: object description: node for pinctrl. $ref: pinmux-node.yaml# + additionalProperties: false properties: function: @@ -236,10 +239,6 @@ patternProperties: groups: enum: [wdt] - additionalProperties: false - - additionalProperties: false - allOf: - $ref: "pinctrl.yaml#" diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml index 7fd0df880a76..4f3e0af7d18f 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml @@ -22,11 +22,14 @@ properties: patternProperties: '-pins$': type: object + additionalProperties: false + patternProperties: '^(.*-)?pinmux$': type: object description: node for pinctrl. $ref: pinmux-node.yaml# + additionalProperties: false properties: function: @@ -116,10 +119,6 @@ patternProperties: groups: enum: [pci] - additionalProperties: false - - additionalProperties: false - allOf: - $ref: "pinctrl.yaml#" diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml index 4d66ca752a30..9e45d851def6 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml @@ -23,11 +23,14 @@ properties: patternProperties: '-pins$': type: object + additionalProperties: false + patternProperties: '^(.*-)?pinmux$': type: object description: node for pinctrl. $ref: pinmux-node.yaml# + additionalProperties: false properties: function: @@ -249,10 +252,6 @@ patternProperties: groups: enum: [spi_cs1] - additionalProperties: false - - additionalProperties: false - allOf: - $ref: "pinctrl.yaml#" diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml index 008d93181aea..4bea19d4ad7b 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml @@ -22,11 +22,14 @@ properties: patternProperties: '-pins$': type: object + additionalProperties: false + patternProperties: '^(.*-)?pinmux$': type: object description: node for pinctrl. $ref: pinmux-node.yaml# + additionalProperties: false properties: function: @@ -236,10 +239,6 @@ patternProperties: groups: enum: [uartlite] - additionalProperties: false - - additionalProperties: false - allOf: - $ref: "pinctrl.yaml#" From patchwork Fri Mar 17 21:29:57 2023 Content-Type: text/plain; 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Fri, 17 Mar 2023 14:30:34 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.30.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:30:33 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Rob Herring , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?utf-8?q?Bernhard_Rosenkr=C3=A4nze?= =?utf-8?q?r?= , Sergio Paracuellos , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 07/21] dt-bindings: pinctrl: ralink: drop quotes from referred schemas Date: Sat, 18 Mar 2023 00:29:57 +0300 Message-Id: <20230317213011.13656-8-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Arınç ÜNAL Drop the quotes from the referred schemas. Signed-off-by: Arınç ÜNAL Reviewed-by: Rob Herring --- .../devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml | 2 +- .../devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml | 2 +- .../devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml | 2 +- .../devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml | 2 +- .../devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml index b25e0db77cb3..cde6de77e228 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml @@ -636,7 +636,7 @@ patternProperties: enum: [i2c, spi cs1, uart0] allOf: - - $ref: "pinctrl.yaml#" + - $ref: pinctrl.yaml# required: - compatible diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml index 60f6273930f5..fb8c5459ea93 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml @@ -240,7 +240,7 @@ patternProperties: enum: [wdt] allOf: - - $ref: "pinctrl.yaml#" + - $ref: pinctrl.yaml# required: - compatible diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml index 4f3e0af7d18f..e51667316b2e 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml @@ -120,7 +120,7 @@ patternProperties: enum: [pci] allOf: - - $ref: "pinctrl.yaml#" + - $ref: pinctrl.yaml# required: - compatible diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml index 9e45d851def6..8b1256af09c3 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml @@ -253,7 +253,7 @@ patternProperties: enum: [spi_cs1] allOf: - - $ref: "pinctrl.yaml#" + - $ref: pinctrl.yaml# required: - compatible diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml index 4bea19d4ad7b..adc4f42a175d 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml @@ -240,7 +240,7 @@ patternProperties: enum: [uartlite] allOf: - - $ref: "pinctrl.yaml#" + - $ref: pinctrl.yaml# required: - compatible From patchwork Fri Mar 17 21:29:58 2023 Content-Type: text/plain; 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Fri, 17 Mar 2023 14:30:36 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.30.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:30:36 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Rob Herring , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?utf-8?q?Bernhard_Rosenkr=C3=A4nze?= =?utf-8?q?r?= , Sergio Paracuellos , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 08/21] dt-bindings: pinctrl: ralink: add new compatible strings Date: Sat, 18 Mar 2023 00:29:58 +0300 Message-Id: <20230317213011.13656-9-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Arınç ÜNAL Add the new compatible strings for mt7620, mt76x8, and rt305x to be able to properly document the pin muxing information of each SoC, or SoCs that use the same pinmux data. Signed-off-by: Arınç ÜNAL Reviewed-by: Rob Herring --- .../devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml | 4 +++- .../devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml | 5 ++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml index cde6de77e228..09ebb8ac22ac 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml @@ -17,7 +17,9 @@ description: properties: compatible: - const: ralink,mt7620-pinctrl + enum: + - ralink,mt7620-pinctrl + - ralink,mt76x8-pinctrl patternProperties: '-pins$': diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml index 8b1256af09c3..23fb82f9959c 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml @@ -18,7 +18,10 @@ description: properties: compatible: - const: ralink,rt305x-pinctrl + enum: + - ralink,rt305x-pinctrl + - ralink,rt3352-pinctrl + - ralink,rt5350-pinctrl patternProperties: '-pins$': From patchwork Fri Mar 17 21:29:59 2023 Content-Type: text/plain; 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Fri, 17 Mar 2023 14:30:39 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.30.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:30:38 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Rob Herring , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?utf-8?q?Bernhard_Rosenkr=C3=A4nze?= =?utf-8?q?r?= , Sergio Paracuellos , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 09/21] dt-bindings: pinctrl: ralink: {mt7620,mt7621}: rename to mediatek Date: Sat, 18 Mar 2023 00:29:59 +0300 Message-Id: <20230317213011.13656-10-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Arınç ÜNAL Rename schemas of pin controllers for MediaTek MT7620 and MT7621 SoCs to be on par with other pin controllers for MediaTek SoCs. Signed-off-by: Arınç ÜNAL Reviewed-by: Rob Herring --- ...ink,mt7620-pinctrl.yaml => mediatek,mt7620-pinctrl.yaml} | 6 +++--- ...ink,mt7621-pinctrl.yaml => mediatek,mt7621-pinctrl.yaml} | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) rename Documentation/devicetree/bindings/pinctrl/{ralink,mt7620-pinctrl.yaml => mediatek,mt7620-pinctrl.yaml} (98%) rename Documentation/devicetree/bindings/pinctrl/{ralink,mt7621-pinctrl.yaml => mediatek,mt7621-pinctrl.yaml} (97%) diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml similarity index 98% rename from Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml rename to Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml index 09ebb8ac22ac..0dcdc3788e66 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml @@ -1,17 +1,17 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/ralink,mt7620-pinctrl.yaml# +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7620-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Ralink MT7620 Pin Controller +title: MediaTek MT7620 Pin Controller maintainers: - Arınç ÜNAL - Sergio Paracuellos description: - Ralink MT7620 pin controller for MT7620, MT7628 and MT7688 SoCs. + MediaTek MT7620 pin controller for MT7620, MT7628 and MT7688 SoCs. The pin controller can only set the muxing of pin groups. Muxing individual pins is not supported. There is no pinconf support. diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl.yaml similarity index 97% rename from Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml rename to Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl.yaml index fb8c5459ea93..32506c538459 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl.yaml @@ -1,17 +1,17 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/ralink,mt7621-pinctrl.yaml# +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7621-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Ralink MT7621 Pin Controller +title: MediaTek MT7621 Pin Controller maintainers: - Arınç ÜNAL - Sergio Paracuellos description: - Ralink MT7621 pin controller for MT7621 SoC. + MediaTek MT7621 pin controller for MT7621 SoC. The pin controller can only set the muxing of pin groups. Muxing individual pins is not supported. There is no pinconf support. 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Signed-off-by: Arınç ÜNAL Acked-by: Rob Herring --- ...ediatek,pinctrl-mt6795.yaml => mediatek,mt6795-pinctrl.yaml} | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) rename Documentation/devicetree/bindings/pinctrl/{mediatek,pinctrl-mt6795.yaml => mediatek,mt6795-pinctrl.yaml} (98%) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,pinctrl-mt6795.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml similarity index 98% rename from Documentation/devicetree/bindings/pinctrl/mediatek,pinctrl-mt6795.yaml rename to Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml index 9399e0215526..c5131f053b61 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,pinctrl-mt6795.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/mediatek,pinctrl-mt6795.yaml# +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6795-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Mediatek MT6795 Pin Controller From patchwork Fri Mar 17 21:30:01 2023 Content-Type: text/plain; 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Fri, 17 Mar 2023 14:30:44 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.30.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:30:43 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Rob Herring , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?utf-8?q?Bernhard_Rosenkr=C3=A4nze?= =?utf-8?q?r?= , Sergio Paracuellos , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 11/21] dt-bindings: pinctrl: mediatek: mt8186: rename to mediatek,mt8186-pinctrl Date: Sat, 18 Mar 2023 00:30:01 +0300 Message-Id: <20230317213011.13656-12-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Arınç ÜNAL Rename pinctrl-mt8186.yaml to mediatek,mt8186-pinctrl.yaml to be on par with the compatible string and other mediatek dt-binding schemas. Signed-off-by: Arınç ÜNAL Acked-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno --- .../{pinctrl-mt8186.yaml => mediatek,mt8186-pinctrl.yaml} | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) rename Documentation/devicetree/bindings/pinctrl/{pinctrl-mt8186.yaml => mediatek,mt8186-pinctrl.yaml} (99%) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml similarity index 99% rename from Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml rename to Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml index 26573a793b57..32d64416eb16 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8186.yaml# +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8186-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Mediatek MT8186 Pin Controller From patchwork Fri Mar 17 21:30:02 2023 Content-Type: text/plain; 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Fri, 17 Mar 2023 14:30:46 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.30.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:30:46 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Rob Herring , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?utf-8?q?Bernhard_Rosenkr=C3=A4nze?= =?utf-8?q?r?= , Sergio Paracuellos , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 12/21] dt-bindings: pinctrl: mediatek: mt8192: rename to mediatek,mt8192-pinctrl Date: Sat, 18 Mar 2023 00:30:02 +0300 Message-Id: <20230317213011.13656-13-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Arınç ÜNAL Rename pinctrl-mt8192.yaml to mediatek,mt8192-pinctrl.yaml to be on par with the compatible string and other mediatek dt-binding schemas. Signed-off-by: Arınç ÜNAL Acked-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno --- .../{pinctrl-mt8192.yaml => mediatek,mt8192-pinctrl.yaml} | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) rename Documentation/devicetree/bindings/pinctrl/{pinctrl-mt8192.yaml => mediatek,mt8192-pinctrl.yaml} (98%) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml similarity index 98% rename from Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml rename to Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml index e0e943e5b874..e764cb0f8c1a 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8192.yaml# +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8192-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Mediatek MT8192 Pin Controller From patchwork Fri Mar 17 21:30:03 2023 Content-Type: text/plain; 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Fri, 17 Mar 2023 14:30:49 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.30.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:30:48 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Rob Herring , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?utf-8?q?Bernhard_Rosenkr=C3=A4nze?= =?utf-8?q?r?= , Sergio Paracuellos , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 13/21] dt-bindings: pinctrl: mediatek: mt8195: rename to mediatek,mt8195-pinctrl Date: Sat, 18 Mar 2023 00:30:03 +0300 Message-Id: <20230317213011.13656-14-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Arınç ÜNAL Rename pinctrl-mt8195.yaml to mediatek,mt8195-pinctrl.yaml to be on par with the compatible string and other mediatek dt-binding schemas. Signed-off-by: Arınç ÜNAL Acked-by: Rob Herring --- .../{pinctrl-mt8195.yaml => mediatek,mt8195-pinctrl.yaml} | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) rename Documentation/devicetree/bindings/pinctrl/{pinctrl-mt8195.yaml => mediatek,mt8195-pinctrl.yaml} (99%) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml similarity index 99% rename from Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml rename to Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml index 66fe17e9e4d3..7b3dfc14eedc 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8195.yaml# +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8195-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Mediatek MT8195 Pin Controller From patchwork Fri Mar 17 21:30:04 2023 Content-Type: text/plain; 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Fri, 17 Mar 2023 14:30:51 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.30.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:30:51 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Rob Herring , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?utf-8?q?Bernhard_Rosenkr=C3=A4nze?= =?utf-8?q?r?= , Sergio Paracuellos , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 14/21] dt-bindings: pinctrl: mediatek: fix naming inconsistency Date: Sat, 18 Mar 2023 00:30:04 +0300 Message-Id: <20230317213011.13656-15-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Arınç ÜNAL Some schemas include "MediaTek", some "Mediatek". Rename all to "MediaTek" to address the naming inconsistency. Signed-off-by: Arınç ÜNAL Reviewed-by: Rob Herring --- .../devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml | 4 ++-- .../devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 2 +- .../devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml | 4 ++-- .../devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml | 2 +- .../devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml | 2 +- .../devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml | 2 +- .../devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml | 2 +- .../devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml | 4 ++-- .../devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml | 4 ++-- .../devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml | 4 ++-- .../devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml | 2 +- 11 files changed, 16 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml index a55c8e4ff26e..77b1b52f5799 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml @@ -4,13 +4,13 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT65xx Pin Controller +title: MediaTek MT65xx Pin Controller maintainers: - Sean Wang description: |+ - The Mediatek's Pin controller is used to control SoC pins. + The MediaTek's MT65xx Pin controller is used to control SoC pins. properties: compatible: diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml index a2141eb0854e..c2fea29fa02f 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT6779 Pin Controller +title: MediaTek MT6779 Pin Controller maintainers: - Andy Teng diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml index c5131f053b61..a78df32e6c39 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml @@ -4,14 +4,14 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6795-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT6795 Pin Controller +title: MediaTek MT6795 Pin Controller maintainers: - AngeloGioacchino Del Regno - Sean Wang description: | - The Mediatek's Pin controller is used to control SoC pins. + The MediaTek's MT6795 Pin controller is used to control SoC pins. properties: compatible: diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml index ac93eb8f01a6..3531b63ca4bf 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7622-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT7622 Pin Controller +title: MediaTek MT7622 Pin Controller maintainers: - Sean Wang diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml index 74c66fbcb2ae..c3373290a8a1 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7981-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT7981 Pin Controller +title: MediaTek MT7981 Pin Controller maintainers: - Daniel Golle diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml index 216b356cd519..71033831d03d 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7986-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT7986 Pin Controller +title: MediaTek MT7986 Pin Controller maintainers: - Sean Wang diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml index c30cd0d010dd..3e34b03e11fc 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8183-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT8183 Pin Controller +title: MediaTek MT8183 Pin Controller maintainers: - Sean Wang diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml index 32d64416eb16..a0519acc92fe 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml @@ -4,13 +4,13 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8186-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT8186 Pin Controller +title: MediaTek MT8186 Pin Controller maintainers: - Sean Wang description: | - The Mediatek's Pin controller is used to control SoC pins. + The MediaTek's MT8186 Pin controller is used to control SoC pins. properties: compatible: diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml index e764cb0f8c1a..3c3dd142a989 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml @@ -4,13 +4,13 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8192-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT8192 Pin Controller +title: MediaTek MT8192 Pin Controller maintainers: - Sean Wang description: | - The Mediatek's Pin controller is used to control SoC pins. + The MediaTek's MT8192 Pin controller is used to control SoC pins. properties: compatible: diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml index 7b3dfc14eedc..d4d5357cdd1d 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml @@ -4,13 +4,13 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8195-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT8195 Pin Controller +title: MediaTek MT8195 Pin Controller maintainers: - Sean Wang description: | - The Mediatek's Pin controller is used to control SoC pins. + The MediaTek's MT8195 Pin controller is used to control SoC pins. properties: compatible: diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml index 4b96884a1afc..42964dfa9fdb 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT8365 Pin Controller +title: MediaTek MT8365 Pin Controller maintainers: - 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Fix capitalisation and indentation. Fit the schemas to 80 columns for each line. Signed-off-by: Arınç ÜNAL Reviewed-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno --- .../pinctrl/mediatek,mt65xx-pinctrl.yaml | 22 +++--- .../pinctrl/mediatek,mt6779-pinctrl.yaml | 33 +++++---- .../pinctrl/mediatek,mt6795-pinctrl.yaml | 41 +++++----- .../pinctrl/mediatek,mt7620-pinctrl.yaml | 2 +- .../pinctrl/mediatek,mt7621-pinctrl.yaml | 2 +- .../pinctrl/mediatek,mt7622-pinctrl.yaml | 26 +++---- .../pinctrl/mediatek,mt7981-pinctrl.yaml | 33 +++++---- .../pinctrl/mediatek,mt7986-pinctrl.yaml | 68 ++++++++--------- .../pinctrl/mediatek,mt8183-pinctrl.yaml | 26 ++++--- .../pinctrl/mediatek,mt8186-pinctrl.yaml | 47 ++++++------ .../pinctrl/mediatek,mt8188-pinctrl.yaml | 74 ++++++++++--------- .../pinctrl/mediatek,mt8192-pinctrl.yaml | 47 ++++++------ .../pinctrl/mediatek,mt8195-pinctrl.yaml | 41 +++++----- .../pinctrl/mediatek,mt8365-pinctrl.yaml | 28 +++---- .../pinctrl/ralink,rt2880-pinctrl.yaml | 2 +- .../pinctrl/ralink,rt305x-pinctrl.yaml | 2 +- .../pinctrl/ralink,rt3883-pinctrl.yaml | 2 +- 17 files changed, 258 insertions(+), 238 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml index 77b1b52f5799..5e80621800a9 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml @@ -9,7 +9,7 @@ title: MediaTek MT65xx Pin Controller maintainers: - Sean Wang -description: |+ +description: The MediaTek's MT65xx Pin controller is used to control SoC pins. properties: @@ -30,7 +30,7 @@ properties: pins-are-numbered: $ref: /schemas/types.yaml#/definitions/flag - description: | + description: Specify the subnodes are using numbered pinmux to specify pins. (UNUSED) deprecated: true @@ -38,10 +38,10 @@ properties: "#gpio-cells": const: 2 - description: | - Number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular cells. + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. mediatek,pctl-regmap: $ref: /schemas/types.yaml#/definitions/phandle-array @@ -49,7 +49,7 @@ properties: maxItems: 1 minItems: 1 maxItems: 2 - description: | + description: Should be phandles of the syscfg node. interrupt-controller: true @@ -77,7 +77,7 @@ patternProperties: '(^pins|pins?$)': type: object additionalProperties: false - description: | + description: A pinctrl node should contain at least one subnodes representing the pinctrl groups available on the machine. Each subnode will list the pins it needs, and how they should be configured, with regard to muxer @@ -88,14 +88,14 @@ patternProperties: properties: pinmux: description: - integer array, represents gpio pin number and mux setting. + Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and are defined as macros in -pinfunc.h directly. bias-disable: true bias-pull-up: - description: | + description: Besides generic pinconfig options, it can be used as the pull up settings for 2 pull resistors, R0 and R1. User can configure those special pins. Some macros have been defined for this usage, such @@ -117,7 +117,7 @@ patternProperties: input-schmitt-disable: true drive-strength: - description: | + description: Can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h for valid arguments. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml index c2fea29fa02f..1d038f6f8971 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -11,8 +11,8 @@ maintainers: - Sean Wang description: - The MediaTek pin controller on MT6779 is used to control pin - functions, pull up/down resistance and drive strength options. + The MediaTek pin controller on MT6779 is used to control pin functions, pull + up/down resistance and drive strength options. properties: compatible: @@ -29,22 +29,22 @@ properties: "#gpio-cells": const: 2 - description: | - Number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular cells. + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. gpio-ranges: minItems: 1 maxItems: 5 - description: | + description: GPIO valid number range. interrupt-controller: true interrupts: maxItems: 1 - description: | + description: Specifies the summary IRQ. "#interrupt-cells": @@ -118,19 +118,20 @@ patternProperties: patternProperties: '-pins*$': type: object - description: | + description: A pinctrl node should contain at least one subnodes representing the pinctrl groups available on the machine. Each subnode will list the pins it needs, and how they should be configured, with regard to muxer - configuration, pullups, drive strength, input enable/disable and input schmitt. + configuration, pullups, drive strength, input enable/disable and input + schmitt. $ref: "/schemas/pinctrl/pincfg-node.yaml" properties: pinmux: description: - integer array, represents gpio pin number and mux setting. - Supported pin number and mux varies for different SoCs, and are defined - as macros in boot/dts/-pinfunc.h directly. + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in boot/dts/-pinfunc.h directly. bias-disable: true @@ -159,7 +160,8 @@ patternProperties: mediatek,pull-up-adv: description: | Pull up setings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described as below: + configure those special pins. Valid arguments are described as + below: 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. @@ -170,7 +172,8 @@ patternProperties: mediatek,pull-down-adv: description: | Pull down settings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described as below: + configure those special pins. Valid arguments are described as + below: 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml index a78df32e6c39..c3bf98749fa4 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml @@ -10,7 +10,7 @@ maintainers: - AngeloGioacchino Del Regno - Sean Wang -description: | +description: The MediaTek's MT6795 Pin controller is used to control SoC pins. properties: @@ -20,10 +20,10 @@ properties: gpio-controller: true '#gpio-cells': - description: | + description: Number of cells in GPIO specifier. Since the generic GPIO binding is used, - the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular cells. + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. const: 2 gpio-ranges: @@ -32,7 +32,7 @@ properties: reg: description: - Physical address base for gpio base and eint registers. + Physical address base for GPIO base and eint registers. minItems: 2 reg-names: @@ -65,8 +65,8 @@ patternProperties: A pinctrl node should contain at least one subnodes representing the pinctrl groups available on the machine. Each subnode will list the pins it needs, and how they should be configured, with regard to muxer - configuration, pullups, drive strength, input enable/disable and - input schmitt. + configuration, pullups, drive strength, input enable/disable and input + schmitt. An example of using macro: pincontroller { /* GPIO0 set as multifunction GPIO0 */ @@ -86,11 +86,10 @@ patternProperties: properties: pinmux: - description: | + description: Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and are - defined as macros in dt-bindings/pinctrl/-pinfunc.h - directly. + defined as macros in dt-bindings/pinctrl/-pinfunc.h directly. drive-strength: enum: [2, 4, 6, 8, 10, 12, 14, 16] @@ -100,20 +99,20 @@ patternProperties: - type: boolean - enum: [100, 101, 102, 103] description: mt6795 pull down PUPD/R0/R1 type define value. - description: | - For normal pull down type, it is not necessary to specify R1R0 - values; When pull down type is PUPD/R0/R1, adding R1R0 defines - will set different resistance values. + description: + For normal pull down type, it is not necessary to specify R1R0 + values; When pull down type is PUPD/R0/R1, adding R1R0 defines + will set different resistance values. bias-pull-up: oneOf: - type: boolean - enum: [100, 101, 102, 103] description: mt6795 pull up PUPD/R0/R1 type define value. - description: | - For normal pull up type, it is not necessary to specify R1R0 - values; When pull up type is PUPD/R0/R1, adding R1R0 defines - will set different resistance values. + description: + For normal pull up type, it is not necessary to specify R1R0 + values; When pull up type is PUPD/R0/R1, adding R1R0 defines will + set different resistance values. bias-disable: true @@ -132,7 +131,8 @@ patternProperties: mediatek,pull-up-adv: description: | Pull up setings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described as below: + configure those special pins. Valid arguments are described as + below: 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. @@ -143,7 +143,8 @@ patternProperties: mediatek,pull-down-adv: description: | Pull down settings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described as below: + configure those special pins. Valid arguments are described as + below: 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml index 0dcdc3788e66..808dd8bd276f 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml @@ -10,7 +10,7 @@ maintainers: - Arınç ÜNAL - Sergio Paracuellos -description: +description: | MediaTek MT7620 pin controller for MT7620, MT7628 and MT7688 SoCs. The pin controller can only set the muxing of pin groups. Muxing individual pins is not supported. There is no pinconf support. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl.yaml index 32506c538459..e568b9c13727 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl.yaml @@ -10,7 +10,7 @@ maintainers: - Arınç ÜNAL - Sergio Paracuellos -description: +description: | MediaTek MT7621 pin controller for MT7621 SoC. The pin controller can only set the muxing of pin groups. Muxing individual pins is not supported. There is no pinconf support. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml index 3531b63ca4bf..38dc41c735eb 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml @@ -9,7 +9,7 @@ title: MediaTek MT7622 Pin Controller maintainers: - Sean Wang -description: |+ +description: The MediaTek's MT7622 Pin controller is used to control SoC pins. properties: @@ -29,10 +29,10 @@ properties: "#gpio-cells": const: 2 - description: | - Number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular cells. + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. interrupt-controller: true @@ -68,18 +68,18 @@ patternProperties: '^mux(-|$)': type: object additionalProperties: false - description: | + description: pinmux configuration nodes. $ref: "/schemas/pinctrl/pinmux-node.yaml" properties: function: - description: | + description: A string containing the name of the function to mux to the group. enum: [emmc, eth, i2c, i2s, ir, led, flash, pcie, pmic, pwm, sd, spi, tdm, uart, watchdog, wifi] groups: - description: | + description: An array of strings. Each string contains the name of a group. drive-strength: @@ -247,18 +247,18 @@ patternProperties: '^conf(-|$)': type: object additionalProperties: false - description: | + description: pinconf configuration nodes. $ref: "/schemas/pinctrl/pincfg-node.yaml" properties: groups: - description: | + description: An array of strings. Each string contains the name of a group. Valid values are the same as the pinmux node. pins: - description: | + description: An array of strings. Each string contains the name of a pin. enum: [GPIO_A, I2S1_IN, I2S1_OUT, I2S_BCLK, I2S_WS, I2S_MCLK, TXD0, RXD0, SPI_WP, SPI_HOLD, SPI_CLK, SPI_MOSI, SPI_MISO, SPI_CS, @@ -315,14 +315,14 @@ patternProperties: enum: [0, 1] mediatek,tdsel: - description: | + description: An integer describing the steps for output level shifter duty cycle when asserted (high pulse width adjustment). Valid arguments are from 0 to 15. $ref: /schemas/types.yaml#/definitions/uint32 mediatek,rdsel: - description: | + description: An integer describing the steps for input level shifter duty cycle when asserted (high pulse width adjustment). Valid arguments are from 0 to 63. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml index c3373290a8a1..10717cee9058 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml @@ -37,7 +37,7 @@ properties: "#gpio-cells": const: 2 - description: > + description: Number of cells in GPIO specifier. Since the generic GPIO binding is used, the amount of cells must be specified as 2. See the below mentioned gpio binding representation for description of particular cells. @@ -111,7 +111,9 @@ patternProperties: "watchdog1" "watchdog" 13 "udi" "udi" 9, 10, 11, 12, 13 "drv_vbus" "usb" 14 - "emmc_45" "flash" 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25 + "emmc_45" "flash" 15, 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25 + "snfi" "flash" 16, 17, 18, 19, 20, 21 "spi0" "spi" 16, 17, 18, 19 "spi0_wp_hold" "spi" 20, 21 @@ -148,7 +150,7 @@ patternProperties: "wf5g_led0" "led" 31 "wf5g_led1" "led" 35 "mt7531_int" "eth" 38 - "ant_sel" "ant" 14, 15, 16, 17, 18, 19, 20, 21, 22 + "ant_sel" "ant" 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 $ref: /schemas/pinctrl/pinmux-node.yaml @@ -256,7 +258,8 @@ patternProperties: then: properties: groups: - enum: [gbe_led0, gbe_led1, wf2g_led0, wf2g_led1, wf5g_led0, wf5g_led1] + enum: [gbe_led0, gbe_led1, wf2g_led0, wf2g_led1, wf5g_led0, + wf5g_led1] - if: properties: function: @@ -275,7 +278,8 @@ patternProperties: properties: groups: items: - enum: [spi1_0, spi0, spi0_wp_hold, spi1_1, spi2, spi2_wp_hold] + enum: [spi1_0, spi0, spi0_wp_hold, spi1_1, spi2, + spi2_wp_hold] maxItems: 4 - if: properties: @@ -332,13 +336,14 @@ patternProperties: JTAG_JTDO, JTAG_JTDI, JTAG_JTMS, JTAG_JTCLK, JTAG_JTRST_N, WO_JTAG_JTDO, WO_JTAG_JTDI, WO_JTAG_JTMS, WO_JTAG_JTCLK, WO_JTAG_JTRST_N, USB_VBUS, PWM0, SPI0_CLK, SPI0_MOSI, - SPI0_MISO, SPI0_CS, SPI0_HOLD, SPI0_WP, SPI1_CLK, SPI1_MOSI, - SPI1_MISO, SPI1_CS, SPI2_CLK, SPI2_MOSI, SPI2_MISO, SPI2_CS, - SPI2_HOLD, SPI2_WP, UART0_RXD, UART0_TXD, PCIE_CLK_REQ, - PCIE_WAKE_N, SMI_MDC, SMI_MDIO, GBE_INT, GBE_RESET, - WF_DIG_RESETB, WF_CBA_RESETB, WF_XO_REQ, WF_TOP_CLK, - WF_TOP_DATA, WF_HB1, WF_HB2, WF_HB3, WF_HB4, WF_HB0, - WF_HB0_B, WF_HB5, WF_HB6, WF_HB7, WF_HB8, WF_HB9, WF_HB10] + SPI0_MISO, SPI0_CS, SPI0_HOLD, SPI0_WP, SPI1_CLK, + SPI1_MOSI, SPI1_MISO, SPI1_CS, SPI2_CLK, SPI2_MOSI, + SPI2_MISO, SPI2_CS, SPI2_HOLD, SPI2_WP, UART0_RXD, + UART0_TXD, PCIE_CLK_REQ, PCIE_WAKE_N, SMI_MDC, SMI_MDIO, + GBE_INT, GBE_RESET, WF_DIG_RESETB, WF_CBA_RESETB, + WF_XO_REQ, WF_TOP_CLK, WF_TOP_DATA, WF_HB1, WF_HB2, WF_HB3, + WF_HB4, WF_HB0, WF_HB0_B, WF_HB5, WF_HB6, WF_HB7, WF_HB8, + WF_HB9, WF_HB10] maxItems: 57 bias-disable: true @@ -348,7 +353,7 @@ patternProperties: - type: boolean description: normal pull up. - enum: [100, 101, 102, 103] - description: > + description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in dt-bindings/pinctrl/mt65xx.h. @@ -357,7 +362,7 @@ patternProperties: - type: boolean description: normal pull down. - enum: [100, 101, 102, 103] - description: > + description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in dt-bindings/pinctrl/mt65xx.h. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml index 71033831d03d..7157500a7f81 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml @@ -9,7 +9,7 @@ title: MediaTek MT7986 Pin Controller maintainers: - Sean Wang -description: |+ +description: The MediaTek's MT7986 Pin controller is used to control SoC pins. properties: @@ -37,15 +37,15 @@ properties: "#gpio-cells": const: 2 - description: | - Number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular cells. + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. gpio-ranges: minItems: 1 maxItems: 5 - description: | + description: GPIO valid number range. interrupt-controller: true @@ -81,7 +81,7 @@ patternProperties: The following table shows the effective values of "group", "function" properties and chip pinout pins - groups function pins (in pin#) + groups function pins (in pin#) --------------------------------------------------------------------- "watchdog" "watchdog" 0 "wifi_led" "led" 1, 2 @@ -97,8 +97,9 @@ patternProperties: "pwm1_0" "pwm" 22, "snfi" "flash" 23, 24, 25, 26, 27, 28 "spi1_2" "spi" 29, 30, 31, 32 - "emmc_45" "emmc" 22, 23, 24, 25, 26, 27, 28, 29, 30, - 31, 32 + "emmc_45" "emmc" 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, + 32 + "spi1_1" "spi" 23, 24, 25, 26 "uart1_2_rx_tx" "uart" 29, 30 "uart1_2_cts_rts" "uart" 31, 32 @@ -115,8 +116,9 @@ patternProperties: "pcie_pereset" "pcie" 41 "uart1" "uart" 42, 43, 44, 45 "uart2" "uart" 46, 47, 48, 49 - "emmc_51" "emmc" 50, 51, 52, 53, 54, 55, 56, 57, 57, - 59, 60, 61 + "emmc_51" "emmc" 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, + 60, 61 + "pcm" "audio" 62, 63, 64, 65 "i2s" "audio" 62, 63, 64, 65 "switch_int" "eth" 66 @@ -129,18 +131,17 @@ patternProperties: $ref: "/schemas/pinctrl/pinmux-node.yaml" properties: function: - description: | + description: A string containing the name of the function to mux to the group. There is no "audio", "pcie" functions on mt7986b, you can only use those functions on mt7986a. enum: [audio, emmc, eth, i2c, led, flash, pcie, pwm, spi, uart, watchdog, wifi] groups: - description: | + description: An array of strings. Each string contains the name of a group. - There is no "pcie_pereset", "uart1", "uart2" "emmc_51", "pcm", - and "i2s" groups on mt7986b, you can only use those groups on - mt7986a. + There is no "pcie_pereset", "uart1", "uart2" "emmc_51", "pcm", and + "i2s" groups on mt7986b, you can only use those groups on mt7986a. required: - function - groups @@ -258,29 +259,30 @@ patternProperties: '.*conf.*': type: object additionalProperties: false - description: | + description: pinconf configuration nodes. $ref: "/schemas/pinctrl/pincfg-node.yaml" properties: pins: - description: | - An array of strings. Each string contains the name of a pin. - There is no PIN 41 to PIN 65 above on mt7686b, you can only use - those pins on mt7986a. + description: + An array of strings. Each string contains the name of a pin. There + is no PIN 41 to PIN 65 above on mt7686b, you can only use those + pins on mt7986a. items: enum: [SYS_WATCHDOG, WF2G_LED, WF5G_LED, I2C_SCL, I2C_SDA, GPIO_0, GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5, GPIO_6, GPIO_7, - GPIO_8, GPIO_9, GPIO_10, GPIO_11, GPIO_12, GPIO_13, GPIO_14, - GPIO_15, PWM0, PWM1, SPI0_CLK, SPI0_MOSI, SPI0_MISO, SPI0_CS, - SPI0_HOLD, SPI0_WP, SPI1_CLK, SPI1_MOSI, SPI1_MISO, SPI1_CS, - SPI2_CLK, SPI2_MOSI, SPI2_MISO, SPI2_CS, SPI2_HOLD, SPI2_WP, - UART0_RXD, UART0_TXD, PCIE_PERESET_N, UART1_RXD, UART1_TXD, - UART1_CTS, UART1_RTS, UART2_RXD, UART2_TXD, UART2_CTS, - UART2_RTS, EMMC_DATA_0, EMMC_DATA_1, EMMC_DATA_2, - EMMC_DATA_3, EMMC_DATA_4, EMMC_DATA_5, EMMC_DATA_6, - EMMC_DATA_7, EMMC_CMD, EMMC_CK, EMMC_DSL, EMMC_RSTB, PCM_DTX, - PCM_DRX, PCM_CLK, PCM_FS, MT7531_INT, SMI_MDC, SMI_MDIO, + GPIO_8, GPIO_9, GPIO_10, GPIO_11, GPIO_12, GPIO_13, + GPIO_14, GPIO_15, PWM0, PWM1, SPI0_CLK, SPI0_MOSI, + SPI0_MISO, SPI0_CS, SPI0_HOLD, SPI0_WP, SPI1_CLK, + SPI1_MOSI, SPI1_MISO, SPI1_CS, SPI2_CLK, SPI2_MOSI, + SPI2_MISO, SPI2_CS, SPI2_HOLD, SPI2_WP, UART0_RXD, + UART0_TXD, PCIE_PERESET_N, UART1_RXD, UART1_TXD, UART1_CTS, + UART1_RTS, UART2_RXD, UART2_TXD, UART2_CTS, UART2_RTS, + EMMC_DATA_0, EMMC_DATA_1, EMMC_DATA_2, EMMC_DATA_3, + EMMC_DATA_4, EMMC_DATA_5, EMMC_DATA_6, EMMC_DATA_7, + EMMC_CMD, EMMC_CK, EMMC_DSL, EMMC_RSTB, PCM_DTX, PCM_DRX, + PCM_CLK, PCM_FS, MT7531_INT, SMI_MDC, SMI_MDIO, WF0_DIG_RESETB, WF0_CBA_RESETB, WF0_XO_REQ, WF0_TOP_CLK, WF0_TOP_DATA, WF0_HB1, WF0_HB2, WF0_HB3, WF0_HB4, WF0_HB0, WF0_HB0_B, WF0_HB5, WF0_HB6, WF0_HB7, WF0_HB8, WF0_HB9, @@ -297,7 +299,7 @@ patternProperties: - type: boolean description: normal pull up. - enum: [100, 101, 102, 103] - description: | + description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in dt-bindings/pinctrl/mt65xx.h. @@ -306,7 +308,7 @@ patternProperties: - type: boolean description: normal pull down. - enum: [100, 101, 102, 103] - description: | + description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in dt-bindings/pinctrl/mt65xx.h. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml index 3e34b03e11fc..372a3aefa937 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml @@ -9,7 +9,7 @@ title: MediaTek MT8183 Pin Controller maintainers: - Sean Wang -description: |+ +description: The MediaTek's MT8183 Pin controller is used to control SoC pins. properties: @@ -37,15 +37,15 @@ properties: "#gpio-cells": const: 2 - description: | - Number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular cells. + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. gpio-ranges: minItems: 1 maxItems: 5 - description: | + description: GPIO valid number range. interrupt-controller: true @@ -74,7 +74,7 @@ patternProperties: '^pins': type: object additionalProperties: false - description: | + description: A pinctrl node should contain at least one subnodes representing the pinctrl groups available on the machine. Each subnode will list the pins it needs, and how they should be configured, with regard to muxer @@ -85,7 +85,7 @@ patternProperties: properties: pinmux: description: - integer array, represents gpio pin number and mux setting. + Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and are defined as macros in -pinfunc.h directly. @@ -139,7 +139,8 @@ patternProperties: mediatek,pull-up-adv: description: | Pull up setings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described as below: + configure those special pins. Valid arguments are described as + below: 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. @@ -150,7 +151,8 @@ patternProperties: mediatek,pull-down-adv: description: | Pull down settings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described as below: + configure those special pins. Valid arguments are described as + below: 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. @@ -159,14 +161,14 @@ patternProperties: enum: [0, 1, 2, 3] mediatek,tdsel: - description: | + description: An integer describing the steps for output level shifter duty cycle when asserted (high pulse width adjustment). Valid arguments are from 0 to 15. $ref: /schemas/types.yaml#/definitions/uint32 mediatek,rdsel: - description: | + description: An integer describing the steps for input level shifter duty cycle when asserted (high pulse width adjustment). Valid arguments are from 0 to 63. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml index a0519acc92fe..eb6a5cdecc6c 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml @@ -9,7 +9,7 @@ title: MediaTek MT8186 Pin Controller maintainers: - Sean Wang -description: | +description: The MediaTek's MT8186 Pin controller is used to control SoC pins. properties: @@ -19,10 +19,10 @@ properties: gpio-controller: true '#gpio-cells': - description: | + description: Number of cells in GPIO specifier. Since the generic GPIO binding is used, - the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular cells. + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. const: 2 gpio-ranges: @@ -31,14 +31,14 @@ properties: gpio-line-names: true reg: - description: | - Physical address base for gpio base registers. There are 8 different GPIO + description: + Physical address base for GPIO base registers. There are 8 different GPIO physical address base in mt8186. maxItems: 8 reg-names: - description: | - Gpio base register names. + description: + GPIO base register names. items: - const: iocfg0 - const: iocfg_lt @@ -60,9 +60,9 @@ properties: mediatek,rsel-resistance-in-si-unit: type: boolean - description: | - Identifying i2c pins pull up/down type which is RSEL. It can support - RSEL define or si unit value(ohm) to set different resistance. + description: + Identifying i2c pins pull up/down type which is RSEL. It can support RSEL + define or si unit value(ohm) to set different resistance. # PIN CONFIGURATION NODES patternProperties: @@ -77,8 +77,8 @@ patternProperties: A pinctrl node should contain at least one subnodes representing the pinctrl groups available on the machine. Each subnode will list the pins it needs, and how they should be configured, with regard to muxer - configuration, pullups, drive strength, input enable/disable and - input schmitt. + configuration, pullups, drive strength, input enable/disable and input + schmitt. An example of using macro: pincontroller { /* GPIO0 set as multifunction GPIO0 */ @@ -98,11 +98,10 @@ patternProperties: properties: pinmux: - description: | + description: Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and are - defined as macros in dt-bindings/pinctrl/-pinfunc.h - directly. + defined as macros in dt-bindings/pinctrl/-pinfunc.h directly. drive-strength: enum: [2, 4, 6, 8, 10, 12, 14, 16] @@ -129,10 +128,10 @@ patternProperties: For pull down type is RSEL, it can add RSEL define & resistance value(ohm) to set different resistance by identifying property "mediatek,rsel-resistance-in-si-unit". - It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" - & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" - define in mt8186. It can also support resistance value(ohm) - "75000" & "5000" in mt8186. + It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" & + "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" define in + mt8186. It can also support resistance value(ohm) "75000" & "5000" + in mt8186. An example of using RSEL define: pincontroller { i2c0_pin { @@ -174,10 +173,10 @@ patternProperties: For pull up type is RSEL, it can add RSEL define & resistance value(ohm) to set different resistance by identifying property "mediatek,rsel-resistance-in-si-unit". - It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" - & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" - define in mt8186. It can also support resistance value(ohm) - "1000" & "5000" & "10000" & "75000" in mt8186. + It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" & + "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" define in + mt8186. It can also support resistance value(ohm) "1000" & "5000" + & "10000" & "75000" in mt8186. An example of using si unit resistance value(ohm): &pio { mediatek,rsel-resistance-in-si-unit; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml index 7e750f1e643d..51b3d1247614 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml @@ -9,7 +9,7 @@ title: MediaTek MT8188 Pin Controller maintainers: - Hui Liu -description: | +description: The MediaTek's MT8188 Pin controller is used to control SoC pins. properties: @@ -19,10 +19,10 @@ properties: gpio-controller: true '#gpio-cells': - description: | - Number of cells in GPIO specifier, should be two. The first cell - is the pin number, the second cell is used to specify optional - parameters which are defined in . + description: + Number of cells in GPIO specifier, should be two. The first cell is the + pin number, the second cell is used to specify optional parameters which + are defined in . const: 2 gpio-ranges: @@ -59,10 +59,11 @@ properties: mediatek,rsel-resistance-in-si-unit: type: boolean - description: | - We provide two methods to select the resistance for I2C when pull up or pull down. - The first is by RSEL definition value, another one is by resistance value(ohm). - This flag is used to identify if the method is resistance(si unit) value. + description: + We provide two methods to select the resistance for I2C when pull up or + pull down. The first is by RSEL definition value, another one is by + resistance value(ohm). This flag is used to identify if the method is + resistance(si unit) value. # PIN CONFIGURATION NODES patternProperties: @@ -75,16 +76,16 @@ patternProperties: type: object $ref: "/schemas/pinctrl/pincfg-node.yaml" additionalProperties: false - description: | + description: A pinctrl node should contain at least one subnode representing the pinctrl groups available on the machine. Each subnode will list the pins it needs, and how they should be configured, with regard to muxer - configuration, pullups, drive strength, input enable/disable and - input schmitt. + configuration, pullups, drive strength, input enable/disable and input + schmitt. properties: pinmux: - description: | + description: Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and are defined as macros in dt-bindings/pinctrl/mediatek,-pinfunc.h @@ -106,18 +107,21 @@ patternProperties: - enum: [75000, 5000] description: mt8188 pull down RSEL type si unit value(ohm). description: | - For pull down type is normal, it doesn't need add RSEL & R1R0 define - and resistance value. + For pull down type is normal, it doesn't need add RSEL & R1R0 + define and resistance value. For pull down type is PUPD/R0/R1 type, it can add R1R0 define to set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & - "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & "MTK_PUPD_SET_R1R0_11" - define in mt8188. - For pull down type is RSEL, it can add RSEL define & resistance value(ohm) - to set different resistance by identifying property "mediatek,rsel-resistance-in-si-unit". - It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" - & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & "MTK_PULL_SET_RSEL_100" - & "MTK_PULL_SET_RSEL_101" & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" - define in mt8188. It can also support resistance value(ohm) "75000" & "5000" in mt8188. + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & + "MTK_PUPD_SET_R1R0_11" define in mt8188. + For pull down type is RSEL, it can add RSEL define & resistance + value(ohm) to set different resistance by identifying property + "mediatek,rsel-resistance-in-si-unit". It can support + "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" & + "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & + "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101" & + "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" define in + mt8188. It can also support resistance value(ohm) "75000" & "5000" + in mt8188. bias-pull-up: oneOf: @@ -131,17 +135,19 @@ patternProperties: description: | For pull up type is normal, it don't need add RSEL & R1R0 define and resistance value. - For pull up type is PUPD/R0/R1 type, it can add R1R0 define to - set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & - "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & "MTK_PUPD_SET_R1R0_11" - define in mt8188. - For pull up type is RSEL, it can add RSEL define & resistance value(ohm) - to set different resistance by identifying property "mediatek,rsel-resistance-in-si-unit". - It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" - & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & "MTK_PULL_SET_RSEL_100" - & "MTK_PULL_SET_RSEL_101" & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" - define in mt8188. It can also support resistance value(ohm) - "1000" & "1500" & "2000" & "3000" & "4000" & "5000" & "10000" & "75000" in mt8188. + For pull up type is PUPD/R0/R1 type, it can add R1R0 define to set + different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & + "MTK_PUPD_SET_R1R0_11" define in mt8188. + For pull up type is RSEL, it can add RSEL define & resistance + value(ohm) to set different resistance by identifying property + "mediatek,rsel-resistance-in-si-unit". It can support + "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" & + "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & + "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101" & + "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" define in + mt8188. It can also support resistance value(ohm) "1000" & "1500" + & "2000" & "3000" & "4000" & "5000" & "10000" & "75000" in mt8188. bias-disable: true diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml index 3c3dd142a989..8cca1ce40f25 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml @@ -9,7 +9,7 @@ title: MediaTek MT8192 Pin Controller maintainers: - Sean Wang -description: | +description: The MediaTek's MT8192 Pin controller is used to control SoC pins. properties: @@ -19,27 +19,27 @@ properties: gpio-controller: true '#gpio-cells': - description: | + description: Number of cells in GPIO specifier. Since the generic GPIO binding is used, - the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular cells. + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. const: 2 gpio-ranges: - description: gpio valid number range. + description: GPIO valid number range. maxItems: 1 gpio-line-names: true reg: - description: | - Physical address base for gpio base registers. There are 11 GPIO - physical address base in mt8192. + description: + Physical address base for GPIO base registers. There are 11 GPIO physical + address base in mt8192. maxItems: 11 reg-names: - description: | - Gpio base register names. + description: + GPIO base register names. maxItems: 11 interrupt-controller: true @@ -59,25 +59,26 @@ patternProperties: patternProperties: '^pins': type: object - description: | + description: A pinctrl node should contain at least one subnodes representing the pinctrl groups available on the machine. Each subnode will list the pins it needs, and how they should be configured, with regard to muxer - configuration, pullups, drive strength, input enable/disable and - input schmitt. + configuration, pullups, drive strength, input enable/disable and input + schmitt. $ref: "pinmux-node.yaml" properties: pinmux: - description: | + description: Integer array, represents gpio pin number and mux setting. - Supported pin number and mux varies for different SoCs, and are defined - as macros in dt-bindings/pinctrl/-pinfunc.h directly. + Supported pin number and mux varies for different SoCs, and are + defined as macros in dt-bindings/pinctrl/-pinfunc.h directly. drive-strength: - description: | - It can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See - dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10/12/14/16mA in mt8192. + description: + It can support some arguments, such as MTK_DRIVE_4mA, + MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h. It can only + support 2/4/6/8/10/12/14/16mA in mt8192. enum: [2, 4, 6, 8, 10, 12, 14, 16] drive-strength-microamp: @@ -91,8 +92,8 @@ patternProperties: description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0_ defines in dt-bindings/pinctrl/mt65xx.h. - enum: [200, 201, 202, 203] - description: RSEL pull down type. See MTK_PULL_SET_RSEL_ - defines in dt-bindings/pinctrl/mt65xx.h. + description: RSEL pull down type. See MTK_PULL_SET_RSEL_ defines + in dt-bindings/pinctrl/mt65xx.h. bias-pull-up: oneOf: @@ -102,8 +103,8 @@ patternProperties: description: PUPD/R1/R0 pull up type. See MTK_PUPD_SET_R1R0_ defines in dt-bindings/pinctrl/mt65xx.h. - enum: [200, 201, 202, 203] - description: RSEL pull up type. See MTK_PULL_SET_RSEL_ - defines in dt-bindings/pinctrl/mt65xx.h. + description: RSEL pull up type. See MTK_PULL_SET_RSEL_ defines + in dt-bindings/pinctrl/mt65xx.h. bias-disable: true diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml index d4d5357cdd1d..b8ba260d74cd 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml @@ -9,7 +9,7 @@ title: MediaTek MT8195 Pin Controller maintainers: - Sean Wang -description: | +description: The MediaTek's MT8195 Pin controller is used to control SoC pins. properties: @@ -19,27 +19,27 @@ properties: gpio-controller: true '#gpio-cells': - description: | + description: Number of cells in GPIO specifier. Since the generic GPIO binding is used, - the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular cells. + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. const: 2 gpio-ranges: - description: gpio valid number range. + description: GPIO valid number range. maxItems: 1 gpio-line-names: true reg: - description: | - Physical address base for gpio base registers. There are 8 GPIO - physical address base in mt8195. + description: + Physical address base for GPIO base registers. There are 8 GPIO physical + address base in mt8195. maxItems: 8 reg-names: - description: | - Gpio base register names. + description: + GPIO base register names. maxItems: 8 interrupt-controller: true @@ -53,9 +53,9 @@ properties: mediatek,rsel-resistance-in-si-unit: type: boolean - description: | - Identifying i2c pins pull up/down type which is RSEL. It can support - RSEL define or si unit value(ohm) to set different resistance. + description: + Identifying i2c pins pull up/down type which is RSEL. It can support RSEL + define or si unit value(ohm) to set different resistance. # PIN CONFIGURATION NODES patternProperties: @@ -70,8 +70,8 @@ patternProperties: A pinctrl node should contain at least one subnodes representing the pinctrl groups available on the machine. Each subnode will list the pins it needs, and how they should be configured, with regard to muxer - configuration, pullups, drive strength, input enable/disable and - input schmitt. + configuration, pullups, drive strength, input enable/disable and input + schmitt. An example of using macro: pincontroller { /* GPIO0 set as multifunction GPIO0 */ @@ -91,11 +91,10 @@ patternProperties: properties: pinmux: - description: | + description: Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and are - defined as macros in dt-bindings/pinctrl/-pinfunc.h - directly. + defined as macros in dt-bindings/pinctrl/-pinfunc.h directly. drive-strength: enum: [2, 4, 6, 8, 10, 12, 14, 16] @@ -174,9 +173,9 @@ patternProperties: & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101" & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" - define in mt8195. It can also support resistance value(ohm) - "1000" & "1500" & "2000" & "3000" & "4000" & "5000" & "10000" & - "75000" in mt8195. + define in mt8195. It can also support resistance value(ohm) "1000" + & "1500" & "2000" & "3000" & "4000" & "5000" & "10000" & "75000" + in mt8195. An example of using RSEL define: pincontroller { i2c0-pins { diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml index 42964dfa9fdb..5aa8ba4cb547 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml @@ -10,7 +10,7 @@ maintainers: - Zhiyong Tao - Bernhard Rosenkränzer -description: | +description: The MediaTek's MT8365 Pin controller is used to control SoC pins. properties: @@ -26,17 +26,17 @@ properties: maxItems: 1 minItems: 1 maxItems: 2 - description: | + description: Should be phandles of the syscfg node. gpio-controller: true "#gpio-cells": const: 2 - description: | - Number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular cells. + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. interrupt-controller: true @@ -54,7 +54,7 @@ patternProperties: "pins$": type: object additionalProperties: false - description: | + description: A pinctrl node should contain at least one subnode representing the pinctrl groups available on the machine. Each subnode will list the pins it needs, and how they should be configured, with regard to muxer @@ -65,14 +65,14 @@ patternProperties: properties: pinmux: description: - integer array, represents gpio pin number and mux setting. + Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and are defined as macros in -pinfunc.h directly. bias-disable: true bias-pull-up: - description: | + description: Besides generic pinconfig options, it can be used as the pull up settings for 2 pull resistors, R0 and R1. User can configure those special pins. @@ -120,7 +120,8 @@ patternProperties: mediatek,pull-up-adv: description: | Pull up setings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described as below: + configure those special pins. Valid arguments are described as + below: 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. @@ -131,7 +132,8 @@ patternProperties: mediatek,pull-down-adv: description: | Pull down settings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described as below: + configure those special pins. Valid arguments are described as + below: 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. @@ -140,14 +142,14 @@ patternProperties: enum: [0, 1, 2, 3] mediatek,tdsel: - description: | + description: An integer describing the steps for output level shifter duty cycle when asserted (high pulse width adjustment). Valid arguments are from 0 to 15. $ref: /schemas/types.yaml#/definitions/uint32 mediatek,rdsel: - description: | + description: An integer describing the steps for input level shifter duty cycle when asserted (high pulse width adjustment). Valid arguments are from 0 to 63. diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml index e51667316b2e..43b33dbf115b 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml @@ -10,7 +10,7 @@ maintainers: - Arınç ÜNAL - Sergio Paracuellos -description: +description: | Ralink RT2880 pin controller for RT2880 SoC. The pin controller can only set the muxing of pin groups. Muxing individual pins is not supported. There is no pinconf support. diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml index 23fb82f9959c..55c6f9826e76 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml @@ -10,7 +10,7 @@ maintainers: - Arınç ÜNAL - Sergio Paracuellos -description: +description: | Ralink RT305X pin controller for RT3050, RT3052, RT3350, RT3352 and RT5350 SoCs. The pin controller can only set the muxing of pin groups. Muxing individual diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml index adc4f42a175d..8d14e525b25e 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml @@ -10,7 +10,7 @@ maintainers: - Arınç ÜNAL - Sergio Paracuellos -description: +description: | Ralink RT3883 pin controller for RT3883 SoC. The pin controller can only set the muxing of pin groups. Muxing individual pins is not supported. There is no pinconf support. From patchwork Fri Mar 17 21:30:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 664644 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79E10C7618B for ; Fri, 17 Mar 2023 21:32:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230383AbjCQVcA (ORCPT ); Fri, 17 Mar 2023 17:32:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230385AbjCQVbf (ORCPT ); Fri, 17 Mar 2023 17:31:35 -0400 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC5FA2F793; Fri, 17 Mar 2023 14:31:00 -0700 (PDT) Received: by mail-ed1-x530.google.com with SMTP id cy23so25349146edb.12; Fri, 17 Mar 2023 14:31:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679088657; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=277v3QDHxGQ1e2vDSHNJ1RgrCQUtqjYsBl0P+spQaKY=; b=AKZeqzQtnCUfHf+sC2z6FujqATaMDElVe1Kb7asiqi2gApeooDYo+dvNc18Yi1rnaC 1vzmZ//1f4NHby7q8Imaq7/tO3LMrIp45cKpL2wo466wrDA7wX6rQiPdWNgztj+59QwC OgwCOtJfLbmTScN4eySQ0Uu+fGls2BB6afCCIYzyZeqaP1BwFGCe+IVy2NSdZCJnYDwv /6Q22L8kwHDYAGEj8fwePcOXZsQqI3Es/o7xX2TB7Y+W+0hgsap8voTvZt4F6vDxNpzO iV5XgWUyGF6rs4pf45z5M5Eqfa5PTm+DzXL8alzLyJsJ5pOxdfcVGWvSqa1RfmsgJCg/ PyQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679088657; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=277v3QDHxGQ1e2vDSHNJ1RgrCQUtqjYsBl0P+spQaKY=; b=qbJ4sle2ZCO3qSq2fCRX9gkmFhuEDiTJ2z2SAqmgp4EGPPjAPNpC3eBMg+vhcJWVd6 ylhAA102hMHdpBbPT02+8roy8WMydURmZYEcw+YVmD+ev8h7kWzGt5FxTRXcP1rdmWWQ RGdujb3V0PbHqp3QIA2XSZfi/ffGgVVijEwZAtJ9/9lRRBdZCnsIFh6iUj+us18G9M62 pXAOL7+Qdujf+FuGTSI0QpqrR8CJUCY0LfX68JMRSKqQcQ9IMRHU4L4iEZcBOUZwcAd6 8nzuM57CayB2+DzryuxLR7rkN8SpWVcygnvdAUbil52CrUN76MvjULS1fHSyTXXmDZa1 iZ3A== X-Gm-Message-State: AO0yUKXDIPoYpRrum6ioYnnK63IB3BfWdcqdnybhJ6rd7FMJcOjg0YZD tw39M0niCs5Z0ZEt3nZ82WU= X-Google-Smtp-Source: AK7set8J5Y0Ip/HTJOArW+lQprOCLQawHAUMxX8XoeiqqznMShgkzJGiK4AMIN4ygknSUFodhayigg== X-Received: by 2002:aa7:d6c8:0:b0:4fa:785d:121 with SMTP id x8-20020aa7d6c8000000b004fa785d0121mr4391276edr.16.1679088657090; Fri, 17 Mar 2023 14:30:57 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.30.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:30:56 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Rob Herring , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?utf-8?q?Bernhard_Rosenkr=C3=A4nze?= =?utf-8?q?r?= , Sergio Paracuellos , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 16/21] dt-bindings: pinctrl: mediatek: fix pinmux header location Date: Sat, 18 Mar 2023 00:30:06 +0300 Message-Id: <20230317213011.13656-17-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Arınç ÜNAL Fix the location of the pinmux header files mentioned on the schemas. Signed-off-by: Arınç ÜNAL Reviewed-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml | 2 +- .../devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 2 +- .../devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml index 5e80621800a9..3b3d59140073 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml @@ -90,7 +90,7 @@ patternProperties: description: Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and are - defined as macros in -pinfunc.h directly. + defined as macros in dt-bindings/pinctrl/-pinfunc.h directly. bias-disable: true diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml index 1d038f6f8971..e5e7143674b5 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -131,7 +131,7 @@ patternProperties: description: Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and are - defined as macros in boot/dts/-pinfunc.h directly. + defined as macros in dt-bindings/pinctrl/-pinfunc.h directly. bias-disable: true diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml index 51b3d1247614..028146fb173f 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml @@ -88,8 +88,8 @@ patternProperties: description: Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and are - defined as macros in dt-bindings/pinctrl/mediatek,-pinfunc.h - directly. + defined as macros in dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h + directly, for this SoC. drive-strength: enum: [2, 4, 6, 8, 10, 12, 14, 16] From patchwork Fri Mar 17 21:30:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 665079 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5EE99C6FD1D for ; Fri, 17 Mar 2023 21:32:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231256AbjCQVcB (ORCPT ); Fri, 17 Mar 2023 17:32:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230387AbjCQVbh (ORCPT ); Fri, 17 Mar 2023 17:31:37 -0400 Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8553647835; Fri, 17 Mar 2023 14:31:02 -0700 (PDT) Received: by mail-ed1-x534.google.com with SMTP id x13so25489336edd.1; Fri, 17 Mar 2023 14:31:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679088659; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IRRRjQq3YR+UffmCBrvj5g0GLFd9Ga+6nn8JCLDb/LY=; b=gd7/k2Dsv3cvSTMDoIhJiW+kYCEnvSwtq3EhasiCnlb8kdELNv3Yku+pkcoPbQW9Yv bWRTaXjlNaFwbdgalWz7ZwT/oqaLrgDVIpBHwAIhN+s5NZRo391aSb4g4X7xbgcELdrH oomojyX4lmS8BLqNcCwSHj8BzyaCXGMtFGrCtLFkhGGdwR+COApf2RVlDjLm6Pt9J2YM zGUO4GrFy4HvY/1jkaUvct3Mnwg4tHFVl39iy2pQGVjlXi0+xLQSQIxuBuKYncQoVoWV whSRoMX3RE7qckKUDUFGAW2hMgSFe3mZIQw27AuaM2Yi8bUbXHIOWLG7EVcBJ4vNaI4Q prIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679088659; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IRRRjQq3YR+UffmCBrvj5g0GLFd9Ga+6nn8JCLDb/LY=; b=Fb6CRJzzQvUu3pPZadN1wzpsGZjqDy4aLWfodAjU11zN2TSlzUQwbWGzPW797MmXhR Ac+4MJ+8KoE3deUp2LpU82+BA1GjWHwVB7LgwO0Up+wwP0K0jlK+4Vo7aRQikQQt6Ltz i0yrdeEBdVnaq8f6B7H+YxEtSnWY/XERPWfgvvhL4PASXolLTAUithpMwQfGzaAGNztr FTTGnTOEJaGFGRHzBKquzozq1jDX/KilQmc8NV26VFqbOPQbyt9OuatuDGOlChnScbu9 H1YQgsVqcxUZRkL8CxsPax1yLutFCNetwhKe2SGf3bJQ7VwrVT04NQ4d6ZlFncp9NU1o NfYQ== X-Gm-Message-State: AO0yUKUgaVTnI8vQPTW7RIKNPjojMXCOdbK7Yr82nw0SWlICKs1Ju/BB c4HUAdCFzA9CrOiIE1Qw2nU= X-Google-Smtp-Source: AK7set/wLlTE2egESzRiiLAbGob9reK+bCtPzcpYCbbRURE3vgs3lFuaz+ljmGw5GJFnbMJTZoOQsA== X-Received: by 2002:a17:906:37d4:b0:922:78e2:7680 with SMTP id o20-20020a17090637d400b0092278e27680mr797923ejc.52.1679088659557; Fri, 17 Mar 2023 14:30:59 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.30.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:30:59 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Rob Herring , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?utf-8?q?Bernhard_Rosenkr=C3=A4nze?= =?utf-8?q?r?= , Sergio Paracuellos , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 17/21] dt-bindings: pinctrl: mediatek: drop quotes from referred schemas Date: Sat, 18 Mar 2023 00:30:07 +0300 Message-Id: <20230317213011.13656-18-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Arınç ÜNAL Drop the quotes from the referred schemas. Signed-off-by: Arınç ÜNAL Reviewed-by: Rob Herring --- .../bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml | 4 ++-- .../bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 4 ++-- .../bindings/pinctrl/mediatek,mt6795-pinctrl.yaml | 4 ++-- .../bindings/pinctrl/mediatek,mt7622-pinctrl.yaml | 6 +++--- .../bindings/pinctrl/mediatek,mt7986-pinctrl.yaml | 6 +++--- .../bindings/pinctrl/mediatek,mt8183-pinctrl.yaml | 4 ++-- .../bindings/pinctrl/mediatek,mt8186-pinctrl.yaml | 2 +- .../bindings/pinctrl/mediatek,mt8188-pinctrl.yaml | 2 +- .../bindings/pinctrl/mediatek,mt8192-pinctrl.yaml | 4 ++-- .../bindings/pinctrl/mediatek,mt8195-pinctrl.yaml | 4 ++-- 10 files changed, 20 insertions(+), 20 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml index 3b3d59140073..bccff08a5ba3 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml @@ -67,7 +67,7 @@ required: - "#gpio-cells" allOf: - - $ref: "pinctrl.yaml#" + - $ref: pinctrl.yaml# patternProperties: 'pins$': @@ -83,7 +83,7 @@ patternProperties: pins it needs, and how they should be configured, with regard to muxer configuration, pullups, drive strength, input enable/disable and input schmitt. - $ref: "/schemas/pinctrl/pincfg-node.yaml" + $ref: /schemas/pinctrl/pincfg-node.yaml properties: pinmux: diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml index e5e7143674b5..7f0e2d6cd6d9 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -58,7 +58,7 @@ required: - "#gpio-cells" allOf: - - $ref: "pinctrl.yaml#" + - $ref: pinctrl.yaml# - if: properties: compatible: @@ -124,7 +124,7 @@ patternProperties: pins it needs, and how they should be configured, with regard to muxer configuration, pullups, drive strength, input enable/disable and input schmitt. - $ref: "/schemas/pinctrl/pincfg-node.yaml" + $ref: /schemas/pinctrl/pincfg-node.yaml properties: pinmux: diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml index c3bf98749fa4..601d86aecdd4 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml @@ -82,7 +82,7 @@ patternProperties: } }; }; - $ref: "pinmux-node.yaml" + $ref: pinmux-node.yaml properties: pinmux: @@ -156,7 +156,7 @@ patternProperties: - pinmux allOf: - - $ref: "pinctrl.yaml#" + - $ref: pinctrl.yaml# required: - compatible diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml index 38dc41c735eb..bd72a326e6e0 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml @@ -43,7 +43,7 @@ properties: const: 2 allOf: - - $ref: "pinctrl.yaml#" + - $ref: pinctrl.yaml# required: - compatible @@ -70,7 +70,7 @@ patternProperties: additionalProperties: false description: pinmux configuration nodes. - $ref: "/schemas/pinctrl/pinmux-node.yaml" + $ref: /schemas/pinctrl/pinmux-node.yaml properties: function: description: @@ -249,7 +249,7 @@ patternProperties: additionalProperties: false description: pinconf configuration nodes. - $ref: "/schemas/pinctrl/pincfg-node.yaml" + $ref: /schemas/pinctrl/pincfg-node.yaml properties: groups: diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml index 7157500a7f81..31c36689438c 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml @@ -57,7 +57,7 @@ properties: const: 2 allOf: - - $ref: "pinctrl.yaml#" + - $ref: pinctrl.yaml# required: - compatible @@ -128,7 +128,7 @@ patternProperties: "wf_dbdc" "wifi" 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85 - $ref: "/schemas/pinctrl/pinmux-node.yaml" + $ref: /schemas/pinctrl/pinmux-node.yaml properties: function: description: @@ -261,7 +261,7 @@ patternProperties: additionalProperties: false description: pinconf configuration nodes. - $ref: "/schemas/pinctrl/pincfg-node.yaml" + $ref: /schemas/pinctrl/pincfg-node.yaml properties: pins: diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml index 372a3aefa937..bf67d4672455 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml @@ -57,7 +57,7 @@ properties: const: 2 allOf: - - $ref: "pinctrl.yaml#" + - $ref: pinctrl.yaml# required: - compatible @@ -80,7 +80,7 @@ patternProperties: pins it needs, and how they should be configured, with regard to muxer configuration, pullups, drive strength, input enable/disable and input schmitt. - $ref: "/schemas/pinctrl/pincfg-node.yaml" + $ref: /schemas/pinctrl/pincfg-node.yaml properties: pinmux: diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml index eb6a5cdecc6c..69136ddd0bbc 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml @@ -94,7 +94,7 @@ patternProperties: } }; }; - $ref: "pinmux-node.yaml" + $ref: pinmux-node.yaml properties: pinmux: diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml index 028146fb173f..e994b0c70dbf 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml @@ -74,7 +74,7 @@ patternProperties: patternProperties: '^pins': type: object - $ref: "/schemas/pinctrl/pincfg-node.yaml" + $ref: /schemas/pinctrl/pincfg-node.yaml additionalProperties: false description: A pinctrl node should contain at least one subnode representing the diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml index 8cca1ce40f25..c43338cafd61 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml @@ -65,7 +65,7 @@ patternProperties: pins it needs, and how they should be configured, with regard to muxer configuration, pullups, drive strength, input enable/disable and input schmitt. - $ref: "pinmux-node.yaml" + $ref: pinmux-node.yaml properties: pinmux: @@ -126,7 +126,7 @@ patternProperties: additionalProperties: false allOf: - - $ref: "pinctrl.yaml#" + - $ref: pinctrl.yaml# required: - compatible diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml index b8ba260d74cd..33cb71775db9 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml @@ -87,7 +87,7 @@ patternProperties: } }; }; - $ref: "pinmux-node.yaml" + $ref: pinmux-node.yaml properties: pinmux: @@ -216,7 +216,7 @@ patternProperties: - pinmux allOf: - - $ref: "pinctrl.yaml#" + - $ref: pinctrl.yaml# required: - compatible From patchwork Fri Mar 17 21:30:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 665078 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40561C74A5B for ; Fri, 17 Mar 2023 21:32:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231207AbjCQVcQ (ORCPT ); Fri, 17 Mar 2023 17:32:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43964 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231199AbjCQVbo (ORCPT ); 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Fri, 17 Mar 2023 14:31:01 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Rob Herring , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?utf-8?q?Bernhard_Rosenkr=C3=A4nze?= =?utf-8?q?r?= , Sergio Paracuellos , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 18/21] dt-bindings: pinctrl: mediatek: mt7986: fix patternProperties regex Date: Sat, 18 Mar 2023 00:30:08 +0300 Message-Id: <20230317213011.13656-19-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Arınç ÜNAL Set second level patternProperties to '^.*mux.*$' and '^.*conf.*$' on mediatek,mt7986-pinctrl.yaml to be on par with other schemas. Signed-off-by: Arınç ÜNAL Reviewed-by: Rob Herring --- .../devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml index 31c36689438c..0f615ada290a 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml @@ -72,7 +72,7 @@ patternProperties: additionalProperties: false patternProperties: - '.*mux.*': + '^.*mux.*$': type: object additionalProperties: false description: | @@ -256,7 +256,7 @@ patternProperties: items: enum: [wf_2g, wf_5g, wf_dbdc] maxItems: 3 - '.*conf.*': + '^.*conf.*$': type: object additionalProperties: false description: From patchwork Fri Mar 17 21:30:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 664642 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4C0CC74A5B for ; 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Fri, 17 Mar 2023 14:31:04 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Rob Herring , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?utf-8?q?Bernhard_Rosenkr=C3=A4nze?= =?utf-8?q?r?= , Sergio Paracuellos , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 19/21] dt-bindings: pinctrl: ralink: rt305x: split binding Date: Sat, 18 Mar 2023 00:30:09 +0300 Message-Id: <20230317213011.13656-20-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Arınç ÜNAL The RT3352 and RT5350 SoCs each contain different pin muxing information, therefore, should be split. This can be done now that there are compatible strings to distinguish them from other SoCs. Split the schema out to ralink,rt3352-pinctrl.yaml and ralink,rt5350-pinctrl.yaml. Remove ralink,rt3352-pinctrl and ralink,rt5350-pinctrl from rt305x. Signed-off-by: Arınç ÜNAL Reviewed-by: Rob Herring --- .../pinctrl/ralink,rt305x-pinctrl.yaml | 83 +----- .../pinctrl/ralink,rt3352-pinctrl.yaml | 243 ++++++++++++++++++ .../pinctrl/ralink,rt5350-pinctrl.yaml | 206 +++++++++++++++ 3 files changed, 455 insertions(+), 77 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/ralink,rt3352-pinctrl.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/ralink,rt5350-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml index 55c6f9826e76..95a904273009 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml @@ -11,17 +11,13 @@ maintainers: - Sergio Paracuellos description: | - Ralink RT305X pin controller for RT3050, RT3052, RT3350, RT3352 and RT5350 - SoCs. + Ralink RT305X pin controller for RT3050, RT3052, and RT3350 SoCs. The pin controller can only set the muxing of pin groups. Muxing individual pins is not supported. There is no pinconf support. properties: compatible: - enum: - - ralink,rt305x-pinctrl - - ralink,rt3352-pinctrl - - ralink,rt5350-pinctrl + const: ralink,rt305x-pinctrl patternProperties: '-pins$': @@ -39,21 +35,9 @@ patternProperties: function: description: A string containing the name of the function to mux to the group. - anyOf: - - description: For RT3050, RT3052 and RT3350 SoCs - enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, mdio, - pcm gpio, pcm i2s, pcm uartf, rgmii, sdram, spi, uartf, - uartlite] - - - description: For RT3352 SoC - enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, - lna, mdio, pa, pcm gpio, pcm i2s, pcm uartf, rgmii, spi, - spi_cs1, uartf, uartlite, wdg_cs1] - - - description: For RT5350 SoC - enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, - pcm gpio, pcm i2s, pcm uartf, spi, spi_cs1, uartf, - uartlite, wdg_cs1] + enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, mdio, + pcm gpio, pcm i2s, pcm uartf, rgmii, sdram, spi, uartf, + uartlite] groups: description: @@ -72,17 +56,7 @@ patternProperties: then: properties: groups: - anyOf: - - description: For RT3050, RT3052 and RT3350 SoCs - enum: [i2c, jtag, mdio, rgmii, sdram, spi, uartf, - uartlite] - - - description: For RT3352 SoC - enum: [i2c, jtag, led, lna, mdio, pa, rgmii, spi, spi_cs1, - uartf, uartlite] - - - description: For RT5350 SoC - enum: [i2c, jtag, led, spi, spi_cs1, uartf, uartlite] + enum: [i2c, jtag, mdio, rgmii, sdram, spi, uartf, uartlite] - if: properties: @@ -129,24 +103,6 @@ patternProperties: groups: enum: [jtag] - - if: - properties: - function: - const: led - then: - properties: - groups: - enum: [led] - - - if: - properties: - function: - const: lna - then: - properties: - groups: - enum: [lna] - - if: properties: function: @@ -156,15 +112,6 @@ patternProperties: groups: enum: [mdio] - - if: - properties: - function: - const: pa - then: - properties: - groups: - enum: [pa] - - if: properties: function: @@ -219,15 +166,6 @@ patternProperties: groups: enum: [spi] - - if: - properties: - function: - const: spi_cs1 - then: - properties: - groups: - enum: [spi_cs1] - - if: properties: function: @@ -246,15 +184,6 @@ patternProperties: groups: enum: [uartlite] - - if: - properties: - function: - const: wdg_cs1 - then: - properties: - groups: - enum: [spi_cs1] - allOf: - $ref: pinctrl.yaml# diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt3352-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt3352-pinctrl.yaml new file mode 100644 index 000000000000..c9bc6cfd834c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt3352-pinctrl.yaml @@ -0,0 +1,243 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ralink,rt3352-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ralink RT3352 Pin Controller + +maintainers: + - Arınç ÜNAL + - Sergio Paracuellos + +description: | + Ralink RT3352 pin controller for RT3352 SoC. + The pin controller can only set the muxing of pin groups. Muxing individual + pins is not supported. There is no pinconf support. + +properties: + compatible: + const: ralink,rt3352-pinctrl + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^(.*-)?pinmux$': + type: object + description: node for pinctrl. + $ref: pinmux-node.yaml# + additionalProperties: false + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, lna, + mdio, pa, pcm gpio, pcm i2s, pcm uartf, rgmii, spi, spi_cs1, + uartf, uartlite, wdg_cs1] + + groups: + description: + An array of strings. Each string contains the name of a group. + maxItems: 1 + + required: + - groups + - function + + allOf: + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [i2c, jtag, led, lna, mdio, pa, rgmii, spi, spi_cs1, + uartf, uartlite] + + - if: + properties: + function: + const: gpio i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: gpio uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: i2s uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag] + + - if: + properties: + function: + const: led + then: + properties: + groups: + enum: [led] + + - if: + properties: + function: + const: lna + then: + properties: + groups: + enum: [lna] + + - if: + properties: + function: + const: mdio + then: + properties: + groups: + enum: [mdio] + + - if: + properties: + function: + const: pa + then: + properties: + groups: + enum: [pa] + + - if: + properties: + function: + const: pcm gpio + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: rgmii + then: + properties: + groups: + enum: [rgmii] + + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: spi_cs1 + then: + properties: + groups: + enum: [spi_cs1] + + - if: + properties: + function: + const: uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: uartlite + then: + properties: + groups: + enum: [uartlite] + + - if: + properties: + function: + const: wdg_cs1 + then: + properties: + groups: + enum: [spi_cs1] + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + +additionalProperties: false + +examples: + - | + pinctrl { + compatible = "ralink,rt3352-pinctrl"; + + i2c_pins: i2c0-pins { + pinmux { + groups = "i2c"; + function = "i2c"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt5350-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt5350-pinctrl.yaml new file mode 100644 index 000000000000..f248202ce866 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt5350-pinctrl.yaml @@ -0,0 +1,206 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ralink,rt5350-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ralink RT5350 Pin Controller + +maintainers: + - Arınç ÜNAL + - Sergio Paracuellos + +description: | + Ralink RT5350 pin controller for RT5350 SoC. + The pin controller can only set the muxing of pin groups. Muxing individual + pins is not supported. There is no pinconf support. + +properties: + compatible: + const: ralink,rt5350-pinctrl + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^(.*-)?pinmux$': + type: object + description: node for pinctrl. + $ref: pinmux-node.yaml# + additionalProperties: false + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, + pcm gpio, pcm i2s, pcm uartf, spi, spi_cs1, uartf, uartlite, + wdg_cs1] + + groups: + description: + An array of strings. Each string contains the name of a group. + maxItems: 1 + + required: + - groups + - function + + allOf: + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [i2c, jtag, led, spi, spi_cs1, uartf, uartlite] + + - if: + properties: + function: + const: gpio i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: gpio uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: i2s uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag] + + - if: + properties: + function: + const: led + then: + properties: + groups: + enum: [led] + + - if: + properties: + function: + const: pcm gpio + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: spi_cs1 + then: + properties: + groups: + enum: [spi_cs1] + + - if: + properties: + function: + const: uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: uartlite + then: + properties: + groups: + enum: [uartlite] + + - if: + properties: + function: + const: wdg_cs1 + then: + properties: + groups: + enum: [spi_cs1] + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + +additionalProperties: false + +examples: + - | + pinctrl { + compatible = "ralink,rt5350-pinctrl"; + + i2c_pins: i2c0-pins { + pinmux { + groups = "i2c"; + function = "i2c"; + }; + }; + }; From patchwork Fri Mar 17 21:30:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 665077 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D843C761A6 for ; Fri, 17 Mar 2023 21:32:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231293AbjCQVcU (ORCPT ); Fri, 17 Mar 2023 17:32:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44208 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231231AbjCQVbu (ORCPT ); Fri, 17 Mar 2023 17:31:50 -0400 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33488B6D3C; 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This can be done now that there are compatible strings to distinguish them from other SoCs. Split the schema out to mediatek,mt76x8-pinctrl.yaml. Remove mediatek,mt76x8-pinctrl from mt7620. Signed-off-by: Arınç ÜNAL Reviewed-by: Rob Herring --- .../pinctrl/mediatek,mt7620-pinctrl.yaml | 379 +-------------- .../pinctrl/mediatek,mt76x8-pinctrl.yaml | 450 ++++++++++++++++++ 2 files changed, 459 insertions(+), 370 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt76x8-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml index 808dd8bd276f..591bc0664ec6 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml @@ -11,15 +11,13 @@ maintainers: - Sergio Paracuellos description: | - MediaTek MT7620 pin controller for MT7620, MT7628 and MT7688 SoCs. + MediaTek MT7620 pin controller for MT7620 SoC. The pin controller can only set the muxing of pin groups. Muxing individual pins is not supported. There is no pinconf support. properties: compatible: - enum: - - ralink,mt7620-pinctrl - - ralink,mt76x8-pinctrl + const: ralink,mt7620-pinctrl patternProperties: '-pins$': @@ -37,19 +35,10 @@ patternProperties: function: description: A string containing the name of the function to mux to the group. - anyOf: - - description: For MT7620 SoC - enum: [ephy, gpio, gpio i2s, gpio uartf, i2c, i2s uartf, mdio, nand, pa, - pcie refclk, pcie rst, pcm gpio, pcm i2s, pcm uartf, refclk, - rgmii1, rgmii2, sd, spi, spi refclk, uartf, uartlite, wdt refclk, - wdt rst, wled] - - - description: For MT7628 and MT7688 SoCs - enum: [antenna, debug, gpio, i2c, i2s, jtag, p0led_an, p0led_kn, - p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, p3led_kn, - p4led_an, p4led_kn, pcie, pcm, perst, pwm, pwm0, pwm1, pwm_uart2, - refclk, rsvd, sdxc, sdxc d5 d4, sdxc d6, sdxc d7, spi, spi cs1, - spis, sw_r, uart0, uart1, uart2, utif, wdt, wled_an, wled_kn, -] + enum: [ephy, gpio, gpio i2s, gpio uartf, i2c, i2s uartf, mdio, nand, + pa, pcie refclk, pcie rst, pcm gpio, pcm i2s, pcm uartf, + refclk, rgmii1, rgmii2, sd, spi, spi refclk, uartf, uartlite, + wdt refclk, wdt rst, wled] groups: description: @@ -61,24 +50,6 @@ patternProperties: - function allOf: - - if: - properties: - function: - const: antenna - then: - properties: - groups: - enum: [i2s] - - - if: - properties: - function: - const: debug - then: - properties: - groups: - enum: [i2c] - - if: properties: function: @@ -95,17 +66,8 @@ patternProperties: then: properties: groups: - anyOf: - - description: For MT7620 SoC - enum: [ephy, i2c, mdio, nd_sd, pa, pcie, rgmii1, rgmii2, - spi, spi refclk, uartf, uartlite, wdt, wled] - - - description: For MT7628 and MT7688 SoCs - enum: [gpio, i2c, i2s, p0led_an, p0led_kn, p1led_an, - p1led_kn, p2led_an, p2led_kn, p3led_an, p3led_kn, - p4led_an, p4led_kn, perst, pwm0, pwm1, refclk, - sdmode, spi, spi cs1, spis, uart0, uart1, uart2, - wdt, wled_an, wled_kn] + enum: [ephy, i2c, mdio, nd_sd, pa, pcie, rgmii1, rgmii2, spi, + spi refclk, uartf, uartlite, wdt, wled] - if: properties: @@ -134,15 +96,6 @@ patternProperties: groups: enum: [i2c] - - if: - properties: - function: - const: i2s - then: - properties: - groups: - enum: [i2s] - - if: properties: function: @@ -152,17 +105,6 @@ patternProperties: groups: enum: [uartf] - - if: - properties: - function: - const: jtag - then: - properties: - groups: - enum: [p0led_an, p0led_kn, p1led_an, p1led_kn, p2led_an, - p2led_kn, p3led_an, p3led_kn, p4led_an, p4led_kn, - sdmode] - - if: properties: function: @@ -181,96 +123,6 @@ patternProperties: groups: enum: [nd_sd] - - if: - properties: - function: - const: p0led_an - then: - properties: - groups: - enum: [p0led_an] - - - if: - properties: - function: - const: p0led_kn - then: - properties: - groups: - enum: [p0led_kn] - - - if: - properties: - function: - const: p1led_an - then: - properties: - groups: - enum: [p1led_an] - - - if: - properties: - function: - const: p1led_kn - then: - properties: - groups: - enum: [p1led_kn] - - - if: - properties: - function: - const: p2led_an - then: - properties: - groups: - enum: [p2led_an] - - - if: - properties: - function: - const: p2led_kn - then: - properties: - groups: - enum: [p2led_kn] - - - if: - properties: - function: - const: p3led_an - then: - properties: - groups: - enum: [p3led_an] - - - if: - properties: - function: - const: p3led_kn - then: - properties: - groups: - enum: [p3led_kn] - - - if: - properties: - function: - const: p4led_an - then: - properties: - groups: - enum: [p4led_an] - - - if: - properties: - function: - const: p4led_kn - then: - properties: - groups: - enum: [p4led_kn] - - if: properties: function: @@ -280,15 +132,6 @@ patternProperties: groups: enum: [pa] - - if: - properties: - function: - const: pcie - then: - properties: - groups: - enum: [gpio] - - if: properties: function: @@ -307,15 +150,6 @@ patternProperties: groups: enum: [pcie] - - if: - properties: - function: - const: pcm - then: - properties: - groups: - enum: [i2s] - - if: properties: function: @@ -343,51 +177,6 @@ patternProperties: groups: enum: [uartf] - - if: - properties: - function: - const: perst - then: - properties: - groups: - enum: [perst] - - - if: - properties: - function: - const: pwm - then: - properties: - groups: - enum: [uart1, uart2] - - - if: - properties: - function: - const: pwm0 - then: - properties: - groups: - enum: [pwm0] - - - if: - properties: - function: - const: pwm1 - then: - properties: - groups: - enum: [pwm1] - - - if: - properties: - function: - const: pwm_uart2 - then: - properties: - groups: - enum: [spis] - - if: properties: function: @@ -395,12 +184,7 @@ patternProperties: then: properties: groups: - anyOf: - - description: For MT7620 SoC - enum: [mdio] - - - description: For MT7628 and MT7688 SoCs - enum: [gpio, refclk, spi cs1] + enum: [mdio] - if: properties: @@ -420,15 +204,6 @@ patternProperties: groups: enum: [rgmii2] - - if: - properties: - function: - const: rsvd - then: - properties: - groups: - enum: [p0led_an, p0led_kn, wled_an, wled_kn] - - if: properties: function: @@ -438,42 +213,6 @@ patternProperties: groups: enum: [nd_sd] - - if: - properties: - function: - const: sdxc - then: - properties: - groups: - enum: [sdmode] - - - if: - properties: - function: - const: sdxc d5 d4 - then: - properties: - groups: - enum: [uart2] - - - if: - properties: - function: - const: sdxc d6 - then: - properties: - groups: - enum: [pwm1] - - - if: - properties: - function: - const: sdxc d7 - then: - properties: - groups: - enum: [pwm0] - - if: properties: function: @@ -483,15 +222,6 @@ patternProperties: groups: enum: [spi] - - if: - properties: - function: - const: spi cs1 - then: - properties: - groups: - enum: [spi cs1] - - if: properties: function: @@ -501,51 +231,6 @@ patternProperties: groups: enum: [spi refclk] - - if: - properties: - function: - const: spis - then: - properties: - groups: - enum: [spis] - - - if: - properties: - function: - const: sw_r - then: - properties: - groups: - enum: [uart1] - - - if: - properties: - function: - const: uart0 - then: - properties: - groups: - enum: [uart0] - - - if: - properties: - function: - const: uart1 - then: - properties: - groups: - enum: [uart1] - - - if: - properties: - function: - const: uart2 - then: - properties: - groups: - enum: [uart2] - - if: properties: function: @@ -564,25 +249,6 @@ patternProperties: groups: enum: [uartlite] - - if: - properties: - function: - const: utif - then: - properties: - groups: - enum: [p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, - p3led_kn, p4led_an, p4led_kn, pwm0, pwm1, sdmode, spis] - - - if: - properties: - function: - const: wdt - then: - properties: - groups: - enum: [wdt] - - if: properties: function: @@ -610,33 +276,6 @@ patternProperties: groups: enum: [wled] - - if: - properties: - function: - const: wled_an - then: - properties: - groups: - enum: [wled_an] - - - if: - properties: - function: - const: wled_kn - then: - properties: - groups: - enum: [wled_kn] - - - if: - properties: - function: - const: "-" - then: - properties: - groups: - enum: [i2c, spi cs1, uart0] - allOf: - $ref: pinctrl.yaml# diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt76x8-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt76x8-pinctrl.yaml new file mode 100644 index 000000000000..31849dd5940b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt76x8-pinctrl.yaml @@ -0,0 +1,450 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt76x8-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT76X8 Pin Controller + +maintainers: + - Arınç ÜNAL + - Sergio Paracuellos + +description: | + MediaTek MT76X8 pin controller for MT7628 and MT7688 SoCs. + The pin controller can only set the muxing of pin groups. Muxing individual + pins is not supported. There is no pinconf support. + +properties: + compatible: + const: ralink,mt76x8-pinctrl + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^(.*-)?pinmux$': + type: object + description: node for pinctrl. + $ref: pinmux-node.yaml# + additionalProperties: false + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [antenna, debug, gpio, i2c, i2s, jtag, p0led_an, p0led_kn, + p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, p3led_kn, + p4led_an, p4led_kn, pcie, pcm, perst, pwm, pwm0, pwm1, + pwm_uart2, refclk, rsvd, sdxc, sdxc d5 d4, sdxc d6, sdxc d7, + spi, spi cs1, spis, sw_r, uart0, uart1, uart2, utif, wdt, + wled_an, wled_kn, -] + + groups: + description: + An array of strings. Each string contains the name of a group. + maxItems: 1 + + required: + - groups + - function + + allOf: + - if: + properties: + function: + const: antenna + then: + properties: + groups: + enum: [i2s] + + - if: + properties: + function: + const: debug + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [gpio, i2c, i2s, p0led_an, p0led_kn, p1led_an, p1led_kn, + p2led_an, p2led_kn, p3led_an, p3led_kn, p4led_an, + p4led_kn, perst, pwm0, pwm1, refclk, sdmode, spi, + spi cs1, spis, uart0, uart1, uart2, wdt, wled_an, + wled_kn] + + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: i2s + then: + properties: + groups: + enum: [i2s] + + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [p0led_an, p0led_kn, p1led_an, p1led_kn, p2led_an, + p2led_kn, p3led_an, p3led_kn, p4led_an, p4led_kn, + sdmode] + + - if: + properties: + function: + const: p0led_an + then: + properties: + groups: + enum: [p0led_an] + + - if: + properties: + function: + const: p0led_kn + then: + properties: + groups: + enum: [p0led_kn] + + - if: + properties: + function: + const: p1led_an + then: + properties: + groups: + enum: [p1led_an] + + - if: + properties: + function: + const: p1led_kn + then: + properties: + groups: + enum: [p1led_kn] + + - if: + properties: + function: + const: p2led_an + then: + properties: + groups: + enum: [p2led_an] + + - if: + properties: + function: + const: p2led_kn + then: + properties: + groups: + enum: [p2led_kn] + + - if: + properties: + function: + const: p3led_an + then: + properties: + groups: + enum: [p3led_an] + + - if: + properties: + function: + const: p3led_kn + then: + properties: + groups: + enum: [p3led_kn] + + - if: + properties: + function: + const: p4led_an + then: + properties: + groups: + enum: [p4led_an] + + - if: + properties: + function: + const: p4led_kn + then: + properties: + groups: + enum: [p4led_kn] + + - if: + properties: + function: + const: pcie + then: + properties: + groups: + enum: [gpio] + + - if: + properties: + function: + const: pcm + then: + properties: + groups: + enum: [i2s] + + - if: + properties: + function: + const: perst + then: + properties: + groups: + enum: [perst] + + - if: + properties: + function: + const: pwm + then: + properties: + groups: + enum: [uart1, uart2] + + - if: + properties: + function: + const: pwm0 + then: + properties: + groups: + enum: [pwm0] + + - if: + properties: + function: + const: pwm1 + then: + properties: + groups: + enum: [pwm1] + + - if: + properties: + function: + const: pwm_uart2 + then: + properties: + groups: + enum: [spis] + + - if: + properties: + function: + const: refclk + then: + properties: + groups: + enum: [gpio, refclk, spi cs1] + + - if: + properties: + function: + const: rsvd + then: + properties: + groups: + enum: [p0led_an, p0led_kn, wled_an, wled_kn] + + - if: + properties: + function: + const: sdxc + then: + properties: + groups: + enum: [sdmode] + + - if: + properties: + function: + const: sdxc d5 d4 + then: + properties: + groups: + enum: [uart2] + + - if: + properties: + function: + const: sdxc d6 + then: + properties: + groups: + enum: [pwm1] + + - if: + properties: + function: + const: sdxc d7 + then: + properties: + groups: + enum: [pwm0] + + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: spi cs1 + then: + properties: + groups: + enum: [spi cs1] + + - if: + properties: + function: + const: spis + then: + properties: + groups: + enum: [spis] + + - if: + properties: + function: + const: sw_r + then: + properties: + groups: + enum: [uart1] + + - if: + properties: + function: + const: uart0 + then: + properties: + groups: + enum: [uart0] + + - if: + properties: + function: + const: uart1 + then: + properties: + groups: + enum: [uart1] + + - if: + properties: + function: + const: uart2 + then: + properties: + groups: + enum: [uart2] + + - if: + properties: + function: + const: utif + then: + properties: + groups: + enum: [p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, + p3led_kn, p4led_an, p4led_kn, pwm0, pwm1, sdmode, spis] + + - if: + properties: + function: + const: wdt + then: + properties: + groups: + enum: [wdt] + + - if: + properties: + function: + const: wled_an + then: + properties: + groups: + enum: [wled_an] + + - if: + properties: + function: + const: wled_kn + then: + properties: + groups: + enum: [wled_kn] + + - if: + properties: + function: + const: "-" + then: + properties: + groups: + enum: [i2c, spi cs1, uart0] + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + +additionalProperties: false + +examples: + - | + pinctrl { + compatible = "ralink,mt76x8-pinctrl"; + + i2c_pins: i2c0-pins { + pinmux { + groups = "i2c"; + function = "i2c"; + }; + }; + }; From patchwork Fri Mar 17 21:30:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 664641 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8ECBC76195 for ; Fri, 17 Mar 2023 21:32:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231284AbjCQVcT (ORCPT ); Fri, 17 Mar 2023 17:32:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43424 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231149AbjCQVbu (ORCPT ); Fri, 17 Mar 2023 17:31:50 -0400 Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0319BE1939; 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Move the maintainer information accordingly. Add dt-binding schema files. Add linux-mediatek@lists.infradead.org as an associated mailing list. Signed-off-by: Arınç ÜNAL Acked-by: Sergio Paracuellos --- MAINTAINERS | 29 ++++++++++++++++++++++------- 1 file changed, 22 insertions(+), 7 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 6048bbe0e672..f4ee11dab1ab 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16521,6 +16521,28 @@ F: Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml F: Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml F: drivers/pinctrl/mediatek/ +PIN CONTROLLER - MEDIATEK MIPS +M: Arınç ÜNAL +M: Sergio Paracuellos +L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) +L: linux-mips@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml +F: Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl.yaml +F: Documentation/devicetree/bindings/pinctrl/mediatek,mt76x8-pinctrl.yaml +F: Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml +F: Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml +F: Documentation/devicetree/bindings/pinctrl/ralink,rt3352-pinctrl.yaml +F: Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml +F: Documentation/devicetree/bindings/pinctrl/ralink,rt5350-pinctrl.yaml +F: drivers/pinctrl/mediatek/pinctrl-mt7620.c +F: drivers/pinctrl/mediatek/pinctrl-mt7621.c +F: drivers/pinctrl/mediatek/pinctrl-mt76x8.c +F: drivers/pinctrl/mediatek/pinctrl-mtmips.* +F: drivers/pinctrl/mediatek/pinctrl-rt2880.c +F: drivers/pinctrl/mediatek/pinctrl-rt305x.c +F: drivers/pinctrl/mediatek/pinctrl-rt3883.c + PIN CONTROLLER - MICROCHIP AT91 M: Ludovic Desroches L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -17496,13 +17518,6 @@ L: linux-mips@vger.kernel.org S: Maintained F: arch/mips/boot/dts/ralink/mt7621* -RALINK PINCTRL DRIVER -M: Arınç ÜNAL -M: Sergio Paracuellos -L: linux-mips@vger.kernel.org -S: Maintained -F: drivers/pinctrl/ralink/ - RALINK RT2X00 WIRELESS LAN DRIVER M: Stanislaw Gruszka M: Helmut Schaa