From patchwork Mon May 20 08:30:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 164571 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp7819ili; Mon, 20 May 2019 01:31:29 -0700 (PDT) X-Google-Smtp-Source: APXvYqwu7W8tqWGaSTevHBHXfnBLjiMRdosA09F86HGJF4hnVI17ITaMvVg9IeAJLAJEs0ek1xIF X-Received: by 2002:a63:d615:: with SMTP id q21mr73259266pgg.401.1558341089049; Mon, 20 May 2019 01:31:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558341089; cv=none; d=google.com; s=arc-20160816; b=oqSKYt+Ftthbi4n9DdcEzpH3SaATTVUAEvr+26Gu1G2JUrj9oPTM0P3QYZS0towPYU ezHRajSAue4BXHLCMmLwePEvv9CquQ0CZRoavewVheFOwjXHfGwF4cFmVEtYoOgwJ65P RhlP5cwnhHwM8+UNPu+tzoRNAKv2hOcs1B9b6a8boy3/obEOXC/HHO0cAb61Ejtgn3h7 b/HtUY77e592BUyPb5phpqURSqFfbEIs2b2Qv0BRaod80UoWKmALT+Yn9oEvUq4L8/oC DoitdnWZ/9QqhHdQ8zJAncVhiR8BdXMCE9ttQSDVHdVWsgMpTy3CLn1pDChWYwFG9x5S mp7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=OWo8Uulihvaq9zy3I0w67p1cVDmaIdDDpV04dYtjBE8=; b=JYZsEoH8Qr9H91V9ENb4jxC+qsE6dzpd6It7HZQuhdaIW65lJJU8nxkJ0jWj+czzB+ 8g95N0mQq7q8MjjSkHyNHifIbrqkn98mQM3N8/KYVwwjLjV0GMgkGU2IJ/yRW3cRcJG6 rMd/gORoEZEDtRFVM6vvvlHMkSY/e1NR+TzymOeZrpi/+aF0hfh52XSf04sYnywvyGq4 z8oFr5GZllcoVK8G4i+lp8223/raibaxu0/dezVWqpf1s5NLp0LNPuDrmWPD/p+1FiO0 kDWZ3r3lEHCV8HI/K6VatK1zFBMKkxxTEtWF3ombjwLko0C2quxrVWyUp7aMdmz27gg9 SWMw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KyWXseoP; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f138si20401800pfa.150.2019.05.20.01.31.28; Mon, 20 May 2019 01:31:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KyWXseoP; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731166AbfETIb2 (ORCPT + 5 others); Mon, 20 May 2019 04:31:28 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:35794 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729882AbfETIb2 (ORCPT ); Mon, 20 May 2019 04:31:28 -0400 Received: by mail-pg1-f194.google.com with SMTP id t1so5022353pgc.2 for ; Mon, 20 May 2019 01:31:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OWo8Uulihvaq9zy3I0w67p1cVDmaIdDDpV04dYtjBE8=; b=KyWXseoPwNWVph/2LYqJ7XtWB++4XFV14lGAlh0XyfkDC+WFnwSAVrpHZ7LnWmVHNE /+OJJm/I2OI/6rwUZL4YNI3DV3sZnUqWe4nbib6CR3PGfaFrxtjJA+ARiJLuKXPl3Phx +IV8YI7LAA1WxsrFW7o8lOnwnfdUpYfktee+Xfhf8BFt9z9OXSsOg2OTQufei6iVkOk5 n0Hf31CIwq3xCOKdcff7Aa3ZMywrRrX0OuIoYetcoEBGCPpFNCPswN+wekoiwwKAsxbp g5VELbnAmdPMNGrjkCRCj4rg6G2ebRtzIxPjYaslK+2OBBXeC/3kod5v1EtN43HxCMJ9 oLIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OWo8Uulihvaq9zy3I0w67p1cVDmaIdDDpV04dYtjBE8=; b=GmyYaA4G5lTA3vM6Kgcuhl2ovNFkE8C1F2WdpCSnz0cs4ko7gshFCeSh2m4sw1vL6f iZhYXsbADqpGmcjR841C25Ll7UmxHcBmcuK6d4vDvRoE55IRcBHiq4tvazKLLKk5zKgq 08JODioCmocBmWcbYRLdLn3gVlOaQbwA1FKPaFyhBsI4/e4XIDK7RpEoIMEe1rvcfOkm NUEKt8lW9h2WVMzyKLRpUkvP4eafC3Y5tc2aUaw9qzoI0HgSFqc+xmD9A2xJ/5y6JY4p 2AXDDmyck9Ijav5e8dhHN2aCk4rfHb5MkPaN1Fr6jLmLkP1XSR+ttjVZEI7tT1bOBrpb ZcwA== X-Gm-Message-State: APjAAAVUT5G7YmqNdl2AKVrlBUMFYLtFrI63p6vsgttkBdaUQ5VHA+4d Uum8EK9KmLPvO+nrOcZ+hVTb X-Received: by 2002:a63:e406:: with SMTP id a6mr75142659pgi.132.1558341087636; Mon, 20 May 2019 01:31:27 -0700 (PDT) Received: from localhost.localdomain ([2405:204:7203:2717:7d22:7fdb:b76e:242c]) by smtp.gmail.com with ESMTPSA id s72sm24068220pgc.65.2019.05.20.01.31.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 20 May 2019 01:31:27 -0700 (PDT) From: Manivannan Sadhasivam To: linus.walleij@linaro.org, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, haitao.suo@bitmain.com, darren.tsao@bitmain.com, linux-gpio@vger.kernel.org, alec.lin@bitmain.com, Manivannan Sadhasivam Subject: [PATCH 2/5] arm64: dts: bitmain: Modify pin controller memory map Date: Mon, 20 May 2019 14:00:58 +0530 Message-Id: <20190520083101.10229-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190520083101.10229-1-manivannan.sadhasivam@linaro.org> References: <20190520083101.10229-1-manivannan.sadhasivam@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Earlier, the PWM registers were included as part of the pinctrl memory map, but this turned to be useless as the muxing is being handled by the SoC pin controller itself. Hence, this commit removes the pwm register mapping from the pinctrl node to make it more clean. Fixes: af2ff87de413 ("arm64: dts: bitmain: Add pinctrl support for BM1880 SoC") Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/bitmain/bm1880.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/arch/arm64/boot/dts/bitmain/bm1880.dtsi b/arch/arm64/boot/dts/bitmain/bm1880.dtsi index ee7e6abcc813..b2497a090402 100644 --- a/arch/arm64/boot/dts/bitmain/bm1880.dtsi +++ b/arch/arm64/boot/dts/bitmain/bm1880.dtsi @@ -88,9 +88,9 @@ #size-cells = <1>; ranges = <0x0 0x0 0x50010000 0x1000>; - pinctrl: pinctrl@50 { + pinctrl: pinctrl@400 { compatible = "bitmain,bm1880-pinctrl"; - reg = <0x50 0x4B0>; + reg = <0x400 0x120>; }; rst: reset-controller@c00 { From patchwork Mon May 20 08:31:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 164573 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp8021ili; Mon, 20 May 2019 01:31:40 -0700 (PDT) X-Google-Smtp-Source: APXvYqxsciazuIXy3fsGo0I4KggKMogdNUcV93RmPSPebN0pai1il/ps/ZWhI6Dh0mME4hDKkKdV X-Received: by 2002:a17:902:8f8d:: with SMTP id z13mr7126963plo.166.1558341100284; Mon, 20 May 2019 01:31:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558341100; cv=none; d=google.com; s=arc-20160816; b=pbDdrVlvPT70wK+Yl3fjWfFi921VlxlWB8soOvFNAFfueH4CgzpOvyX4UWK7rE6ksq ySBlNAGcEDo9R6aixlmPiSzqKheaSgqFEty4YEy3s4BMx3L6jiqw2bMFlEce/VUoRFj9 uNib4qH9NcGLTcXqPHVvU1EuQNhgYSazGKYy6QBc/MaDaT9fhfN7iI6UeCkOqN/A8I1p 9sWYdA0GXd3uvtUngbwenl4oTpGpIFUyFcEpqXRmfmwDoXjuE1un0PCDGc/Zp+sY8nND CrlUMF34q5NBVEtKfCTQIrsxp5LwpV3E/6tSFfs42/wPiCLc45Y+lHJBUCk0pYlNay8C k5vw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=OrAQvth9DS0BbK/1+rVAaMvZOv12ORH6Kc00AQPR8j8=; b=HimQe6kAkuWfBVxXsvMin17l3lejf4yWCbMrtVQV84gYFR65EYGyUGD7H5bELNKths cFXaLAuHA2/1xUs9bKBdfCg2unvljmv1miOlOJrABBff3uYP+X1aR8TzU7DlnhaTjr8p B5tSM+xQSiNg8oI9xxCHE1XYWwyIQRVE5uhdXJreF2AKmgqUm1ikh5xS5Yju1LoM9wVv dSqmLNE6ss7HpkXVMfEfWw2n/LxhHCcaOB+KTceTDsObdtjPhB66RoXy62UI3qfvyM4s NTyO1LDcYkDHAgRZLIlZ3Ej7e+SvcpNoXZR9madH+VM8rjwtTMzQkqM58KQNlF4dV4kF vH5g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dm6WPKZx; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t5si17258992pgf.112.2019.05.20.01.31.40; Mon, 20 May 2019 01:31:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dm6WPKZx; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730315AbfETIbj (ORCPT + 5 others); Mon, 20 May 2019 04:31:39 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:35809 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728619AbfETIbj (ORCPT ); Mon, 20 May 2019 04:31:39 -0400 Received: by mail-pg1-f194.google.com with SMTP id t1so5022575pgc.2 for ; Mon, 20 May 2019 01:31:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OrAQvth9DS0BbK/1+rVAaMvZOv12ORH6Kc00AQPR8j8=; b=dm6WPKZxmB25DrwGg++fHJm7U4ZvExHZBZbglSw4gklBHn7XmbHZWA7UhRO/EXoyj+ yVYK0JxaNy//NoByPOPnQfEzIYErYUuyDkY6JMY2G/QSE4zTSu10r0DDGslwPlyj/WbN 0jq8VTC+UPGw5vAKD//RW6rMlEBZsK0/215Ds7ewPT/vCTfNV4K3qt6zl7Ft/IKXVyfQ bMotSTi4Kb0snz8HhVPyWs/7WmOVyzZskCG/iehWSgBdHYoAaZIeS9dfGD51TZEV9KFt Kc6RsMQoTX2XSJC4zPr9f5VnZosnYQF+nUQ5NmnBTfUmMd/GZ1cB62pJaMX67wocQsu9 mNIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OrAQvth9DS0BbK/1+rVAaMvZOv12ORH6Kc00AQPR8j8=; b=L/p+IL4Om5YMb1+d05IgmKxx/RRLE6M8Wu7VR2di6cd7o6gbjfiEi1CK2HeRshftfU KTg8/sBVZaTlLMab5aOXJVLL+ySOxiDrv2plcFlvm0PgmA2Tyje0VYQTAlJupZjkZPNK LsTg3TEMuR8qUf4JFh0/32h86SZEZSG8PKTGnLgNN1+GCVtE0ix1U7x38MKa7GlAeRVx fqBdC8kZr9BuuQ4eNjpuj6MFejGPZDIaRgbH3tfuS3n0R4cMRXS6MKm096XGicY+ceZz i260Uswn2Y25I0jZN9g4el4ckG3hNX5TTTfQg7zF5PJmX+TN2WrC5kz2iZ4Sw8bFkSnb tgUQ== X-Gm-Message-State: APjAAAXxYFrjGrTjVS4Jd39M4AmYL7NSR3Ya17u0Q+wFXdvSYo0pbrVJ bu8bxlduNSbRFGcCzbYWr72k X-Received: by 2002:a65:64da:: with SMTP id t26mr74512781pgv.322.1558341098785; Mon, 20 May 2019 01:31:38 -0700 (PDT) Received: from localhost.localdomain ([2405:204:7203:2717:7d22:7fdb:b76e:242c]) by smtp.gmail.com with ESMTPSA id s72sm24068220pgc.65.2019.05.20.01.31.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 20 May 2019 01:31:38 -0700 (PDT) From: Manivannan Sadhasivam To: linus.walleij@linaro.org, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, haitao.suo@bitmain.com, darren.tsao@bitmain.com, linux-gpio@vger.kernel.org, alec.lin@bitmain.com, Manivannan Sadhasivam Subject: [PATCH 4/5] dt-bindings: pinctrl: Document pinconf bindings for BM1880 SoC Date: Mon, 20 May 2019 14:01:00 +0530 Message-Id: <20190520083101.10229-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190520083101.10229-1-manivannan.sadhasivam@linaro.org> References: <20190520083101.10229-1-manivannan.sadhasivam@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Document pinconf bindings for Bitmain BM1880 SoC. Signed-off-by: Manivannan Sadhasivam --- .../pinctrl/bitmain,bm1880-pinctrl.txt | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt index cc9a89aa4170..4eb089bcb5f3 100644 --- a/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt @@ -14,7 +14,8 @@ phrase "pin configuration node". The pin configuration nodes act as a container for an arbitrary number of subnodes. Each of these subnodes represents some desired configuration for a pin, a group, or a list of pins or groups. This configuration for BM1880 SoC -includes only pinmux as there is no pinconf support available in SoC. +includes pinmux and various pin configuration parameters, such as pull-up, +slew rate etc... Each configuration node can consist of multiple nodes describing the pinmux options. The name of each subnode is not important; all subnodes should be @@ -84,6 +85,22 @@ Required Properties: gpio66, gpio67, eth1, i2s0, i2s0_mclkin, i2s1, i2s1_mclkin, spi0 +Optional Properties: + +- bias-disable: No arguments. Disable pin bias. +- bias-pull-down: No arguments. The specified pins should be configured as + pull down. +- bias-pull-up: No arguments. The specified pins should be configured as + pull up. +- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified + pins +- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified + pins +- slew-rate: Integer. Sets slew rate for the specified pins. + Valid values are: + <0> - Slow + <1> - Fast + Example: pinctrl: pinctrl@400 { compatible = "bitmain,bm1880-pinctrl"; From patchwork Mon May 20 08:31:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 164574 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp8105ili; Mon, 20 May 2019 01:31:45 -0700 (PDT) X-Google-Smtp-Source: APXvYqygRgi+UyUO2VJUCVYF1b4hbHMuLnvGlJqk90EpyoWRfMbFnbV/UIOsDrTqSukKV+80J+R+ X-Received: by 2002:a63:7982:: with SMTP id u124mr73167536pgc.352.1558341105146; Mon, 20 May 2019 01:31:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558341105; cv=none; d=google.com; s=arc-20160816; b=vKGb44YcwUcTWWFrKvayE1lkPgffjDH9p4K7qAqNMJLVbvLF8JIQyK+P2nUXZecnF/ 9GeW4uNzlEWv1kuHXD8p15PeZVQM/PsDWuJLIQ7XRduhTTHu1vK5F+ZyZUmcKhFhKLOT hz/bFfU9oP/bFq7vvZm1DnPoqu1lPKjPYTtxv8wfU0AXVeY+fOi44UUqVFHKPlsbgygq voWfrEWMPcR/1XsvUt9YBlB6wbU3SvUoujKn4G94Zrle16G0YD97b85JThkS0b0wGvoT cuMud4rW3NwfYCfIK/ZjhC6y2sAtFq9KZnFQZ5ir+Oty3C6/+oix3qycbUrv6DNux3rd w0lA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=wZmd2sSqxBswncIP49DIhHiOiWPLqbCT+QWxEkOy/co=; b=j9S8jvb6E+usbhoI0GVm5VE+0wL5VMnb/AS1F8bg1/VcY/ikyDitUmlgxdo/eraZbG 0ESts+KzI4iVkbEZ0/JEh8uz/Yx8LvwJI+pN041g8iRrVYibi6h7gj2Rzd8oJv+xwDC3 UDsDJqHBMjU6PSOeYu6SSvsE0OJskPOyBv2bKhEZbm/0ipN8kJOMJvg0TViaAIJHroqW CFmCTfuuTZV65zkPPLoN72e+NFrYizP4WTI1VnaFsAPFQ90cFuhme3iqi8wYGAToCOA1 7kwM2vDngDpQWZjukouAV6Rjij2ErQmi5ocz8g0NfOk9/Pb/WQ713e1gUaXkW8UyZYqc O+Jg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wYliaoyk; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Pinconf support includes pin bias, slew rate and schmitt trigger. Drive strength support will be added later. Signed-off-by: Manivannan Sadhasivam --- drivers/pinctrl/pinctrl-bm1880.c | 134 +++++++++++++++++++++++++++++++ 1 file changed, 134 insertions(+) -- 2.17.1 diff --git a/drivers/pinctrl/pinctrl-bm1880.c b/drivers/pinctrl/pinctrl-bm1880.c index bddb705ea142..1aaed46d5c30 100644 --- a/drivers/pinctrl/pinctrl-bm1880.c +++ b/drivers/pinctrl/pinctrl-bm1880.c @@ -4,6 +4,8 @@ * * Copyright (c) 2019 Linaro Ltd. * Author: Manivannan Sadhasivam + * + * TODO: Drive strength support */ #include @@ -872,6 +874,137 @@ static int bm1880_pinmux_set_mux(struct pinctrl_dev *pctldev, return 0; } +#define BM1880_PINCONF(pin, idx) ((!((pin + 1) & 1) << 4) + idx) +#define BM1880_PINCONF_PULLCTRL(pin) BM1880_PINCONF(pin, 0) +#define BM1880_PINCONF_PULLUP(pin) BM1880_PINCONF(pin, 1) +#define BM1880_PINCONF_PULLDOWN(pin) BM1880_PINCONF(pin, 2) +#define BM1880_PINCONF_SCHMITT(pin) BM1880_PINCONF(pin, 9) +#define BM1880_PINCONF_SLEW(pin) BM1880_PINCONF(pin, 10) + +static int bm1880_pinconf_cfg_get(struct pinctrl_dev *pctldev, + unsigned int pin, + unsigned long *config) +{ + struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + unsigned int param = pinconf_to_config_param(*config); + unsigned int arg = 0; + u32 regval, offset, bit_offset; + + offset = (pin >> 1) << 2; + regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + offset); + + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + bit_offset = BM1880_PINCONF_PULLUP(pin); + arg = !!(regval & BIT(bit_offset)); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + bit_offset = BM1880_PINCONF_PULLDOWN(pin); + arg = !!(regval & BIT(bit_offset)); + break; + case PIN_CONFIG_BIAS_DISABLE: + bit_offset = BM1880_PINCONF_PULLCTRL(pin); + arg = !!(regval & BIT(bit_offset)); + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + bit_offset = BM1880_PINCONF_SCHMITT(pin); + arg = !!(regval & BIT(bit_offset)); + break; + case PIN_CONFIG_SLEW_RATE: + bit_offset = BM1880_PINCONF_SLEW(pin); + arg = !!(regval & BIT(bit_offset)); + break; + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int bm1880_pinconf_cfg_set(struct pinctrl_dev *pctldev, + unsigned int pin, + unsigned long *configs, + unsigned int num_configs) +{ + struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + u32 regval, offset, bit_offset; + int i; + + offset = (pin >> 1) << 2; + regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + offset); + + for (i = 0; i < num_configs; i++) { + unsigned int param = pinconf_to_config_param(configs[i]); + unsigned int arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + bit_offset = BM1880_PINCONF_PULLUP(pin); + regval |= BIT(bit_offset); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + bit_offset = BM1880_PINCONF_PULLDOWN(pin); + regval |= BIT(bit_offset); + break; + case PIN_CONFIG_BIAS_DISABLE: + bit_offset = BM1880_PINCONF_PULLCTRL(pin); + regval |= BIT(bit_offset); + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + bit_offset = BM1880_PINCONF_SCHMITT(pin); + if (arg) + regval |= BIT(bit_offset); + else + regval &= ~BIT(bit_offset); + break; + case PIN_CONFIG_SLEW_RATE: + bit_offset = BM1880_PINCONF_SLEW(pin); + if (arg) + regval |= BIT(bit_offset); + else + regval &= ~BIT(bit_offset); + break; + default: + dev_warn(pctldev->dev, + "unsupported configuration parameter '%u'\n", + param); + continue; + } + + writel_relaxed(regval, pctrl->base + BM1880_REG_MUX + offset); + } + + return 0; +} + +static int bm1880_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned long *configs, + unsigned int num_configs) +{ + int i, ret; + struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct bm1880_pctrl_group *pgrp = &pctrl->groups[selector]; + + for (i = 0; i < pgrp->npins; i++) { + ret = bm1880_pinconf_cfg_set(pctldev, pgrp->pins[i], configs, + num_configs); + if (ret) + return ret; + } + + return 0; +} + +static const struct pinconf_ops bm1880_pinconf_ops = { + .is_generic = true, + .pin_config_get = bm1880_pinconf_cfg_get, + .pin_config_set = bm1880_pinconf_cfg_set, + .pin_config_group_set = bm1880_pinconf_group_set, +}; + static const struct pinmux_ops bm1880_pinmux_ops = { .get_functions_count = bm1880_pmux_get_functions_count, .get_function_name = bm1880_pmux_get_function_name, @@ -885,6 +1018,7 @@ static struct pinctrl_desc bm1880_desc = { .npins = ARRAY_SIZE(bm1880_pins), .pctlops = &bm1880_pctrl_ops, .pmxops = &bm1880_pinmux_ops, + .confops = &bm1880_pinconf_ops, .owner = THIS_MODULE, };