From patchwork Tue Mar 21 21:56:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 665775 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7B28C76195 for ; Tue, 21 Mar 2023 21:56:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229826AbjCUV4g (ORCPT ); Tue, 21 Mar 2023 17:56:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56506 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229783AbjCUV4e (ORCPT ); Tue, 21 Mar 2023 17:56:34 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 978ED3FBAA; Tue, 21 Mar 2023 14:56:33 -0700 (PDT) Received: from localhost (unknown [188.24.179.102]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id E8FEC66030DE; Tue, 21 Mar 2023 21:56:31 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1679435792; bh=xlJOx3+BWzJjnvbq3Qx6ToCI9eSAdqOI6uhZgvbAeZo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=l0AqkVN95YJGx/ASGaao9kh++1IZeZLcCcM4JgDq7PgYErL5x0ArdP7IInpQclbkj cspW85oZgxJst126hJdzYVTuwApoSXsPlPtk0y0EQK/Hbufitiu2g6Z+w2IWiHZLiA dZ9LAEGyqKlqxkQW6joE953xgBlVA4Nc1DrMCVAnS1Kv70Hhfux+iFcVHti7oki50M 0dN6RtG8TTRFyfT1fV8ugic5scgfN95uBxkMT0ZwSM49l4ziz6qsAaPhd2eEikFd+2 Ybxhi27SL4CDyeb2BZ8YsKxECSHvxfb5oCWfkCZTzFVSXXMpqinnLhpmguE7D3YCdo I6nLVsaA9cbKw== From: Cristian Ciocaltea To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Heiko Stuebner , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Nicolas Frattaroli Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, kernel@collabora.com Subject: [PATCH v2 01/10] dt-bindings: serial: snps-dw-apb-uart: Switch dma-names order Date: Tue, 21 Mar 2023 23:56:15 +0200 Message-Id: <20230321215624.78383-2-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230321215624.78383-1-cristian.ciocaltea@collabora.com> References: <20230321215624.78383-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Commit 370f696e4474 ("dt-bindings: serial: snps-dw-apb-uart: add dma & dma-names properties") documented dma-names property to handle Allwinner D1 dtbs_check warnings, but relies on the rx->tx ordering, which is the reverse of what a different board expects: rk3326-odroid-go2.dtb: serial@ff030000: dma-names:0: 'rx' was expected A quick and incomplete check shows the inconsistency is present in many other DTS files: $ git grep -A10 snps,dw-apb-uart | grep dma-names | sort -u arch/arm64/boot/dts/rockchip/px30.dtsi- dma-names = "tx", "rx"; arch/arm64/boot/dts/rockchip/rk3328.dtsi- dma-names = "tx", "rx"; arch/arm64/boot/dts/rockchip/rk3588s.dtsi- dma-names = "tx", "rx"; arch/arm/boot/dts/rk3066a.dtsi- dma-names = "tx", "rx"; arch/arm/boot/dts/rk3128.dtsi- dma-names = "tx", "rx"; arch/arm/boot/dts/rk3288.dtsi- dma-names = "tx", "rx"; arch/arm/boot/dts/rv1126.dtsi- dma-names = "tx", "rx"; arch/arm/boot/dts/socfpga.dtsi- dma-names = "tx", "rx"; arch/arm/boot/dts/sun6i-a31.dtsi- dma-names = "rx", "tx"; arch/arm/boot/dts/sun8i-a23-a33.dtsi- dma-names = "rx", "tx"; arch/arm/boot/dts/sun8i-v3s.dtsi- dma-names = "rx", "tx"; arch/arm/boot/dts/sunxi-h3-h5.dtsi- dma-names = "rx", "tx"; arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi- dma-names = "rx", "tx"; The initial proposed solution was to allow a flexible dma-names order in the binding, due to potential ABI breakage concerns after fixing the DTS files. But luckily the Allwinner boards are not really affected, since all of them are using a shared DMA channel for rx and tx: $ git grep -A10 snps,dw-apb-uart | grep 'sun.*dmas' | sort -u arch/arm/boot/dts/sun6i-a31.dtsi- dmas = <&dma 10>, <&dma 10>; arch/arm/boot/dts/sun6i-a31.dtsi- dmas = <&dma 22>, <&dma 22>; arch/arm/boot/dts/sun6i-a31.dtsi- dmas = <&dma 6>, <&dma 6>; arch/arm/boot/dts/sun6i-a31.dtsi- dmas = <&dma 7>, <&dma 7>; arch/arm/boot/dts/sun6i-a31.dtsi- dmas = <&dma 8>, <&dma 8>; arch/arm/boot/dts/sun6i-a31.dtsi- dmas = <&dma 9>, <&dma 9>; arch/arm/boot/dts/sun8i-a23-a33.dtsi- dmas = <&dma 10>, <&dma 10>; arch/arm/boot/dts/sun8i-a23-a33.dtsi- dmas = <&dma 6>, <&dma 6>; arch/arm/boot/dts/sun8i-a23-a33.dtsi- dmas = <&dma 7>, <&dma 7>; arch/arm/boot/dts/sun8i-a23-a33.dtsi- dmas = <&dma 8>, <&dma 8>; arch/arm/boot/dts/sun8i-a23-a33.dtsi- dmas = <&dma 9>, <&dma 9>; arch/arm/boot/dts/sun8i-v3s.dtsi- dmas = <&dma 6>, <&dma 6>; arch/arm/boot/dts/sun8i-v3s.dtsi- dmas = <&dma 7>, <&dma 7>; arch/arm/boot/dts/sun8i-v3s.dtsi- dmas = <&dma 8>, <&dma 8>; arch/arm/boot/dts/sunxi-h3-h5.dtsi- dmas = <&dma 6>, <&dma 6>; arch/arm/boot/dts/sunxi-h3-h5.dtsi- dmas = <&dma 7>, <&dma 7>; arch/arm/boot/dts/sunxi-h3-h5.dtsi- dmas = <&dma 8>, <&dma 8>; arch/arm/boot/dts/sunxi-h3-h5.dtsi- dmas = <&dma 9>, <&dma 9>; arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi- dmas = <&dma 14>, <&dma 14>; arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi- dmas = <&dma 15>, <&dma 15>; arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi- dmas = <&dma 16>, <&dma 16>; arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi- dmas = <&dma 17>, <&dma 17>; arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi- dmas = <&dma 18>, <&dma 18>; arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi- dmas = <&dma 19>, <&dma 19>; Switch dma-names order to tx->rx as the first step in fixing the inconsistency. The remaining DTS fixes will be handled by separate patches. Signed-off-by: Cristian Ciocaltea Reviewed-by: Conor Dooley Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml index 2becdfab4f15..d28cc96fa8e9 100644 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -72,8 +72,8 @@ properties: dma-names: items: - - const: rx - const: tx + - const: rx snps,uart-16550-compatible: description: reflects the value of UART_16550_COMPATIBLE configuration From patchwork Tue Mar 21 21:56:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 665774 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D732C6FD1D for ; Tue, 21 Mar 2023 21:56:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229936AbjCUV4w (ORCPT ); Tue, 21 Mar 2023 17:56:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56724 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230008AbjCUV4o (ORCPT ); Tue, 21 Mar 2023 17:56:44 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 346F0532BC; Tue, 21 Mar 2023 14:56:40 -0700 (PDT) Received: from localhost (unknown [188.24.179.102]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id 962C566030E5; Tue, 21 Mar 2023 21:56:38 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1679435798; bh=JQqVAql/b8lfHBRY2dfjEmOJ6R42cKTw5nJB8IbERcE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OrWD7eS5eHKkF4roA1WuJnkTZmgbA4XGwGyshEv6hiavNLOZpgg3HnvskW1qdpVXr NlwI89bNcvHnL1AJrr1se3DO/uwwHBSvONkP3WzGUCpJa8YmJ/ctkhKKOscWbF0PjN QnEdB56yPKMyzEg2J9m/PJN40J8JsIb/QIvs3NeyGgZ+zCZbEg9bfQfjQ0JkU844jC vCnHCVngezBzfzXLWHEQU9xr7DcNWbveQVBBSPys/1QiPQGOJdi2qX0ss0uD/K7w3W 7q7TkerSbs+pDOJHUzINIDCc6Hpt4lVZW6QB+Q7BiWHq/sqwHF71cucBFFZ93HeMXT K6ntiQauyQwvg== From: Cristian Ciocaltea To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Heiko Stuebner , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Nicolas Frattaroli Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, kernel@collabora.com Subject: [PATCH v2 03/10] ARM: dts: sun8i: a23/a33: Switch dma-names order for snps,dw-apb-uart nodes Date: Tue, 21 Mar 2023 23:56:17 +0200 Message-Id: <20230321215624.78383-4-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230321215624.78383-1-cristian.ciocaltea@collabora.com> References: <20230321215624.78383-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Commit 370f696e4474 ("dt-bindings: serial: snps-dw-apb-uart: add dma & dma-names properties") documented dma-names property to handle Allwinner D1 dtbs_check warnings, but relies on the rx->tx ordering, which is the reverse of what a bunch of different boards expect. The initial proposed solution was to allow a flexible dma-names order in the binding, due to potential ABI breakage concerns after fixing the DTS files. But luckily the Allwinner boards are not affected, since they are using a shared DMA channel for rx and tx. Hence, the first step in fixing the inconsistency was to change dma-names order in the binding to tx->rx. Do the same for the snps,dw-apb-uart nodes in the DTS file. Signed-off-by: Cristian Ciocaltea Acked-by: Jernej Skrabec --- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index f630ab55bb6a..4aa9d88c9ea3 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -490,7 +490,7 @@ uart0: serial@1c28000 { clocks = <&ccu CLK_BUS_UART0>; resets = <&ccu RST_BUS_UART0>; dmas = <&dma 6>, <&dma 6>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -503,7 +503,7 @@ uart1: serial@1c28400 { clocks = <&ccu CLK_BUS_UART1>; resets = <&ccu RST_BUS_UART1>; dmas = <&dma 7>, <&dma 7>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -516,7 +516,7 @@ uart2: serial@1c28800 { clocks = <&ccu CLK_BUS_UART2>; resets = <&ccu RST_BUS_UART2>; dmas = <&dma 8>, <&dma 8>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -529,7 +529,7 @@ uart3: serial@1c28c00 { clocks = <&ccu CLK_BUS_UART3>; resets = <&ccu RST_BUS_UART3>; dmas = <&dma 9>, <&dma 9>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -542,7 +542,7 @@ uart4: serial@1c29000 { clocks = <&ccu CLK_BUS_UART4>; resets = <&ccu RST_BUS_UART4>; dmas = <&dma 10>, <&dma 10>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; From patchwork Tue Mar 21 21:56:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 665773 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFB65C6FD1D for ; Tue, 21 Mar 2023 21:57:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230146AbjCUV5z (ORCPT ); Tue, 21 Mar 2023 17:57:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58020 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230150AbjCUV5C (ORCPT ); Tue, 21 Mar 2023 17:57:02 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AEECF591F0; Tue, 21 Mar 2023 14:56:47 -0700 (PDT) Received: from localhost (unknown [188.24.179.102]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id 5EEE266030E8; Tue, 21 Mar 2023 21:56:45 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1679435805; bh=6Pn4h5hBqV5Mx/XTEaAivfDdSRY70HW5NEjSKaEvQGU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HNds7UKN7y1p2cduDi0Vgr7IKmadoc+8Hc0tJb0c79MWm7R0s4opLuHs9TwoxtAmP HqXP7iL7BftmWxaT6TpsF9TD5ivwgydc8VfBkvEE1L/e81wA8KFCM/6F7Rw7h2Ogyd PmWhAgcID/M0MILvYzd0j9JZQ81qMxKzQqVUlaxm0QwLuEn/gTH1CrN99M8cui7guQ NP1Go7ZFsn8utZZDAY8qxLf+BnWkcod2hBexQwdQaRuZamQZYlCjFIKiGROw4Szqli hZO3afvFXq2q2vaQZqbd0Ywwg+hTRgQyi4jwsaonJ9e5KPwiRgwXVJASU3LxR9LThy 977C6DdG5csAg== From: Cristian Ciocaltea To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Heiko Stuebner , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Nicolas Frattaroli Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, kernel@collabora.com Subject: [PATCH v2 05/10] ARM: dts: sunxi: h3/h5: Switch dma-names order for snps,dw-apb-uart nodes Date: Tue, 21 Mar 2023 23:56:19 +0200 Message-Id: <20230321215624.78383-6-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230321215624.78383-1-cristian.ciocaltea@collabora.com> References: <20230321215624.78383-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Commit 370f696e4474 ("dt-bindings: serial: snps-dw-apb-uart: add dma & dma-names properties") documented dma-names property to handle Allwinner D1 dtbs_check warnings, but relies on the rx->tx ordering, which is the reverse of what a bunch of different boards expect. The initial proposed solution was to allow a flexible dma-names order in the binding, due to potential ABI breakage concerns after fixing the DTS files. But luckily the Allwinner boards are not affected, since they are using a shared DMA channel for rx and tx. Hence, the first step in fixing the inconsistency was to change dma-names order in the binding to tx->rx. Do the same for the snps,dw-apb-uart nodes in the DTS file. Signed-off-by: Cristian Ciocaltea Acked-by: Jernej Skrabec --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 686193bd6bd9..ade1cd50e445 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -710,7 +710,7 @@ uart0: serial@1c28000 { clocks = <&ccu CLK_BUS_UART0>; resets = <&ccu RST_BUS_UART0>; dmas = <&dma 6>, <&dma 6>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -723,7 +723,7 @@ uart1: serial@1c28400 { clocks = <&ccu CLK_BUS_UART1>; resets = <&ccu RST_BUS_UART1>; dmas = <&dma 7>, <&dma 7>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -736,7 +736,7 @@ uart2: serial@1c28800 { clocks = <&ccu CLK_BUS_UART2>; resets = <&ccu RST_BUS_UART2>; dmas = <&dma 8>, <&dma 8>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -749,7 +749,7 @@ uart3: serial@1c28c00 { clocks = <&ccu CLK_BUS_UART3>; resets = <&ccu RST_BUS_UART3>; dmas = <&dma 9>, <&dma 9>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; From patchwork Tue Mar 21 21:56:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 665772 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57927C6FD20 for ; Tue, 21 Mar 2023 21:58:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230021AbjCUV6N (ORCPT ); Tue, 21 Mar 2023 17:58:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58482 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230026AbjCUV5L (ORCPT ); Tue, 21 Mar 2023 17:57:11 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 08CA359416; Tue, 21 Mar 2023 14:56:53 -0700 (PDT) Received: from localhost (unknown [188.24.179.102]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id DDA8A66030EC; Tue, 21 Mar 2023 21:56:51 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1679435812; bh=+MtX3jyXI+IUnWH8L4gmCzjEp2lgpmeRUn7E2R8gEZE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VzXWPHcPGumZEt6p92/sYRVKTJy7TawAlOsfr0i0+FkosNRd7SnKRt2zwb7N0Fec9 BPDfQSzTOvBEdEo3QUcQvE2hrSw4uibFWJdJMTvTzeHGxs4UCONLMvliItUwZdEDA9 fyctN2f7sTmNgBUt6mKoJ6d8wnLzx0NG2c1vRDMD8DQJ/ImgOJVn4FR9cZ+QLQf33G Gztc+a1mvtLGCNUH7IH8rHbp6D9Bgw1718z62irSyfm/DZfURKu6zESJjJMIdRtM9E rRe4Eh2/iL1X/kzWAp7H0l2W4haeQIvMRaLFTP9dxeETqJ/32kP3ZEWiDbvjiO5geY 9h43t8Wd4XMiQ== From: Cristian Ciocaltea To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Heiko Stuebner , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Nicolas Frattaroli Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, kernel@collabora.com Subject: [PATCH v2 07/10] arm64: dts: rockchip: rk3588s: Move assigned-clocks/assigned-clock-rates out of scmi Date: Tue, 21 Mar 2023 23:56:21 +0200 Message-Id: <20230321215624.78383-8-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230321215624.78383-1-cristian.ciocaltea@collabora.com> References: <20230321215624.78383-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Since commit df4fdd0db475 ("dt-bindings: firmware: arm,scmi: Restrict protocol child node properties") the following dtbs_check warning is shown: rk3588-rock-5b.dtb: scmi: protocol@14: Unevaluated properties are not allowed ('assigned-clock-rates', 'assigned-clocks' were unexpected) Since adding the missing properties to Documentation/devicetree/bindings/firmware/arm,scmi.yaml was not an acceptable solution, move them from scmi to cpu nodes. Signed-off-by: Cristian Ciocaltea --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index fca8503aed8c..24039144dfec 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -136,6 +136,8 @@ cpu_b0: cpu@400 { enable-method = "psci"; capacity-dmips-mhz = <1024>; clocks = <&scmi_clk SCMI_CLK_CPUB01>; + assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; + assigned-clock-rates = <1200000000>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <65536>; i-cache-line-size = <64>; @@ -174,6 +176,8 @@ cpu_b2: cpu@600 { enable-method = "psci"; capacity-dmips-mhz = <1024>; clocks = <&scmi_clk SCMI_CLK_CPUB23>; + assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; + assigned-clock-rates = <1200000000>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <65536>; i-cache-line-size = <64>; @@ -304,10 +308,6 @@ scmi: scmi { scmi_clk: protocol@14 { reg = <0x14>; - assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>, - <&scmi_clk SCMI_CLK_CPUB23>; - assigned-clock-rates = <1200000000>, - <1200000000>; #clock-cells = <1>; }; From patchwork Tue Mar 21 21:56:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 665771 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ADE81C761A6 for ; Tue, 21 Mar 2023 21:58:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230301AbjCUV6g (ORCPT ); Tue, 21 Mar 2023 17:58:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58058 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229995AbjCUV55 (ORCPT ); Tue, 21 Mar 2023 17:57:57 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 08CA859433; Tue, 21 Mar 2023 14:57:00 -0700 (PDT) Received: from localhost (unknown [188.24.179.102]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id 0F1E266030EE; Tue, 21 Mar 2023 21:56:59 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1679435819; bh=VEHW/c/2s4Nzddue0SQRQN8yI6FlgApEF6XFoJ9BplU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YHikRZMkteArmXf+6j+Pv+yyRFh6kTGWLU14uJXvbGqwk9ak6k/qAp0oWm2DLoU/U 8InnJQRHA5oiDb2hB6mg3LC0xrx8uHHJnSAG7fM9l2yf27di8fe6PCG+uPoBt+VjXt aGwM/tHVP48G9ppE97w2xu9/tJCG5S/0KbLUNMSUS/dc7fhbAXXHnqRqfCE+NeRilc 0egSiQtMWrSug3p6oVjYDwaDXA9iTAv3ZCWaNmoiorMceAmj1Kxf/qC7MSOI0WEKxW GMKyda18nDxGNuoLv1NeM4vu9gQfdM/G+KcwSHBQOyEUb9WG7C+t09ZqQMZ8VdN2pF n9ZJ0ThXS6Sdg== From: Cristian Ciocaltea To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Heiko Stuebner , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Nicolas Frattaroli Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, kernel@collabora.com Subject: [PATCH v2 09/10] arm64: dts: rockchip: rk3588: Add I2S nodes Date: Tue, 21 Mar 2023 23:56:23 +0200 Message-Id: <20230321215624.78383-10-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230321215624.78383-1-cristian.ciocaltea@collabora.com> References: <20230321215624.78383-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org In addition to the five I2S/PCM/TDM controllers and the two I2S/PCM controllers shared between the RK3588 and RK3588S SoCs, RK3588 provides another group of four I2S/PCM/TDM controllers. Add the DT nodes corresponding to the additional controllers. Signed-off-by: Cristian Ciocaltea --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 68 ++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi index d085e57fbc4c..8be75556af8f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -7,6 +7,74 @@ #include "rk3588-pinctrl.dtsi" / { + i2s8_8ch: i2s@fddc8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc8000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 22>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO0>; + resets = <&cru SRST_M_I2S8_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s6_8ch: i2s@fddf4000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf4000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 4>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S6_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s7_8ch: i2s@fddf8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf8000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 21>; + dma-names = "rx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S7_8CH_RX>; + reset-names = "rx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s10_8ch: i2s@fde00000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfde00000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 24>; + dma-names = "rx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S10_8CH_RX>; + reset-names = "rx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + gmac0: ethernet@fe1b0000 { compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; reg = <0x0 0xfe1b0000 0x0 0x10000>;