From patchwork Fri Mar 24 09:42:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 666708 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C84DC6FD1C for ; Fri, 24 Mar 2023 09:43:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231540AbjCXJmj (ORCPT ); Fri, 24 Mar 2023 05:42:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58072 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231857AbjCXJmU (ORCPT ); Fri, 24 Mar 2023 05:42:20 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B6BB25955; Fri, 24 Mar 2023 02:42:14 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 613086603113; Fri, 24 Mar 2023 09:42:12 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1679650933; bh=AB9OIdGkG7L+x9jKjTVnJOyjqXiyjeKHV7UwTBXh5Cc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JHgECBcLpYhbwwEFGM9QDII8gC3Sp6/OdblXdDbTzRj+x0XI+PgbWzSgOWnOMwTOM 7LZCnoeIbVCOx3aQuoohwiwbkM+VfNnvUoll/ZubFhUoYnv2s7+6pMM+7Gg9wm4LYk EX+xjJnJXZwPsgLXOQph6xOUVNSZgwoZzdAvJ4dgSejJTIg7mPg/qp+OAypOXDoST9 tbZ1q0FJkAf2zkBNens1y2JJ9c339Ahl0/qt16KBh3KuXXTvvfI/lCKSyVA5OSeoz+ tS64RkyRE0+B4lNlAoXZQq4E7rKhbuJ+cL3te5DSDjb2wlGQaMsHeaZkgRlfKSyNiN sCPf4h73Iuezw== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, amergnat@baylibre.com, flora.fu@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno Subject: [PATCH v2 2/6] soc: mediatek: pwrap: Move PMIC read test sequence in function Date: Fri, 24 Mar 2023 10:42:01 +0100 Message-Id: <20230324094205.33266-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230324094205.33266-1-angelogioacchino.delregno@collabora.com> References: <20230324094205.33266-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The PMIC read test is performed in two places: pwrap_init_dual_io() and pwrap_init_sidly(). In preparation for adding support for PMICs requiring a companion part, move this sequence to a new function pwrap_pmic_read_test(). Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-pmic-wrap.c | 32 +++++++++++++++++----------- 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c index 15789a03e6c6..5c500be48f7c 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -1455,6 +1455,18 @@ static int pwrap_regmap_write(void *context, u32 adr, u32 wdata) return pwrap_write(context, adr, wdata); } +static bool pwrap_pmic_read_test(struct pmic_wrapper *wrp, const u32 *dew_regs, + u16 read_test_val) +{ + bool is_success; + u32 rdata; + + pwrap_read(wrp, dew_regs[PWRAP_DEW_READ_TEST], &rdata); + is_success = ((rdata & U16_MAX) == read_test_val); + + return is_success; +} + static int pwrap_reset_spislave(struct pmic_wrapper *wrp) { bool tmp; @@ -1498,18 +1510,18 @@ static int pwrap_reset_spislave(struct pmic_wrapper *wrp) */ static int pwrap_init_sidly(struct pmic_wrapper *wrp) { - u32 rdata; u32 i; u32 pass = 0; + bool read_ok; signed char dly[16] = { -1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 1 }; for (i = 0; i < 4; i++) { pwrap_writel(wrp, i, PWRAP_SIDLY); - pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], - &rdata); - if (rdata == PWRAP_DEW_READ_TEST_VAL) { + read_ok = pwrap_pmic_read_test(wrp, wrp->slave->dew_regs, + PWRAP_DEW_READ_TEST_VAL); + if (read_ok) { dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i); pass |= 1 << i; } @@ -1529,8 +1541,7 @@ static int pwrap_init_sidly(struct pmic_wrapper *wrp) static int pwrap_init_dual_io(struct pmic_wrapper *wrp) { int ret; - bool tmp; - u32 rdata; + bool read_ok, tmp; /* Enable dual IO mode */ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1); @@ -1546,12 +1557,9 @@ static int pwrap_init_dual_io(struct pmic_wrapper *wrp) pwrap_writel(wrp, 1, PWRAP_DIO_EN); /* Read Test */ - pwrap_read(wrp, - wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata); - if (rdata != PWRAP_DEW_READ_TEST_VAL) { - dev_err(wrp->dev, - "Read failed on DIO mode: 0x%04x!=0x%04x\n", - PWRAP_DEW_READ_TEST_VAL, rdata); + read_ok = pwrap_pmic_read_test(wrp, wrp->slave->dew_regs, PWRAP_DEW_READ_TEST_VAL); + if (!read_ok) { + dev_err(wrp->dev, "Read failed on DIO mode.\n"); return -EFAULT; } From patchwork Fri Mar 24 09:42:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 666709 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78609C76196 for ; Fri, 24 Mar 2023 09:43:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231473AbjCXJmi (ORCPT ); Fri, 24 Mar 2023 05:42:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57886 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231869AbjCXJmW (ORCPT ); Fri, 24 Mar 2023 05:42:22 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5116112852; Fri, 24 Mar 2023 02:42:15 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 2D9EA6603114; Fri, 24 Mar 2023 09:42:13 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1679650933; bh=jE2h/ittsn0tSizCPWhMSnonPGhnh+XeahgZ0uy3c4c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iPFV21rwVMMf5SZqpzqd3iSEj9+NI3BmlLTaK4wWg8pCpUS52lpKpbJI7+al8BSXI UDTm8uCnjhWaalb0V3XWMmmt49hwiqpMP/w4YzGetYIKrHx3K7Lx5PGM+80Uel9Ly3 ro4fpUqs4SpTTat0exOqR4fM2iGAj1zpmL9bdEDCITEulwwW4PY94L8xG+Byk/ZHsi cq8d1kJ+rOWoMdiz0PyGk25mlf59HKB0KeHKgMHOfntDmb4+Xho85g0R47ZJ7CUM/4 2kSW+NKXTXbKqPQGRcrS88ppTpW332406XzKlRCZM1vybBXkn7MxfzmUy2D5pUlCGS Tt+5hX8bSIl8Q== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, amergnat@baylibre.com, flora.fu@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno Subject: [PATCH v2 3/6] soc: mediatek: pwrap: Add kerneldoc for struct pwrap_slv_type Date: Fri, 24 Mar 2023 10:42:02 +0100 Message-Id: <20230324094205.33266-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230324094205.33266-1-angelogioacchino.delregno@collabora.com> References: <20230324094205.33266-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In preparation for adding new members with name abbreviations describe the struct pwrap_slv_type with kerneldoc to enhance human readability. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-pmic-wrap.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c index 5c500be48f7c..a33a1b1820cb 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -1218,11 +1218,17 @@ struct pwrap_slv_regops { int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata); }; +/** + * struct pwrap_slv_type - PMIC device wrapper definitions + * @dew_regs: Device Wrapper (DeW) register offsets + * @type: PMIC Type (model) + * @regops: Register R/W ops + * @caps: Capability flags for the target device + */ struct pwrap_slv_type { const u32 *dew_regs; enum pmic_type type; const struct pwrap_slv_regops *regops; - /* Flags indicating the capability for the target slave */ u32 caps; }; From patchwork Fri Mar 24 09:42:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 666706 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D438C77B74 for ; Fri, 24 Mar 2023 09:43:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231730AbjCXJmm (ORCPT ); Fri, 24 Mar 2023 05:42:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231956AbjCXJm3 (ORCPT ); Fri, 24 Mar 2023 05:42:29 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 47F55E388; Fri, 24 Mar 2023 02:42:21 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id C20A16603116; Fri, 24 Mar 2023 09:42:14 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1679650935; bh=uPt2ekOUU4OrWa4bXI3WCTu8A736wA5awt8ihZXf3HM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LRt0XMYJc0tZffnjZeQrDM63d2iYy9N+K1NNJT4yjz5HIswfUyzqmH19Mw84D6RrO WrcWe4g9Yc2Y3H/RIHxKCf0rC1KGDIG5U2Edq80RF5C6bk771/AawQRGotm2ogcBDY dPGyNG6TrpfxEhOkT6bGZh6+wAjNJ3dTUNn7Kk9p/r5rpVF7k25ShPqPvRLBNANX+N 6G5REi4H2Eq27mnxj8+Y30JXYQeilbhKy5rAVf0xCapc+jU0+ptXOmyyj4/tho8R5J Lj85+gNs8YNaW1L1Mrl+TOuuWIDJNjQMb6yXP0Y1nwYZeIfw5VXYC4xXss+0BQUGuW wnIZwVhEcsf8A== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, amergnat@baylibre.com, flora.fu@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno Subject: [PATCH v2 5/6] soc: mediatek: mtk-pmic-wrap: Add support for MT6331 w/ MT6332 companion Date: Fri, 24 Mar 2023 10:42:04 +0100 Message-Id: <20230324094205.33266-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230324094205.33266-1-angelogioacchino.delregno@collabora.com> References: <20230324094205.33266-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for the MT6331 PMIC and for its companion MT6332 PMIC. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat --- drivers/soc/mediatek/mtk-pmic-wrap.c | 47 ++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c index 366e40b802e4..ceeac43f7bd1 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -170,6 +170,40 @@ static const u32 mt6323_regs[] = { [PWRAP_DEW_RDDMY_NO] = 0x01a4, }; +static const u32 mt6331_regs[] = { + [PWRAP_DEW_DIO_EN] = 0x018c, + [PWRAP_DEW_READ_TEST] = 0x018e, + [PWRAP_DEW_WRITE_TEST] = 0x0190, + [PWRAP_DEW_CRC_SWRST] = 0x0192, + [PWRAP_DEW_CRC_EN] = 0x0194, + [PWRAP_DEW_CRC_VAL] = 0x0196, + [PWRAP_DEW_MON_GRP_SEL] = 0x0198, + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x019a, + [PWRAP_DEW_CIPHER_IV_SEL] = 0x019c, + [PWRAP_DEW_CIPHER_EN] = 0x019e, + [PWRAP_DEW_CIPHER_RDY] = 0x01a0, + [PWRAP_DEW_CIPHER_MODE] = 0x01a2, + [PWRAP_DEW_CIPHER_SWRST] = 0x01a4, + [PWRAP_DEW_RDDMY_NO] = 0x01a6, +}; + +static const u32 mt6332_regs[] = { + [PWRAP_DEW_DIO_EN] = 0x80f6, + [PWRAP_DEW_READ_TEST] = 0x80f8, + [PWRAP_DEW_WRITE_TEST] = 0x80fa, + [PWRAP_DEW_CRC_SWRST] = 0x80fc, + [PWRAP_DEW_CRC_EN] = 0x80fe, + [PWRAP_DEW_CRC_VAL] = 0x8100, + [PWRAP_DEW_MON_GRP_SEL] = 0x8102, + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x8104, + [PWRAP_DEW_CIPHER_IV_SEL] = 0x8106, + [PWRAP_DEW_CIPHER_EN] = 0x8108, + [PWRAP_DEW_CIPHER_RDY] = 0x810a, + [PWRAP_DEW_CIPHER_MODE] = 0x810c, + [PWRAP_DEW_CIPHER_SWRST] = 0x810e, + [PWRAP_DEW_RDDMY_NO] = 0x8110, +}; + static const u32 mt6351_regs[] = { [PWRAP_DEW_DIO_EN] = 0x02F2, [PWRAP_DEW_READ_TEST] = 0x02F4, @@ -1182,6 +1216,8 @@ static int mt8186_regs[] = { enum pmic_type { PMIC_MT6323, + PMIC_MT6331, + PMIC_MT6332, PMIC_MT6351, PMIC_MT6357, PMIC_MT6358, @@ -2041,6 +2077,16 @@ static const struct pwrap_slv_type pmic_mt6323 = { PWRAP_SLV_CAP_SECURITY, }; +static const struct pwrap_slv_type pmic_mt6331 = { + .dew_regs = mt6331_regs, + .type = PMIC_MT6331, + .comp_dew_regs = mt6332_regs, + .comp_type = PMIC_MT6332, + .regops = &pwrap_regops16, + .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO | + PWRAP_SLV_CAP_SECURITY, +}; + static const struct pwrap_slv_type pmic_mt6351 = { .dew_regs = mt6351_regs, .type = PMIC_MT6351, @@ -2086,6 +2132,7 @@ static const struct pwrap_slv_type pmic_mt6397 = { static const struct of_device_id of_slave_match_tbl[] = { { .compatible = "mediatek,mt6323", .data = &pmic_mt6323 }, + { .compatible = "mediatek,mt6331", .data = &pmic_mt6331 }, { .compatible = "mediatek,mt6351", .data = &pmic_mt6351 }, { .compatible = "mediatek,mt6357", .data = &pmic_mt6357 }, { .compatible = "mediatek,mt6358", .data = &pmic_mt6358 }, From patchwork Fri Mar 24 09:42:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 666707 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 830ACC77B70 for ; Fri, 24 Mar 2023 09:43:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231668AbjCXJml (ORCPT ); Fri, 24 Mar 2023 05:42:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231958AbjCXJma (ORCPT ); Fri, 24 Mar 2023 05:42:30 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 48BA2132D5; Fri, 24 Mar 2023 02:42:21 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 94F0B6603118; Fri, 24 Mar 2023 09:42:15 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1679650936; bh=WdXcGK3CsaHTkqYryGIVfgOynuLMpMlln7V83aW3v68=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=D/Ns1tOEGIFCwhXfF1KaM9kjzvr1Ia5vKjoiRKGlhj50bDwcBsZNZcEcxxAsXdOsY uw7JHy/SdJO80hIi4WG0SmUvO3fGh6MmzMoX/MsqeedwgIwwCTn0JpiEw/ShrJgGbr groZT5C3ygdod8jV6RImH9Z++mHDGXRAC7olcfeSUJN5Ay0mumVGbcMs/EAHwxdoP+ lCOA3m/0Dh1P+Pb7zB9VP5ce0Sx1mr5cpcp7IChSWdO+9kp+PP1ICJvBbfmMLh62MM +bkoTLe2o7C+ilPlMU8X5ceXARoJtVm4Ty6IJvDACteuVlXwi3GhacmSSGS8vdGdKZ ylI+7ra8dI9kg== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, amergnat@baylibre.com, flora.fu@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno Subject: [PATCH v2 6/6] soc: mediatek: pwrap: Add support for MT6795 Helio X10 Date: Fri, 24 Mar 2023 10:42:05 +0100 Message-Id: <20230324094205.33266-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230324094205.33266-1-angelogioacchino.delregno@collabora.com> References: <20230324094205.33266-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the necessary bits to support the MT6795 Helio X10 smartphone SoC: this is always paired with a MT6331 PMIC, with MT6332 companion. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-pmic-wrap.c | 131 ++++++++++++++++++++++++++- 1 file changed, 130 insertions(+), 1 deletion(-) diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c index ceeac43f7bd1..20d32328382a 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -639,6 +639,91 @@ static int mt6779_regs[] = { [PWRAP_WACS2_VLDCLR] = 0xC28, }; +static int mt6795_regs[] = { + [PWRAP_MUX_SEL] = 0x0, + [PWRAP_WRAP_EN] = 0x4, + [PWRAP_DIO_EN] = 0x8, + [PWRAP_SIDLY] = 0xc, + [PWRAP_RDDMY] = 0x10, + [PWRAP_SI_CK_CON] = 0x14, + [PWRAP_CSHEXT_WRITE] = 0x18, + [PWRAP_CSHEXT_READ] = 0x1c, + [PWRAP_CSLEXT_START] = 0x20, + [PWRAP_CSLEXT_END] = 0x24, + [PWRAP_STAUPD_PRD] = 0x28, + [PWRAP_STAUPD_GRPEN] = 0x2c, + [PWRAP_EINT_STA0_ADR] = 0x30, + [PWRAP_EINT_STA1_ADR] = 0x34, + [PWRAP_STAUPD_MAN_TRIG] = 0x40, + [PWRAP_STAUPD_STA] = 0x44, + [PWRAP_WRAP_STA] = 0x48, + [PWRAP_HARB_INIT] = 0x4c, + [PWRAP_HARB_HPRIO] = 0x50, + [PWRAP_HIPRIO_ARB_EN] = 0x54, + [PWRAP_HARB_STA0] = 0x58, + [PWRAP_HARB_STA1] = 0x5c, + [PWRAP_MAN_EN] = 0x60, + [PWRAP_MAN_CMD] = 0x64, + [PWRAP_MAN_RDATA] = 0x68, + [PWRAP_MAN_VLDCLR] = 0x6c, + [PWRAP_WACS0_EN] = 0x70, + [PWRAP_INIT_DONE0] = 0x74, + [PWRAP_WACS0_CMD] = 0x78, + [PWRAP_WACS0_RDATA] = 0x7c, + [PWRAP_WACS0_VLDCLR] = 0x80, + [PWRAP_WACS1_EN] = 0x84, + [PWRAP_INIT_DONE1] = 0x88, + [PWRAP_WACS1_CMD] = 0x8c, + [PWRAP_WACS1_RDATA] = 0x90, + [PWRAP_WACS1_VLDCLR] = 0x94, + [PWRAP_WACS2_EN] = 0x98, + [PWRAP_INIT_DONE2] = 0x9c, + [PWRAP_WACS2_CMD] = 0xa0, + [PWRAP_WACS2_RDATA] = 0xa4, + [PWRAP_WACS2_VLDCLR] = 0xa8, + [PWRAP_INT_EN] = 0xac, + [PWRAP_INT_FLG_RAW] = 0xb0, + [PWRAP_INT_FLG] = 0xb4, + [PWRAP_INT_CLR] = 0xb8, + [PWRAP_SIG_ADR] = 0xbc, + [PWRAP_SIG_MODE] = 0xc0, + [PWRAP_SIG_VALUE] = 0xc4, + [PWRAP_SIG_ERRVAL] = 0xc8, + [PWRAP_CRC_EN] = 0xcc, + [PWRAP_TIMER_EN] = 0xd0, + [PWRAP_TIMER_STA] = 0xd4, + [PWRAP_WDT_UNIT] = 0xd8, + [PWRAP_WDT_SRC_EN] = 0xdc, + [PWRAP_WDT_FLG] = 0xe0, + [PWRAP_DEBUG_INT_SEL] = 0xe4, + [PWRAP_DVFS_ADR0] = 0xe8, + [PWRAP_DVFS_WDATA0] = 0xec, + [PWRAP_DVFS_ADR1] = 0xf0, + [PWRAP_DVFS_WDATA1] = 0xf4, + [PWRAP_DVFS_ADR2] = 0xf8, + [PWRAP_DVFS_WDATA2] = 0xfc, + [PWRAP_DVFS_ADR3] = 0x100, + [PWRAP_DVFS_WDATA3] = 0x104, + [PWRAP_DVFS_ADR4] = 0x108, + [PWRAP_DVFS_WDATA4] = 0x10c, + [PWRAP_DVFS_ADR5] = 0x110, + [PWRAP_DVFS_WDATA5] = 0x114, + [PWRAP_DVFS_ADR6] = 0x118, + [PWRAP_DVFS_WDATA6] = 0x11c, + [PWRAP_DVFS_ADR7] = 0x120, + [PWRAP_DVFS_WDATA7] = 0x124, + [PWRAP_SPMINF_STA] = 0x128, + [PWRAP_CIPHER_KEY_SEL] = 0x12c, + [PWRAP_CIPHER_IV_SEL] = 0x130, + [PWRAP_CIPHER_EN] = 0x134, + [PWRAP_CIPHER_RDY] = 0x138, + [PWRAP_CIPHER_MODE] = 0x13c, + [PWRAP_CIPHER_SWRST] = 0x140, + [PWRAP_DCM_EN] = 0x144, + [PWRAP_DCM_DBC_PRD] = 0x148, + [PWRAP_EXT_CK] = 0x14c, +}; + static int mt6797_regs[] = { [PWRAP_MUX_SEL] = 0x0, [PWRAP_WRAP_EN] = 0x4, @@ -1230,6 +1315,7 @@ enum pwrap_type { PWRAP_MT2701, PWRAP_MT6765, PWRAP_MT6779, + PWRAP_MT6795, PWRAP_MT6797, PWRAP_MT6873, PWRAP_MT7622, @@ -1650,6 +1736,20 @@ static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write, static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp) { switch (wrp->master->type) { + case PWRAP_MT6795: + if (wrp->slave->type == PMIC_MT6331) { + const u32 *dew_regs = wrp->slave->dew_regs; + + pwrap_write(wrp, dew_regs[PWRAP_DEW_RDDMY_NO], 0x8); + + if (wrp->slave->comp_type == PMIC_MT6332) { + dew_regs = wrp->slave->comp_dew_regs; + pwrap_write(wrp, dew_regs[PWRAP_DEW_RDDMY_NO], 0x8); + } + } + pwrap_writel(wrp, 0x88, PWRAP_RDDMY); + pwrap_init_chip_select_ext(wrp, 15, 15, 15, 15); + break; case PWRAP_MT8173: pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2); break; @@ -1744,6 +1844,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) case PWRAP_MT2701: case PWRAP_MT6765: case PWRAP_MT6779: + case PWRAP_MT6795: case PWRAP_MT6797: case PWRAP_MT8173: case PWRAP_MT8186: @@ -1914,6 +2015,19 @@ static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp) return 0; } +static int pwrap_mt6795_init_soc_specific(struct pmic_wrapper *wrp) +{ + pwrap_writel(wrp, 0xf, PWRAP_STAUPD_GRPEN); + + if (wrp->slave->type == PMIC_MT6331) + pwrap_writel(wrp, 0x1b4, PWRAP_EINT_STA0_ADR); + + if (wrp->slave->comp_type == PMIC_MT6332) + pwrap_writel(wrp, 0x8112, PWRAP_EINT_STA1_ADR); + + return 0; +} + static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp) { pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD); @@ -1949,7 +2063,8 @@ static int pwrap_init(struct pmic_wrapper *wrp) if (wrp->rstc_bridge) reset_control_reset(wrp->rstc_bridge); - if (wrp->master->type == PWRAP_MT8173) { + if (wrp->master->type == PWRAP_MT8173 || + wrp->master->type == PWRAP_MT6795) { /* Enable DCM */ pwrap_writel(wrp, 3, PWRAP_DCM_EN); pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD); @@ -2185,6 +2300,19 @@ static const struct pmic_wrapper_type pwrap_mt6779 = { .init_soc_specific = NULL, }; +static const struct pmic_wrapper_type pwrap_mt6795 = { + .regs = mt6795_regs, + .type = PWRAP_MT6795, + .arb_en_all = 0x3f, + .int_en_all = ~(u32)(BIT(31) | BIT(2) | BIT(1)), + .int1_en_all = 0, + .spi_w = PWRAP_MAN_CMD_SPI_WRITE, + .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD, + .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM, + .init_reg_clock = pwrap_common_init_reg_clock, + .init_soc_specific = pwrap_mt6795_init_soc_specific, +}; + static const struct pmic_wrapper_type pwrap_mt6797 = { .regs = mt6797_regs, .type = PWRAP_MT6797, @@ -2318,6 +2446,7 @@ static const struct of_device_id of_pwrap_match_tbl[] = { { .compatible = "mediatek,mt2701-pwrap", .data = &pwrap_mt2701 }, { .compatible = "mediatek,mt6765-pwrap", .data = &pwrap_mt6765 }, { .compatible = "mediatek,mt6779-pwrap", .data = &pwrap_mt6779 }, + { .compatible = "mediatek,mt6795-pwrap", .data = &pwrap_mt6795 }, { .compatible = "mediatek,mt6797-pwrap", .data = &pwrap_mt6797 }, { .compatible = "mediatek,mt6873-pwrap", .data = &pwrap_mt6873 }, { .compatible = "mediatek,mt7622-pwrap", .data = &pwrap_mt7622 },