From patchwork Tue May 21 15:45:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Erwan Le Ray X-Patchwork-Id: 164733 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp1768202ili; Tue, 21 May 2019 08:46:39 -0700 (PDT) X-Google-Smtp-Source: APXvYqyLJeS9f9xuIOxU4dTLU4DewDtbtSpJcoq95w0ZszmtwowVTMe/qYgFOEsYrJwJgBQrpJM2 X-Received: by 2002:a63:1344:: with SMTP id 4mr82021797pgt.448.1558453599809; Tue, 21 May 2019 08:46:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558453599; cv=none; d=google.com; s=arc-20160816; b=IHabFyUBrgrMS4N3OZ8/UIFQwrIAyxuQCCcngB6aX9wxdydyhr1edL2jAt5rytWEgb LN6axeZPCQTmsafy7Rl7NZCDXqXudSkJMKtX8bM6zDIsRQvI/PsZlZ0RgrkCa8PqJK6p uqENNorx80TBBcGaeglgTmuSLyHW+rTqCMl48L/lHYxUzIfTYhCaQ8bZOBhXeDNQSKVS suuBZTlnm7SN04bNwqkJwJcCJKiFluNNt7j+z9UM/6kNbgNYPHUU9Fp7zAPSmtJFkPgU 7DtFbl0G/p/PtDRn889dVGnjfVcGeLz5JC/kqjWodzfP93gMhrO7JLbeuybSeTcTXIF8 ETeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=dckJd0TpTuYSyAzItwV1CCOJi+gwS5cSNQ1t2XCMxko=; b=f+GWiysIkJtyhx/I4GhY2Vkbff5dmV9Z0oKwMwFGJeS0fDC3TEsmt9ethY0SvfBf1N WWu+f9d7OooFHAt1LN63X4ZZNhANeY5TIkcwKChBj7ZuBSWwYGSCApzuo9LY0+5BpIJX fcEB4ZyJcFP4OnyxAWHX381tOYug/nXQ9FmMDgYYXbUq5RPwk2VtY1YHGzIoQI+7lU3Q 42siK/iOwF0XqY+KSK2qX8Fc4VDe2b5OwjBZrQP4xVe1P/8/6Lnxk6GX7hGOcgSpQpRW JQIJZTVFR86DC4RC10hTCikTBT/0GEZRAyLPIjNeCsm2z2faEbyvBSqVu4VvZnuoNbtf gX4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@st.com header.s=STMicroelectronics header.b=TgRfIKBE; spf=pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-serial-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id co12si22260996plb.384.2019.05.21.08.46.39; Tue, 21 May 2019 08:46:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@st.com header.s=STMicroelectronics header.b=TgRfIKBE; spf=pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-serial-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728324AbfEUPqj (ORCPT + 1 other); Tue, 21 May 2019 11:46:39 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:2446 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728137AbfEUPqj (ORCPT ); Tue, 21 May 2019 11:46:39 -0400 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x4LFaPZb018181; Tue, 21 May 2019 17:46:23 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=STMicroelectronics; bh=dckJd0TpTuYSyAzItwV1CCOJi+gwS5cSNQ1t2XCMxko=; b=TgRfIKBE+t3bCcXLVaNETIeBSG0XdkKbtAnjgEyP62B3LfDR5m9VXVFFjo9GZXQ0dDQe xktcCgjoU90ckS8rhHyAIPwRStE+LGoZ3Ip//U8gzn5pQjlwd4v6+dmy7A4F8/28RxTI HamghdvFQO2cAvoI/DhPbX02e1vTnQNK9NXqtG0MOQuft7luStomJ0onOgTxVGp6ku95 kzZ5EDNeQJ0TzoqIUDjapz9N7/3wzkNlvLqrKPew8/GSSd1rO9IWdtVRf99PHp4r7Zfi MEjaI7STsaofbQo9DidmeVnQ/g5SRA0PVx7nE0kc+dpqdFrV6K2Qvj3bCo4yByZs+0Kq 9w== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2sj7742uaa-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 21 May 2019 17:46:23 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 48EDA38; Tue, 21 May 2019 15:46:22 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas22.st.com [10.75.90.92]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 2DA4F2CEA; Tue, 21 May 2019 15:46:22 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.46) by Safex1hubcas22.st.com (10.75.90.92) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 21 May 2019 17:46:22 +0200 Received: from localhost (10.201.23.31) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 21 May 2019 17:46:21 +0200 From: Erwan Le Ray To: Greg Kroah-Hartman , Jiri Slaby , Maxime Coquelin , "Alexandre Torgue" CC: , , , , "Erwan Le Ray" , Fabrice Gasnier Subject: [PATCH 1/7] serial: stm32: fix word length configuration Date: Tue, 21 May 2019 17:45:41 +0200 Message-ID: <1558453547-22866-2-git-send-email-erwan.leray@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1558453547-22866-1-git-send-email-erwan.leray@st.com> References: <1558453547-22866-1-git-send-email-erwan.leray@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.31] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-05-21_03:, , signatures=0 Sender: linux-serial-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org STM32 supports either: - 8 and 9 bits word length (including parity bit) for stm32f4 compatible devices - 7, 8 and 9 bits word length (including parity bit) for stm32f7 and stm32h7 compatible devices. As a consequence STM32 supports the following termios configurations: - CS7 with parity bit, and CS8 (with or without parity bit) for stm32f4 compatible devices. - CS6 with parity bit, CS7 and CS8 (with or without parity bit) for stm32f7 and stm32h7 compatible devices. This patch is fixing word length by configuring correctly the SoC with supported configurations. Fixes: ada8618ff3bf ("serial: stm32: adding support for stm32f7") Signed-off-by: Erwan Le Ray -- 1.9.1 diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c index e8d7a7b..e832185 100644 --- a/drivers/tty/serial/stm32-usart.c +++ b/drivers/tty/serial/stm32-usart.c @@ -599,6 +599,36 @@ static void stm32_shutdown(struct uart_port *port) free_irq(port->irq, port); } +unsigned int stm32_get_databits(struct ktermios *termios) +{ + unsigned int bits; + + tcflag_t cflag = termios->c_cflag; + + switch (cflag & CSIZE) { + /* + * CSIZE settings are not necessarily supported in hardware. + * CSIZE unsupported configurations are handled here to set word length + * to 8 bits word as default configuration and to print debug message. + */ + case CS5: + bits = 5; + break; + case CS6: + bits = 6; + break; + case CS7: + bits = 7; + break; + /* default including CS8 */ + default: + bits = 8; + break; + } + + return bits; +} + static void stm32_set_termios(struct uart_port *port, struct ktermios *termios, struct ktermios *old) { @@ -606,7 +636,7 @@ static void stm32_set_termios(struct uart_port *port, struct ktermios *termios, struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; struct stm32_usart_config *cfg = &stm32_port->info->cfg; struct serial_rs485 *rs485conf = &port->rs485; - unsigned int baud; + unsigned int baud, bits; u32 usartdiv, mantissa, fraction, oversampling; tcflag_t cflag = termios->c_cflag; u32 cr1, cr2, cr3; @@ -632,16 +662,28 @@ static void stm32_set_termios(struct uart_port *port, struct ktermios *termios, if (cflag & CSTOPB) cr2 |= USART_CR2_STOP_2B; + bits = stm32_get_databits(termios); + if (cflag & PARENB) { + bits++; cr1 |= USART_CR1_PCE; - if ((cflag & CSIZE) == CS8) { - if (cfg->has_7bits_data) - cr1 |= USART_CR1_M0; - else - cr1 |= USART_CR1_M; - } } + /* + * Word length configuration: + * CS8 + parity, 9 bits word aka [M1:M0] = 0b01 + * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10 + * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00 + * M0 and M1 already cleared by cr1 initialization. + */ + if (bits == 9) + cr1 |= USART_CR1_M0; + else if ((bits == 7) && cfg->has_7bits_data) + cr1 |= USART_CR1_M1; + else if (bits != 8) + dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" + , bits); + if (cflag & PARODD) cr1 |= USART_CR1_PS; diff --git a/drivers/tty/serial/stm32-usart.h b/drivers/tty/serial/stm32-usart.h index 6f294e2..a70aa50 100644 --- a/drivers/tty/serial/stm32-usart.h +++ b/drivers/tty/serial/stm32-usart.h @@ -151,8 +151,7 @@ struct stm32_usart_info stm32h7_info = { #define USART_CR1_PS BIT(9) #define USART_CR1_PCE BIT(10) #define USART_CR1_WAKE BIT(11) -#define USART_CR1_M BIT(12) -#define USART_CR1_M0 BIT(12) /* F7 */ +#define USART_CR1_M0 BIT(12) /* F7 (CR1_M for F4) */ #define USART_CR1_MME BIT(13) /* F7 */ #define USART_CR1_CMIE BIT(14) /* F7 */ #define USART_CR1_OVER8 BIT(15) From patchwork Tue May 21 15:45:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Erwan Le Ray X-Patchwork-Id: 164734 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp1768333ili; Tue, 21 May 2019 08:46:47 -0700 (PDT) X-Google-Smtp-Source: APXvYqymkH7oaH5qzqgXxU09uYVO5APRHQQHxLL3yXil7dXq96LvMxlI1iGD6gGusl6dLVIBEyaf X-Received: by 2002:a17:902:9693:: with SMTP id n19mr83006759plp.92.1558453607373; Tue, 21 May 2019 08:46:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558453607; cv=none; d=google.com; s=arc-20160816; b=Z1CidAhRIkQDCPBFvCS8OQ2fBZXSF0rvLrmK1pOE0VaT1xphHYypEjF1qtYzloPzfm df1U1NqxTGY3uKlm9LzqxjryAj5z2/Ydt+GOX7iwNK1KkELrkYzahZBOKfSJN2+ZXcJ1 MxxOR2bl4YcxJRvxU0X808VmCnPA7niCk77HQKR0MqtmHMzdiU86O/RaaeL6dKFxCyrt XtWnzWh55nPNH3foPcw104mC/9+8MPMeb+/MeGNkUUhZIwIC/cVNHMcejK6bbworykai tKHIBjJ+AFodzPoutlJlqYoEw3c5HmO3JHQsaCjbPlYxpw+WsDMb2I0gswL6yN7/8A/z ieuA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=rQqGqIPdtFsAv80u4VmO2si2K4Clhl1dHI+hNTrHmpo=; b=hQyxOaWxm2fDIuHf0c9J10vLsDH9VXwE+rAhHxeGK6/mzlCDO5+gO64crIIPE/r98U 1gBvSLXXpblx9vkLNuN7VbCD+15/cZGLBPGkimDQnjyjfckzSUtzYpnSkK0iRDEvB3vG NJdQyamU1EbdiA6lsrS0OeIGLSjH1rOeQCqXK04+dENHQ4vvCnJYzE6QOPtSd70cRw5N bZ4BBFomFrRvgLnl+KGJi6absNudqucnJI5AckkI/M3x9Y69ehS/k/P15mbQyPEBrL4a w3xjTV6eED9UinO6hWhK/mqDeSM/4LBw2DeMdwbM8Xek30BAHTih+VNrgV6iiXvv5nFI +U+A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@st.com header.s=STMicroelectronics header.b=Qh2BWwjH; spf=pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-serial-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u185si165404pgd.386.2019.05.21.08.46.47; Tue, 21 May 2019 08:46:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@st.com header.s=STMicroelectronics header.b=Qh2BWwjH; spf=pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-serial-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728485AbfEUPqq (ORCPT + 1 other); Tue, 21 May 2019 11:46:46 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:13220 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728183AbfEUPqq (ORCPT ); Tue, 21 May 2019 11:46:46 -0400 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x4LFaOBU018176; Tue, 21 May 2019 17:46:33 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=STMicroelectronics; bh=rQqGqIPdtFsAv80u4VmO2si2K4Clhl1dHI+hNTrHmpo=; b=Qh2BWwjHG6jwoVMC/qtzp3U8RpDMJhYm+twQBhp3KIjDOhhx1dllQ2gj4Wy6t/IOKek6 wgW/UgEzIzWmm3Q9jOtKwtrIHRB2pq4Xt9bwDbs91hGelvlGEKBsUfzZivN9MTP6LJkf 2QKkmm6gK4CNlAy7pwetdsxpA/h+gvEMx7/0B4xzvo0ogcKGo5N+IhLFwt1GgB5xx6qJ +zFP4NqCb9DK2r40f/Y5KNUqYcQuFhVThmy4JiczJRhuYq1PpqQavTk+gVwE4VlJIbZp Q5X8U++cqrw29GkR7xTQm3+EpWd9CCzVaCzKJHKxVLSK/KbkJG5uv3mckRIglFi1tvP0 LQ== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2sj7742ub0-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 21 May 2019 17:46:33 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 3F51B3D; Tue, 21 May 2019 15:46:30 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas24.st.com [10.75.90.94]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 06B902CEF; Tue, 21 May 2019 15:46:30 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.46) by Safex1hubcas24.st.com (10.75.90.94) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 21 May 2019 17:46:29 +0200 Received: from localhost (10.201.23.31) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 21 May 2019 17:46:29 +0200 From: Erwan Le Ray To: Greg Kroah-Hartman , Jiri Slaby , Maxime Coquelin , "Alexandre Torgue" CC: , , , , "Erwan Le Ray" , Fabrice Gasnier Subject: [PATCH 2/7] serial: stm32: fix rx error handling Date: Tue, 21 May 2019 17:45:42 +0200 Message-ID: <1558453547-22866-3-git-send-email-erwan.leray@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1558453547-22866-1-git-send-email-erwan.leray@st.com> References: <1558453547-22866-1-git-send-email-erwan.leray@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.31] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-05-21_03:, , signatures=0 Sender: linux-serial-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org - Fixes parity and framing error bit by clearing parity and framing error flag. The current implementation doesn't clear the error bits when an error is detected. - Fixes the incorrect name of framing error clearing flag in header file. - Fixes misalignement between data frame and errors status. The status read for "n" frame was the status of "n+1" frame". - Fixes break detection was not triggered by the expected register. Fixes: 48a6092fb41f ("serial: stm32-usart: Add STM32 USART Driver") Signed-off-by: Erwan Le Ray -- 1.9.1 diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c index e832185..f6b7393 100644 --- a/drivers/tty/serial/stm32-usart.c +++ b/drivers/tty/serial/stm32-usart.c @@ -225,35 +225,51 @@ static void stm32_receive_chars(struct uart_port *port, bool threaded) while (stm32_pending_rx(port, &sr, &stm32_port->last_res, threaded)) { sr |= USART_SR_DUMMY_RX; - c = stm32_get_char(port, &sr, &stm32_port->last_res); flag = TTY_NORMAL; - port->icount.rx++; + /* + * Status bits has to be cleared before reading the RDR: + * In FIFO mode, reading the RDR will pop the next data + * (if any) along with its status bits into the SR. + * Not doing so leads to misalignement between RDR and SR, + * and clear status bits of the next rx data. + * + * Clear errors flags for stm32f7 and stm32h7 compatible + * devices. On stm32f4 compatible devices, the error bit is + * cleared by the sequence [read SR - read DR]. + */ + if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG) + stm32_clr_bits(port, ofs->icr, USART_ICR_ORECF | + USART_ICR_PECF | USART_ICR_FECF); + + c = stm32_get_char(port, &sr, &stm32_port->last_res); + port->icount.rx++; if (sr & USART_SR_ERR_MASK) { - if (sr & USART_SR_LBD) { - port->icount.brk++; - if (uart_handle_break(port)) - continue; - } else if (sr & USART_SR_ORE) { - if (ofs->icr != UNDEF_REG) - writel_relaxed(USART_ICR_ORECF, - port->membase + - ofs->icr); + if (sr & USART_SR_ORE) { port->icount.overrun++; } else if (sr & USART_SR_PE) { port->icount.parity++; } else if (sr & USART_SR_FE) { - port->icount.frame++; + /* Break detection if character is null */ + if (!c) { + port->icount.brk++; + if (uart_handle_break(port)) + continue; + } else { + port->icount.frame++; + } } sr &= port->read_status_mask; - if (sr & USART_SR_LBD) - flag = TTY_BREAK; - else if (sr & USART_SR_PE) + if (sr & USART_SR_PE) { flag = TTY_PARITY; - else if (sr & USART_SR_FE) - flag = TTY_FRAME; + } else if (sr & USART_SR_FE) { + if (!c) + flag = TTY_BREAK; + else + flag = TTY_FRAME; + } } if (uart_handle_sysrq_char(port, c)) @@ -721,14 +737,14 @@ static void stm32_set_termios(struct uart_port *port, struct ktermios *termios, if (termios->c_iflag & INPCK) port->read_status_mask |= USART_SR_PE | USART_SR_FE; if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) - port->read_status_mask |= USART_SR_LBD; + port->read_status_mask |= USART_SR_FE; /* Characters to ignore */ port->ignore_status_mask = 0; if (termios->c_iflag & IGNPAR) port->ignore_status_mask = USART_SR_PE | USART_SR_FE; if (termios->c_iflag & IGNBRK) { - port->ignore_status_mask |= USART_SR_LBD; + port->ignore_status_mask |= USART_SR_FE; /* * If we're ignoring parity and break indicators, * ignore overruns too (for real raw support). diff --git a/drivers/tty/serial/stm32-usart.h b/drivers/tty/serial/stm32-usart.h index a70aa50..8d34802 100644 --- a/drivers/tty/serial/stm32-usart.h +++ b/drivers/tty/serial/stm32-usart.h @@ -108,7 +108,6 @@ struct stm32_usart_info stm32h7_info = { #define USART_SR_RXNE BIT(5) #define USART_SR_TC BIT(6) #define USART_SR_TXE BIT(7) -#define USART_SR_LBD BIT(8) #define USART_SR_CTSIF BIT(9) #define USART_SR_CTS BIT(10) /* F7 */ #define USART_SR_RTOF BIT(11) /* F7 */ @@ -120,8 +119,7 @@ struct stm32_usart_info stm32h7_info = { #define USART_SR_SBKF BIT(18) /* F7 */ #define USART_SR_WUF BIT(20) /* H7 */ #define USART_SR_TEACK BIT(21) /* F7 */ -#define USART_SR_ERR_MASK (USART_SR_LBD | USART_SR_ORE | \ - USART_SR_FE | USART_SR_PE) +#define USART_SR_ERR_MASK (USART_SR_ORE | USART_SR_FE | USART_SR_PE) /* Dummy bits */ #define USART_SR_DUMMY_RX BIT(16) @@ -168,8 +166,6 @@ struct stm32_usart_info stm32h7_info = { /* USART_CR2 */ #define USART_CR2_ADD_MASK GENMASK(3, 0) /* F4 */ #define USART_CR2_ADDM7 BIT(4) /* F7 */ -#define USART_CR2_LBDL BIT(5) -#define USART_CR2_LBDIE BIT(6) #define USART_CR2_LBCL BIT(8) #define USART_CR2_CPHA BIT(9) #define USART_CR2_CPOL BIT(10) @@ -226,12 +222,10 @@ struct stm32_usart_info stm32h7_info = { /* USART_ICR */ #define USART_ICR_PECF BIT(0) /* F7 */ -#define USART_ICR_FFECF BIT(1) /* F7 */ -#define USART_ICR_NCF BIT(2) /* F7 */ +#define USART_ICR_FECF BIT(1) /* F7 */ #define USART_ICR_ORECF BIT(3) /* F7 */ #define USART_ICR_IDLECF BIT(4) /* F7 */ #define USART_ICR_TCCF BIT(6) /* F7 */ -#define USART_ICR_LBDCF BIT(8) /* F7 */ #define USART_ICR_CTSCF BIT(9) /* F7 */ #define USART_ICR_RTOCF BIT(11) /* F7 */ #define USART_ICR_EOBCF BIT(12) /* F7 */ From patchwork Tue May 21 15:45:43 2019 Content-Type: text/plain; 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[209.132.180.67]) by mx.google.com with ESMTP id i12si5507406plt.287.2019.05.21.08.47.22; Tue, 21 May 2019 08:47:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@st.com header.s=STMicroelectronics header.b=OJB0s+yP; spf=pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-serial-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728316AbfEUPrW (ORCPT + 1 other); Tue, 21 May 2019 11:47:22 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:20680 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728212AbfEUPrW (ORCPT ); Tue, 21 May 2019 11:47:22 -0400 Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x4LFjw7P004981; Tue, 21 May 2019 17:46:38 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=STMicroelectronics; bh=qEx6uDe0U5ghEnBHm99gzwaV8EBDYsz7AHTItZcDFEI=; b=OJB0s+yPhWGa2riM+WQcEmikoIcHn9qFrpXobf2+XbjfYFTcePdkfELu1iPgLH9ZaEzs Wj2RvfWDFP8rMcXte8Ns5Jv0GhMtKqgikVnvH4BdePxL2yYjjOA5UTmDyXyzQmIOqu5n cZiWR9dFmn/w8u9i0RMDaLX2F5MUhN8b3KUOkottCtIMDUlR9FpTMC0ALxt/DQzXwDZl iS0O48fITRub/fbS772sR29o/SLB4bnGJbE11nYqcfDHXF9UUVMCl3ulC4pVDiEWvetk bGnf0RKE5/HYGWg9abWZEI7g6HXV3NONtyI4/WdJmXBUianUH6t9iEHK4c6N7T2Nir+0 Xw== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2sj7tu2h6r-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 21 May 2019 17:46:38 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id BEB8D3D; Tue, 21 May 2019 15:46:37 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A9A352CEA; Tue, 21 May 2019 15:46:37 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.46) by SAFEX1HUBCAS21.st.com (10.75.90.44) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 21 May 2019 17:46:37 +0200 Received: from localhost (10.201.23.31) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 21 May 2019 17:46:36 +0200 From: Erwan Le Ray To: Greg Kroah-Hartman , Jiri Slaby , Maxime Coquelin , "Alexandre Torgue" CC: , , , , "Erwan Le Ray" , Fabrice Gasnier Subject: [PATCH 3/7] serial: stm32: fix rx data length when parity enabled Date: Tue, 21 May 2019 17:45:43 +0200 Message-ID: <1558453547-22866-4-git-send-email-erwan.leray@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1558453547-22866-1-git-send-email-erwan.leray@st.com> References: <1558453547-22866-1-git-send-email-erwan.leray@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.31] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-05-21_03:, , signatures=0 Sender: linux-serial-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org - Fixes a rx data error when data length < 8 bits and parity is enabled. RDR register MSB is used for parity bit reception. - Adds a mask to ignore MSB when data is get from RDR. Fixes: 3489187204eb ("serial: stm32: adding dma support") Signed-off-by: Erwan Le Ray -- 1.9.1 diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c index f6b7393..0a7953e 100644 --- a/drivers/tty/serial/stm32-usart.c +++ b/drivers/tty/serial/stm32-usart.c @@ -194,8 +194,8 @@ static int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res, return 0; } -static unsigned long -stm32_get_char(struct uart_port *port, u32 *sr, int *last_res) +static unsigned long stm32_get_char(struct uart_port *port, u32 *sr, + int *last_res) { struct stm32_port *stm32_port = to_stm32_port(port); struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; @@ -205,10 +205,13 @@ static int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res, c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--]; if ((*last_res) == 0) *last_res = RX_BUF_L; - return c; } else { - return readl_relaxed(port->membase + ofs->rdr); + c = readl_relaxed(port->membase + ofs->rdr); + /* apply RDR data mask */ + c &= stm32_port->rdr_mask; } + + return c; } static void stm32_receive_chars(struct uart_port *port, bool threaded) @@ -679,6 +682,7 @@ static void stm32_set_termios(struct uart_port *port, struct ktermios *termios, cr2 |= USART_CR2_STOP_2B; bits = stm32_get_databits(termios); + stm32_port->rdr_mask = (BIT(bits) - 1); if (cflag & PARENB) { bits++; diff --git a/drivers/tty/serial/stm32-usart.h b/drivers/tty/serial/stm32-usart.h index 8d34802..30d2433 100644 --- a/drivers/tty/serial/stm32-usart.h +++ b/drivers/tty/serial/stm32-usart.h @@ -254,6 +254,7 @@ struct stm32_port { bool hw_flow_control; bool fifoen; int wakeirq; + int rdr_mask; /* receive data register mask */ }; static struct stm32_port stm32_ports[STM32_MAX_PORTS]; From patchwork Tue May 21 15:45:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Erwan Le Ray X-Patchwork-Id: 164735 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp1768559ili; Tue, 21 May 2019 08:47:00 -0700 (PDT) X-Google-Smtp-Source: APXvYqziLhhA0HXSAxyYVp2oPoC9rCYk1HlmYbOuxvCMik4o4P80IaIHgWd1pIWMe6bY+PjhOhP3 X-Received: by 2002:a63:c203:: with SMTP id b3mr52666861pgd.398.1558453620885; Tue, 21 May 2019 08:47:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558453620; cv=none; d=google.com; s=arc-20160816; b=O06T5qgAuSjcIYNEjB02gb3MjmIoAXHbPZOZnoxEnO5wgrbFnqfsDLfdP7v0fvhPlA Uk2PgrVd6AAI2Gexl0K8cTVVHG55sQfPVHj7SP9nUrp78nzwBPQDEwWjw/Kyx9yBFGKq SR3cu3UnPstFn/ZfpxX8tlwZq9Lw9wN4rsmoBVvLz9ddwlcvj+tZrDIign+pWcBEGqnS BohlNqezzW0Q0//6laNJnjMTTKKetpPGzVbiiuPWcKaASn+er/ZIMkqXw1Mb66LngMx5 1L3MHeNHmKw8C+2I/dVs5DN4Xl+FmQv3FV2fjRFD4Us6cCyk0AhpW6wDGpy43Pwk7omk PeQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=xrTHJ0r+41B9UrJgw1m/5JY+7XA7C34gtShA4N4DL9w=; b=ahDiW3bEYk2SN8101YDTsTSMaEsurI/x8i2ioY+0kdiT+rTmEihmbHNcSIc3tEnRQJ UyXZTwAgglpMlsMasALZZqJzDNnp1unhDJ64SiIaEr2GMuWDG2D+jSCb3iF490M6mTDG VXk4XD5o8Kxw0GzRen6wqFFhskOQv5hExhjAPv2DYRMA8LjLjwWa0ZjBhK+VIqqWu8jw 43/c7eTmFDIvWwPXKvOEQpgrM+BB8B3g3UZSI0stS5w9uMKXRUHxldDM0ipv4jOPmX4N v2VaHA3yC7Hu+GIatEMtxCcRnlEXgWE9PhdKT0gv1y8MNC2t8TCE13SEJQclw7/ED/v/ Gj8g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@st.com header.s=STMicroelectronics header.b="LD3+dh/2"; spf=pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-serial-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n33si16140232pgl.403.2019.05.21.08.47.00; Tue, 21 May 2019 08:47:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@st.com header.s=STMicroelectronics header.b="LD3+dh/2"; spf=pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-serial-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728882AbfEUPrA (ORCPT + 1 other); Tue, 21 May 2019 11:47:00 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:20724 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728183AbfEUPrA (ORCPT ); Tue, 21 May 2019 11:47:00 -0400 Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x4LFk1Hs004995; Tue, 21 May 2019 17:46:42 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=STMicroelectronics; bh=xrTHJ0r+41B9UrJgw1m/5JY+7XA7C34gtShA4N4DL9w=; b=LD3+dh/2tOz4V3p4dxXNTMik4VHrbynG3K0V2a7YfkJm9RB6f4hEvy083hEsXEKlSwEr MlfKX1Ef4B6lfoFoiIBIN/ZJNThNkEwShD9jTJT2xiScWu0GxAD+4U/oXTl0igBprNXg T7X1iWvWmOt7BQXfi+zMfl7JwyMbp4PGUHhLGyqWGDITLT8knrlsOExjLe/jqP7p95wF KF0nnOJ1Mn0WHkqbEH9ZQGIrZw6XXd2u6VRpoZddqBZRWlBTn0JGulgeXQbsbc4Ye4or Xgt+QhX7CgPX6McyGcXzn98YPjATOmYLTEZcikq+4lQbxsm2WEpIYJr0ww5y54g5Gojn jA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2sj7tu2h74-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 21 May 2019 17:46:42 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A517B38; Tue, 21 May 2019 15:46:41 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas22.st.com [10.75.90.92]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 5F4592CEA; Tue, 21 May 2019 15:46:41 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.46) by Safex1hubcas22.st.com (10.75.90.92) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 21 May 2019 17:46:41 +0200 Received: from localhost (10.201.23.31) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 21 May 2019 17:46:40 +0200 From: Erwan Le Ray To: Greg Kroah-Hartman , Jiri Slaby , Maxime Coquelin , "Alexandre Torgue" CC: , , , , "Erwan Le Ray" , Fabrice Gasnier Subject: [PATCH 5/7] serial: stm32: Add support of TC bit status check Date: Tue, 21 May 2019 17:45:45 +0200 Message-ID: <1558453547-22866-6-git-send-email-erwan.leray@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1558453547-22866-1-git-send-email-erwan.leray@st.com> References: <1558453547-22866-1-git-send-email-erwan.leray@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.31] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-05-21_03:, , signatures=0 Sender: linux-serial-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Adds a check on the Transmission Complete bit status before closing the com port. Prevents the port closure before the end of the transmission. TC poll loop is moved from stm32_tx_dma_complete to stm32_shutdown routine, in order to check TC before shutdown in both dma and PIO tx modes. TC clear is added in stm32_transmit_char routine, in order to be cleared before transmitting in both dma and PIO tx modes. Fixes: 3489187204eb ("serial: stm32: adding dma support") Signed-off-by: Erwan Le Ray -- 1.9.1 diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c index 2e7757d..d603be9 100644 --- a/drivers/tty/serial/stm32-usart.c +++ b/drivers/tty/serial/stm32-usart.c @@ -290,21 +290,6 @@ static void stm32_tx_dma_complete(void *arg) struct uart_port *port = arg; struct stm32_port *stm32port = to_stm32_port(port); struct stm32_usart_offsets *ofs = &stm32port->info->ofs; - unsigned int isr; - int ret; - - ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, - isr, - (isr & USART_SR_TC), - 10, 100000); - - if (ret) - dev_err(port->dev, "terminal count not set\n"); - - if (ofs->icr == UNDEF_REG) - stm32_clr_bits(port, ofs->isr, USART_SR_TC); - else - stm32_set_bits(port, ofs->icr, USART_CR_TC); stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); stm32port->tx_dma_busy = false; @@ -396,7 +381,6 @@ static void stm32_transmit_chars_dma(struct uart_port *port) /* Issue pending DMA TX requests */ dma_async_issue_pending(stm32port->tx_ch); - stm32_clr_bits(port, ofs->isr, USART_SR_TC); stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT); xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); @@ -425,6 +409,11 @@ static void stm32_transmit_chars(struct uart_port *port) return; } + if (ofs->icr == UNDEF_REG) + stm32_clr_bits(port, ofs->isr, USART_SR_TC); + else + stm32_set_bits(port, ofs->icr, USART_ICR_TCCF); + if (stm32_port->tx_ch) stm32_transmit_chars_dma(port); else @@ -601,12 +590,21 @@ static void stm32_shutdown(struct uart_port *port) struct stm32_port *stm32_port = to_stm32_port(port); struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; struct stm32_usart_config *cfg = &stm32_port->info->cfg; - u32 val; + u32 val, isr; + int ret; val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE; val |= BIT(cfg->uart_enable_bit); if (stm32_port->fifoen) val |= USART_CR1_FIFOEN; + + ret = readl_relaxed_poll_timeout(port->membase + ofs->isr, + isr, (isr & USART_SR_TC), + 10, 100000); + + if (ret) + dev_err(port->dev, "transmission complete not set\n"); + stm32_clr_bits(port, ofs->cr1, val); dev_pm_clear_wake_irq(port->dev); From patchwork Tue May 21 15:45:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Erwan Le Ray X-Patchwork-Id: 164739 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp1769059ili; Tue, 21 May 2019 08:47:28 -0700 (PDT) X-Google-Smtp-Source: APXvYqwFaUbyhKBFohvKLYJ3jRutNWRB11GBOwTY8cQsJEfFOhA7FzQv0ZmJ1LiEaq9EvKrtcwaK X-Received: by 2002:aa7:8dc3:: with SMTP id j3mr88778166pfr.141.1558453648054; Tue, 21 May 2019 08:47:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558453648; cv=none; d=google.com; s=arc-20160816; b=HrLK2H+ORQlEtH5tPhD76kN1bk+9MstYuHM3mdBQyghAezg9mu3+gCQzQrvdDHrelT 42csRtZGkevowyYd03bEk4mOgWe0/6PcrfNFstT0UsvGVy9V2Zv7owdPKxZcX4JS0hLR 5dgumiP2JiAEeknDlDYmLYYY3zhlrXgDl7+tws6Pv3ih8q68bdtRCUE2IqTFGe5/aLl8 pJNRMVFnFs1NvwnAdh+JhhCngXV6q+sOfWIS2X5n+tL4w74rhEE+72oEnC5njRJzvl+B kQiKR08qYYsy0IienqJ+MGnyQm9QEjjB0+xkGqd+jynIXuX1zd/SkEIqWjNvoF9iPaV/ e3MQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=/FwJ1TQFru+32XoeDMyEaHFno8vBWsvjxdibmbx8Z44=; b=n1PcKb+TZGjFIxbm2CyujYoPAjyYKwibtyD4OwkG13hE3kkxsOsTbdP3kBgq3wPnW/ 2uVRT59wCHkT8XJTl1WVZyuu0aHxXov/8bQl6Zvc6YUJ7nuBgzrsl3I8OGgagqLxVhW7 rTK6YhjJ5kU2/lZR8DjiTAKz48va6hN/T2VVPUDqBNYT9rNO2Sfl1A6gObP8f2wVT+gi WKAWvPKckNFU4wu9Id+Qb7c1D6TS/4S29phlcqOV4Gyu3peG9u4SeLM7lJKnkCkTxfC3 npJTLS04go+XZbj/tg5h5zdsN5c3PmrzXQTvkacdac6qG6qe7Low+DbVL+YmaF01hh9E g+Jg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@st.com header.s=STMicroelectronics header.b=gbBFvw9P; spf=pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-serial-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p1si21356340plr.220.2019.05.21.08.47.27; Tue, 21 May 2019 08:47:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@st.com header.s=STMicroelectronics header.b=gbBFvw9P; spf=pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-serial-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729010AbfEUPr1 (ORCPT + 1 other); Tue, 21 May 2019 11:47:27 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:35802 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728212AbfEUPr1 (ORCPT ); Tue, 21 May 2019 11:47:27 -0400 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x4LFkWKv028109; Tue, 21 May 2019 17:46:46 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=STMicroelectronics; bh=/FwJ1TQFru+32XoeDMyEaHFno8vBWsvjxdibmbx8Z44=; b=gbBFvw9PfoW4Jz1Z5DI5evS/YoZjHP52RrV3HaNP/qCmI+pE+lF5J1aHrDRpoiRo8ugv eueMNl8Oed88Ojs9BomX52FAr+86xmAVlTb9LN5sy2P9u4FK5YumzMcNjrr7SufkZR2e s2G6lVfq6UDuTD0jexrlTomUSgiG7BYulNcqB8pStV9yxmtnsQCovd8Z7d2gdfE/KgsU eakofKIn0tJPCHqWS23ZnEOHpj+aJmX0aJNXEkobP+WRF5gl+WuhgS06y2i44abJAAq9 sRnfNEMpyLqUOp/PiFW5kJlJB9el1v4bkkep7gvNuXihyWVl6NKXkdnokN0IN0vEncKF kA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2sj7h0tkyr-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 21 May 2019 17:46:46 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 522913A; Tue, 21 May 2019 15:46:45 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas24.st.com [10.75.90.94]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 35CBE2CED; Tue, 21 May 2019 15:46:45 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.46) by Safex1hubcas24.st.com (10.75.90.94) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 21 May 2019 17:46:45 +0200 Received: from localhost (10.201.23.31) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 21 May 2019 17:46:43 +0200 From: Erwan Le Ray To: Greg Kroah-Hartman , Jiri Slaby , Maxime Coquelin , "Alexandre Torgue" CC: , , , , "Erwan Le Ray" , Fabrice Gasnier , "Fabien Dessenne" Subject: [PATCH 7/7] serial: stm32: fix the get_irq error case Date: Tue, 21 May 2019 17:45:47 +0200 Message-ID: <1558453547-22866-8-git-send-email-erwan.leray@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1558453547-22866-1-git-send-email-erwan.leray@st.com> References: <1558453547-22866-1-git-send-email-erwan.leray@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.31] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-05-21_03:, , signatures=0 Sender: linux-serial-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Checks the returned values of platform_get_irq() for both required "event" and optional "wakeup" IRQs during probe. This allows the driver probe to be deferred if needed. Removes redundant checks for 'cfg.has_wakeup'. Signed-off-by: Fabien Dessenne Signed-off-by: Erwan Le Ray -- 1.9.1 diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c index 1334e42..9c2b04e 100644 --- a/drivers/tty/serial/stm32-usart.c +++ b/drivers/tty/serial/stm32-usart.c @@ -852,12 +852,31 @@ static int stm32_init_port(struct stm32_port *stm32port, port->flags = UPF_BOOT_AUTOCONF; port->ops = &stm32_uart_ops; port->dev = &pdev->dev; - port->irq = platform_get_irq(pdev, 0); + + ret = platform_get_irq(pdev, 0); + if (ret <= 0) { + if (ret != -EPROBE_DEFER) + dev_err(&pdev->dev, "Can't get event IRQ: %d\n", ret); + return ret ? ret : -ENODEV; + } + port->irq = ret; + port->rs485_config = stm32_config_rs485; stm32_init_rs485(port, pdev); - stm32port->wakeirq = platform_get_irq(pdev, 1); + if (stm32port->info->cfg.has_wakeup) { + stm32port->wakeirq = platform_get_irq(pdev, 1); + if (stm32port->wakeirq <= 0 && stm32port->wakeirq != -ENXIO) { + if (stm32port->wakeirq != -EPROBE_DEFER) + dev_err(&pdev->dev, + "Can't get event wake IRQ: %d\n", + stm32port->wakeirq); + return stm32port->wakeirq ? stm32port->wakeirq : + -ENODEV; + } + } + stm32port->fifoen = stm32port->info->cfg.has_fifo; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -1064,7 +1083,7 @@ static int stm32_serial_probe(struct platform_device *pdev) if (ret) return ret; - if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0) { + if (stm32port->wakeirq > 0) { ret = device_init_wakeup(&pdev->dev, true); if (ret) goto err_uninit; @@ -1094,11 +1113,11 @@ static int stm32_serial_probe(struct platform_device *pdev) return 0; err_wirq: - if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0) + if (stm32port->wakeirq > 0) dev_pm_clear_wake_irq(&pdev->dev); err_nowup: - if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0) + if (stm32port->wakeirq > 0) device_init_wakeup(&pdev->dev, false); err_uninit: @@ -1112,7 +1131,6 @@ static int stm32_serial_remove(struct platform_device *pdev) struct uart_port *port = platform_get_drvdata(pdev); struct stm32_port *stm32_port = to_stm32_port(port); struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; - struct stm32_usart_config *cfg = &stm32_port->info->cfg; stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR); @@ -1134,7 +1152,7 @@ static int stm32_serial_remove(struct platform_device *pdev) TX_BUF_L, stm32_port->tx_buf, stm32_port->tx_dma_buf); - if (cfg->has_wakeup && stm32_port->wakeirq >= 0) { + if (stm32_port->wakeirq > 0) { dev_pm_clear_wake_irq(&pdev->dev); device_init_wakeup(&pdev->dev, false); } @@ -1252,7 +1270,7 @@ static void stm32_serial_enable_wakeup(struct uart_port *port, bool enable) struct stm32_usart_config *cfg = &stm32_port->info->cfg; u32 val; - if (!cfg->has_wakeup || stm32_port->wakeirq < 0) + if (stm32_port->wakeirq <= 0) return; if (enable) {