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[87.0.102.254]) by smtp.gmail.com with ESMTPSA id m2-20020a50d7c2000000b00501fc87352fsm6869333edj.13.2023.03.26.09.03.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Mar 2023 09:03:31 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Amarula patchwork , Rob Herring , Krzysztof Kozlowski , Marc Kleine-Budde , michael@amarulasolutions.com, Vincent Mailhol , Alexandre Torgue , Dario Binacchi , Alexandre Belloni , Christophe Roullier , Hans Verkuil , Krzysztof Kozlowski , Matti Vaittinen , Maxime Coquelin , Rob Herring , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v8 1/5] dt-bindings: arm: stm32: add compatible for syscon gcan node Date: Sun, 26 Mar 2023 18:03:21 +0200 Message-Id: <20230326160325.3771891-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20230326160325.3771891-1-dario.binacchi@amarulasolutions.com> References: <20230326160325.3771891-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Since commit ad440432d1f9 ("dt-bindings: mfd: Ensure 'syscon' has a more specific compatible") It is required to provide at least 2 compatibles string for syscon node. This patch documents the new compatible for stm32f4 SoC to support global/shared CAN registers access for bxCAN controllers. Signed-off-by: Dario Binacchi Acked-by: Rob Herring --- (no changes since v5) Changes in v5: - Add Rob Herring's Acked-by tag. .../devicetree/bindings/arm/stm32/st,stm32-syscon.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml index b2b156cc160a..ad8e51aa01b0 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -20,6 +20,7 @@ properties: - st,stm32-syscfg - st,stm32-power-config - st,stm32-tamp + - st,stm32f4-gcan - const: syscon - items: - const: st,stm32-tamp @@ -42,6 +43,7 @@ if: contains: enum: - st,stm32mp157-syscfg + - st,stm32f4-gcan then: required: - clocks From patchwork Sun Mar 26 16:03:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 667220 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 033BBC77B62 for ; Sun, 26 Mar 2023 16:03:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232618AbjCZQDj (ORCPT ); Sun, 26 Mar 2023 12:03:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35394 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232585AbjCZQDi (ORCPT ); Sun, 26 Mar 2023 12:03:38 -0400 Received: from mail-ed1-x536.google.com (mail-ed1-x536.google.com [IPv6:2a00:1450:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C0FCC422F for ; Sun, 26 Mar 2023 09:03:36 -0700 (PDT) Received: by mail-ed1-x536.google.com with SMTP id ew6so26201119edb.7 for ; Sun, 26 Mar 2023 09:03:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1679846615; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=90w47meUN1AAVQio6KlRg3XgdW53vJW4u/H89twTllI=; b=IGpkTrSY08rQpriigTycwI/pVPZuNL3LmyjzqBtRzJdVky7fNF+s2Lu/uDzVr8KNcn py8Se8tVeuwNXUJzn36teS2EI3MjrjVg1D1QEAj9s283J2z6gTmZXD0AwfKi1Rp9QaAb 259T4Bg8O5UZh2dVoHJQqkWmejCTLGGqecwbg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679846615; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=90w47meUN1AAVQio6KlRg3XgdW53vJW4u/H89twTllI=; b=j1b2q7DU5SnB3Lk97VJ4V+iFoFnC7BNS0pdMSdECBsxL/dhrDotcXxOMJxiHv1eflT 7A3rNMJRdI0tTUjlKICNPvrrDfWtmDys2hk5re1IV3Snzdzc8nilWouGq/6p0UDwztPf DheEfVmQl3oyngJYQVH7ILECjV8XviUFe/2nbgCRbHm9qFrT53iJxnhsCkNQ68dFDpz/ pjFRsVAcXi33XBXGQqN+2tVA2USclk/HOsx0I+KoH9ZFjIilmMVkHgRuIGdEMnRX0Ztu FKSeNlG2b68acVispVVREJiwlMNfyGT/Eokqh0hgc34ot98GNg95oDQ1BfM+BfQGqGwR PlrA== X-Gm-Message-State: AAQBX9dYpg8feF58exqMwoenbf/xfCmoRqB1pEUszM3pOiLfBq35HPwP WKAhefyNhKYHhdnIeMDTAZIFmQ== X-Google-Smtp-Source: AKy350bIfwMFk2pvBaJBigXVw+T4hWlt844pXbucNzIoAEIMfanFS6jc1aUnie97VTAQDIpd5pTB2A== X-Received: by 2002:aa7:d14e:0:b0:500:58cb:3b05 with SMTP id r14-20020aa7d14e000000b0050058cb3b05mr8961649edo.27.1679846614987; Sun, 26 Mar 2023 09:03:34 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-87-0-102-254.retail.telecomitalia.it. [87.0.102.254]) by smtp.gmail.com with ESMTPSA id m2-20020a50d7c2000000b00501fc87352fsm6869333edj.13.2023.03.26.09.03.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Mar 2023 09:03:34 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Amarula patchwork , Rob Herring , Krzysztof Kozlowski , Marc Kleine-Budde , michael@amarulasolutions.com, Vincent Mailhol , Alexandre Torgue , Dario Binacchi , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v8 3/5] ARM: dts: stm32: add CAN support on stm32f429 Date: Sun, 26 Mar 2023 18:03:23 +0200 Message-Id: <20230326160325.3771891-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20230326160325.3771891-1-dario.binacchi@amarulasolutions.com> References: <20230326160325.3771891-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for bxcan (Basic eXtended CAN controller) to STM32F429. The chip contains two CAN peripherals, CAN1 the master and CAN2 the slave, that share some of the required logic like clock and filters. This means that the slave CAN can't be used without the master CAN. Signed-off-by: Dario Binacchi --- (no changes since v6) Changes in v6: - move can1 node before gcan to keep ordering by address. Changes in v4: - Replace the node can@40006400 (compatible "st,stm32f4-bxcan-core") with the gcan@40006600 node ("sysnode" compatible). The gcan node contains clocks and memory addresses shared by the two can nodes of which it's no longer the parent. - Add to can nodes the "st,gcan" property (global can memory) which references the gcan@40006600 node ("sysnode compatibble). Changes in v3: - Remove 'Dario Binacchi ' SOB. - Add "clocks" to can@0 node. arch/arm/boot/dts/stm32f429.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index c31ceb821231..809b2842ded9 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -362,6 +362,35 @@ i2c3: i2c@40005c00 { status = "disabled"; }; + can1: can@40006400 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006400 0x200>; + interrupts = <19>, <20>, <21>, <22>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN1)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + st,can-master; + st,gcan = <&gcan>; + status = "disabled"; + }; + + gcan: gcan@40006600 { + compatible = "st,stm32f4-gcan", "syscon"; + reg = <0x40006600 0x200>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + }; + + can2: can@40006800 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006800 0x200>; + interrupts = <63>, <64>, <65>, <66>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN2)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>; + st,gcan = <&gcan>; + status = "disabled"; + }; + dac: dac@40007400 { compatible = "st,stm32f4-dac-core"; reg = <0x40007400 0x400>;