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[87.0.102.254]) by smtp.gmail.com with ESMTPSA id u26-20020a02b1da000000b003a958f51423sm5594759jah.167.2023.03.27.13.16.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 13:16:46 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Marc Kleine-Budde , Alexandre Torgue , Rob Herring , Amarula patchwork , Vincent Mailhol , michael@amarulasolutions.com, Krzysztof Kozlowski , Dario Binacchi , Christophe Roullier , Dmitry Torokhov , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , Sebastian Reichel , Ulf Hansson , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v9 1/5] dt-bindings: arm: stm32: add compatible for syscon gcan node Date: Mon, 27 Mar 2023 22:16:26 +0200 Message-Id: <20230327201630.3874028-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20230327201630.3874028-1-dario.binacchi@amarulasolutions.com> References: <20230327201630.3874028-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Since commit ad440432d1f9 ("dt-bindings: mfd: Ensure 'syscon' has a more specific compatible") it is required to provide at least 2 compatibles string for syscon node. This patch documents the new compatible for stm32f4 SoC to support global/shared CAN registers access for bxCAN controllers. Signed-off-by: Dario Binacchi Acked-by: Rob Herring --- Changes in v9: - Fix commit description formatting. No semantic changes have been made. Changes in v5: - Add Rob Herring's Acked-by tag. .../devicetree/bindings/arm/stm32/st,stm32-syscon.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml index b2b156cc160a..ad8e51aa01b0 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -20,6 +20,7 @@ properties: - st,stm32-syscfg - st,stm32-power-config - st,stm32-tamp + - st,stm32f4-gcan - const: syscon - items: - const: st,stm32-tamp @@ -42,6 +43,7 @@ if: contains: enum: - st,stm32mp157-syscfg + - st,stm32f4-gcan then: required: - clocks From patchwork Mon Mar 27 20:16:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 667619 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91D1EC6FD1D for ; Mon, 27 Mar 2023 20:17:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232769AbjC0URN (ORCPT ); Mon, 27 Mar 2023 16:17:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43598 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232661AbjC0URF (ORCPT ); Mon, 27 Mar 2023 16:17:05 -0400 Received: from mail-il1-x133.google.com (mail-il1-x133.google.com [IPv6:2607:f8b0:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B97C44AA for ; Mon, 27 Mar 2023 13:16:57 -0700 (PDT) Received: by mail-il1-x133.google.com with SMTP id h11so5243979ild.11 for ; Mon, 27 Mar 2023 13:16:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1679948217; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PQBAqyGpgtibuEQ07wkfyoJFQhHr9Hz8PDMB/KLLeHM=; b=JTjIYf+c214XaxQnu0kKEL9Eo7jLRGqw+K7R8lqR0oNNC8MVwOVZPZ2fxTrYbvC1Ri CCAZZSSlnBkr3Coou+GNmEyPu1mNmlpeThmdRoKJGRmCh3COBylHJZ4SR5LNWhhRZ4xe x6jcC2+eZ77HFwsra4tlZUWwIsLlZBi1Q4Qto= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679948217; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PQBAqyGpgtibuEQ07wkfyoJFQhHr9Hz8PDMB/KLLeHM=; b=wV5aTOVtf6zX/K1QUlY6DCBZLqgZETGF9Kph9YBMPxiP54vTUX+GkjYehLsq5SMSjd zbB1mPekGxLqNVNVC4CoqMdDh9kDNa7bIBArfpzS0gQkx+AK3dN7BHhMaPbsVKVjNlpl Iqeqm//JFkEpgyFPlSHOx0sjaaV9onlFg28ikLEof2Q1SwUQlVx0Kdkq90+2g/t5IFWO +MN/HqGwhYPKKrgrFCOv3tNcasIEUu028/hyWd8njyCYdd8M9tjverXPPH7m4XQq8d/A 6XKQEqbd/vYMbHm3wpnhushLhcDcRmgEvopQQHvfCJOBzPZKk1T8s0MrrW9heQR7DCPh 4kRw== X-Gm-Message-State: AAQBX9cGm2Hdo6V5QOnlpIyr77Ysv1nAbLjC9xNFK+Y4+m9qQTtn2vvF mpIB5WayJyenwhGfLfUKyTfj0g== X-Google-Smtp-Source: AKy350adLi+OaoxxRwg4JjV3hshajTUMAPaxd6bf7+Kdg4CU5S3sd2AFjyNuz2UKvfj6cTH0OVf8Uw== X-Received: by 2002:a05:6e02:1212:b0:325:dc0c:73f5 with SMTP id a18-20020a056e02121200b00325dc0c73f5mr8544921ilq.14.1679948216966; Mon, 27 Mar 2023 13:16:56 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.pdxnet.pdxeng.ch (host-87-0-102-254.retail.telecomitalia.it. [87.0.102.254]) by smtp.gmail.com with ESMTPSA id u26-20020a02b1da000000b003a958f51423sm5594759jah.167.2023.03.27.13.16.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 13:16:56 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Marc Kleine-Budde , Alexandre Torgue , Rob Herring , Amarula patchwork , Vincent Mailhol , michael@amarulasolutions.com, Krzysztof Kozlowski , Dario Binacchi , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v9 3/5] ARM: dts: stm32: add CAN support on stm32f429 Date: Mon, 27 Mar 2023 22:16:28 +0200 Message-Id: <20230327201630.3874028-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20230327201630.3874028-1-dario.binacchi@amarulasolutions.com> References: <20230327201630.3874028-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for bxcan (Basic eXtended CAN controller) to STM32F429. The chip contains two CAN peripherals, CAN1 the primary and CAN2 the secondary, that share some of the required logic like clock and filters. This means that the secondary CAN can't be used without the primary CAN. Signed-off-by: Dario Binacchi --- Changes in v9: - Replace master/slave terms with primary/secondary. Changes in v6: - move can1 node before gcan to keep ordering by address. Changes in v4: - Replace the node can@40006400 (compatible "st,stm32f4-bxcan-core") with the gcan@40006600 node ("sysnode" compatible). The gcan node contains clocks and memory addresses shared by the two can nodes of which it's no longer the parent. - Add to can nodes the "st,gcan" property (global can memory) which references the gcan@40006600 node ("sysnode compatibble). Changes in v3: - Remove 'Dario Binacchi ' SOB. - Add "clocks" to can@0 node. arch/arm/boot/dts/stm32f429.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index c31ceb821231..c9e05e3540d6 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -362,6 +362,35 @@ i2c3: i2c@40005c00 { status = "disabled"; }; + can1: can@40006400 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006400 0x200>; + interrupts = <19>, <20>, <21>, <22>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN1)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + st,can-primary; + st,gcan = <&gcan>; + status = "disabled"; + }; + + gcan: gcan@40006600 { + compatible = "st,stm32f4-gcan", "syscon"; + reg = <0x40006600 0x200>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + }; + + can2: can@40006800 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006800 0x200>; + interrupts = <63>, <64>, <65>, <66>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN2)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>; + st,gcan = <&gcan>; + status = "disabled"; + }; + dac: dac@40007400 { compatible = "st,stm32f4-dac-core"; reg = <0x40007400 0x400>;