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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id f17-20020a17090ac29100b00232cc61e16bsm5029301pjt.35.2023.03.27.19.19.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 19:19:22 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, arnd@arndb.de, schung@nuvoton.com, mjchen@nuvoton.com, Jacky Huang Subject: [PATCH v6 01/12] arm64: Kconfig.platforms: Add config for Nuvoton MA35 platform Date: Tue, 28 Mar 2023 02:19:01 +0000 Message-Id: <20230328021912.177301-2-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230328021912.177301-1-ychuang570808@gmail.com> References: <20230328021912.177301-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Jacky Huang Add ARCH_NUVOTON configuration option for Nuvoton MA35 family SoCs. Signed-off-by: Jacky Huang --- arch/arm64/Kconfig.platforms | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 89a0b13b058d..c1f277c05569 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -236,6 +236,15 @@ config ARCH_NPCM General support for NPCM8xx BMC (Arbel). Nuvoton NPCM8xx BMC based on the Cortex A35. +config ARCH_NUVOTON + bool "Nuvoton MA35 Platforms" + select GPIOLIB + select PINCTRL + select RESET_CONTROLLER + help + This enables support for the ARMv8 based Nuvoton SoCs such + as MA35D1. + config ARCH_QCOM bool "Qualcomm Platforms" select GPIOLIB From patchwork Tue Mar 28 02:19:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Huang X-Patchwork-Id: 668812 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 288A5C77B61 for ; Tue, 28 Mar 2023 02:19:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232259AbjC1CTb (ORCPT ); Mon, 27 Mar 2023 22:19:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43898 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231881AbjC1CT3 (ORCPT ); Mon, 27 Mar 2023 22:19:29 -0400 Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 63D4B2736; Mon, 27 Mar 2023 19:19:26 -0700 (PDT) Received: by mail-pj1-x102b.google.com with SMTP id om3-20020a17090b3a8300b0023efab0e3bfso13724161pjb.3; Mon, 27 Mar 2023 19:19:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679969966; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CaSv0fqLKCElmpWFPdMbQfJoPfoV6HUW2XrOse+W9mw=; b=dZefeMxtwXiPA+uVGntQkHb5kQ5RvKohl3FkllwFiBehryzS/ywPXlplhTOaVz8D44 4RRnIXm0SVaJ/CfN+GCx8TnkElLDPRSGCOOTBd/1s8edMs/RzB3W4A++03yPZKVJEWxB 1Kloimvlua9SIGbrHh/+rERyq+sH5/tFfGAYYuZLQBItUaNPI6qA0TxSaGjfXtLYMoO0 04q3Tnq+0cnXy3eK3B5sos1HrdNhapzxfOelfEe3hE74WmAP0SoaAXZiYS+aJJ7Run2X x+RTviBksxvi7YgWGbgw4W4jScG47xXhFuSKcaZPLWXI9D7Jk+ELqZoNVo4mLFW0ckpd QmKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679969966; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CaSv0fqLKCElmpWFPdMbQfJoPfoV6HUW2XrOse+W9mw=; b=Qp6t/TpcQyK91avqTl+F5EIgjGjGIGWSlzhdQs1G3VaaeBAmxjnd3yzNUxPYsy6afR x25bDOxnTqa1wlYTUgWlk/mOpLwK3BnO8wUu5DixMI5soCOMTfbWZjqHOsPBhRYQIxCf MIl5klWZ1RpmvDuw0xCiATKaikLy7d8Wk+k8WZBofZKbi11mr6wOnWAZRohkSulKyfrU C6/R0SnBQ9pnlTEC+O/duc67jE91EddtW8gXHLfPE6TcJlTIWYLkAhhMKX1qX966fshe z+HYvs2dR2p2xmbJBDu2Bvd85WUa9yAxIV7NzjISAsevGcTL8cEz9wx6ulJKBqIyiJIA bjAA== X-Gm-Message-State: AAQBX9e9QJvRxZbWvW0p6PjQKum2/rNIjmxXvrUzllC51wt1/wbwAgEM 4d2cEnmwsRYRJXdfiHHu9no= X-Google-Smtp-Source: AKy350ZZyf1nEh9VkNgaBZVXfsQcFR+H0vcOCtB3IuysSh6TfYnrWyClBBi3MRCPyVeXT8U2OO6BZw== X-Received: by 2002:a17:90b:1e01:b0:23f:b35b:7789 with SMTP id pg1-20020a17090b1e0100b0023fb35b7789mr15353524pjb.28.1679969965791; Mon, 27 Mar 2023 19:19:25 -0700 (PDT) Received: from a28aa0606c51.. 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id f17-20020a17090ac29100b00232cc61e16bsm5029301pjt.35.2023.03.27.19.19.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 19:19:25 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, arnd@arndb.de, schung@nuvoton.com, mjchen@nuvoton.com, Jacky Huang Subject: [PATCH v6 02/12] arm64: defconfig: Add support for Nuvoton MA35 family SoCs Date: Tue, 28 Mar 2023 02:19:02 +0000 Message-Id: <20230328021912.177301-3-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230328021912.177301-1-ychuang570808@gmail.com> References: <20230328021912.177301-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Jacky Huang This adds support for the Nuvoton MA35 family SoCs which are based on the Cortex-A35 Armv8-A 64-bit architecture. Signed-off-by: Jacky Huang --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 7790ee42c68a..c96189acb02c 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -53,6 +53,7 @@ CONFIG_ARCH_LAYERSCAPE=y CONFIG_ARCH_MXC=y CONFIG_ARCH_S32=y CONFIG_ARCH_NPCM=y +CONFIG_ARCH_NUVOTON=y CONFIG_ARCH_QCOM=y CONFIG_ARCH_RENESAS=y CONFIG_ARCH_ROCKCHIP=y From patchwork Tue Mar 28 02:19:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Huang X-Patchwork-Id: 668089 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC83FC761A6 for ; Tue, 28 Mar 2023 02:19:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232531AbjC1CTg (ORCPT ); Mon, 27 Mar 2023 22:19:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43978 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232220AbjC1CTa (ORCPT ); Mon, 27 Mar 2023 22:19:30 -0400 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A48B1984; Mon, 27 Mar 2023 19:19:29 -0700 (PDT) Received: by mail-pl1-x635.google.com with SMTP id ja10so10282012plb.5; Mon, 27 Mar 2023 19:19:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679969968; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=E3H97QC/49lG7sVpBotvCbRxqmE2T4wmzwE6sz7I2fM=; b=WOiCfDeuyepPYPlnLDQGHXSD0k6n1wot1dRuxV1CeDBTSiKSD8TU7DEm3P98DaZAkv xVhevfW9HuFLEmOV4+MTMo9Nb5M64+gek5XcSoIX8MJMBksmfi+iKb5nU9R/Ez61Y42w ATVCh9jSMH/Ix04+y6qEOvVmt6LWJFOHaCH9hT0qKeDH1jjw8BvHbGjRs6wKn/yXAGCj uBkdw9ryc0ewSa/Nz9VfBqgMfTOUVfbmIlVRx+YWiKSeIs8s4fWrnWvxVm7Pq4aPsj+6 yhsjbKUWoU5xadKw3jHarYrLdbKcLjJmAVfMzzUCxQQDyXG/cwtkGsEszk3FZRxuehPw yZaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679969968; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E3H97QC/49lG7sVpBotvCbRxqmE2T4wmzwE6sz7I2fM=; b=c2yxLSjQPZ6JIDVeviHVHJc6sq9RP4P+sRd8fG8485lNTeQ7rWmpNvQpIoeTiPyXNA LjE/JnVijgt81NdjuF1nPe3ndPkwosSYxPfPARcgwKD9GSRXUaIbY8wfTrLgas4JTMut lmipJlnHo21MhKVeN4c0O02sJv9HbionhBjK5yh6Py9MY38rLCok8WNbqnleD9KuIHz6 LnH5WC/MPcrkb7ORwZXUEqxtXhTADydAHzxCURbnoQzWb6UDJ/JGARFeEjdaOMpblXNc 1m5kmEjW1fk9HavFrG5d/zsOnZKRtqBynzH1fzZwgn0HRFnuuqmfND/MlvpZS8WeS2yZ ZWIQ== X-Gm-Message-State: AAQBX9cZdwxL9g8597TG8m0utlS4KyktS02JRA0Qal+Xpf7Bjxdlzm6z BnnhonlvjnTRP+Be8641T64JJCkrN1DmjQ== X-Google-Smtp-Source: AKy350Z2v1Cc+pPNsRVQZBV+hjZrUktYjnPX7jXnxcUjuQ7ReftzGPU5hz7Ql5Dv2Tw1Dneh+EJjzg== X-Received: by 2002:a17:90b:314e:b0:23d:286:47d3 with SMTP id ip14-20020a17090b314e00b0023d028647d3mr15795483pjb.40.1679969968480; Mon, 27 Mar 2023 19:19:28 -0700 (PDT) Received: from a28aa0606c51.. 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id f17-20020a17090ac29100b00232cc61e16bsm5029301pjt.35.2023.03.27.19.19.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 19:19:28 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, arnd@arndb.de, schung@nuvoton.com, mjchen@nuvoton.com, Jacky Huang Subject: [PATCH v6 03/12] dt-bindings: clock: nuvoton: add binding for ma35d1 clock controller Date: Tue, 28 Mar 2023 02:19:03 +0000 Message-Id: <20230328021912.177301-4-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230328021912.177301-1-ychuang570808@gmail.com> References: <20230328021912.177301-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Jacky Huang Add the dt-bindings header for Nuvoton ma35d1, that gets shared between the clock controller and clock references in the dts. Add documentation to describe nuvoton ma35d1 clock driver. Signed-off-by: Jacky Huang Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/nuvoton,ma35d1-clk.yaml | 72 +++++ .../dt-bindings/clock/nuvoton,ma35d1-clk.h | 253 ++++++++++++++++++ 2 files changed, 325 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml create mode 100644 include/dt-bindings/clock/nuvoton,ma35d1-clk.h diff --git a/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml new file mode 100644 index 000000000000..0a9c2a115e6b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nuvoton,ma35d1-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 Clock Controller Module + +maintainers: + - Chi-Fang Li + - Jacky Huang + +description: | + The MA35D1 clock controller generates clocks for the whole chip, + including system clocks and all peripheral clocks. + + See also: + include/dt-bindings/clock/ma35d1-clk.h + +properties: + compatible: + items: + - const: nuvoton,ma35d1-clk + - const: syscon + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + clocks: + maxItems: 1 + + nuvoton,pll-mode: + description: + A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL, + EPLL, and VPLL in sequential. + maxItems: 5 + items: + enum: + - integer + - fractional + - spread-spectrum + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + + nuvoton,sys: + description: + Use to unlock and lock some clock controller registers. The lock + control register is in system controller. + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - reg + - "#clock-cells" + - clocks + - nuvoton,sys + +additionalProperties: false + +examples: + - | + + clock-controller@40460200 { + compatible = "nuvoton,ma35d1-clk", "syscon"; + reg = <0x40460200 0x100>; + #clock-cells = <1>; + clocks = <&clk_hxt>; + nuvoton,sys = <&sys>; + }; +... diff --git a/include/dt-bindings/clock/nuvoton,ma35d1-clk.h b/include/dt-bindings/clock/nuvoton,ma35d1-clk.h new file mode 100644 index 000000000000..ba2d70f776a6 --- /dev/null +++ b/include/dt-bindings/clock/nuvoton,ma35d1-clk.h @@ -0,0 +1,253 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Nuvoton Technologies. + */ + +#ifndef __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H +#define __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H + +/* external and internal oscillator clocks */ +#define HXT 0 +#define HXT_GATE 1 +#define LXT 2 +#define LXT_GATE 3 +#define HIRC 4 +#define HIRC_GATE 5 +#define LIRC 6 +#define LIRC_GATE 7 +/* PLLs */ +#define CAPLL 8 +#define SYSPLL 9 +#define DDRPLL 10 +#define APLL 11 +#define EPLL 12 +#define VPLL 13 +/* EPLL divider */ +#define EPLL_DIV2 14 +#define EPLL_DIV4 15 +#define EPLL_DIV8 16 +/* CPU clock, system clock, AXI, HCLK and PCLK */ +#define CA35CLK_MUX 17 +#define AXICLK_DIV2 18 +#define AXICLK_DIV4 19 +#define AXICLK_MUX 20 +#define SYSCLK0_MUX 21 +#define SYSCLK1_MUX 22 +#define SYSCLK1_DIV2 23 +#define HCLK0 24 +#define HCLK1 25 +#define HCLK2 26 +#define PCLK0 27 +#define PCLK1 28 +#define PCLK2 29 +#define HCLK3 30 +#define PCLK3 31 +#define PCLK4 32 +/* AXI and AHB peripheral clocks */ +#define USBPHY0 33 +#define USBPHY1 34 +#define DDR0_GATE 35 +#define DDR6_GATE 36 +#define CAN0_MUX 37 +#define CAN0_DIV 38 +#define CAN0_GATE 39 +#define CAN1_MUX 40 +#define CAN1_DIV 41 +#define CAN1_GATE 42 +#define CAN2_MUX 43 +#define CAN2_DIV 44 +#define CAN2_GATE 45 +#define CAN3_MUX 46 +#define CAN3_DIV 47 +#define CAN3_GATE 48 +#define SDH0_MUX 49 +#define SDH0_GATE 50 +#define SDH1_MUX 51 +#define SDH1_GATE 52 +#define NAND_GATE 53 +#define USBD_GATE 54 +#define USBH_GATE 55 +#define HUSBH0_GATE 56 +#define HUSBH1_GATE 57 +#define GFX_MUX 58 +#define GFX_GATE 59 +#define VC8K_GATE 60 +#define DCU_MUX 61 +#define DCU_GATE 62 +#define DCUP_DIV 63 +#define EMAC0_GATE 64 +#define EMAC1_GATE 65 +#define CCAP0_MUX 66 +#define CCAP0_DIV 67 +#define CCAP0_GATE 68 +#define CCAP1_MUX 69 +#define CCAP1_DIV 70 +#define CCAP1_GATE 71 +#define PDMA0_GATE 72 +#define PDMA1_GATE 73 +#define PDMA2_GATE 74 +#define PDMA3_GATE 75 +#define WH0_GATE 76 +#define WH1_GATE 77 +#define HWS_GATE 78 +#define EBI_GATE 79 +#define SRAM0_GATE 80 +#define SRAM1_GATE 81 +#define ROM_GATE 82 +#define TRA_GATE 83 +#define DBG_MUX 84 +#define DBG_GATE 85 +#define CKO_MUX 86 +#define CKO_DIV 87 +#define CKO_GATE 88 +#define GTMR_GATE 89 +#define GPA_GATE 90 +#define GPB_GATE 91 +#define GPC_GATE 92 +#define GPD_GATE 93 +#define GPE_GATE 94 +#define GPF_GATE 95 +#define GPG_GATE 96 +#define GPH_GATE 97 +#define GPI_GATE 98 +#define GPJ_GATE 99 +#define GPK_GATE 100 +#define GPL_GATE 101 +#define GPM_GATE 102 +#define GPN_GATE 103 +/* APB peripheral clocks */ +#define TMR0_MUX 104 +#define TMR0_GATE 105 +#define TMR1_MUX 106 +#define TMR1_GATE 107 +#define TMR2_MUX 108 +#define TMR2_GATE 109 +#define TMR3_MUX 110 +#define TMR3_GATE 111 +#define TMR4_MUX 112 +#define TMR4_GATE 113 +#define TMR5_MUX 114 +#define TMR5_GATE 115 +#define TMR6_MUX 116 +#define TMR6_GATE 117 +#define TMR7_MUX 118 +#define TMR7_GATE 119 +#define TMR8_MUX 120 +#define TMR8_GATE 121 +#define TMR9_MUX 122 +#define TMR9_GATE 123 +#define TMR10_MUX 124 +#define TMR10_GATE 125 +#define TMR11_MUX 126 +#define TMR11_GATE 127 +#define UART0_MUX 128 +#define UART0_DIV 129 +#define UART0_GATE 130 +#define UART1_MUX 131 +#define UART1_DIV 132 +#define UART1_GATE 133 +#define UART2_MUX 134 +#define UART2_DIV 135 +#define UART2_GATE 136 +#define UART3_MUX 137 +#define UART3_DIV 138 +#define UART3_GATE 139 +#define UART4_MUX 140 +#define UART4_DIV 141 +#define UART4_GATE 142 +#define UART5_MUX 143 +#define UART5_DIV 144 +#define UART5_GATE 145 +#define UART6_MUX 146 +#define UART6_DIV 147 +#define UART6_GATE 148 +#define UART7_MUX 149 +#define UART7_DIV 150 +#define UART7_GATE 151 +#define UART8_MUX 152 +#define UART8_DIV 153 +#define UART8_GATE 154 +#define UART9_MUX 155 +#define UART9_DIV 156 +#define UART9_GATE 157 +#define UART10_MUX 158 +#define UART10_DIV 159 +#define UART10_GATE 160 +#define UART11_MUX 161 +#define UART11_DIV 162 +#define UART11_GATE 163 +#define UART12_MUX 164 +#define UART12_DIV 165 +#define UART12_GATE 166 +#define UART13_MUX 167 +#define UART13_DIV 168 +#define UART13_GATE 169 +#define UART14_MUX 170 +#define UART14_DIV 171 +#define UART14_GATE 172 +#define UART15_MUX 173 +#define UART15_DIV 174 +#define UART15_GATE 175 +#define UART16_MUX 176 +#define UART16_DIV 177 +#define UART16_GATE 178 +#define RTC_GATE 179 +#define DDR_GATE 180 +#define KPI_MUX 181 +#define KPI_DIV 182 +#define KPI_GATE 183 +#define I2C0_GATE 184 +#define I2C1_GATE 185 +#define I2C2_GATE 186 +#define I2C3_GATE 187 +#define I2C4_GATE 188 +#define I2C5_GATE 189 +#define QSPI0_MUX 190 +#define QSPI0_GATE 191 +#define QSPI1_MUX 192 +#define QSPI1_GATE 193 +#define SMC0_MUX 194 +#define SMC0_DIV 195 +#define SMC0_GATE 196 +#define SMC1_MUX 197 +#define SMC1_DIV 198 +#define SMC1_GATE 199 +#define WDT0_MUX 200 +#define WDT0_GATE 201 +#define WDT1_MUX 202 +#define WDT1_GATE 203 +#define WDT2_MUX 204 +#define WDT2_GATE 205 +#define WWDT0_MUX 206 +#define WWDT1_MUX 207 +#define WWDT2_MUX 208 +#define EPWM0_GATE 209 +#define EPWM1_GATE 210 +#define EPWM2_GATE 211 +#define I2S0_MUX 212 +#define I2S0_GATE 213 +#define I2S1_MUX 214 +#define I2S1_GATE 215 +#define SSMCC_GATE 216 +#define SSPCC_GATE 217 +#define SPI0_MUX 218 +#define SPI0_GATE 219 +#define SPI1_MUX 220 +#define SPI1_GATE 221 +#define SPI2_MUX 222 +#define SPI2_GATE 223 +#define SPI3_MUX 224 +#define SPI3_GATE 225 +#define ECAP0_GATE 226 +#define ECAP1_GATE 227 +#define ECAP2_GATE 228 +#define QEI0_GATE 229 +#define QEI1_GATE 230 +#define QEI2_GATE 231 +#define ADC_DIV 232 +#define ADC_GATE 233 +#define EADC_DIV 234 +#define EADC_GATE 235 +#define CLK_MAX_IDX 236 + +#endif /* __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H */ From patchwork Tue Mar 28 02:19:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Huang X-Patchwork-Id: 668811 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79614C76195 for ; Tue, 28 Mar 2023 02:19:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232579AbjC1CTr (ORCPT ); Mon, 27 Mar 2023 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id f17-20020a17090ac29100b00232cc61e16bsm5029301pjt.35.2023.03.27.19.19.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 19:19:31 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, arnd@arndb.de, schung@nuvoton.com, mjchen@nuvoton.com, Jacky Huang Subject: [PATCH v6 04/12] dt-bindings: reset: nuvoton: add binding for ma35d1 IP reset control Date: Tue, 28 Mar 2023 02:19:04 +0000 Message-Id: <20230328021912.177301-5-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230328021912.177301-1-ychuang570808@gmail.com> References: <20230328021912.177301-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Jacky Huang Add the dt-bindings header for Nuvoton ma35d1, that gets shared between the reset controller and reset references in the dts. Add documentation to describe nuvoton ma35d1 reset driver. Signed-off-by: Jacky Huang --- .../bindings/reset/nuvoton,ma35d1-reset.yaml | 44 +++++++ .../dt-bindings/reset/nuvoton,ma35d1-reset.h | 108 ++++++++++++++++++ 2 files changed, 152 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml create mode 100644 include/dt-bindings/reset/nuvoton,ma35d1-reset.h diff --git a/Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml b/Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml new file mode 100644 index 000000000000..342717257e5c --- /dev/null +++ b/Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/nuvoton,ma35d1-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 Reset Controller + +maintainers: + - Chi-Fang Li + - Jacky Huang + +description: + The system reset controller can be used to reset various peripheral + controllers in MA35D1 SoC. + +properties: + compatible: + const: nuvoton,ma35d1-reset + + '#reset-cells': + const: 1 + +required: + - compatible + - '#reset-cells' + +additionalProperties: false + +examples: + # system reset controller node: + - | + + system-management@40460000 { + compatible = "nuvoton,ma35d1-sys", "syscon", "simple-mfd"; + reg = <0x40460000 0x200>; + + reset-controller { + compatible = "nuvoton,ma35d1-reset"; + #reset-cells = <1>; + }; + }; +... + diff --git a/include/dt-bindings/reset/nuvoton,ma35d1-reset.h b/include/dt-bindings/reset/nuvoton,ma35d1-reset.h new file mode 100644 index 000000000000..f3088bc0afec --- /dev/null +++ b/include/dt-bindings/reset/nuvoton,ma35d1-reset.h @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Nuvoton Technologies. + * Author: Chi-Fen Li + * + * Device Tree binding constants for MA35D1 reset controller. + */ + +#ifndef __DT_BINDINGS_RESET_MA35D1_H +#define __DT_BINDINGS_RESET_MA35D1_H + +#define MA35D1_RESET_CHIP 0 +#define MA35D1_RESET_CA35CR0 1 +#define MA35D1_RESET_CA35CR1 2 +#define MA35D1_RESET_CM4 3 +#define MA35D1_RESET_PDMA0 4 +#define MA35D1_RESET_PDMA1 5 +#define MA35D1_RESET_PDMA2 6 +#define MA35D1_RESET_PDMA3 7 +#define MA35D1_RESET_DISP 9 +#define MA35D1_RESET_VCAP0 10 +#define MA35D1_RESET_VCAP1 11 +#define MA35D1_RESET_GFX 12 +#define MA35D1_RESET_VDEC 13 +#define MA35D1_RESET_WHC0 14 +#define MA35D1_RESET_WHC1 15 +#define MA35D1_RESET_GMAC0 16 +#define MA35D1_RESET_GMAC1 17 +#define MA35D1_RESET_HWSEM 18 +#define MA35D1_RESET_EBI 19 +#define MA35D1_RESET_HSUSBH0 20 +#define MA35D1_RESET_HSUSBH1 21 +#define MA35D1_RESET_HSUSBD 22 +#define MA35D1_RESET_USBHL 23 +#define MA35D1_RESET_SDH0 24 +#define MA35D1_RESET_SDH1 25 +#define MA35D1_RESET_NAND 26 +#define MA35D1_RESET_GPIO 27 +#define MA35D1_RESET_MCTLP 28 +#define MA35D1_RESET_MCTLC 29 +#define MA35D1_RESET_DDRPUB 30 +#define MA35D1_RESET_TMR0 34 +#define MA35D1_RESET_TMR1 35 +#define MA35D1_RESET_TMR2 36 +#define MA35D1_RESET_TMR3 37 +#define MA35D1_RESET_I2C0 40 +#define MA35D1_RESET_I2C1 41 +#define MA35D1_RESET_I2C2 42 +#define MA35D1_RESET_I2C3 43 +#define MA35D1_RESET_QSPI0 44 +#define MA35D1_RESET_SPI0 45 +#define MA35D1_RESET_SPI1 46 +#define MA35D1_RESET_SPI2 47 +#define MA35D1_RESET_UART0 48 +#define MA35D1_RESET_UART1 49 +#define MA35D1_RESET_UART2 50 +#define MA35D1_RESET_UAER3 51 +#define MA35D1_RESET_UART4 52 +#define MA35D1_RESET_UART5 53 +#define MA35D1_RESET_UART6 54 +#define MA35D1_RESET_UART7 55 +#define MA35D1_RESET_CANFD0 56 +#define MA35D1_RESET_CANFD1 57 +#define MA35D1_RESET_EADC0 60 +#define MA35D1_RESET_I2S0 61 +#define MA35D1_RESET_SC0 64 +#define MA35D1_RESET_SC1 65 +#define MA35D1_RESET_QSPI1 68 +#define MA35D1_RESET_SPI3 70 +#define MA35D1_RESET_EPWM0 80 +#define MA35D1_RESET_EPWM1 81 +#define MA35D1_RESET_QEI0 86 +#define MA35D1_RESET_QEI1 87 +#define MA35D1_RESET_ECAP0 90 +#define MA35D1_RESET_ECAP1 91 +#define MA35D1_RESET_CANFD2 92 +#define MA35D1_RESET_ADC0 95 +#define MA35D1_RESET_TMR4 96 +#define MA35D1_RESET_TMR5 97 +#define MA35D1_RESET_TMR6 98 +#define MA35D1_RESET_TMR7 99 +#define MA35D1_RESET_TMR8 100 +#define MA35D1_RESET_TMR9 101 +#define MA35D1_RESET_TMR10 102 +#define MA35D1_RESET_TMR11 103 +#define MA35D1_RESET_UART8 104 +#define MA35D1_RESET_UART9 105 +#define MA35D1_RESET_UART10 106 +#define MA35D1_RESET_UART11 107 +#define MA35D1_RESET_UART12 108 +#define MA35D1_RESET_UART13 109 +#define MA35D1_RESET_UART14 110 +#define MA35D1_RESET_UART15 111 +#define MA35D1_RESET_UART16 112 +#define MA35D1_RESET_I2S1 113 +#define MA35D1_RESET_I2C4 114 +#define MA35D1_RESET_I2C5 115 +#define MA35D1_RESET_EPWM2 116 +#define MA35D1_RESET_ECAP2 117 +#define MA35D1_RESET_QEI2 118 +#define MA35D1_RESET_CANFD3 119 +#define MA35D1_RESET_KPI 120 +#define MA35D1_RESET_GIC 124 +#define MA35D1_RESET_SSMCC 126 +#define MA35D1_RESET_SSPCC 127 +#define MA35D1_RESET_COUNT 128 + +#endif From patchwork Tue Mar 28 02:19:05 2023 Content-Type: text/plain; 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id f17-20020a17090ac29100b00232cc61e16bsm5029301pjt.35.2023.03.27.19.19.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 19:19:33 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, arnd@arndb.de, schung@nuvoton.com, mjchen@nuvoton.com, Jacky Huang Subject: [PATCH v6 05/12] dt-bindings: mfd: syscon: Add nuvoton,ma35d1-sys compatible Date: Tue, 28 Mar 2023 02:19:05 +0000 Message-Id: <20230328021912.177301-6-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230328021912.177301-1-ychuang570808@gmail.com> References: <20230328021912.177301-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Jacky Huang Add Nuvoton ma35d1 system registers compatible. Signed-off-by: Jacky Huang --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index c828c4f5e4a7..7ee1d27f59dd 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -56,6 +56,7 @@ properties: - microchip,lan966x-cpu-syscon - microchip,sparx5-cpu-syscon - mstar,msc313-pmsleep + - nuvoton,ma35d1-sys - nuvoton,wpcm450-shm - rockchip,px30-qos - rockchip,rk3036-qos From patchwork Tue Mar 28 02:19:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Huang X-Patchwork-Id: 668810 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A1B4C6FD1D for ; Tue, 28 Mar 2023 02:20:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232658AbjC1CUI (ORCPT ); Mon, 27 Mar 2023 22:20:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44246 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232394AbjC1CTu (ORCPT ); Mon, 27 Mar 2023 22:19:50 -0400 Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 613F62D76; Mon, 27 Mar 2023 19:19:38 -0700 (PDT) Received: by mail-pj1-x102f.google.com with SMTP id j13so9515236pjd.1; Mon, 27 Mar 2023 19:19:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679969977; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9jyCpXhdQrRdIItZilRrI84sFNyhhCD7V61mef/guao=; b=nG1dUPYlvn/ycTll+sB9SJovsn4+INiDFfdakFCw8UZZ0t5GqvYOZQBmQWKGRyoOtH xlJ7KM3LkysX1Ys2CS4e4RHz57RBNcrv6n28N9Hi6t3IxuAkaz9V/B3f/EKx9IRv3wKp ujCxKbT5cXO6M+I2J+mGeiXOJ+iV8SGmPENtk0sYjiCctpp6lZrBx/FREBm13kJD9e+T CZQ3xcVLsgb489GksxuAbokkMyxyMZYUFGKc/guHpi0G5mlSjKx1wK9NN+9D9OmmEroj sQ7h0NrgzMxqWsJYOMWXH8T84hnpP5rlTHnRsRyi3/5MpioR5hHfPVukpPkBP9uMCzPE M+mQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679969977; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9jyCpXhdQrRdIItZilRrI84sFNyhhCD7V61mef/guao=; b=pJaRDghNertJuGI0h34z/eGGnsslfvscIve9qxQ3GI5YSPkggXf8sUCvtaAlpfBpPn xRGaefnr4rNxcOTRvnpeNUYWAzZ0eLN6SjXXiFnIVDIVWZuVteoMvpRwqgf/CUgMndTt 4EJpbPzDYhyEM0a8CfzJvSAyUhKSUno4FEW9QOkVvnea7X8uGr5Qwhwx8X5BT9cbs523 Db5A5US1GtcLzexz5rbPN4CHiL9ros1uGjD5i3a6PR5ujlLOw5PM1bjYZlD4RvcQTcWX Te/PgLfvDON6Y/6OShhQzEpcRVGwLHuI1HJbKGRhxmsxEr0+Gmf5Lijz1B9UMjlpUO48 hdWg== X-Gm-Message-State: AAQBX9cKq7qYrNsMqPW2KNriZ6qdZlOjkvUT/8k25HcTvKs1JBGthwO8 hiDx3j25NVdWo3ceeY8oHkc= X-Google-Smtp-Source: AKy350Zx7DLve3aH5qT1Wofayb+2R58sClIDBVU3v+M0f8Q6z2BJPjgWqTQPFfCyEZVpt94TPBBtJA== X-Received: by 2002:a17:90b:350a:b0:23b:4388:7d8a with SMTP id ls10-20020a17090b350a00b0023b43887d8amr14139825pjb.21.1679969977016; Mon, 27 Mar 2023 19:19:37 -0700 (PDT) Received: from a28aa0606c51.. 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id f17-20020a17090ac29100b00232cc61e16bsm5029301pjt.35.2023.03.27.19.19.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 19:19:36 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, arnd@arndb.de, schung@nuvoton.com, mjchen@nuvoton.com, Jacky Huang Subject: [PATCH v6 06/12] dt-bindings: arm: Add initial bindings for Nuvoton platform Date: Tue, 28 Mar 2023 02:19:06 +0000 Message-Id: <20230328021912.177301-7-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230328021912.177301-1-ychuang570808@gmail.com> References: <20230328021912.177301-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Jacky Huang Rename the bindings/arm/npcm directory as nuvoton. Add binding for ARMv8 based Nuvotn SoCs and platform boards. Add initial bindings for ma35d1 series development boards. Signed-off-by: Jacky Huang --- .../bindings/arm/nuvoton/nuvoton,ma35d1.yaml | 30 +++++++++++++++++++ .../nuvoton,npcm-gcr.yaml} | 2 +- .../npcm.yaml => nuvoton/nuvoton,npcm.yaml} | 2 +- 3 files changed, 32 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/nuvoton/nuvoton,ma35d1.yaml rename Documentation/devicetree/bindings/arm/{npcm/nuvoton,gcr.yaml => nuvoton/nuvoton,npcm-gcr.yaml} (93%) rename Documentation/devicetree/bindings/arm/{npcm/npcm.yaml => nuvoton/nuvoton,npcm.yaml} (93%) diff --git a/Documentation/devicetree/bindings/arm/nuvoton/nuvoton,ma35d1.yaml b/Documentation/devicetree/bindings/arm/nuvoton/nuvoton,ma35d1.yaml new file mode 100644 index 000000000000..fb190db61525 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/nuvoton/nuvoton,ma35d1.yaml @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/nuvoton/nuvoton,ma35d1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35 series SoC based platforms + +maintainers: + - Jacky Huang + +description: | + Boards with an ARMv8 based Nuvoton MA35 series SoC shall have + the following properties. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: MA35D1 based boards + items: + - enum: + - nuvoton,ma35d1-iot + - nuvoton,ma35d1-som + - const: nuvoton,ma35d1 + +additionalProperties: true +... diff --git a/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml b/Documentation/devicetree/bindings/arm/nuvoton/nuvoton,npcm-gcr.yaml similarity index 93% rename from Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml rename to Documentation/devicetree/bindings/arm/nuvoton/nuvoton,npcm-gcr.yaml index 94e72f25b331..1f354aa900ea 100644 --- a/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml +++ b/Documentation/devicetree/bindings/arm/nuvoton/nuvoton,npcm-gcr.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- -$id: http://devicetree.org/schemas/arm/npcm/nuvoton,gcr.yaml# +$id: http://devicetree.org/schemas/arm/nuvoton/nuvoton,npcm-gcr.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Global Control Registers block in Nuvoton SoCs diff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.yaml b/Documentation/devicetree/bindings/arm/nuvoton/nuvoton,npcm.yaml similarity index 93% rename from Documentation/devicetree/bindings/arm/npcm/npcm.yaml rename to Documentation/devicetree/bindings/arm/nuvoton/nuvoton,npcm.yaml index 6871483947c5..d386744c8815 100644 --- a/Documentation/devicetree/bindings/arm/npcm/npcm.yaml +++ b/Documentation/devicetree/bindings/arm/nuvoton/nuvoton,npcm.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- -$id: http://devicetree.org/schemas/arm/npcm/npcm.yaml# +$id: http://devicetree.org/schemas/arm/nuvoton/nuvoton,npcm.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: NPCM Platforms From patchwork Tue Mar 28 02:19:07 2023 Content-Type: text/plain; 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id f17-20020a17090ac29100b00232cc61e16bsm5029301pjt.35.2023.03.27.19.19.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 19:19:39 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, arnd@arndb.de, schung@nuvoton.com, mjchen@nuvoton.com, Jacky Huang Subject: [PATCH v6 07/12] dt-bindings: serial: Document ma35d1 uart controller Date: Tue, 28 Mar 2023 02:19:07 +0000 Message-Id: <20230328021912.177301-8-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230328021912.177301-1-ychuang570808@gmail.com> References: <20230328021912.177301-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Jacky Huang Add documentation to describe nuvoton ma35d1 uart driver bindings. Signed-off-by: Jacky Huang Reviewed-by: Krzysztof Kozlowski --- .../serial/nuvoton,ma35d1-serial.yaml | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/nuvoton,ma35d1-serial.yaml diff --git a/Documentation/devicetree/bindings/serial/nuvoton,ma35d1-serial.yaml b/Documentation/devicetree/bindings/serial/nuvoton,ma35d1-serial.yaml new file mode 100644 index 000000000000..a76af0f6009b --- /dev/null +++ b/Documentation/devicetree/bindings/serial/nuvoton,ma35d1-serial.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/nuvoton,ma35d1-serial.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 Universal Asynchronous Receiver/Transmitter (UART) + +maintainers: + - Min-Jen Chen + - Jacky Huang + +allOf: + - $ref: serial.yaml + +properties: + compatible: + const: nuvoton,ma35d1-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + #include + + serial@40700000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x40700000 0x100>; + interrupts = ; + clocks = <&clk UART0_GATE>; + }; +... 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id f17-20020a17090ac29100b00232cc61e16bsm5029301pjt.35.2023.03.27.19.19.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 19:19:42 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, arnd@arndb.de, schung@nuvoton.com, mjchen@nuvoton.com, Jacky Huang Subject: [PATCH v6 08/12] arm64: dts: nuvoton: Add initial ma35d1 device tree Date: Tue, 28 Mar 2023 02:19:08 +0000 Message-Id: <20230328021912.177301-9-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230328021912.177301-1-ychuang570808@gmail.com> References: <20230328021912.177301-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Jacky Huang Add initial device tree support for Nuvoton ma35d1 SoC, including cpu, clock, reset, and serial controllers. Add reference boards som-256m and iot-512m. Signed-off-by: Jacky Huang --- arch/arm64/boot/dts/nuvoton/Makefile | 2 + .../boot/dts/nuvoton/ma35d1-iot-512m.dts | 56 +++++ .../boot/dts/nuvoton/ma35d1-som-256m.dts | 56 +++++ arch/arm64/boot/dts/nuvoton/ma35d1.dtsi | 231 ++++++++++++++++++ 4 files changed, 345 insertions(+) create mode 100644 arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts create mode 100644 arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts create mode 100644 arch/arm64/boot/dts/nuvoton/ma35d1.dtsi diff --git a/arch/arm64/boot/dts/nuvoton/Makefile b/arch/arm64/boot/dts/nuvoton/Makefile index a99dab90472a..c11ab4eac9c7 100644 --- a/arch/arm64/boot/dts/nuvoton/Makefile +++ b/arch/arm64/boot/dts/nuvoton/Makefile @@ -1,2 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_NPCM) += nuvoton-npcm845-evb.dtb +dtb-$(CONFIG_ARCH_NUVOTON) += ma35d1-iot-512m.dtb +dtb-$(CONFIG_ARCH_NUVOTON) += ma35d1-som-256m.dtb diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts new file mode 100644 index 000000000000..b89e2be6abae --- /dev/null +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Shan-Chun Hung + * Jacky huang + */ + +/dts-v1/; +#include "ma35d1.dtsi" + +/ { + model = "Nuvoton MA35D1-IoT"; + compatible = "nuvoton,ma35d1-iot", "nuvoton,ma35d1"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + mem: memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x20000000>; /* 512M DRAM */ + }; + + clk_hxt: clock-hxt { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "clk_hxt"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&clk { + assigned-clocks = <&clk CAPLL>, + <&clk DDRPLL>, + <&clk APLL>, + <&clk EPLL>, + <&clk VPLL>; + assigned-clock-rates = <800000000>, + <266000000>, + <180000000>, + <500000000>, + <102000000>; + nuvoton,pll-mode = "integer", + "fractional", + "integer", + "integer", + "integer"; +}; diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts new file mode 100644 index 000000000000..a1ebddecb7f8 --- /dev/null +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Shan-Chun Hung + * Jacky huang + */ + +/dts-v1/; +#include "ma35d1.dtsi" + +/ { + model = "Nuvoton MA35D1-SOM"; + compatible = "nuvoton,ma35d1-som", "nuvoton,ma35d1"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + mem: memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x10000000>; /* 256M DRAM */ + }; + + clk_hxt: clock-hxt { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "clk_hxt"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&clk { + assigned-clocks = <&clk CAPLL>, + <&clk DDRPLL>, + <&clk APLL>, + <&clk EPLL>, + <&clk VPLL>; + assigned-clock-rates = <800000000>, + <266000000>, + <180000000>, + <500000000>, + <102000000>; + nuvoton,pll-mode = "integer", + "fractional", + "integer", + "integer", + "integer"; +}; diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi new file mode 100644 index 000000000000..0740b0b218a7 --- /dev/null +++ b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Shan-Chun Hung + * Jacky huang + */ + +#include +#include +#include +#include +#include + +/ { + compatible = "nuvoton,ma35d1"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + clock-frequency = <12000000>; + interrupt-parent = <&gic>; + }; + + sys: system-management@40460000 { + compatible = "nuvoton,ma35d1-sys", "syscon", "simple-mfd"; + reg = <0x0 0x40460000 0x0 0x200>; + + reset: reset-controller { + compatible = "nuvoton,ma35d1-reset"; + #reset-cells = <1>; + }; + }; + + clk: clock-controller@40460200 { + compatible = "nuvoton,ma35d1-clk", "syscon"; + reg = <0x00000000 0x40460200 0x0 0x100>; + #clock-cells = <1>; + clocks = <&clk_hxt>; + nuvoton,sys = <&sys>; + }; + + gic: interrupt-controller@50801000 { + compatible = "arm,gic-400"; + reg = <0x0 0x50801000 0 0x1000>, /* GICD */ + <0x0 0x50802000 0 0x2000>, /* GICC */ + <0x0 0x50804000 0 0x2000>, /* GICH */ + <0x0 0x50806000 0 0x2000>; /* GICV */ + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + interrupts = ; + }; + + uart0:serial@40700000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40700000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART0_GATE>; + status = "disabled"; + }; + + uart1:serial@40710000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40710000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART1_GATE>; + status = "disabled"; + }; + + uart2:serial@40720000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40720000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART2_GATE>; + status = "disabled"; + }; + + uart3:serial@40730000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40730000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART3_GATE>; + status = "disabled"; + }; + + uart4:serial@40740000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40740000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART4_GATE>; + status = "disabled"; + }; + + uart5:serial@40750000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40750000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART5_GATE>; + status = "disabled"; + }; + + uart6:serial@40760000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40760000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART6_GATE>; + status = "disabled"; + }; + + uart7:serial@40770000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40770000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART7_GATE>; + status = "disabled"; + }; + + uart8:serial@40780000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40780000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART8_GATE>; + status = "disabled"; + }; + + uart9:serial@40790000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40790000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART9_GATE>; + status = "disabled"; + }; + + uart10:serial@407a0000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x407a0000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART10_GATE>; + status = "disabled"; + }; + + uart11:serial@407b0000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x407b0000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART11_GATE>; + status = "disabled"; + }; + + uart12:serial@407c0000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x407c0000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART12_GATE>; + status = "disabled"; + }; + + uart13:serial@407d0000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x407d0000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART13_GATE>; + status = "disabled"; + }; + + uart14:serial@407e0000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x407e0000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART14_GATE>; + status = "disabled"; + }; + + uart15:serial@407f0000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x407f0000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART15_GATE>; + status = "disabled"; + }; + + uart16:serial@40880000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40880000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART16_GATE>; + status = "disabled"; + }; +}; From patchwork Tue Mar 28 02:19:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Huang X-Patchwork-Id: 668086 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 612CAC761A6 for ; Tue, 28 Mar 2023 02:20:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232729AbjC1CUi (ORCPT ); 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id f17-20020a17090ac29100b00232cc61e16bsm5029301pjt.35.2023.03.27.19.19.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 19:19:45 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, arnd@arndb.de, schung@nuvoton.com, mjchen@nuvoton.com, Jacky Huang Subject: [PATCH v6 09/12] clk: nuvoton: Add clock driver for ma35d1 clock controller Date: Tue, 28 Mar 2023 02:19:09 +0000 Message-Id: <20230328021912.177301-10-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230328021912.177301-1-ychuang570808@gmail.com> References: <20230328021912.177301-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Jacky Huang The clock controller generates clocks for the whole chip, including system clocks and all peripheral clocks. This driver support ma35d1 clock gating, divider, and individual PLL configuration. There are 6 PLLs in ma35d1 SoC: - CA-PLL for the two Cortex-A35 CPU clock - SYS-PLL for system bus, which comes from the companion MCU and cannot be programmed by clock controller. - DDR-PLL for DDR - EPLL for GMAC and GFX, Display, and VDEC IPs. - VPLL for video output pixel clock - APLL for SDHC, I2S audio, and other IPs. CA-PLL has only one operation mode. DDR-PLL, EPLL, VPLL, and APLL are advanced PLLs which have 3 operation modes: integer mode, fraction mode, and spread specturm mode. Signed-off-by: Jacky Huang --- drivers/clk/Makefile | 1 + drivers/clk/nuvoton/Kconfig | 19 + drivers/clk/nuvoton/Makefile | 4 + drivers/clk/nuvoton/clk-ma35d1-divider.c | 140 ++++ drivers/clk/nuvoton/clk-ma35d1-pll.c | 350 ++++++++ drivers/clk/nuvoton/clk-ma35d1.c | 963 +++++++++++++++++++++++ drivers/clk/nuvoton/clk-ma35d1.h | 123 +++ 7 files changed, 1600 insertions(+) create mode 100644 drivers/clk/nuvoton/Kconfig create mode 100644 drivers/clk/nuvoton/Makefile create mode 100644 drivers/clk/nuvoton/clk-ma35d1-divider.c create mode 100644 drivers/clk/nuvoton/clk-ma35d1-pll.c create mode 100644 drivers/clk/nuvoton/clk-ma35d1.c create mode 100644 drivers/clk/nuvoton/clk-ma35d1.h diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index e3ca0d058a25..2e7916d269e1 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -103,6 +103,7 @@ endif obj-y += mstar/ obj-y += mvebu/ obj-$(CONFIG_ARCH_MXS) += mxs/ +obj-$(CONFIG_ARCH_NUVOTON) += nuvoton/ obj-$(CONFIG_COMMON_CLK_NXP) += nxp/ obj-$(CONFIG_COMMON_CLK_PISTACHIO) += pistachio/ obj-$(CONFIG_COMMON_CLK_PXA) += pxa/ diff --git a/drivers/clk/nuvoton/Kconfig b/drivers/clk/nuvoton/Kconfig new file mode 100644 index 000000000000..c1324efedcb9 --- /dev/null +++ b/drivers/clk/nuvoton/Kconfig @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0 +# common clock support for Nuvoton SoC family. + +config COMMON_CLK_NUVOTON + bool "Nuvoton clock controller common support" + depends on ARCH_NUVOTON + default ARCH_NUVOTON + help + Say y here to enable common clock controller for Nuvoton platforms. + +if COMMON_CLK_NUVOTON +config CLK_MA35D1 + bool "Nuvoton MA35D1 clock controller support" + depends on ARM64 || COMPILE_TEST + default y + help + Build the driver for MA35D1 Clock Driver. + +endif diff --git a/drivers/clk/nuvoton/Makefile b/drivers/clk/nuvoton/Makefile new file mode 100644 index 000000000000..d2c092541b8d --- /dev/null +++ b/drivers/clk/nuvoton/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_ARCH_NUVOTON) += clk-ma35d1.o +obj-$(CONFIG_ARCH_NUVOTON) += clk-ma35d1-divider.o +obj-$(CONFIG_ARCH_NUVOTON) += clk-ma35d1-pll.o diff --git a/drivers/clk/nuvoton/clk-ma35d1-divider.c b/drivers/clk/nuvoton/clk-ma35d1-divider.c new file mode 100644 index 000000000000..340a889a1417 --- /dev/null +++ b/drivers/clk/nuvoton/clk-ma35d1-divider.c @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Chi-Fang Li + */ + +#include +#include +#include +#include + +#include "clk-ma35d1.h" + +#define clk_div_mask(width) ((1 << (width)) - 1) + +struct ma35d1_adc_clk_div { + struct clk_hw hw; + void __iomem *reg; + u8 shift; + u8 width; + u32 mask; + const struct clk_div_table *table; + /* protects concurrent access to clock divider registers */ + spinlock_t *lock; +}; + +static inline struct ma35d1_adc_clk_div *to_ma35d1_adc_clk_div(struct clk_hw *_hw) +{ + return container_of(_hw, struct ma35d1_adc_clk_div, hw); +} + +static inline unsigned long ma35d1_clkdiv_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + unsigned int val; + struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw); + + val = readl_relaxed(dclk->reg) >> dclk->shift; + val &= clk_div_mask(dclk->width); + val += 1; + return divider_recalc_rate(hw, parent_rate, val, dclk->table, + CLK_DIVIDER_ROUND_CLOSEST, dclk->width); +} + +static inline long ma35d1_clkdiv_round_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long *prate) +{ + struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw); + + return divider_round_rate(hw, rate, prate, dclk->table, + dclk->width, CLK_DIVIDER_ROUND_CLOSEST); +} + +static inline int ma35d1_clkdiv_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + int value; + unsigned long flags = 0; + u32 data; + struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw); + + value = divider_get_val(rate, parent_rate, dclk->table, + dclk->width, CLK_DIVIDER_ROUND_CLOSEST); + + if (dclk->lock) + spin_lock_irqsave(dclk->lock, flags); + + data = readl_relaxed(dclk->reg); + data &= ~(clk_div_mask(dclk->width) << dclk->shift); + data |= (value - 1) << dclk->shift; + data |= dclk->mask; + + writel_relaxed(data, dclk->reg); + + if (dclk->lock) + spin_unlock_irqrestore(dclk->lock, flags); + + return 0; +} + +static const struct clk_ops ma35d1_adc_clkdiv_ops = { + .recalc_rate = ma35d1_clkdiv_recalc_rate, + .round_rate = ma35d1_clkdiv_round_rate, + .set_rate = ma35d1_clkdiv_set_rate, +}; + +struct clk_hw *ma35d1_reg_adc_clkdiv(struct device *dev, const char *name, + const char *parent_name, + spinlock_t *lock, + unsigned long flags, void __iomem *reg, + u8 shift, u8 width, u32 mask_bit) +{ + struct ma35d1_adc_clk_div *div; + struct clk_init_data init; + struct clk_div_table *table; + u32 max_div, min_div; + struct clk_hw *hw; + int ret; + int i; + + div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); + if (!div) + return ERR_PTR(-ENOMEM); + + max_div = clk_div_mask(width) + 1; + min_div = 1; + + table = devm_kcalloc(dev, max_div + 1, sizeof(*table), GFP_KERNEL); + if (!table) + return ERR_PTR(-ENOMEM); + + for (i = 0; i < max_div; i++) { + table[i].val = (min_div + i); + table[i].div = 2 * table[i].val; + } + table[max_div].val = 0; + table[max_div].div = 0; + + init.name = name; + init.ops = &ma35d1_adc_clkdiv_ops; + init.flags |= flags; + init.parent_names = parent_name ? &parent_name : NULL; + init.num_parents = parent_name ? 1 : 0; + + div->reg = reg; + div->shift = shift; + div->width = width; + div->mask = mask_bit ? BIT(mask_bit) : 0; + div->lock = lock; + div->hw.init = &init; + div->table = table; + + hw = &div->hw; + ret = devm_clk_hw_register(dev, hw); + if (ret < 0) + return ERR_PTR(ret); + return hw; +} diff --git a/drivers/clk/nuvoton/clk-ma35d1-pll.c b/drivers/clk/nuvoton/clk-ma35d1-pll.c new file mode 100644 index 000000000000..b36fbda4fa0a --- /dev/null +++ b/drivers/clk/nuvoton/clk-ma35d1-pll.c @@ -0,0 +1,350 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Chi-Fang Li + */ + +#include +#include +#include +#include + +#include "clk-ma35d1.h" + +#define REG_SYS_RLKTZNS 0x1a4 /* Register Lock Control */ + +struct ma35d1_clk_pll { + struct clk_hw hw; + u8 type; + u8 mode; + unsigned long rate; + void __iomem *ctl0_base; + void __iomem *ctl1_base; + void __iomem *ctl2_base; + struct regmap *regmap; +}; + +static inline struct ma35d1_clk_pll *to_ma35d1_clk_pll(struct clk_hw *_hw) +{ + return container_of(_hw, struct ma35d1_clk_pll, hw); +} + +static void ma35d1_unlock_regs(struct ma35d1_clk_pll *pll) +{ + int ret; + + do { + regmap_write(pll->regmap, REG_SYS_RLKTZNS, 0x59); + regmap_write(pll->regmap, REG_SYS_RLKTZNS, 0x16); + regmap_write(pll->regmap, REG_SYS_RLKTZNS, 0x88); + regmap_read(pll->regmap, REG_SYS_RLKTZNS, &ret); + } while (ret == 0); +} + +static void ma35d1_lock_regs(struct ma35d1_clk_pll *pll) +{ + regmap_write(pll->regmap, REG_SYS_RLKTZNS, 0x0); +} + +static unsigned long ma35d1_calc_smic_pll_freq(u32 pll0_ctl0, + unsigned long parent_rate) +{ + u32 m, n, p, outdiv; + u64 pll_freq; + u32 clk_div_table[] = { 1, 2, 4, 8 }; + + if (pll0_ctl0 & SPLL0_CTL0_BP) + return parent_rate; + + n = FIELD_GET(SPLL0_CTL0_FBDIV, pll0_ctl0); + m = FIELD_GET(SPLL0_CTL0_INDIV, pll0_ctl0); + p = FIELD_GET(SPLL0_CTL0_OUTDIV, pll0_ctl0); + outdiv = clk_div_table[p]; + pll_freq = (u64)parent_rate * n; + do_div(pll_freq, m * outdiv); + return (unsigned long)pll_freq; +} + +static unsigned long ma35d1_calc_pll_freq(u8 mode, u32 *reg_ctl, + unsigned long parent_rate) +{ + u32 m, n, p; + u64 pll_freq, x; + + if (reg_ctl[1] & PLL_CTL1_BP) + return parent_rate; + + if (mode == PLL_MODE_INT) { + n = FIELD_GET(PLL_CTL0_FBDIV, reg_ctl[0]); + m = FIELD_GET(PLL_CTL0_INDIV, reg_ctl[0]); + p = FIELD_GET(PLL_CTL1_OUTDIV, reg_ctl[1]); + pll_freq = (u64)parent_rate * n; + do_div(pll_freq, m * p); + } else { + n = FIELD_GET(PLL_CTL0_FBDIV, reg_ctl[0]); + m = FIELD_GET(PLL_CTL0_INDIV, reg_ctl[0]); + p = FIELD_GET(PLL_CTL1_OUTDIV, reg_ctl[1]); + x = FIELD_GET(PLL_CTL1_FRAC, reg_ctl[1]); + /* 2 decimal places floating to integer (ex. 1.23 to 123) */ + n = n * 100 + ((x * 100) / FIELD_MAX(PLL_CTL1_FRAC)); + pll_freq = ((u64)parent_rate * n) / 100 / m / p; + } + return (unsigned long)pll_freq; +} + +static int ma35d1_pll_find_closest(struct ma35d1_clk_pll *pll, + unsigned long rate, + unsigned long parent_rate, + u32 *reg_ctl, unsigned long *freq) +{ + int p, m, n; + int fbdiv_min, fbdiv_max; + unsigned long diff = 0xffffffff; + + *freq = 0; + if ((rate < PLL_FCLKO_MIN_FREQ) || (rate > PLL_FCLKO_MAX_FREQ)) + return -EINVAL; + + if (pll->mode == PLL_MODE_INT) { + fbdiv_min = FBDIV_MIN; + fbdiv_max = FBDIV_MAX; + } else { + fbdiv_min = FBDIV_FRAC_MIN; + fbdiv_max = FBDIV_FRAC_MAX; + } + + for (m = INDIV_MIN; m <= INDIV_MAX; m++) { + for (n = fbdiv_min; n <= fbdiv_max; n++) { + for (p = OUTDIV_MIN; p <= OUTDIV_MAX; p++) { + unsigned long tmp, fout; + u64 fclk; + + tmp = parent_rate / m; + if (tmp < PLL_FREF_M_MIN_FREQ || + tmp > PLL_FREF_M_MAX_FREQ) + continue; /* constrain */ + + fclk = (u64)parent_rate * n / m; + /* for 2 decimal places */ + if (pll->mode != PLL_MODE_INT) + fclk /= 100; + + if (fclk < PLL_FCLK_MIN_FREQ || + fclk > PLL_FCLK_MAX_FREQ) + continue; /* constrain */ + + fout = (unsigned long)(fclk / p); + if (fout < PLL_FCLKO_MIN_FREQ || + fout > PLL_FCLKO_MAX_FREQ) + continue; /* constrain */ + + if (abs(rate - fout) < diff) { + reg_ctl[0] = FIELD_PREP(PLL_CTL0_INDIV, m) | + FIELD_PREP(PLL_CTL0_FBDIV, n); + reg_ctl[1] = FIELD_PREP(PLL_CTL1_OUTDIV, p); + *freq = fout; + diff = abs(rate - fout); + if (diff == 0) + break; + } + } + } + } + if (*freq == 0) + return -EINVAL; /* cannot find even one valid setting */ + return 0; +} + +static int ma35d1_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw); + u32 reg_ctl[3] = { 0 }; + unsigned long pll_freq; + int ret; + + if ((parent_rate < PLL_FREF_MIN_FREQ) || + (parent_rate > PLL_FREF_MAX_FREQ)) + return -EINVAL; + + if ((pll->type == MA35D1_CAPLL) || (pll->type == MA35D1_DDRPLL)) { + pr_warn("Nuvoton MA35D1 CAPLL/DDRPLL is read only.\n"); + return -EACCES; + } + + ret = ma35d1_pll_find_closest(pll, rate, parent_rate, reg_ctl, &pll_freq); + if (ret != 0) + return ret; + pll->rate = pll_freq; + + switch (pll->mode) { + case PLL_MODE_INT: + reg_ctl[0] |= FIELD_PREP(PLL_CTL0_MODE, PLL_MODE_INT); + break; + case PLL_MODE_FRAC: + reg_ctl[0] |= FIELD_PREP(PLL_CTL0_MODE, PLL_MODE_FRAC); + break; + case PLL_MODE_SS: + reg_ctl[0] |= FIELD_PREP(PLL_CTL0_MODE, PLL_MODE_SS) | + FIELD_PREP(PLL_CTL0_SSRATE, PLL_SS_RATE); + reg_ctl[2] = FIELD_PREP(PLL_CTL2_SLOPE, PLL_SLOPE); + break; + } + reg_ctl[1] |= PLL_CTL1_PD; + + ma35d1_unlock_regs(pll); + writel_relaxed(reg_ctl[0], pll->ctl0_base); + writel_relaxed(reg_ctl[1], pll->ctl1_base); + writel_relaxed(reg_ctl[2], pll->ctl2_base); + ma35d1_lock_regs(pll); + return 0; +} + +static unsigned long ma35d1_clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw); + u32 reg_ctl[3]; + unsigned long pll_freq; + + if ((parent_rate < PLL_FREF_MIN_FREQ) || (parent_rate > PLL_FREF_MAX_FREQ)) + return 0; + + switch (pll->type) { + case MA35D1_CAPLL: + reg_ctl[0] = readl_relaxed(pll->ctl0_base); + pll_freq = ma35d1_calc_smic_pll_freq(reg_ctl[0], parent_rate); + break; + case MA35D1_DDRPLL: + case MA35D1_APLL: + case MA35D1_EPLL: + case MA35D1_VPLL: + reg_ctl[0] = readl_relaxed(pll->ctl0_base); + reg_ctl[1] = readl_relaxed(pll->ctl1_base); + pll_freq = ma35d1_calc_pll_freq(pll->mode, reg_ctl, parent_rate); + break; + } + return pll_freq; +} + +static long ma35d1_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw); + u32 reg_ctl[3] = { 0 }; + unsigned long pll_freq; + long ret; + + if (*parent_rate < PLL_FREF_MIN_FREQ || *parent_rate > PLL_FREF_MAX_FREQ) + return -EINVAL; + + ret = ma35d1_pll_find_closest(pll, rate, *parent_rate, reg_ctl, &pll_freq); + if (ret != 0) + return ret; + + switch (pll->type) { + case MA35D1_CAPLL: + reg_ctl[0] = readl_relaxed(pll->ctl0_base); + pll_freq = ma35d1_calc_smic_pll_freq(reg_ctl[0], *parent_rate); + break; + case MA35D1_DDRPLL: + case MA35D1_APLL: + case MA35D1_EPLL: + case MA35D1_VPLL: + reg_ctl[0] = readl_relaxed(pll->ctl0_base); + reg_ctl[1] = readl_relaxed(pll->ctl1_base); + pll_freq = ma35d1_calc_pll_freq(pll->mode, reg_ctl, *parent_rate); + break; + } + return pll_freq; +} + +static int ma35d1_clk_pll_is_prepared(struct clk_hw *hw) +{ + struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw); + u32 val = readl_relaxed(pll->ctl1_base); + + return val & PLL_CTL1_PD ? 0 : 1; +} + +static int ma35d1_clk_pll_prepare(struct clk_hw *hw) +{ + struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw); + u32 val; + + if ((pll->type == MA35D1_CAPLL) || (pll->type == MA35D1_DDRPLL)) { + pr_warn("Nuvoton MA35D1 CAPLL/DDRPLL is read only.\n"); + return -EACCES; + } + + ma35d1_unlock_regs(pll); + val = readl_relaxed(pll->ctl1_base); + val &= ~PLL_CTL1_PD; + writel_relaxed(val, pll->ctl1_base); + ma35d1_lock_regs(pll); + return 0; +} + +static void ma35d1_clk_pll_unprepare(struct clk_hw *hw) +{ + struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw); + u32 val; + + if ((pll->type == MA35D1_CAPLL) || (pll->type == MA35D1_DDRPLL)) { + pr_warn("Nuvoton MA35D1 CAPLL/DDRPLL is read only.\n"); + } else { + val = readl_relaxed(pll->ctl1_base); + val |= PLL_CTL1_PD; + writel_relaxed(val, pll->ctl1_base); + } +} + +static const struct clk_ops ma35d1_clk_pll_ops = { + .is_prepared = ma35d1_clk_pll_is_prepared, + .prepare = ma35d1_clk_pll_prepare, + .unprepare = ma35d1_clk_pll_unprepare, + .set_rate = ma35d1_clk_pll_set_rate, + .recalc_rate = ma35d1_clk_pll_recalc_rate, + .round_rate = ma35d1_clk_pll_round_rate, +}; + +struct clk_hw *ma35d1_reg_clk_pll(enum ma35d1_pll_type type, + u8 u8mode, const char *name, + const char *parent, + unsigned long targetFreq, + void __iomem *base, + struct regmap *regmap) +{ + struct ma35d1_clk_pll *pll; + struct clk_hw *hw; + struct clk_init_data init; + int ret; + + pll = kmalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + pll->type = type; + pll->mode = u8mode; + pll->rate = targetFreq; + pll->ctl0_base = base + REG_PLL_CTL0_OFFSET; + pll->ctl1_base = base + REG_PLL_CTL1_OFFSET; + pll->ctl2_base = base + REG_PLL_CTL2_OFFSET; + pll->regmap = regmap; + + init.name = name; + init.flags = 0; + init.parent_names = &parent; + init.num_parents = 1; + init.ops = &ma35d1_clk_pll_ops; + pll->hw.init = &init; + hw = &pll->hw; + + ret = clk_hw_register(NULL, hw); + if (ret) { + pr_err("failed to register vsi-pll clock!!!\n"); + kfree(pll); + return ERR_PTR(ret); + } + return hw; +} diff --git a/drivers/clk/nuvoton/clk-ma35d1.c b/drivers/clk/nuvoton/clk-ma35d1.c new file mode 100644 index 000000000000..e4d3ced396a3 --- /dev/null +++ b/drivers/clk/nuvoton/clk-ma35d1.c @@ -0,0 +1,963 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Chi-Fang Li + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk-ma35d1.h" + +static DEFINE_SPINLOCK(ma35d1_lock); + +static const char *const ca35clk_sel_clks[] = { + "hxt", "capll", "ddrpll", "dummy" +}; + +static const char *const sysclk0_sel_clks[] = { + "epll_div2", "syspll" +}; + +static const char *const sysclk1_sel_clks[] = { + "hxt", "syspll" +}; + +static const char *const axiclk_sel_clks[] = { + "capll_div2", "capll_div4" +}; + +static const char *const ccap_sel_clks[] = { + "hxt", "vpll", "apll", "syspll" +}; + +static const char *const sdh_sel_clks[] = { + "syspll", "apll", "dummy", "dummy" +}; + +static const char *const dcu_sel_clks[] = { + "epll_div2", "syspll" +}; + +static const char *const gfx_sel_clks[] = { + "epll", "syspll" +}; + +static const char *const dbg_sel_clks[] = { + "hirc", "syspll" +}; + +static const char *const timer0_sel_clks[] = { + "hxt", "lxt", "pclk0", "dummy", "dummy", "lirc", "dummy", "hirc" +}; + +static const char *const timer1_sel_clks[] = { + "hxt", "lxt", "pclk0", "dummy", "dummy", "lirc", "dummy", "hirc" +}; + +static const char *const timer2_sel_clks[] = { + "hxt", "lxt", "pclk1", "dummy", "dummy", "lirc", "dummy", "hirc" +}; + +static const char *const timer3_sel_clks[] = { + "hxt", "lxt", "pclk1", "dummy", "dummy", "lirc", "dummy", "hirc" +}; + +static const char *const timer4_sel_clks[] = { + "hxt", "lxt", "pclk2", "dummy", "dummy", "lirc", "dummy", "hirc" +}; + +static const char *const timer5_sel_clks[] = { + "hxt", "lxt", "pclk2", "dummy", "dummy", "lirc", "dummy", "hirc" +}; + +static const char *const timer6_sel_clks[] = { + "hxt", "lxt", "pclk0", "dummy", "dummy", "lirc", "dummy", "hirc" +}; + +static const char *const timer7_sel_clks[] = { + "hxt", "lxt", "pclk0", "dummy", "dummy", "lirc", "dummy", "hirc" +}; + +static const char *const timer8_sel_clks[] = { + "hxt", "lxt", "pclk1", "dummy", "dummy", "lirc", "dummy", "hirc" +}; + +static const char *const timer9_sel_clks[] = { + "hxt", "lxt", "pclk1", "dummy", "dummy", "lirc", "dummy", "hirc" +}; + +static const char *const timer10_sel_clks[] = { + "hxt", "lxt", "pclk2", "dummy", "dummy", "lirc", "dummy", "hirc" +}; + +static const char *const timer11_sel_clks[] = { + "hxt", "lxt", "pclk2", "dummy", "dummy", "lirc", "dummy", "hirc" +}; + +static const char *const uart_sel_clks[] = { + "hxt", "sysclk1_div2", "dummy", "dummy" +}; + +static const char *const wdt0_sel_clks[] = { + "dummy", "lxt", "pclk3_div4096", "lirc" +}; + +static const char *const wdt1_sel_clks[] = { + "dummy", "lxt", "pclk3_div4096", "lirc" +}; + +static const char *const wdt2_sel_clks[] = { + "dummy", "lxt", "pclk4_div4096", "lirc" +}; + +static const char *const wwdt0_sel_clks[] = { + "dummy", "dummy", "pclk3_div4096", "lirc" +}; + +static const char *const wwdt1_sel_clks[] = { + "dummy", "dummy", "pclk3_div4096", "lirc" +}; + +static const char *const wwdt2_sel_clks[] = { + "dummy", "dummy", "pclk4_div4096", "lirc" +}; + +static const char *const spi0_sel_clks[] = { + "pclk1", "apll", "dummy", "dummy" +}; + +static const char *const spi1_sel_clks[] = { + "pclk2", "apll", "dummy", "dummy" +}; + +static const char *const spi2_sel_clks[] = { + "pclk1", "apll", "dummy", "dummy" +}; + +static const char *const spi3_sel_clks[] = { + "pclk2", "apll", "dummy", "dummy" +}; + +static const char *const qspi0_sel_clks[] = { + "pclk0", "apll", "dummy", "dummy" +}; + +static const char *const qspi1_sel_clks[] = { + "pclk0", "apll", "dummy", "dummy" +}; + +static const char *const i2s0_sel_clks[] = { + "apll", "sysclk1_div2", "dummy", "dummy" +}; + +static const char *const i2s1_sel_clks[] = { + "apll", "sysclk1_div2", "dummy", "dummy" +}; + +static const char *const can_sel_clks[] = { + "apll", "vpll" +}; + +static const char *const cko_sel_clks[] = { + "hxt", "lxt", "hirc", "lirc", "capll_div4", "syspll", + "ddrpll", "epll_div2", "apll", "vpll", "dummy", "dummy", + "dummy", "dummy", "dummy", "dummy" +}; + +static const char *const smc_sel_clks[] = { + "hxt", "pclk4" +}; + +static const char *const kpi_sel_clks[] = { + "hxt", "lxt" +}; + +static const struct clk_div_table ip_div_table[] = { + {0, 2}, {1, 4}, {2, 6}, {3, 8}, {4, 10}, + {5, 12}, {6, 14}, {7, 16}, {0, 0}, +}; + +static const struct clk_div_table eadc_div_table[] = { + {0, 2}, {1, 4}, {2, 6}, {3, 8}, {4, 10}, + {5, 12}, {6, 14}, {7, 16}, {8, 18}, + {9, 20}, {10, 22}, {11, 24}, {12, 26}, + {13, 28}, {14, 30}, {15, 32}, {0, 0}, +}; + +static inline struct clk_hw *ma35d1_clk_fixed(const char *name, int rate) +{ + return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate); +} + +static inline struct clk_hw *ma35d1_clk_mux(const char *name, + void __iomem *reg, + u8 shift, u8 width, + const char *const *parents, + int num_parents) +{ + return clk_hw_register_mux(NULL, name, parents, num_parents, + CLK_SET_RATE_NO_REPARENT, reg, shift, + width, 0, &ma35d1_lock); +} + +static inline struct clk_hw *ma35d1_clk_divider(const char *name, + const char *parent, + void __iomem *reg, u8 shift, + u8 width) +{ + return clk_hw_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, + reg, shift, width, 0, &ma35d1_lock); +} + +static inline struct clk_hw *ma35d1_clk_divider_pow2(const char *name, + const char *parent, + void __iomem *reg, + u8 shift, u8 width) +{ + return clk_hw_register_divider(NULL, name, parent, + CLK_DIVIDER_POWER_OF_TWO, reg, shift, + width, 0, &ma35d1_lock); +} + +static inline struct clk_hw *ma35d1_clk_divider_table(const char *name, + const char *parent, + void __iomem *reg, + u8 shift, u8 width, + const struct clk_div_table *table) +{ + return clk_hw_register_divider_table(NULL, name, parent, 0, + reg, shift, width, 0, table, + &ma35d1_lock); +} + +static inline struct clk_hw *ma35d1_clk_fixed_factor(const char *name, + const char *parent, + unsigned int mult, + unsigned int div) +{ + return clk_hw_register_fixed_factor(NULL, name, parent, + CLK_SET_RATE_PARENT, mult, div); +} + +static inline struct clk_hw *ma35d1_clk_gate(const char *name, + const char *parent, + void __iomem *reg, u8 shift) +{ + return clk_hw_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, + reg, shift, 0, &ma35d1_lock); +} + +static int ma35d1_get_pll_setting(struct device_node *clk_node, + u32 *pllmode, u32 *pllfreq) +{ + const char *of_str; + int i; + + for (i = 0; i < PLL_MAX_NUM; i++) { + if (of_property_read_string_index(clk_node, "nuvoton,pll-mode", i, &of_str)) + return -EINVAL; + if (!strcmp(of_str, "integer")) + pllmode[i] = PLL_MODE_INT; + else if (!strcmp(of_str, "fractional")) + pllmode[i] = PLL_MODE_FRAC; + else if (!strcmp(of_str, "spread-spectrum")) + pllmode[i] = PLL_MODE_SS; + else + return -EINVAL; + } + return of_property_read_u32_array(clk_node, "assigned-clock-rates", + pllfreq, PLL_MAX_NUM); +} + +static int ma35d1_clocks_probe(struct platform_device *pdev) +{ + struct device_node *clk_node = pdev->dev.of_node; + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + void __iomem *clk_base; + struct regmap *regmap; + static struct clk_hw **hws; + static struct clk_hw_onecell_data *ma35d1_hw_data; + u32 pllmode[PLL_MAX_NUM]; + u32 pllfreq[PLL_MAX_NUM]; + int ret; + + ma35d1_hw_data = devm_kzalloc(&pdev->dev, struct_size(ma35d1_hw_data, + hws, CLK_MAX_IDX), GFP_KERNEL); + if (WARN_ON(!ma35d1_hw_data)) + return -ENOMEM; + + ma35d1_hw_data->num = CLK_MAX_IDX; + hws = ma35d1_hw_data->hws; + + clk_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(clk_base)) + return PTR_ERR(clk_base); + + regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "nuvoton,sys"); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + ret = ma35d1_get_pll_setting(clk_node, pllmode, pllfreq); + if (ret < 0) { + dev_err(&pdev->dev, "Invalid PLL setting!\n"); + return -EINVAL; + } + + hws[HXT] = ma35d1_clk_fixed("hxt", 24000000); + hws[HXT_GATE] = ma35d1_clk_gate("hxt_gate", "hxt", + clk_base + REG_CLK_PWRCTL, 0); + hws[LXT] = ma35d1_clk_fixed("lxt", 32768); + hws[LXT_GATE] = ma35d1_clk_gate("lxt_gate", "lxt", + clk_base + REG_CLK_PWRCTL, 1); + hws[HIRC] = ma35d1_clk_fixed("hirc", 12000000); + hws[HIRC_GATE] = ma35d1_clk_gate("hirc_gate", "hirc", + clk_base + REG_CLK_PWRCTL, 2); + hws[LIRC] = ma35d1_clk_fixed("lirc", 32000); + hws[LIRC_GATE] = ma35d1_clk_gate("lirc_gate", "lirc", + clk_base + REG_CLK_PWRCTL, 3); + + hws[CAPLL] = ma35d1_reg_clk_pll(MA35D1_CAPLL, pllmode[0], "capll", + "hxt", pllfreq[0], + clk_base + REG_CLK_PLL0CTL0, regmap); + hws[SYSPLL] = ma35d1_clk_fixed("syspll", 180000000); + + hws[DDRPLL] = ma35d1_reg_clk_pll(MA35D1_DDRPLL, pllmode[1], + "ddrpll", "hxt", pllfreq[1], + clk_base + REG_CLK_PLL2CTL0, regmap); + hws[APLL] = ma35d1_reg_clk_pll(MA35D1_APLL, pllmode[2], "apll", "hxt", + pllfreq[2], clk_base + REG_CLK_PLL3CTL0, regmap); + hws[EPLL] = ma35d1_reg_clk_pll(MA35D1_EPLL, pllmode[3], "epll", "hxt", + pllfreq[3], clk_base + REG_CLK_PLL4CTL0, regmap); + hws[VPLL] = ma35d1_reg_clk_pll(MA35D1_VPLL, pllmode[4], "vpll", "hxt", + pllfreq[4], clk_base + REG_CLK_PLL5CTL0, regmap); + hws[EPLL_DIV2] = ma35d1_clk_fixed_factor("epll_div2", "epll", 1, 2); + hws[EPLL_DIV4] = ma35d1_clk_fixed_factor("epll_div4", "epll", 1, 4); + hws[EPLL_DIV8] = ma35d1_clk_fixed_factor("epll_div8", "epll", 1, 8); + + hws[CA35CLK_MUX] = ma35d1_clk_mux("ca35clk_mux", clk_base + REG_CLK_CLKSEL0, 0, 2, + ca35clk_sel_clks, ARRAY_SIZE(ca35clk_sel_clks)); + hws[AXICLK_DIV2] = ma35d1_clk_fixed_factor("capll_div2", "ca35clk_mux", 1, 2); + hws[AXICLK_DIV4] = ma35d1_clk_fixed_factor("capll_div4", "ca35clk_mux", 1, 4); + hws[AXICLK_MUX] = ma35d1_clk_mux("axiclk_mux", clk_base + REG_CLK_CLKDIV0, 26, 1, + axiclk_sel_clks, ARRAY_SIZE(axiclk_sel_clks)); + + hws[SYSCLK0_MUX] = ma35d1_clk_mux("sysclk0_mux", clk_base + REG_CLK_CLKSEL0, 2, 1, + sysclk0_sel_clks, ARRAY_SIZE(sysclk0_sel_clks)); + hws[SYSCLK1_MUX] = ma35d1_clk_mux("sysclk1_mux", clk_base + REG_CLK_CLKSEL0, 4, 1, + sysclk1_sel_clks, ARRAY_SIZE(sysclk1_sel_clks)); + hws[SYSCLK1_DIV2] = ma35d1_clk_fixed_factor("sysclk1_div2", "sysclk1_mux", 1, 2); + + /* HCLK0~3 & PCLK0~4 */ + hws[HCLK0] = ma35d1_clk_fixed_factor("hclk0", "sysclk1_mux", 1, 1); + hws[HCLK1] = ma35d1_clk_fixed_factor("hclk1", "sysclk1_mux", 1, 1); + hws[HCLK2] = ma35d1_clk_fixed_factor("hclk2", "sysclk1_mux", 1, 1); + hws[PCLK0] = ma35d1_clk_fixed_factor("pclk0", "sysclk1_mux", 1, 1); + hws[PCLK1] = ma35d1_clk_fixed_factor("pclk1", "sysclk1_mux", 1, 1); + hws[PCLK2] = ma35d1_clk_fixed_factor("pclk2", "sysclk1_mux", 1, 1); + + hws[HCLK3] = ma35d1_clk_fixed_factor("hclk3", "sysclk1_mux", 1, 2); + hws[PCLK3] = ma35d1_clk_fixed_factor("pclk3", "sysclk1_mux", 1, 2); + hws[PCLK4] = ma35d1_clk_fixed_factor("pclk4", "sysclk1_mux", 1, 2); + + hws[USBPHY0] = ma35d1_clk_fixed("usbphy0", 480000000); + hws[USBPHY1] = ma35d1_clk_fixed("usbphy1", 480000000); + + /* DDR */ + hws[DDR0_GATE] = ma35d1_clk_gate("ddr0_gate", "ddrpll", + clk_base + REG_CLK_SYSCLK0, 4); + hws[DDR6_GATE] = ma35d1_clk_gate("ddr6_gate", "ddrpll", + clk_base + REG_CLK_SYSCLK0, 5); + + hws[CAN0_MUX] = ma35d1_clk_mux("can0_mux", clk_base + REG_CLK_CLKSEL4, + 16, 1, + can_sel_clks, ARRAY_SIZE(can_sel_clks)); + hws[CAN0_DIV] = ma35d1_clk_divider_table("can0_div", "can0_mux", + clk_base + REG_CLK_CLKDIV0, + 0, 3, ip_div_table); + hws[CAN0_GATE] = ma35d1_clk_gate("can0_gate", "can0_div", + clk_base + REG_CLK_SYSCLK0, 8); + hws[CAN1_MUX] = ma35d1_clk_mux("can1_mux", clk_base + REG_CLK_CLKSEL4, + 17, 1, can_sel_clks, + ARRAY_SIZE(can_sel_clks)); + hws[CAN1_DIV] = ma35d1_clk_divider_table("can1_div", "can1_mux", + clk_base + REG_CLK_CLKDIV0, + 4, 3, ip_div_table); + hws[CAN1_GATE] = ma35d1_clk_gate("can1_gate", "can1_div", + clk_base + REG_CLK_SYSCLK0, 9); + hws[CAN2_MUX] = ma35d1_clk_mux("can2_mux", clk_base + REG_CLK_CLKSEL4, + 18, 1, can_sel_clks, + ARRAY_SIZE(can_sel_clks)); + hws[CAN2_DIV] = ma35d1_clk_divider_table("can2_div", "can2_mux", + clk_base + REG_CLK_CLKDIV0, + 8, 3, ip_div_table); + hws[CAN2_GATE] = ma35d1_clk_gate("can2_gate", "can2_div", + clk_base + REG_CLK_SYSCLK0, 10); + hws[CAN3_MUX] = ma35d1_clk_mux("can3_mux", clk_base + REG_CLK_CLKSEL4, + 19, 1, can_sel_clks, + ARRAY_SIZE(can_sel_clks)); + hws[CAN3_DIV] = ma35d1_clk_divider_table("can3_div", "can3_mux", + clk_base + REG_CLK_CLKDIV0, + 12, 3, ip_div_table); + hws[CAN3_GATE] = ma35d1_clk_gate("can3_gate", "can3_div", + clk_base + REG_CLK_SYSCLK0, 11); + + hws[SDH0_MUX] = ma35d1_clk_mux("sdh0_mux", clk_base + REG_CLK_CLKSEL0, + 16, 2, sdh_sel_clks, + ARRAY_SIZE(sdh_sel_clks)); + hws[SDH0_GATE] = ma35d1_clk_gate("sdh0_gate", "sdh0_mux", + clk_base + REG_CLK_SYSCLK0, 16); + hws[SDH1_MUX] = ma35d1_clk_mux("sdh1_mux", clk_base + REG_CLK_CLKSEL0, + 18, 2, sdh_sel_clks, + ARRAY_SIZE(sdh_sel_clks)); + hws[SDH1_GATE] = ma35d1_clk_gate("sdh1_gate", "sdh1_mux", + clk_base + REG_CLK_SYSCLK0, 17); + + hws[NAND_GATE] = ma35d1_clk_gate("nand_gate", "hclk1", + clk_base + REG_CLK_SYSCLK0, 18); + + hws[USBD_GATE] = ma35d1_clk_gate("usbd_gate", "usbphy0", + clk_base + REG_CLK_SYSCLK0, 19); + hws[USBH_GATE] = ma35d1_clk_gate("usbh_gate", "usbphy0", + clk_base + REG_CLK_SYSCLK0, 20); + hws[HUSBH0_GATE] = ma35d1_clk_gate("husbh0_gate", "usbphy0", + clk_base + REG_CLK_SYSCLK0, 21); + hws[HUSBH1_GATE] = ma35d1_clk_gate("husbh1_gate", "usbphy0", + clk_base + REG_CLK_SYSCLK0, 22); + + hws[GFX_MUX] = ma35d1_clk_mux("gfx_mux", clk_base + REG_CLK_CLKSEL0, + 26, 1, gfx_sel_clks, + ARRAY_SIZE(gfx_sel_clks)); + hws[GFX_GATE] = ma35d1_clk_gate("gfx_gate", "gfx_mux", + clk_base + REG_CLK_SYSCLK0, 24); + hws[VC8K_GATE] = ma35d1_clk_gate("vc8k_gate", "sysclk0_mux", + clk_base + REG_CLK_SYSCLK0, 25); + hws[DCU_MUX] = ma35d1_clk_mux("dcu_mux", clk_base + REG_CLK_CLKSEL0, + 24, 1, dcu_sel_clks, + ARRAY_SIZE(dcu_sel_clks)); + hws[DCU_GATE] = ma35d1_clk_gate("dcu_gate", "dcu_mux", + clk_base + REG_CLK_SYSCLK0, 26); + hws[DCUP_DIV] = ma35d1_clk_divider_table("dcup_div", "vpll", + clk_base + REG_CLK_CLKDIV0, + 16, 3, ip_div_table); + + hws[EMAC0_GATE] = ma35d1_clk_gate("emac0_gate", "epll_div2", + clk_base + REG_CLK_SYSCLK0, 27); + hws[EMAC1_GATE] = ma35d1_clk_gate("emac1_gate", "epll_div2", + clk_base + REG_CLK_SYSCLK0, 28); + + hws[CCAP0_MUX] = ma35d1_clk_mux("ccap0_mux", + clk_base + REG_CLK_CLKSEL0, + 12, 1, ccap_sel_clks, + ARRAY_SIZE(ccap_sel_clks)); + hws[CCAP0_DIV] = ma35d1_clk_divider("ccap0_div", "ccap0_mux", + clk_base + REG_CLK_CLKDIV1, 8, 4); + hws[CCAP0_GATE] = ma35d1_clk_gate("ccap0_gate", "ccap0_div", + clk_base + REG_CLK_SYSCLK0, 29); + hws[CCAP1_MUX] = ma35d1_clk_mux("ccap1_mux", + clk_base + REG_CLK_CLKSEL0, + 14, 1, ccap_sel_clks, + ARRAY_SIZE(ccap_sel_clks)); + hws[CCAP1_DIV] = ma35d1_clk_divider("ccap1_div", "ccap1_mux", + clk_base + REG_CLK_CLKDIV1, + 12, 4); + hws[CCAP1_GATE] = ma35d1_clk_gate("ccap1_gate", "ccap1_div", + clk_base + REG_CLK_SYSCLK0, 30); + + hws[PDMA0_GATE] = ma35d1_clk_gate("pdma0_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 0); + hws[PDMA1_GATE] = ma35d1_clk_gate("pdma1_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 1); + hws[PDMA2_GATE] = ma35d1_clk_gate("pdma2_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 2); + hws[PDMA3_GATE] = ma35d1_clk_gate("pdma3_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 3); + + hws[WH0_GATE] = ma35d1_clk_gate("wh0_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 4); + hws[WH1_GATE] = ma35d1_clk_gate("wh1_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 5); + + hws[HWS_GATE] = ma35d1_clk_gate("hws_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 6); + + hws[EBI_GATE] = ma35d1_clk_gate("ebi_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 7); + + hws[SRAM0_GATE] = ma35d1_clk_gate("sram0_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 8); + hws[SRAM1_GATE] = ma35d1_clk_gate("sram1_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 9); + + hws[ROM_GATE] = ma35d1_clk_gate("rom_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 10); + + hws[TRA_GATE] = ma35d1_clk_gate("tra_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 11); + + hws[DBG_MUX] = ma35d1_clk_mux("dbg_mux", clk_base + REG_CLK_CLKSEL0, + 27, 1, dbg_sel_clks, + ARRAY_SIZE(dbg_sel_clks)); + hws[DBG_GATE] = ma35d1_clk_gate("dbg_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 12); + + hws[CKO_MUX] = ma35d1_clk_mux("cko_mux", clk_base + REG_CLK_CLKSEL4, + 24, 4, cko_sel_clks, + ARRAY_SIZE(cko_sel_clks)); + hws[CKO_DIV] = ma35d1_clk_divider_pow2("cko_div", "cko_mux", + clk_base + REG_CLK_CLKOCTL, 0, 4); + hws[CKO_GATE] = ma35d1_clk_gate("cko_gate", "cko_div", + clk_base + REG_CLK_SYSCLK1, 13); + + hws[GTMR_GATE] = ma35d1_clk_gate("gtmr_gate", "hirc", + clk_base + REG_CLK_SYSCLK1, 14); + + hws[GPA_GATE] = ma35d1_clk_gate("gpa_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 16); + hws[GPB_GATE] = ma35d1_clk_gate("gpb_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 17); + hws[GPC_GATE] = ma35d1_clk_gate("gpc_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 18); + hws[GPD_GATE] = ma35d1_clk_gate("gpd_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 19); + hws[GPE_GATE] = ma35d1_clk_gate("gpe_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 20); + hws[GPF_GATE] = ma35d1_clk_gate("gpf_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 21); + hws[GPG_GATE] = ma35d1_clk_gate("gpg_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 22); + hws[GPH_GATE] = ma35d1_clk_gate("gph_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 23); + hws[GPI_GATE] = ma35d1_clk_gate("gpi_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 24); + hws[GPJ_GATE] = ma35d1_clk_gate("gpj_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 25); + hws[GPK_GATE] = ma35d1_clk_gate("gpk_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 26); + hws[GPL_GATE] = ma35d1_clk_gate("gpl_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 27); + hws[GPM_GATE] = ma35d1_clk_gate("gpm_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 28); + hws[GPN_GATE] = ma35d1_clk_gate("gpn_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 29); + + hws[TMR0_MUX] = ma35d1_clk_mux("tmr0_mux", clk_base + REG_CLK_CLKSEL1, + 0, 3, timer0_sel_clks, + ARRAY_SIZE(timer0_sel_clks)); + hws[TMR0_GATE] = ma35d1_clk_gate("tmr0_gate", "tmr0_mux", + clk_base + REG_CLK_APBCLK0, 0); + hws[TMR1_MUX] = ma35d1_clk_mux("tmr1_mux", clk_base + REG_CLK_CLKSEL1, + 4, 3, timer1_sel_clks, + ARRAY_SIZE(timer1_sel_clks)); + hws[TMR1_GATE] = ma35d1_clk_gate("tmr1_gate", "tmr1_mux", + clk_base + REG_CLK_APBCLK0, 1); + hws[TMR2_MUX] = ma35d1_clk_mux("tmr2_mux", clk_base + REG_CLK_CLKSEL1, + 8, 3, timer2_sel_clks, + ARRAY_SIZE(timer2_sel_clks)); + hws[TMR2_GATE] = ma35d1_clk_gate("tmr2_gate", "tmr2_mux", + clk_base + REG_CLK_APBCLK0, 2); + hws[TMR3_MUX] = ma35d1_clk_mux("tmr3_mux", clk_base + REG_CLK_CLKSEL1, + 12, 3, timer3_sel_clks, + ARRAY_SIZE(timer3_sel_clks)); + hws[TMR3_GATE] = ma35d1_clk_gate("tmr3_gate", "tmr3_mux", + clk_base + REG_CLK_APBCLK0, 3); + hws[TMR4_MUX] = ma35d1_clk_mux("tmr4_mux", clk_base + REG_CLK_CLKSEL1, + 16, 3, timer4_sel_clks, + ARRAY_SIZE(timer4_sel_clks)); + hws[TMR4_GATE] = ma35d1_clk_gate("tmr4_gate", "tmr4_mux", + clk_base + REG_CLK_APBCLK0, 4); + hws[TMR5_MUX] = ma35d1_clk_mux("tmr5_mux", clk_base + REG_CLK_CLKSEL1, + 20, 3, timer5_sel_clks, + ARRAY_SIZE(timer5_sel_clks)); + hws[TMR5_GATE] = ma35d1_clk_gate("tmr5_gate", "tmr5_mux", + clk_base + REG_CLK_APBCLK0, 5); + hws[TMR6_MUX] = ma35d1_clk_mux("tmr6_mux", clk_base + REG_CLK_CLKSEL1, + 24, 3, timer6_sel_clks, + ARRAY_SIZE(timer6_sel_clks)); + hws[TMR6_GATE] = ma35d1_clk_gate("tmr6_gate", "tmr6_mux", + clk_base + REG_CLK_APBCLK0, 6); + hws[TMR7_MUX] = ma35d1_clk_mux("tmr7_mux", clk_base + REG_CLK_CLKSEL1, + 28, 3, timer7_sel_clks, + ARRAY_SIZE(timer7_sel_clks)); + hws[TMR7_GATE] = ma35d1_clk_gate("tmr7_gate", "tmr7_mux", + clk_base + REG_CLK_APBCLK0, 7); + hws[TMR8_MUX] = ma35d1_clk_mux("tmr8_mux", clk_base + REG_CLK_CLKSEL2, + 0, 3, timer8_sel_clks, + ARRAY_SIZE(timer8_sel_clks)); + hws[TMR8_GATE] = ma35d1_clk_gate("tmr8_gate", "tmr8_mux", + clk_base + REG_CLK_APBCLK0, 8); + hws[TMR9_MUX] = ma35d1_clk_mux("tmr9_mux", clk_base + REG_CLK_CLKSEL2, + 4, 3, timer9_sel_clks, + ARRAY_SIZE(timer9_sel_clks)); + hws[TMR9_GATE] = ma35d1_clk_gate("tmr9_gate", "tmr9_mux", + clk_base + REG_CLK_APBCLK0, 9); + hws[TMR10_MUX] = ma35d1_clk_mux("tmr10_mux", + clk_base + REG_CLK_CLKSEL2, + 8, 3, timer10_sel_clks, + ARRAY_SIZE(timer10_sel_clks)); + hws[TMR10_GATE] = ma35d1_clk_gate("tmr10_gate", "tmr10_mux", + clk_base + REG_CLK_APBCLK0, 10); + hws[TMR11_MUX] = ma35d1_clk_mux("tmr11_mux", + clk_base + REG_CLK_CLKSEL2, + 12, 3, timer11_sel_clks, + ARRAY_SIZE(timer11_sel_clks)); + hws[TMR11_GATE] = ma35d1_clk_gate("tmr11_gate", "tmr11_mux", + clk_base + REG_CLK_APBCLK0, 11); + + hws[UART0_MUX] = ma35d1_clk_mux("uart0_mux", + clk_base + REG_CLK_CLKSEL2, + 16, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART0_DIV] = ma35d1_clk_divider("uart0_div", "uart0_mux", + clk_base + REG_CLK_CLKDIV1, + 16, 4); + hws[UART0_GATE] = ma35d1_clk_gate("uart0_gate", "uart0_div", + clk_base + REG_CLK_APBCLK0, 12); + hws[UART1_MUX] = ma35d1_clk_mux("uart1_mux", + clk_base + REG_CLK_CLKSEL2, + 18, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART1_DIV] = ma35d1_clk_divider("uart1_div", "uart1_mux", + clk_base + REG_CLK_CLKDIV1, + 20, 4); + hws[UART1_GATE] = ma35d1_clk_gate("uart1_gate", "uart1_div", + clk_base + REG_CLK_APBCLK0, 13); + hws[UART2_MUX] = ma35d1_clk_mux("uart2_mux", + clk_base + REG_CLK_CLKSEL2, + 20, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART2_DIV] = ma35d1_clk_divider("uart2_div", "uart2_mux", + clk_base + REG_CLK_CLKDIV1, + 24, 4); + hws[UART2_GATE] = ma35d1_clk_gate("uart2_gate", "uart2_div", + clk_base + REG_CLK_APBCLK0, 14); + hws[UART3_MUX] = ma35d1_clk_mux("uart3_mux", + clk_base + REG_CLK_CLKSEL2, + 22, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART3_DIV] = ma35d1_clk_divider("uart3_div", "uart3_mux", + clk_base + REG_CLK_CLKDIV1, + 28, 4); + hws[UART3_GATE] = ma35d1_clk_gate("uart3_gate", "uart3_div", + clk_base + REG_CLK_APBCLK0, 15); + hws[UART4_MUX] = ma35d1_clk_mux("uart4_mux", + clk_base + REG_CLK_CLKSEL2, + 24, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART4_DIV] = ma35d1_clk_divider("uart4_div", "uart4_mux", + clk_base + REG_CLK_CLKDIV2, + 0, 4); + hws[UART4_GATE] = ma35d1_clk_gate("uart4_gate", "uart4_div", + clk_base + REG_CLK_APBCLK0, 16); + hws[UART5_MUX] = ma35d1_clk_mux("uart5_mux", + clk_base + REG_CLK_CLKSEL2, + 26, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART5_DIV] = ma35d1_clk_divider("uart5_div", "uart5_mux", + clk_base + REG_CLK_CLKDIV2, + 4, 4); + hws[UART5_GATE] = ma35d1_clk_gate("uart5_gate", "uart5_div", + clk_base + REG_CLK_APBCLK0, 17); + hws[UART6_MUX] = ma35d1_clk_mux("uart6_mux", + clk_base + REG_CLK_CLKSEL2, + 28, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART6_DIV] = ma35d1_clk_divider("uart6_div", "uart6_mux", + clk_base + REG_CLK_CLKDIV2, + 8, 4); + hws[UART6_GATE] = ma35d1_clk_gate("uart6_gate", "uart6_div", + clk_base + REG_CLK_APBCLK0, 18); + hws[UART7_MUX] = ma35d1_clk_mux("uart7_mux", + clk_base + REG_CLK_CLKSEL2, + 30, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART7_DIV] = ma35d1_clk_divider("uart7_div", "uart7_mux", + clk_base + REG_CLK_CLKDIV2, + 12, 4); + hws[UART7_GATE] = ma35d1_clk_gate("uart7_gate", "uart7_div", + clk_base + REG_CLK_APBCLK0, 19); + hws[UART8_MUX] = ma35d1_clk_mux("uart8_mux", + clk_base + REG_CLK_CLKSEL3, + 0, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART8_DIV] = ma35d1_clk_divider("uart8_div", "uart8_mux", + clk_base + REG_CLK_CLKDIV2, + 16, 4); + hws[UART8_GATE] = ma35d1_clk_gate("uart8_gate", "uart8_div", + clk_base + REG_CLK_APBCLK0, 20); + hws[UART9_MUX] = ma35d1_clk_mux("uart9_mux", + clk_base + REG_CLK_CLKSEL3, + 2, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART9_DIV] = ma35d1_clk_divider("uart9_div", "uart9_mux", + clk_base + REG_CLK_CLKDIV2, + 20, 4); + hws[UART9_GATE] = ma35d1_clk_gate("uart9_gate", "uart9_div", + clk_base + REG_CLK_APBCLK0, 21); + hws[UART10_MUX] = ma35d1_clk_mux("uart10_mux", + clk_base + REG_CLK_CLKSEL3, + 4, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART10_DIV] = ma35d1_clk_divider("uart10_div", "uart10_mux", + clk_base + REG_CLK_CLKDIV2, + 24, 4); + hws[UART10_GATE] = ma35d1_clk_gate("uart10_gate", "uart10_div", + clk_base + REG_CLK_APBCLK0, 22); + hws[UART11_MUX] = ma35d1_clk_mux("uart11_mux", + clk_base + REG_CLK_CLKSEL3, + 6, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART11_DIV] = ma35d1_clk_divider("uart11_div", "uart11_mux", + clk_base + REG_CLK_CLKDIV2, + 28, 4); + hws[UART11_GATE] = ma35d1_clk_gate("uart11_gate", "uart11_div", + clk_base + REG_CLK_APBCLK0, 23); + hws[UART12_MUX] = ma35d1_clk_mux("uart12_mux", + clk_base + REG_CLK_CLKSEL3, + 8, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART12_DIV] = ma35d1_clk_divider("uart12_div", "uart12_mux", + clk_base + REG_CLK_CLKDIV3, + 0, 4); + hws[UART12_GATE] = ma35d1_clk_gate("uart12_gate", "uart12_div", + clk_base + REG_CLK_APBCLK0, 24); + hws[UART13_MUX] = ma35d1_clk_mux("uart13_mux", + clk_base + REG_CLK_CLKSEL3, + 10, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART13_DIV] = ma35d1_clk_divider("uart13_div", "uart13_mux", + clk_base + REG_CLK_CLKDIV3, + 4, 4); + hws[UART13_GATE] = ma35d1_clk_gate("uart13_gate", "uart13_div", + clk_base + REG_CLK_APBCLK0, 25); + hws[UART14_MUX] = ma35d1_clk_mux("uart14_mux", + clk_base + REG_CLK_CLKSEL3, + 12, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART14_DIV] = ma35d1_clk_divider("uart14_div", "uart14_mux", + clk_base + REG_CLK_CLKDIV3, + 8, 4); + hws[UART14_GATE] = ma35d1_clk_gate("uart14_gate", "uart14_div", + clk_base + REG_CLK_APBCLK0, 26); + hws[UART15_MUX] = ma35d1_clk_mux("uart15_mux", + clk_base + REG_CLK_CLKSEL3, + 14, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART15_DIV] = ma35d1_clk_divider("uart15_div", "uart15_mux", + clk_base + REG_CLK_CLKDIV3, + 12, 4); + hws[UART15_GATE] = ma35d1_clk_gate("uart15_gate", "uart15_div", + clk_base + REG_CLK_APBCLK0, 27); + hws[UART16_MUX] = ma35d1_clk_mux("uart16_mux", + clk_base + REG_CLK_CLKSEL3, + 16, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART16_DIV] = ma35d1_clk_divider("uart16_div", "uart16_mux", + clk_base + REG_CLK_CLKDIV3, + 16, 4); + hws[UART16_GATE] = ma35d1_clk_gate("uart16_gate", "uart16_div", + clk_base + REG_CLK_APBCLK0, 28); + + hws[RTC_GATE] = ma35d1_clk_gate("rtc_gate", "lxt", + clk_base + REG_CLK_APBCLK0, 29); + hws[DDR_GATE] = ma35d1_clk_gate("ddr_gate", "ddrpll", + clk_base + REG_CLK_APBCLK0, 30); + + hws[KPI_MUX] = ma35d1_clk_mux("kpi_mux", clk_base + REG_CLK_CLKSEL4, + 30, 1, kpi_sel_clks, + ARRAY_SIZE(kpi_sel_clks)); + hws[KPI_DIV] = ma35d1_clk_divider("kpi_div", "kpi_mux", + clk_base + REG_CLK_CLKDIV4, + 24, 8); + hws[KPI_GATE] = ma35d1_clk_gate("kpi_gate", "kpi_div", + clk_base + REG_CLK_APBCLK0, 31); + + hws[I2C0_GATE] = ma35d1_clk_gate("i2c0_gate", "pclk0", + clk_base + REG_CLK_APBCLK1, 0); + hws[I2C1_GATE] = ma35d1_clk_gate("i2c1_gate", "pclk1", + clk_base + REG_CLK_APBCLK1, 1); + hws[I2C2_GATE] = ma35d1_clk_gate("i2c2_gate", "pclk2", + clk_base + REG_CLK_APBCLK1, 2); + hws[I2C3_GATE] = ma35d1_clk_gate("i2c3_gate", "pclk0", + clk_base + REG_CLK_APBCLK1, 3); + hws[I2C4_GATE] = ma35d1_clk_gate("i2c4_gate", "pclk1", + clk_base + REG_CLK_APBCLK1, 4); + hws[I2C5_GATE] = ma35d1_clk_gate("i2c5_gate", "pclk2", + clk_base + REG_CLK_APBCLK1, 5); + + hws[QSPI0_MUX] = ma35d1_clk_mux("qspi0_mux", + clk_base + REG_CLK_CLKSEL4, + 8, 2, qspi0_sel_clks, + ARRAY_SIZE(qspi0_sel_clks)); + hws[QSPI0_GATE] = ma35d1_clk_gate("qspi0_gate", "qspi0_mux", + clk_base + REG_CLK_APBCLK1, 6); + hws[QSPI1_MUX] = ma35d1_clk_mux("qspi1_mux", + clk_base + REG_CLK_CLKSEL4, + 10, 2, qspi1_sel_clks, + ARRAY_SIZE(qspi1_sel_clks)); + hws[QSPI1_GATE] = ma35d1_clk_gate("qspi1_gate", "qspi1_mux", + clk_base + REG_CLK_APBCLK1, 7); + + hws[SMC0_MUX] = ma35d1_clk_mux("smc0_mux", + clk_base + REG_CLK_CLKSEL4, + 28, 1, smc_sel_clks, + ARRAY_SIZE(smc_sel_clks)); + hws[SMC0_DIV] = ma35d1_clk_divider("smc0_div", "smc0_mux", + clk_base + REG_CLK_CLKDIV1, + 0, 4); + hws[SMC0_GATE] = ma35d1_clk_gate("smc0_gate", "smc0_div", + clk_base + REG_CLK_APBCLK1, 12); + hws[SMC1_MUX] = ma35d1_clk_mux("smc1_mux", + clk_base + REG_CLK_CLKSEL4, + 29, 1, smc_sel_clks, + ARRAY_SIZE(smc_sel_clks)); + hws[SMC1_DIV] = ma35d1_clk_divider("smc1_div", "smc1_mux", + clk_base + REG_CLK_CLKDIV1, + 4, 4); + hws[SMC1_GATE] = ma35d1_clk_gate("smc1_gate", "smc1_div", + clk_base + REG_CLK_APBCLK1, 13); + + hws[WDT0_MUX] = ma35d1_clk_mux("wdt0_mux", + clk_base + REG_CLK_CLKSEL3, + 20, 2, wdt0_sel_clks, + ARRAY_SIZE(wdt0_sel_clks)); + hws[WDT0_GATE] = ma35d1_clk_gate("wdt0_gate", "wdt0_mux", + clk_base + REG_CLK_APBCLK1, 16); + hws[WDT1_MUX] = ma35d1_clk_mux("wdt1_mux", + clk_base + REG_CLK_CLKSEL3, + 24, 2, wdt1_sel_clks, + ARRAY_SIZE(wdt1_sel_clks)); + hws[WDT1_GATE] = ma35d1_clk_gate("wdt1_gate", "wdt1_mux", + clk_base + REG_CLK_APBCLK1, 17); + hws[WDT2_MUX] = ma35d1_clk_mux("wdt2_mux", + clk_base + REG_CLK_CLKSEL3, + 28, 2, wdt2_sel_clks, + ARRAY_SIZE(wdt2_sel_clks)); + hws[WDT2_GATE] = ma35d1_clk_gate("wdt2_gate", "wdt2_mux", + clk_base + REG_CLK_APBCLK1, 18); + + hws[WWDT0_MUX] = ma35d1_clk_mux("wwdt0_mux", + clk_base + REG_CLK_CLKSEL3, + 22, 2, wwdt0_sel_clks, + ARRAY_SIZE(wwdt0_sel_clks)); + hws[WWDT1_MUX] = ma35d1_clk_mux("wwdt1_mux", + clk_base + REG_CLK_CLKSEL3, + 26, 2, wwdt1_sel_clks, + ARRAY_SIZE(wwdt1_sel_clks)); + hws[WWDT2_MUX] = ma35d1_clk_mux("wwdt2_mux", + clk_base + REG_CLK_CLKSEL3, + 30, 2, wwdt2_sel_clks, + ARRAY_SIZE(wwdt2_sel_clks)); + + hws[EPWM0_GATE] = ma35d1_clk_gate("epwm0_gate", "pclk1", + clk_base + REG_CLK_APBCLK1, 24); + hws[EPWM1_GATE] = ma35d1_clk_gate("epwm1_gate", "pclk2", + clk_base + REG_CLK_APBCLK1, 25); + hws[EPWM2_GATE] = ma35d1_clk_gate("epwm2_gate", "pclk1", + clk_base + REG_CLK_APBCLK1, 26); + + hws[I2S0_MUX] = ma35d1_clk_mux("i2s0_mux", + clk_base + REG_CLK_CLKSEL4, + 12, 2, i2s0_sel_clks, + ARRAY_SIZE(i2s0_sel_clks)); + hws[I2S0_GATE] = ma35d1_clk_gate("i2s0_gate", "i2s0_mux", + clk_base + REG_CLK_APBCLK2, 0); + hws[I2S1_MUX] = ma35d1_clk_mux("i2s1_mux", + clk_base + REG_CLK_CLKSEL4, + 14, 2, i2s1_sel_clks, + ARRAY_SIZE(i2s1_sel_clks)); + hws[I2S1_GATE] = ma35d1_clk_gate("i2s1_gate", "i2s1_mux", + clk_base + REG_CLK_APBCLK2, 1); + + hws[SSMCC_GATE] = ma35d1_clk_gate("ssmcc_gate", "pclk3", + clk_base + REG_CLK_APBCLK2, 2); + hws[SSPCC_GATE] = ma35d1_clk_gate("sspcc_gate", "pclk3", + clk_base + REG_CLK_APBCLK2, 3); + + hws[SPI0_MUX] = ma35d1_clk_mux("spi0_mux", + clk_base + REG_CLK_CLKSEL4, + 0, 2, spi0_sel_clks, + ARRAY_SIZE(spi0_sel_clks)); + hws[SPI0_GATE] = ma35d1_clk_gate("spi0_gate", "spi0_mux", + clk_base + REG_CLK_APBCLK2, 4); + hws[SPI1_MUX] = ma35d1_clk_mux("spi1_mux", + clk_base + REG_CLK_CLKSEL4, + 2, 2, spi1_sel_clks, + ARRAY_SIZE(spi1_sel_clks)); + hws[SPI1_GATE] = ma35d1_clk_gate("spi1_gate", "spi1_mux", + clk_base + REG_CLK_APBCLK2, 5); + hws[SPI2_MUX] = ma35d1_clk_mux("spi2_mux", + clk_base + REG_CLK_CLKSEL4, + 4, 2, spi2_sel_clks, + ARRAY_SIZE(spi2_sel_clks)); + hws[SPI2_GATE] = ma35d1_clk_gate("spi2_gate", "spi2_mux", + clk_base + REG_CLK_APBCLK2, 6); + hws[SPI3_MUX] = ma35d1_clk_mux("spi3_mux", + clk_base + REG_CLK_CLKSEL4, + 6, 2, spi3_sel_clks, + ARRAY_SIZE(spi3_sel_clks)); + hws[SPI3_GATE] = ma35d1_clk_gate("spi3_gate", "spi3_mux", + clk_base + REG_CLK_APBCLK2, 7); + + hws[ECAP0_GATE] = ma35d1_clk_gate("ecap0_gate", "pclk1", + clk_base + REG_CLK_APBCLK2, 8); + hws[ECAP1_GATE] = ma35d1_clk_gate("ecap1_gate", "pclk2", + clk_base + REG_CLK_APBCLK2, 9); + hws[ECAP2_GATE] = ma35d1_clk_gate("ecap2_gate", "pclk1", + clk_base + REG_CLK_APBCLK2, 10); + + hws[QEI0_GATE] = ma35d1_clk_gate("qei0_gate", "pclk1", + clk_base + REG_CLK_APBCLK2, 12); + hws[QEI1_GATE] = ma35d1_clk_gate("qei1_gate", "pclk2", + clk_base + REG_CLK_APBCLK2, 13); + hws[QEI2_GATE] = ma35d1_clk_gate("qei2_gate", "pclk1", + clk_base + REG_CLK_APBCLK2, 14); + + hws[ADC_DIV] = ma35d1_reg_adc_clkdiv(&pdev->dev, "adc_div", "pclk0", + &ma35d1_lock, 0, + clk_base + REG_CLK_CLKDIV4, + 4, 17, 0x1ffff); + hws[ADC_GATE] = ma35d1_clk_gate("adc_gate", "adc_div", + clk_base + REG_CLK_APBCLK2, 24); + + hws[EADC_DIV] = ma35d1_clk_divider_table("eadc_div", "pclk2", + clk_base + REG_CLK_CLKDIV4, + 0, 4, eadc_div_table); + hws[EADC_GATE] = ma35d1_clk_gate("eadc_gate", "eadc_div", + clk_base + REG_CLK_APBCLK2, 25); + + return devm_of_clk_add_hw_provider(&pdev->dev, + of_clk_hw_onecell_get, + ma35d1_hw_data); +} + +static const struct of_device_id ma35d1_clk_of_match[] = { + { .compatible = "nuvoton,ma35d1-clk" }, + { } +}; +MODULE_DEVICE_TABLE(of, ma35d1_clk_of_match); + +static struct platform_driver ma35d1_clk_driver = { + .probe = ma35d1_clocks_probe, + .driver = { + .name = "ma35d1-clk", + .of_match_table = ma35d1_clk_of_match, + }, +}; + +static int __init ma35d1_clocks_init(void) +{ + return platform_driver_register(&ma35d1_clk_driver); +} + +postcore_initcall(ma35d1_clocks_init); + +MODULE_AUTHOR("Chi-Fang Li "); +MODULE_DESCRIPTION("NUVOTON MA35D1 Clock Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/nuvoton/clk-ma35d1.h b/drivers/clk/nuvoton/clk-ma35d1.h new file mode 100644 index 000000000000..2c47667bfd5d --- /dev/null +++ b/drivers/clk/nuvoton/clk-ma35d1.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Chi-Fang Li + */ + +#ifndef __DRV_CLK_NUVOTON_MA35D1_H +#define __DRV_CLK_NUVOTON_MA35D1_H + +enum ma35d1_pll_type { + MA35D1_CAPLL, + MA35D1_DDRPLL, + MA35D1_APLL, + MA35D1_EPLL, + MA35D1_VPLL, +}; + +enum ma35d1_pll_mode { + PLL_MODE_INT, + PLL_MODE_FRAC, + PLL_MODE_SS, +}; + +#define PLL_MAX_NUM 5 + +/* PLL frequency limits */ +#define PLL_FREF_MAX_FREQ 200000000UL +#define PLL_FREF_MIN_FREQ 1000000UL +#define PLL_FREF_M_MAX_FREQ 40000000UL +#define PLL_FREF_M_MIN_FREQ 10000000UL +#define PLL_FCLK_MAX_FREQ 2400000000UL +#define PLL_FCLK_MIN_FREQ 600000000UL +#define PLL_FCLKO_MAX_FREQ 2400000000UL +#define PLL_FCLKO_MIN_FREQ 85700000UL +#define PLL_SS_RATE 0x77 +#define PLL_SLOPE 0x58CFA + +/* Clock Control Registers Offset */ +#define REG_CLK_PWRCTL 0x00 +#define REG_CLK_SYSCLK0 0x04 +#define REG_CLK_SYSCLK1 0x08 +#define REG_CLK_APBCLK0 0x0C +#define REG_CLK_APBCLK1 0x10 +#define REG_CLK_APBCLK2 0x14 +#define REG_CLK_CLKSEL0 0x18 +#define REG_CLK_CLKSEL1 0x1C +#define REG_CLK_CLKSEL2 0x20 +#define REG_CLK_CLKSEL3 0x24 +#define REG_CLK_CLKSEL4 0x28 +#define REG_CLK_CLKDIV0 0x2C +#define REG_CLK_CLKDIV1 0x30 +#define REG_CLK_CLKDIV2 0x34 +#define REG_CLK_CLKDIV3 0x38 +#define REG_CLK_CLKDIV4 0x3C +#define REG_CLK_CLKOCTL 0x40 +#define REG_CLK_STATUS 0x50 +#define REG_CLK_PLL0CTL0 0x60 +#define REG_CLK_PLL2CTL0 0x80 +#define REG_CLK_PLL2CTL1 0x84 +#define REG_CLK_PLL2CTL2 0x88 +#define REG_CLK_PLL3CTL0 0x90 +#define REG_CLK_PLL3CTL1 0x94 +#define REG_CLK_PLL3CTL2 0x98 +#define REG_CLK_PLL4CTL0 0xA0 +#define REG_CLK_PLL4CTL1 0xA4 +#define REG_CLK_PLL4CTL2 0xA8 +#define REG_CLK_PLL5CTL0 0xB0 +#define REG_CLK_PLL5CTL1 0xB4 +#define REG_CLK_PLL5CTL2 0xB8 +#define REG_CLK_CLKDCTL 0xC0 +#define REG_CLK_CLKDSTS 0xC4 +#define REG_CLK_CDUPB 0xC8 +#define REG_CLK_CDLOWB 0xCC +#define REG_CLK_CKFLTRCTL 0xD0 +#define REG_CLK_TESTCLK 0xF0 +#define REG_CLK_PLLCTL 0x40 + +#define REG_PLL_CTL0_OFFSET 0x0 +#define REG_PLL_CTL1_OFFSET 0x4 +#define REG_PLL_CTL2_OFFSET 0x8 + +/* bit fields for REG_CLK_PLL0CTL0, which is SMIC PLL design */ +#define SPLL0_CTL0_FBDIV GENMASK(7, 0) +#define SPLL0_CTL0_INDIV GENMASK(11, 8) +#define SPLL0_CTL0_OUTDIV GENMASK(13, 12) +#define SPLL0_CTL0_PD BIT(16) +#define SPLL0_CTL0_BP BIT(17) + +/* bit fields for REG_CLK_PLLxCTL0 ~ REG_CLK_PLLxCTL2, where x = 2 ~ 5 */ +#define PLL_CTL0_FBDIV GENMASK(10, 0) +#define PLL_CTL0_INDIV GENMASK(17, 12) +#define PLL_CTL0_MODE GENMASK(19, 18) +#define PLL_CTL0_SSRATE GENMASK(30, 20) +#define PLL_CTL1_PD BIT(0) +#define PLL_CTL1_BP BIT(1) +#define PLL_CTL1_OUTDIV GENMASK(6, 4) +#define PLL_CTL1_FRAC GENMASK(31, 24) +#define PLL_CTL2_SLOPE GENMASK(23, 0) + +#define INDIV_MIN 1 +#define INDIV_MAX 63 +#define FBDIV_MIN 16 +#define FBDIV_MAX 2047 +#define FBDIV_FRAC_MIN 1600 +#define FBDIV_FRAC_MAX 204700 +#define OUTDIV_MIN 1 +#define OUTDIV_MAX 7 + +struct clk_hw *ma35d1_reg_clk_pll(enum ma35d1_pll_type type, u8 u8mode, + const char *name, const char *parent, + unsigned long targetFreq, + void __iomem *base, + struct regmap *regmap); + +struct clk_hw *ma35d1_reg_adc_clkdiv(struct device *dev, + const char *name, + const char *parent_name, + spinlock_t *lock, + unsigned long flags, + void __iomem *reg, u8 shift, + u8 width, u32 mask_bit); + +#endif /* __DRV_CLK_NUVOTON_MA35D1_H */ From patchwork Tue Mar 28 02:19:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Huang X-Patchwork-Id: 668808 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85BBFC6FD1D for ; Tue, 28 Mar 2023 02:20:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232693AbjC1CUn (ORCPT ); Mon, 27 Mar 2023 22:20:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45908 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232692AbjC1CUR (ORCPT ); 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id f17-20020a17090ac29100b00232cc61e16bsm5029301pjt.35.2023.03.27.19.19.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 19:19:48 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, arnd@arndb.de, schung@nuvoton.com, mjchen@nuvoton.com, Jacky Huang Subject: [PATCH v6 10/12] reset: Add Nuvoton ma35d1 reset driver support Date: Tue, 28 Mar 2023 02:19:10 +0000 Message-Id: <20230328021912.177301-11-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230328021912.177301-1-ychuang570808@gmail.com> References: <20230328021912.177301-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Jacky Huang This driver supports individual IP reset for ma35d1. The reset control registers is a subset of system control registers. Signed-off-by: Jacky Huang --- drivers/reset/Kconfig | 6 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-ma35d1.c | 152 +++++++++++++++++++++++++++++++++++ 3 files changed, 159 insertions(+) create mode 100644 drivers/reset/reset-ma35d1.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 2a52c990d4fe..58477c6ca9b8 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -143,6 +143,12 @@ config RESET_NPCM This enables the reset controller driver for Nuvoton NPCM BMC SoCs. +config RESET_NUVOTON_MA35D1 + bool "Nuvton MA35D1 Reset Driver" + default ARCH_NUVOTON || COMPILE_TEST + help + This enables the reset controller driver for Nuvoton MA35D1 SoC. + config RESET_OXNAS bool diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 3e7e5fd633a8..fd52dcf66a99 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o obj-$(CONFIG_RESET_NPCM) += reset-npcm.o +obj-$(CONFIG_RESET_NUVOTON_MA35D1) += reset-ma35d1.o obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o obj-$(CONFIG_RESET_POLARFIRE_SOC) += reset-mpfs.o diff --git a/drivers/reset/reset-ma35d1.c b/drivers/reset/reset-ma35d1.c new file mode 100644 index 000000000000..221299e7b873 --- /dev/null +++ b/drivers/reset/reset-ma35d1.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Chi-Fang Li + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define REG_SYS_IPRST0 0x020 +#define REG_SYS_IPRST1 0x024 +#define REG_SYS_IPRST2 0x028 +#define REG_SYS_IPRST3 0x02C + +#define RST_PRE_REG 32 + +struct ma35d1_reset_data { + struct reset_controller_dev rcdev; + struct regmap *regmap; +}; + +struct ma35d1_reboot_data { + struct notifier_block restart_handler; + struct regmap *regmap; +}; + +static int ma35d1_restart_handler(struct notifier_block *this, + unsigned long mode, void *cmd) +{ + struct ma35d1_reboot_data *data = + container_of(this, struct ma35d1_reboot_data, + restart_handler); + return regmap_write(data->regmap, REG_SYS_IPRST0, 1 << MA35D1_RESET_CHIP); +} + +static int ma35d1_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + unsigned int reg; + int ret; + int offset = (id / RST_PRE_REG) * 4; + struct ma35d1_reset_data *data = + container_of(rcdev, struct ma35d1_reset_data, rcdev); + + ret = regmap_read(data->regmap, REG_SYS_IPRST0 + offset, ®); + if (ret < 0) + return ret; + if (assert) + reg |= 1 << (id % RST_PRE_REG); + else + reg &= ~(1 << (id % RST_PRE_REG)); + + return regmap_write(data->regmap, REG_SYS_IPRST0 + offset, reg); +} + +static int ma35d1_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return ma35d1_reset_update(rcdev, id, true); +} + +static int ma35d1_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return ma35d1_reset_update(rcdev, id, false); +} + +static int ma35d1_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + int reg, ret; + int offset = id / RST_PRE_REG; + struct ma35d1_reset_data *data = + container_of(rcdev, struct ma35d1_reset_data, rcdev); + + ret = regmap_read(data->regmap, REG_SYS_IPRST0 + offset, ®); + if (ret < 0) + return ret; + return !!(reg & BIT(id % RST_PRE_REG)); +} + +static const struct reset_control_ops ma35d1_reset_ops = { + .assert = ma35d1_reset_assert, + .deassert = ma35d1_reset_deassert, + .status = ma35d1_reset_status, +}; + +static const struct of_device_id ma35d1_reset_dt_ids[] = { + { .compatible = "nuvoton,ma35d1-reset" }, + { }, +}; + +static int ma35d1_reset_probe(struct platform_device *pdev) +{ + int err; + struct device *dev = &pdev->dev; + struct device_node *parent; + struct ma35d1_reset_data *reset_data; + struct ma35d1_reboot_data *reboot_data; + + if (!pdev->dev.of_node) { + dev_err(&pdev->dev, "Device tree node not found\n"); + return -EINVAL; + } + + reset_data = devm_kzalloc(dev, sizeof(*reset_data), GFP_KERNEL); + if (!reset_data) + return -ENOMEM; + + reboot_data = devm_kzalloc(dev, sizeof(*reboot_data), GFP_KERNEL); + if (!reboot_data) + return -ENOMEM; + + parent = of_get_parent(dev->of_node); /* parent should be syscon node */ + reset_data->regmap = syscon_node_to_regmap(parent); + of_node_put(parent); + if (IS_ERR(reset_data->regmap)) { + dev_err(&pdev->dev, "Failed to get SYS register base\n"); + return PTR_ERR(reset_data->regmap); + } + + reset_data->rcdev.owner = THIS_MODULE; + reset_data->rcdev.nr_resets = MA35D1_RESET_COUNT; + reset_data->rcdev.ops = &ma35d1_reset_ops; + reset_data->rcdev.of_node = dev->of_node; + + reboot_data->regmap = reset_data->regmap; + reboot_data->restart_handler.notifier_call = ma35d1_restart_handler; + reboot_data->restart_handler.priority = 192; + + err = register_restart_handler(&reboot_data->restart_handler); + if (err) + dev_warn(&pdev->dev, "failed to register restart handler\n"); + + return devm_reset_controller_register(dev, &reset_data->rcdev); +} + +static struct platform_driver ma35d1_reset_driver = { + .probe = ma35d1_reset_probe, + .driver = { + .name = "ma35d1-reset", + .of_match_table = ma35d1_reset_dt_ids, + }, +}; + +builtin_platform_driver(ma35d1_reset_driver); From patchwork Tue Mar 28 02:19:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jacky Huang X-Patchwork-Id: 668807 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81FD4C77B62 for ; Tue, 28 Mar 2023 02:21:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232761AbjC1CVE (ORCPT ); Mon, 27 Mar 2023 22:21:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229718AbjC1CUV (ORCPT ); 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id f17-20020a17090ac29100b00232cc61e16bsm5029301pjt.35.2023.03.27.19.19.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 19:19:51 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, arnd@arndb.de, schung@nuvoton.com, mjchen@nuvoton.com, Jacky Huang Subject: [PATCH v6 11/12] tty: serial: Add Nuvoton ma35d1 serial driver support Date: Tue, 28 Mar 2023 02:19:11 +0000 Message-Id: <20230328021912.177301-12-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230328021912.177301-1-ychuang570808@gmail.com> References: <20230328021912.177301-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Jacky Huang This adds UART and console driver for Nuvoton ma35d1 Soc. It supports full-duplex communication, FIFO control, and hardware flow control. Signed-off-by: Jacky Huang --- drivers/tty/serial/Kconfig | 18 + drivers/tty/serial/Makefile | 1 + drivers/tty/serial/ma35d1_serial.c | 802 +++++++++++++++++++++++++++++ 3 files changed, 821 insertions(+) create mode 100644 drivers/tty/serial/ma35d1_serial.c diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 0072892ca7fc..daa4ae6bc08e 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -1562,6 +1562,24 @@ config SERIAL_SUNPLUS_CONSOLE you can alter that using a kernel command line option such as "console=ttySUPx". +config SERIAL_NUVOTON_MA35D1 + tristate "Nuvoton MA35D1 family UART support" + depends on ARCH_NUVOTON || COMPILE_TEST + select SERIAL_CORE + help + This driver supports Nuvoton MA35D1 family UART ports. If you would + like to use them, you must answer Y or M to this option. Note that + for use as console, it must be included in kernel and not as a + module + +config SERIAL_NUVOTON_MA35D1_CONSOLE + bool "Console on a Nuvotn MA35D1 family UART port" + depends on SERIAL_NUVOTON_MA35D1=y + select SERIAL_CORE_CONSOLE + help + Select this options if you'd like to use the UART port0 of the + Nuvoton MA35D1 family as a console. + endmenu config SERIAL_MCTRL_GPIO diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index cd9afd9e3018..71ebeba06ff2 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -93,3 +93,4 @@ obj-$(CONFIG_SERIAL_MCTRL_GPIO) += serial_mctrl_gpio.o obj-$(CONFIG_SERIAL_KGDB_NMI) += kgdb_nmi.o obj-$(CONFIG_KGDB_SERIAL_CONSOLE) += kgdboc.o +obj-$(CONFIG_SERIAL_NUVOTON_MA35D1) += ma35d1_serial.o diff --git a/drivers/tty/serial/ma35d1_serial.c b/drivers/tty/serial/ma35d1_serial.c new file mode 100644 index 000000000000..75618ab0b2ca --- /dev/null +++ b/drivers/tty/serial/ma35d1_serial.c @@ -0,0 +1,802 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * MA35D1 serial driver + * Copyright (C) 2023 Nuvoton Technology Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define UART_NR 17 + +#define UART_REG_RBR 0x00 +#define UART_REG_THR 0x00 +#define UART_REG_IER 0x04 +#define UART_REG_FCR 0x08 +#define UART_REG_LCR 0x0C +#define UART_REG_MCR 0x10 +#define UART_REG_MSR 0x14 +#define UART_REG_FSR 0x18 +#define UART_REG_ISR 0x1C +#define UART_REG_TOR 0x20 +#define UART_REG_BAUD 0x24 +#define UART_REG_ALTCTL 0x2C +#define UART_FUN_SEL 0x30 +#define UART_REG_WKCTL 0x40 +#define UART_REG_WKSTS 0x44 + +/* UART_REG_IER - Interrupt Enable Register */ +#define IER_RDA_IEN BIT(0) /* RBR Available Interrupt Enable */ +#define IER_THRE_IEN BIT(1) /* THR Empty Interrupt Enable */ +#define IER_RLS_IEN BIT(2) /* RX Line Status Interrupt Enable */ +#define IER_RTO_IEN BIT(4) /* RX Time-out Interrupt Enable */ +#define IER_BUFERR_IEN BIT(5) /* Buffer Error Interrupt Enable */ +#define IER_TIME_OUT_EN BIT(11) /* RX Buffer Time-out Counter Enable */ +#define IER_AUTO_RTS BIT(12) /* nRTS Auto-flow Control Enable */ +#define IER_AUTO_CTS BIT(13) /* nCTS Auto-flow Control Enable */ + +/* UART_REG_FCR - FIFO Control Register */ +#define FCR_RFR BIT(1) /* RX Field Software Reset */ +#define FCR_TFR BIT(2) /* TX Field Software Reset */ +#define FCR_RFITL_MASK GENMASK(7, 4) /* RX FIFO Interrupt Trigger Level */ +#define FCR_RFITL_1BYTE FIELD_PREP(FCR_RFITL_MASK, 0) +#define FCR_RFITL_4BYTES FIELD_PREP(FCR_RFITL_MASK, 1) +#define FCR_RFITL_8BYTES FIELD_PREP(FCR_RFITL_MASK, 2) +#define FCR_RFITL_14BYTES FIELD_PREP(FCR_RFITL_MASK, 3) +#define FCR_RFITL_30BYTES FIELD_PREP(FCR_RFITL_MASK, 4) +#define FCR_RTSTRGLV_MASK GENMASK(19, 16) /* nRTS Trigger Level */ +#define FCR_RTSTRGLV_1BYTE FIELD_PREP(FCR_RTSTRGLV_MASK, 0) +#define FCR_RTSTRGLV_4BYTES FIELD_PREP(FCR_RTSTRGLV_MASK, 1) +#define FCR_RTSTRGLV_8BYTES FIELD_PREP(FCR_RTSTRGLV_MASK, 2) +#define FCR_RTSTRGLV_14BYTES FIELD_PREP(FCR_RTSTRGLV_MASK, 3) +#define FCR_RTSTRGLVL_30BYTES FIELD_PREP(FCR_RTSTRGLV_MASK, 4) + +/* UART_REG_LCR - Line Control Register */ +#define LCR_NSB BIT(2) /* Number of “STOP Bit” */ +#define LCR_PBE BIT(3) /* Parity Bit Enable */ +#define LCR_EPE BIT(4) /* Even Parity Enable */ +#define LCR_SPE BIT(5) /* Stick Parity Enable */ +#define LCR_BREAK BIT(6) /* Break Control */ +#define LCR_WLS_MASK GENMASK(1, 0) /* Word Length Selection */ +#define LCR_WLS_5BITS FIELD_PREP(LCR_WLS_MASK, 0) +#define LCR_WLS_6BITS FIELD_PREP(LCR_WLS_MASK, 1) +#define LCR_WLS_7BITS FIELD_PREP(LCR_WLS_MASK, 2) +#define LCR_WLS_8BITS FIELD_PREP(LCR_WLS_MASK, 3) + +/* UART_REG_MCR - Modem Control Register */ +#define MCR_RTS_CTRL BIT(1) /* nRTS Signal Control */ +#define MCR_RTSACTLV BIT(9) /* nRTS Pin Active Level */ +#define MCR_RTSSTS BIT(13) /* nRTS Pin Status (Read Only) */ + +/* UART_REG_MSR - Modem Status Register */ +#define MSR_CTSDETF BIT(0) /* Detect nCTS State Change Flag */ +#define MSR_CTSSTS BIT(4) /* nCTS Pin Status (Read Only) */ +#define MSR_CTSACTLV BIT(8) /* nCTS Pin Active Level */ + +/* UART_REG_FSR - FIFO Status Register */ +#define FSR_RX_OVER_IF BIT(0) /* RX Overflow Error Interrupt Flag */ +#define FSR_PEF BIT(4) /* Parity Error Flag*/ +#define FSR_FEF BIT(5) /* Framing Error Flag */ +#define FSR_BIF BIT(6) /* Break Interrupt Flag */ +#define FSR_RX_EMPTY BIT(14) /* Receiver FIFO Empty (Read Only) */ +#define FSR_RX_FULL BIT(15) /* Receiver FIFO Full (Read Only) */ +#define FSR_TX_EMPTY BIT(22) /* Transmitter FIFO Empty (Read Only) */ +#define FSR_TX_FULL BIT(23) /* Transmitter FIFO Full (Read Only) */ +#define FSR_TX_OVER_IF BIT(24) /* TX Overflow Error Interrupt Flag */ +#define FSR_TE_FLAG BIT(28) /* Transmitter Empty Flag (Read Only) */ +#define FSR_RXPTR_MSK GENMASK(13, 8) /* TX FIFO Pointer mask */ +#define FSR_TXPTR_MSK GENMASK(21, 16) /* RX FIFO Pointer mask */ + +/* UART_REG_ISR - Interrupt Status Register */ +#define ISR_RDA_IF BIT(0) /* RBR Available Interrupt Flag */ +#define ISR_THRE_IF BIT(1) /* THR Empty Interrupt Flag */ +#define ISR_RLSIF BIT(2) /* Receive Line Interrupt Flag */ +#define ISR_MODEMIF BIT(3) /* MODEM Interrupt Flag */ +#define ISR_RXTO_IF BIT(4) /* RX Time-out Interrupt Flag */ +#define ISR_BUFEIF BIT(5) /* Buffer Error Interrupt Flag */ +#define UART_ISR_WK_IF BIT(6) /* UART Wake-up Interrupt Flag */ +#define UART_ISR_RDAINT BIT(8) /* RBR Available Interrupt Indicator */ +#define ISR_THRE_INT BIT(9) /* THR Empty Interrupt Indicator */ +#define ISR_ALL 0xFFFFFFFF + +/* UART_REG_BAUD - Baud Rate Divider Register */ +#define BAUD_MODE_MASK GENMASK(29, 28) +#define BAUD_MODE0 FIELD_PREP(BAUD_MODE_MASK, 0) +#define BAUD_MODE1 FIELD_PREP(BAUD_MODE_MASK, 2) +#define BAUD_MODE2 FIELD_PREP(BAUD_MODE_MASK, 3) + +/* UART_REG_ALTCTL - Alternate Control/Status Register */ +#define ALTCTL_RS485AUD BIT(10) /* RS-485 Auto Direction Function */ + +/* UART_FUN_SEL - Function Select Register */ +#define FUN_SEL_MASK GENMASK(2, 0) +#define FUN_SEL_UART FIELD_PREP(FUN_SEL_MASK, 0) +#define FUN_SEL_RS485 FIELD_PREP(FUN_SEL_MASK, 3) + +/* UART FIFO depth */ +#define UART_FIFO_DEPTH 32 +/* UART console clock */ +#define UART_CONSOLE_CLK 24000000 +/* UART register ioremap size */ +#define UART_REG_SIZE 0x100 +/* Rx Timeout */ +#define UART_RX_TOUT 0x40 + +#define UART_ISR_IF_CHECK (ISR_RDA_IF | ISR_RXTO_IF | ISR_THRE_INT | ISR_BUFEIF) + +#define LOOP_TIMEOUT 1000 + +static struct uart_driver ma35d1serial_reg; +struct clk *clk; + +struct uart_ma35d1_port { + struct uart_port port; + u16 capabilities; /* port capabilities */ + u8 ier; + u8 lcr; + u8 mcr; + u32 baud_rate; + u32 console_baud_rate; + u32 console_line; + u32 console_int; +}; + +static struct device_node *ma35d1serial_uart_nodes[UART_NR]; +static struct uart_ma35d1_port ma35d1serial_ports[UART_NR] = { 0 }; + +static struct uart_ma35d1_port *to_ma35d1_uart_port(struct uart_port *uart) +{ + return container_of(uart, struct uart_ma35d1_port, port); +} + +static u32 serial_in(struct uart_ma35d1_port *p, u32 offset) +{ + return readl_relaxed(p->port.membase + offset); +} + +static void serial_out(struct uart_ma35d1_port *p, u32 offset, u32 value) +{ + writel_relaxed(value, p->port.membase + offset); +} + +static void __stop_tx(struct uart_ma35d1_port *p) +{ + u32 ier; + + ier = serial_in(p, UART_REG_IER); + if (ier & IER_THRE_IEN) + serial_out(p, UART_REG_IER, ier & ~IER_THRE_IEN); +} + +static void ma35d1serial_stop_tx(struct uart_port *port) +{ + struct uart_ma35d1_port *up = to_ma35d1_uart_port(port); + + __stop_tx(up); +} + +static void transmit_chars(struct uart_ma35d1_port *up) +{ + struct circ_buf *xmit = &up->port.state->xmit; + int count; + u8 ch; + + if (uart_tx_stopped(&up->port)) { + ma35d1serial_stop_tx(&up->port); + return; + } + if (uart_circ_empty(xmit)) { + __stop_tx(up); + return; + } + + count = UART_FIFO_DEPTH - ((serial_in(up, UART_REG_FSR) & FSR_TXPTR_MSK) >> 16); + + uart_port_tx_limited(&up->port, ch, count, + !(serial_in(up, UART_REG_FSR) & FSR_TX_FULL), + serial_out(up, UART_REG_THR, ch), + ({})); + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(&up->port); + + if (uart_circ_empty(xmit)) + __stop_tx(up); +} + +static void ma35d1serial_start_tx(struct uart_port *port) +{ + struct uart_ma35d1_port *up = to_ma35d1_uart_port(port); + u32 ier; + + ier = serial_in(up, UART_REG_IER); + serial_out(up, UART_REG_IER, ier & ~IER_THRE_IEN); + transmit_chars(up); + serial_out(up, UART_REG_IER, ier | IER_THRE_IEN); +} + +static void ma35d1serial_stop_rx(struct uart_port *port) +{ + struct uart_ma35d1_port *up = to_ma35d1_uart_port(port); + + serial_out(up, UART_REG_IER, serial_in(up, UART_REG_IER) & ~IER_RDA_IEN); +} + +static void receive_chars(struct uart_ma35d1_port *up) +{ + u8 flag; + u32 fsr; + unsigned int ch; + int max_count = 256; + + fsr = serial_in(up, UART_REG_FSR); + do { + flag = TTY_NORMAL; + up->port.icount.rx++; + + if (unlikely(fsr & (FSR_BIF | FSR_FEF | FSR_PEF | FSR_RX_OVER_IF))) { + if (fsr & FSR_BIF) { + up->port.icount.brk++; + if (uart_handle_break(&up->port)) + continue; + } + if (fsr & FSR_FEF) + up->port.icount.frame++; + if (fsr & FSR_PEF) + up->port.icount.parity++; + if (fsr & FSR_RX_OVER_IF) + up->port.icount.overrun++; + + serial_out(up, UART_REG_FSR, fsr & + (FSR_BIF | FSR_FEF | FSR_PEF | FSR_RX_OVER_IF)); + + if (fsr & FSR_BIF) + flag = TTY_BREAK; + else if (fsr & FSR_PEF) + flag = TTY_PARITY; + else if (fsr & FSR_FEF) + flag = TTY_FRAME; + } + + ch = serial_in(up, UART_REG_RBR); + if (uart_handle_sysrq_char(&up->port, ch)) + continue; + + spin_lock(&up->port.lock); + uart_insert_char(&up->port, fsr, FSR_RX_OVER_IF, ch, flag); + spin_unlock(&up->port.lock); + + fsr = serial_in(up, UART_REG_FSR); + } while (!(fsr & FSR_RX_EMPTY) && (max_count-- > 0)); + + spin_lock(&up->port.lock); + tty_flip_buffer_push(&up->port.state->port); + spin_unlock(&up->port.lock); +} + +static irqreturn_t ma35d1serial_interrupt(int irq, void *dev_id) +{ + struct uart_port *port = dev_id; + struct uart_ma35d1_port *up = to_ma35d1_uart_port(port); + u32 isr, fsr; + + isr = serial_in(up, UART_REG_ISR); + fsr = serial_in(up, UART_REG_FSR); + + if (!(isr & UART_ISR_IF_CHECK)) + return IRQ_NONE; + + if (isr & (ISR_RDA_IF | ISR_RXTO_IF)) + receive_chars(up); + if (isr & ISR_THRE_INT) + transmit_chars(up); + if (fsr & FSR_TX_OVER_IF) + serial_out(up, UART_REG_FSR, FSR_TX_OVER_IF); + + return IRQ_HANDLED; +} + +static u32 ma35d1serial_tx_empty(struct uart_port *port) +{ + struct uart_ma35d1_port *up = to_ma35d1_uart_port(port); + u32 fsr; + + fsr = serial_in(up, UART_REG_FSR); + return (fsr & (FSR_TE_FLAG | FSR_TX_EMPTY)) == + (FSR_TE_FLAG | FSR_TX_EMPTY) ? TIOCSER_TEMT : 0; +} + +static u32 ma35d1serial_get_mctrl(struct uart_port *port) +{ + struct uart_ma35d1_port *up = to_ma35d1_uart_port(port); + u32 status; + u32 ret = 0; + + status = serial_in(up, UART_REG_MSR); + if (!(status & MSR_CTSSTS)) + ret |= TIOCM_CTS; + return ret; +} + +static void ma35d1serial_set_mctrl(struct uart_port *port, u32 mctrl) +{ + struct uart_ma35d1_port *up = to_ma35d1_uart_port(port); + u32 mcr = 0; + u32 ier = 0; + + if (mctrl & TIOCM_RTS) { + mcr = serial_in(up, UART_REG_MCR); + mcr |= MCR_RTSACTLV; + mcr &= ~MCR_RTS_CTRL; + } + if (up->mcr & UART_MCR_AFE) { + mcr = serial_in(up, UART_REG_MCR); + mcr |= MCR_RTSACTLV; + mcr &= ~MCR_RTS_CTRL; + + serial_out(up, UART_REG_IER, + (serial_in(up, UART_REG_IER) | IER_AUTO_RTS | IER_AUTO_CTS)); + + up->port.flags |= UPF_HARD_FLOW; + } else { + ier = serial_in(up, UART_REG_IER); + ier &= ~(IER_AUTO_RTS | IER_AUTO_CTS); + serial_out(up, UART_REG_IER, ier); + + up->port.flags &= ~UPF_HARD_FLOW; + } + serial_out(up, UART_REG_MSR, (serial_in(up, UART_REG_MSR) | MSR_CTSACTLV)); + serial_out(up, UART_REG_MCR, mcr); +} + +static void ma35d1serial_break_ctl(struct uart_port *port, int break_state) +{ + struct uart_ma35d1_port *up = to_ma35d1_uart_port(port); + unsigned long flags; + u32 lcr; + + spin_lock_irqsave(&up->port.lock, flags); + lcr = serial_in(up, UART_REG_LCR); + if (break_state != 0) + lcr |= LCR_BREAK; + else + lcr &= ~LCR_BREAK; + serial_out(up, UART_REG_LCR, lcr); + spin_unlock_irqrestore(&up->port.lock, flags); +} + +static int ma35d1serial_startup(struct uart_port *port) +{ + struct uart_ma35d1_port *up = to_ma35d1_uart_port(port); + int retval; + + /* Reset FIFO */ + serial_out(up, UART_REG_FCR, FCR_TFR | FCR_RFR); + + /* Clear pending interrupts */ + serial_out(up, UART_REG_ISR, ISR_ALL); + + retval = request_irq(port->irq, ma35d1serial_interrupt, 0, + dev_name(port->dev), port); + if (retval) { + dev_err(up->port.dev, "request irq failed.\n"); + return retval; + } + + serial_out(up, UART_REG_FCR, serial_in(up, UART_REG_FCR) | + FCR_RFITL_4BYTES | FCR_RTSTRGLV_8BYTES); + serial_out(up, UART_REG_LCR, LCR_WLS_8BITS); + serial_out(up, UART_REG_TOR, UART_RX_TOUT); + serial_out(up, UART_REG_IER, IER_RTO_IEN | IER_RDA_IEN | + IER_TIME_OUT_EN | IER_BUFERR_IEN); + return 0; +} + +static void ma35d1serial_shutdown(struct uart_port *port) +{ + struct uart_ma35d1_port *up = to_ma35d1_uart_port(port); + + serial_out(up, UART_REG_IER, 0); + free_irq(port->irq, port); +} + +static u32 ma35d1serial_get_divisor(struct uart_port *port, u32 baud) +{ + return (port->uartclk / baud) - 2; +} + +static void ma35d1serial_set_termios(struct uart_port *port, + struct ktermios *termios, + const struct ktermios *old) +{ + struct uart_ma35d1_port *up = to_ma35d1_uart_port(port); + u32 lcr = 0; + unsigned long flags; + u32 baud, quot; + + lcr = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag)); + + if (termios->c_cflag & CSTOPB) + lcr |= LCR_NSB; + if (termios->c_cflag & PARENB) + lcr |= LCR_PBE; + if (!(termios->c_cflag & PARODD)) + lcr |= LCR_EPE; + if (termios->c_cflag & CMSPAR) + lcr |= LCR_SPE; + + baud = uart_get_baud_rate(port, termios, old, port->uartclk / 0xffff, + port->uartclk / 11); + + quot = ma35d1serial_get_divisor(port, baud); + + /* + * Ok, we're now changing the port state. Do it with + * interrupts disabled. + */ + spin_lock_irqsave(&up->port.lock, flags); + + up->port.read_status_mask = FSR_RX_OVER_IF; + if (termios->c_iflag & INPCK) + up->port.read_status_mask |= FSR_FEF | FSR_PEF; + if (termios->c_iflag & (BRKINT | PARMRK)) + up->port.read_status_mask |= FSR_BIF; + + /* + * Characteres to ignore + */ + up->port.ignore_status_mask = 0; + if (termios->c_iflag & IGNPAR) + up->port.ignore_status_mask |= FSR_FEF | FSR_PEF; + if (termios->c_iflag & IGNBRK) { + up->port.ignore_status_mask |= FSR_BIF; + /* + * If we're ignoring parity and break indicators, + * ignore overruns too (for real raw support). + */ + if (termios->c_iflag & IGNPAR) + up->port.ignore_status_mask |= FSR_RX_OVER_IF; + } + if (termios->c_cflag & CRTSCTS) + up->mcr |= UART_MCR_AFE; + else + up->mcr &= ~UART_MCR_AFE; + + uart_update_timeout(port, termios->c_cflag, baud); + ma35d1serial_set_mctrl(&up->port, up->port.mctrl); + serial_out(up, UART_REG_BAUD, quot | BAUD_MODE2); + serial_out(up, UART_REG_LCR, lcr); + spin_unlock_irqrestore(&up->port.lock, flags); +} + +static const char *ma35d1serial_type(struct uart_port *port) +{ + return "ma35d1-uart"; +} + +static void ma35d1serial_config_port(struct uart_port *port, int flags) +{ + /* + * Driver core for serial ports forces a non-zero value for port type. + * Write an arbitrary value here to accommodate the serial core driver, + * as ID part of UAPI is redundant. + */ + port->type = 1; +} + +static int ma35d1serial_verify_port(struct uart_port *port, + struct serial_struct *ser) +{ + if (port->type != PORT_UNKNOWN && ser->type != 1) + return -EINVAL; + + return 0; +} + +static const struct uart_ops ma35d1serial_ops = { + .tx_empty = ma35d1serial_tx_empty, + .set_mctrl = ma35d1serial_set_mctrl, + .get_mctrl = ma35d1serial_get_mctrl, + .stop_tx = ma35d1serial_stop_tx, + .start_tx = ma35d1serial_start_tx, + .stop_rx = ma35d1serial_stop_rx, + .break_ctl = ma35d1serial_break_ctl, + .startup = ma35d1serial_startup, + .shutdown = ma35d1serial_shutdown, + .set_termios = ma35d1serial_set_termios, + .type = ma35d1serial_type, + .config_port = ma35d1serial_config_port, + .verify_port = ma35d1serial_verify_port, +}; + +static const struct of_device_id ma35d1_serial_of_match[] = { + { .compatible = "nuvoton,ma35d1-uart" }, + {}, +}; +MODULE_DEVICE_TABLE(of, ma35d1_serial_of_match); + +#ifdef CONFIG_SERIAL_NUVOTON_MA35D1_CONSOLE + +static void wait_for_xmitr(struct uart_ma35d1_port *up) +{ + unsigned int tmout; + + /* Wait up to 10ms for the character(s) to be sent. */ + tmout = 10000; + while (--tmout) { + if (serial_in(up, UART_REG_FSR) & FSR_TX_EMPTY) + break; + udelay(1); + } +} + +static void ma35d1serial_console_putchar(struct uart_port *port, unsigned char ch) +{ + struct uart_ma35d1_port *up = to_ma35d1_uart_port(port); + + wait_for_xmitr(up); + serial_out(up, UART_REG_THR, ch); +} + +/* + * Print a string to the serial port trying not to disturb + * any possible real use of the port... + * + * The console_lock must be held when we get here. + */ +static void ma35d1serial_console_write(struct console *co, + const char *s, u32 count) +{ + struct uart_ma35d1_port *up = &ma35d1serial_ports[co->index]; + unsigned long flags; + u32 ier; + + local_irq_save(flags); + + /* + * First save the IER then disable the interrupts + */ + ier = serial_in(up, UART_REG_IER); + serial_out(up, UART_REG_IER, 0); + + uart_console_write(&up->port, s, count, ma35d1serial_console_putchar); + + wait_for_xmitr(up); + + serial_out(up, UART_REG_IER, ier); + local_irq_restore(flags); +} + +static int __init ma35d1serial_console_setup(struct console *co, + char *options) +{ + struct device_node *np = ma35d1serial_uart_nodes[co->index]; + struct uart_ma35d1_port *p = &ma35d1serial_ports[co->index]; + u32 val32[4]; + struct uart_port *port; + int baud = 115200; + int bits = 8; + int parity = 'n'; + int flow = 'n'; + + /* + * Check whether an invalid uart number has been specified, and + * if so, search for the first available port that does have + * console support. + */ + if ((co->index < 0) || (co->index >= UART_NR)) { + pr_debug("Console Port%x out of range\n", co->index); + return -EINVAL; + } + + if (of_property_read_u32_array(np, "reg", val32, 4) != 0) + return -EINVAL; + p->port.iobase = val32[1]; + p->port.membase = ioremap(p->port.iobase, UART_REG_SIZE); + p->port.ops = &ma35d1serial_ops; + p->port.line = 0; + p->port.uartclk = UART_CONSOLE_CLK; + + port = &ma35d1serial_ports[co->index].port; + return uart_set_options(port, co, baud, parity, bits, flow); +} + +static struct console ma35d1serial_console = { + .name = "ttyS", + .write = ma35d1serial_console_write, + .device = uart_console_device, + .setup = ma35d1serial_console_setup, + .flags = CON_PRINTBUFFER | CON_ENABLED, + .index = -1, + .data = &ma35d1serial_reg, +}; + +static void ma35d1serial_console_init_port(void) +{ + int i = 0; + struct device_node *np; + + for_each_matching_node(np, ma35d1_serial_of_match) { + if (ma35d1serial_uart_nodes[i] == NULL) { + of_node_get(np); + ma35d1serial_uart_nodes[i] = np; + i++; + if (i == UART_NR) + break; + } + } +} + +static int __init ma35d1serial_console_init(void) +{ + ma35d1serial_console_init_port(); + register_console(&ma35d1serial_console); + return 0; +} +console_initcall(ma35d1serial_console_init); + +#define MA35D1SERIAL_CONSOLE (&ma35d1serial_console) +#else +#define MA35D1SERIAL_CONSOLE NULL +#endif + +static struct uart_driver ma35d1serial_reg = { + .owner = THIS_MODULE, + .driver_name = "serial", + .dev_name = "ttyS", + .major = TTY_MAJOR, + .minor = 64, + .cons = MA35D1SERIAL_CONSOLE, + .nr = UART_NR, +}; + +/* + * Register a set of serial devices attached to a platform device. + * The list is terminated with a zero flags entry, which means we expect + * all entries to have at least UPF_BOOT_AUTOCONF set. + */ +static int ma35d1serial_probe(struct platform_device *pdev) +{ + struct resource *res_mem; + struct uart_ma35d1_port *up; + int ret; + struct clk *clk; + int err; + + if (pdev->dev.of_node) { + ret = of_alias_get_id(pdev->dev.of_node, "serial"); + if (ret < 0) { + dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n", ret); + return ret; + } + } + up = &ma35d1serial_ports[ret]; + up->port.line = ret; + res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res_mem) + return -ENODEV; + + up->port.iobase = res_mem->start; + up->port.membase = ioremap(up->port.iobase, UART_REG_SIZE); + up->port.ops = &ma35d1serial_ops; + + spin_lock_init(&up->port.lock); + + clk = of_clk_get(pdev->dev.of_node, 0); + if (IS_ERR(clk)) { + err = PTR_ERR(clk); + dev_err(&pdev->dev, "failed to get core clk: %d\n", err); + return -ENOENT; + } + err = clk_prepare_enable(clk); + if (err) + return -ENOENT; + + if (up->port.line != 0) + up->port.uartclk = clk_get_rate(clk); + up->port.irq = platform_get_irq(pdev, 0); + up->port.dev = &pdev->dev; + up->port.flags = UPF_BOOT_AUTOCONF; + ret = uart_add_one_port(&ma35d1serial_reg, &up->port); + platform_set_drvdata(pdev, up); + return 0; +} + +/* + * Remove serial ports registered against a platform device. + */ +static int ma35d1serial_remove(struct platform_device *dev) +{ + struct uart_port *port = platform_get_drvdata(dev); + + if (port) { + uart_remove_one_port(&ma35d1serial_reg, port); + free_irq(port->irq, port); + } + return 0; +} + +static int ma35d1serial_suspend(struct platform_device *dev, pm_message_t state) +{ + int i; + struct uart_ma35d1_port *up; + + if (dev->dev.of_node) + i = of_alias_get_id(dev->dev.of_node, "serial"); + if (i < 0) { + dev_err(&dev->dev, "failed to get alias/pdev id, errno %d\n", i); + return i; + } + up = &ma35d1serial_ports[i]; + if (i == 0) { + up->console_baud_rate = serial_in(up, UART_REG_BAUD); + up->console_line = serial_in(up, UART_REG_LCR); + up->console_int = serial_in(up, UART_REG_IER); + } + return 0; +} + +static int ma35d1serial_resume(struct platform_device *dev) +{ + int i; + struct uart_ma35d1_port *up; + + if (dev->dev.of_node) + i = of_alias_get_id(dev->dev.of_node, "serial"); + if (i < 0) { + dev_err(&dev->dev, "failed to get alias/pdev id, errno %d\n", i); + return i; + } + up = &ma35d1serial_ports[i]; + if (i == 0) { + serial_out(up, UART_REG_BAUD, up->console_baud_rate); + serial_out(up, UART_REG_LCR, up->console_line); + serial_out(up, UART_REG_IER, up->console_int); + } + return 0; +} + +static struct platform_driver ma35d1serial_driver = { + .probe = ma35d1serial_probe, + .remove = ma35d1serial_remove, + .suspend = ma35d1serial_suspend, + .resume = ma35d1serial_resume, + .driver = { + .name = "ma35d1-uart", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(ma35d1_serial_of_match), + }, +}; + +static int __init ma35d1serial_init(void) +{ + int ret; + + ret = uart_register_driver(&ma35d1serial_reg); + if (ret) + return ret; + ret = platform_driver_register(&ma35d1serial_driver); + if (ret) + uart_unregister_driver(&ma35d1serial_reg); + return ret; +} + +static void __exit ma35d1serial_exit(void) +{ + platform_driver_unregister(&ma35d1serial_driver); + uart_unregister_driver(&ma35d1serial_reg); +} + +module_init(ma35d1serial_init); +module_exit(ma35d1serial_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("MA35D1 serial driver"); +MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR); + From patchwork Tue Mar 28 02:19:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Huang X-Patchwork-Id: 668085 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC2EDC6FD1D for ; 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id f17-20020a17090ac29100b00232cc61e16bsm5029301pjt.35.2023.03.27.19.19.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 19:19:53 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, arnd@arndb.de, schung@nuvoton.com, mjchen@nuvoton.com, Jacky Huang Subject: [PATCH v6 12/12] MAINTAINERS: Add entry for NUVOTON MA35 Date: Tue, 28 Mar 2023 02:19:12 +0000 Message-Id: <20230328021912.177301-13-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230328021912.177301-1-ychuang570808@gmail.com> References: <20230328021912.177301-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Jacky Huang Add entry for Nuvton ma35d1 maintainer and files. Signed-off-by: Jacky Huang --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 1dc8bd26b6cf..a3912717f1da 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2501,6 +2501,15 @@ F: drivers/rtc/rtc-ab8500.c F: drivers/rtc/rtc-pl031.c F: drivers/soc/ux500/ +ARM/NUVOTON MA35 ARCHITECTURE +M: Jacky Huang +M: Shan-Chun Hung +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Supported +F: Documentation/devicetree/bindings/*/*nuvoton* +F: arch/arm64/boot/dts/nuvoton/*ma35* +K: ma35d1 + ARM/NUVOTON NPCM ARCHITECTURE M: Avi Fishman M: Tomer Maimon