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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z5sm9700617wmi.34.2019.05.23.07.23.59 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 May 2019 07:23:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 23 May 2019 15:23:46 +0100 Message-Id: <20190523142357.5175-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190523142357.5175-1-peter.maydell@linaro.org> References: <20190523142357.5175-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::330 Subject: [Qemu-devel] [PULL 01/12] target/arm: Use extract2 for EXTR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This is, after all, how we implement extract2 in tcg/aarch64. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20190514011129.11330-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 38 ++++++++++++++++++++------------------ 1 file changed, 20 insertions(+), 18 deletions(-) -- 2.20.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b7c5a928b4a..2b135b938ce 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4114,25 +4114,27 @@ static void disas_extract(DisasContext *s, uint32_t insn) } else { tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm)); } - } else if (rm == rn) { /* ROR */ - tcg_rm = cpu_reg(s, rm); - if (sf) { - tcg_gen_rotri_i64(tcg_rd, tcg_rm, imm); - } else { - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(tmp, tcg_rm); - tcg_gen_rotri_i32(tmp, tmp, imm); - tcg_gen_extu_i32_i64(tcg_rd, tmp); - tcg_temp_free_i32(tmp); - } } else { - tcg_rm = read_cpu_reg(s, rm, sf); - tcg_rn = read_cpu_reg(s, rn, sf); - tcg_gen_shri_i64(tcg_rm, tcg_rm, imm); - tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm); - tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn); - if (!sf) { - tcg_gen_ext32u_i64(tcg_rd, tcg_rd); + tcg_rm = cpu_reg(s, rm); + tcg_rn = cpu_reg(s, rn); + + if (sf) { + /* Specialization to ROR happens in EXTRACT2. */ + tcg_gen_extract2_i64(tcg_rd, tcg_rm, tcg_rn, imm); + } else { + TCGv_i32 t0 = tcg_temp_new_i32(); + + tcg_gen_extrl_i64_i32(t0, tcg_rm); + if (rm == rn) { + tcg_gen_rotri_i32(t0, t0, imm); + } else { + TCGv_i32 t1 = tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(t1, tcg_rn); + tcg_gen_extract2_i32(t0, t0, t1, imm); + tcg_temp_free_i32(t1); + } + tcg_gen_extu_i32_i64(tcg_rd, t0); + tcg_temp_free_i32(t0); } } } From patchwork Thu May 23 14:23:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 165021 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2271955ili; Thu, 23 May 2019 07:32:13 -0700 (PDT) X-Google-Smtp-Source: APXvYqym463IAcihhYlWWSSxNvf+Vn/jKVT5FS6E57GPOrUVi242i46E4iCTqbc0Sa1tppmm892a X-Received: by 2002:a5d:4a92:: with SMTP id o18mr4056418wrq.80.1558621933777; Thu, 23 May 2019 07:32:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558621933; cv=none; d=google.com; s=arc-20160816; b=Cb00noQyuP5Vf1BGRhaR1CEazn8NzUYqGEQhjIsaOx5bB8nZmjCZ7m23I3cZGPOEjm 0VSVUSbO8Qx8MHfxxS3sd941BSz4vB7UM77xvTj3BFacUPigeChEmllCAWBhJkKzjJBf Zg/FXfkKOuw2gGYRPfEZ5iVOAu6qcdvonxeNOlBGxbgCgpdCn5isvp1xRStU9kZLsfgY tjSUxN8B1B9mPgd9jYOMg+msJ9V2wkwNzyuYXbWDF4+15UOchDKZ7BybjIrx23A1Yupy ijcJOvPH0wXHU3mzr5ZICGYvHWScBcsPQ23N2GTCZAe95/iHIi24/UPvGpwMSMT92OFx 6VDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=HbJqlpqkF0phR9V9E/untsO2SeobncFpU3t1rLBGqVo=; b=v2TpMJCtJ/uez6G6rEFIMF9c4bnOjiFCq5VbNISJijY/P/+O+IWxMnJ+uhEvJ1BkHK 7Ns0ueUJCY1b1yeeep3nopZ/HDSSfAaASsN5jqj2ST06Y5BNQpy0BLHWOOJtbkpVCkpT AGJ9fgoDAj0UUoYMThBpfddN7RnQ+OD9o62k3kiv6dvwyDuokURguMHfeo2UVZqwKmxy mNzY50TN3XVHFYwY2C6FxCTHDQmpaGm5ULuNhfx+IMjbWykzWeEgm1skmTLKhMuHEgXe JgARPg0B12BW3AxZNnDOJVu28Nlwnwn5Lmczl4CTLfkwQjA/+KmjB4HDZ/tK5AZKKZJt UXZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=xVi8Djz0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z5sm9700617wmi.34.2019.05.23.07.24.00 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 May 2019 07:24:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 23 May 2019 15:23:47 +0100 Message-Id: <20190523142357.5175-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190523142357.5175-1-peter.maydell@linaro.org> References: <20190523142357.5175-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PULL 02/12] target/arm: Simplify BFXIL expansion X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The mask implied by the extract is redundant with the one implied by the deposit. Also, fix spelling of BFXIL. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-id: 20190514011129.11330-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.20.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2b135b938ce..42999c58011 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4043,8 +4043,8 @@ static void disas_bitfield(DisasContext *s, uint32_t insn) tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len); return; } - /* opc == 1, BXFIL fall through to deposit */ - tcg_gen_extract_i64(tcg_tmp, tcg_tmp, ri, len); + /* opc == 1, BFXIL fall through to deposit */ + tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri); pos = 0; } else { /* Handle the ri > si case with a deposit @@ -4062,7 +4062,7 @@ static void disas_bitfield(DisasContext *s, uint32_t insn) len = ri; } - if (opc == 1) { /* BFM, BXFIL */ + if (opc == 1) { /* BFM, BFXIL */ tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len); } else { /* SBFM or UBFM: We start with zero, and we haven't modified From patchwork Thu May 23 14:23:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 165015 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2261726ili; Thu, 23 May 2019 07:24:34 -0700 (PDT) X-Google-Smtp-Source: APXvYqx+RzKNmDM/LVYqXPlzFANtIXhm2ManaAXpOFVev8Yd+lLeqZcYjJbA4DMPjwJAKsdiA7Ge X-Received: by 2002:a50:893d:: with SMTP id e58mr93864117ede.244.1558621474438; Thu, 23 May 2019 07:24:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558621474; cv=none; d=google.com; s=arc-20160816; b=IQjfP0GgcwiPGlXurPqHEsB+AqX05f2OQt1gbNXqBPMnhkoBNaFmopTrPumIujeyYc Q+w4UB1o88yatWm1alLEHr1STSx1oDINpAPpbwAe98iw4pW+PRPDwXxUzOc3m3EXLnX3 WUphPhumm/j8poD2+LzRu2+Zh1/f6l+bWOvN0XShg322ju/uYmLCOPTG1jL8xZMlJbpy 6ITVdEu6IjzNJsW5K+VdVvo+TZcmRgEmAgL85bnvFqblzeMueiPSQzIa9NdP3iodw8Yz yiVoaNGCjN3ZH9fhQFOOMDPShLyn9X3iqgqIq9MyP/7o3kHz/8oTW30RHRNuL2o9Uh6U JAsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=8woPEtG8YS4MOTdISE4mp0N5yE3FIOBq9YtwFKXxb9k=; b=MsaAbC4oVWwBuMQ9PZ+TWFtKd8o62GcTYTPNJcFj9PnYM6QxcHxw4ki3DjQmaE2HdP /zN6I8P77t+Jictmto7lDaURHJuSyrujL67dDZKLHyobiyFhBTb4S0Zm38DW/k26DmaV McNgojcE7KX0mpiUVi259unOfnJIlhTpavtWOkkVlOR8B4j+4IDIdsOAzBssn5XuYAsZ i6ARNdCt1Puvy6JlejqIO6r8YWNfjty/ORjJ0eC7+lur+k83YiFMFXX81xI9kjhoLOwb uNsqLSrWSLi47d1uuHXa2et2jF0dUZzAstwufBBXtiDwkFpewSgqoXj/IYLKaDxvZjuf f/bg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=sqZ+Y5xJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z5sm9700617wmi.34.2019.05.23.07.24.01 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 May 2019 07:24:01 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 23 May 2019 15:23:48 +0100 Message-Id: <20190523142357.5175-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190523142357.5175-1-peter.maydell@linaro.org> References: <20190523142357.5175-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PULL 03/12] target/arm: Fix vector operation segfault X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis Commit 89e68b575 "target/arm: Use vector operations for saturation" causes this abort() when booting QEMU ARM with a Cortex-A15: 0 0x00007ffff4c2382f in raise () at /usr/lib/libc.so.6 1 0x00007ffff4c0e672 in abort () at /usr/lib/libc.so.6 2 0x00005555559c1839 in disas_neon_data_insn (insn=, s=) at ./target/arm/translate.c:6673 3 0x00005555559c1839 in disas_neon_data_insn (s=, insn=) at ./target/arm/translate.c:6386 4 0x00005555559cd8a4 in disas_arm_insn (insn=4081107068, s=0x7fffe59a9510) at ./target/arm/translate.c:9289 5 0x00005555559cd8a4 in arm_tr_translate_insn (dcbase=0x7fffe59a9510, cpu=) at ./target/arm/translate.c:13612 6 0x00005555558d1d39 in translator_loop (ops=0x5555561cc580 , db=0x7fffe59a9510, cpu=0x55555686a2f0, tb=, max_insns=) at ./accel/tcg/translator.c:96 7 0x00005555559d10d4 in gen_intermediate_code (cpu=cpu@entry=0x55555686a2f0, tb=tb@entry=0x7fffd7840080 , max_insns=max_insns@entry=512) at ./target/arm/translate.c:13901 8 0x00005555558d06b9 in tb_gen_code (cpu=cpu@entry=0x55555686a2f0, pc=3067096216, cs_base=0, flags=192, cflags=-16252928, cflags@entry=524288) at ./accel/tcg/translate-all.c:1736 9 0x00005555558ce467 in tb_find (cf_mask=524288, tb_exit=1, last_tb=0x7fffd783e640 , cpu=0x1) at ./accel/tcg/cpu-exec.c:407 10 0x00005555558ce467 in cpu_exec (cpu=cpu@entry=0x55555686a2f0) at ./accel/tcg/cpu-exec.c:728 11 0x000055555588b0cf in tcg_cpu_exec (cpu=0x55555686a2f0) at ./cpus.c:1431 12 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=0x55555686a2f0) at ./cpus.c:1735 13 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=arg@entry=0x55555686a2f0) at ./cpus.c:1709 14 0x0000555555d2629a in qemu_thread_start (args=) at ./util/qemu-thread-posix.c:502 15 0x00007ffff4db8a92 in start_thread () at /usr/lib/libpthread. This patch ensures that we don't hit the abort() in the second switch case in disas_neon_data_insn() as we will return from the first case. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Tested-by: Alex Bennée Message-id: ad91b397f360b2fc7f4087e476f7df5b04d42ddb.1558021877.git.alistair.francis@wdc.com Signed-off-by: Peter Maydell --- target/arm/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.20.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index dd053c80d62..298c262825d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6598,13 +6598,13 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc), rn_ofs, rm_ofs, vec_size, vec_size, (u ? uqadd_op : sqadd_op) + size); - break; + return 0; case NEON_3R_VQSUB: tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc), rn_ofs, rm_ofs, vec_size, vec_size, (u ? uqsub_op : sqsub_op) + size); - break; + return 0; case NEON_3R_VMUL: /* VMUL */ if (u) { From patchwork Thu May 23 14:23:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 165022 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2272609ili; Thu, 23 May 2019 07:32:41 -0700 (PDT) X-Google-Smtp-Source: APXvYqxCap2l1ybzIACR4WXX+m5JK9ILKg+Xxrm6EIw1ZVUfhBCn4kXPSc7S39KJYe1yKMOC6NHD X-Received: by 2002:a50:8903:: with SMTP id e3mr96164362ede.11.1558621961040; Thu, 23 May 2019 07:32:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558621961; cv=none; d=google.com; s=arc-20160816; b=DfWiBd27H4CEQmW1KEklUjxr+weoCJXci4qjfEgIgYxVwDL1MU/nT7WpuQn0956eXQ OfMevQuD1NOI98WwNBjfigMjgtLTL4qr1NiBEO1CqY0reElG9COdv37jFBeVXCI1q9e+ XUtn0tbCZ855rVpVU0Gp2j6CaTaMsd5uViyQ98bBPwWT0R4GVNedL50My2PUo1VjeqVC a2eYUR2c+Nc7r2jwcdaVumcuU0J3E38dkZEOv774eMj+9V68rpHYPDb0oZSyMxJEM4cd EyDhLP5+WfvTBb2R14/G1dGXgS5e+vHHFiZ3qiy1jVCUjtpokkj/b3ZyuRuUWZrGvwqT Avxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=k8+as5vxyhPXtpSjQtu+M6OtKD81u0dXi3n3hnTR2ug=; b=zonc7yBWiz5kX1OF0dImyj1ayR2qaiGzZujsGLRVYAoCY6HT7bfCzV38+FtQJrN+jb VYC0FBs+8ZzeL4QtWDCiUZsJTHSuhp//OIqBNkXFoTpm4TuXuDKKVqH+/gIWlQYVo58w 9rSbAXshVV5x0/FEXSNqDQthxefXgKyPi+62EN8SdizekE0xm4umAAtDleuBVtaXBrKU 3FpzCUhfg5jGLKCOHhYzH15KHVUbGR4mwqjPaNqHQTWmSItGHgXVhcsoYsH3cevHf+Z2 nb0F3rEvraLtqOg4E4ySyeFBnzYP44E3jHSbPoWpUWAMWaS9spcZPAQj+r6A3fh+nQMy RVOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=q6JOjqqi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z5sm9700617wmi.34.2019.05.23.07.24.02 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 May 2019 07:24:03 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 23 May 2019 15:23:49 +0100 Message-Id: <20190523142357.5175-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190523142357.5175-1-peter.maydell@linaro.org> References: <20190523142357.5175-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PULL 04/12] arm: Move system_clock_scale to armv7m_systick.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The system_clock_scale global is used only by the armv7m systick device; move the extern declaration to the armv7m_systick.h header, and expand the comment to explain what it is and that it should ideally be replaced with a different approach. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Message-id: 20190516163857.6430-2-peter.maydell@linaro.org --- include/hw/arm/arm.h | 4 ---- include/hw/timer/armv7m_systick.h | 22 ++++++++++++++++++++++ 2 files changed, 22 insertions(+), 4 deletions(-) -- 2.20.1 diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h index ffed39252d8..ba3a9b41422 100644 --- a/include/hw/arm/arm.h +++ b/include/hw/arm/arm.h @@ -167,8 +167,4 @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, const struct arm_boot_info *info, hwaddr mvbar_addr); -/* Multiplication factor to convert from system clock ticks to qemu timer - ticks. */ -extern int system_clock_scale; - #endif /* HW_ARM_H */ diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h index cca04defd8e..25e5ceacc85 100644 --- a/include/hw/timer/armv7m_systick.h +++ b/include/hw/timer/armv7m_systick.h @@ -31,4 +31,26 @@ typedef struct SysTickState { qemu_irq irq; } SysTickState; +/* + * Multiplication factor to convert from system clock ticks to qemu timer + * ticks. This should be set (by board code, usually) to a value + * equal to NANOSECONDS_PER_SECOND / frq, where frq is the clock frequency + * in Hz of the CPU. + * + * This value is used by the systick device when it is running in + * its "use the CPU clock" mode (ie when SYST_CSR.CLKSOURCE == 1) to + * set how fast the timer should tick. + * + * TODO: we should refactor this so that rather than using a global + * we use a device property or something similar. This is complicated + * because (a) the property would need to be plumbed through from the + * board code down through various layers to the systick device + * and (b) the property needs to be modifiable after realize, because + * the stellaris board uses this to implement the behaviour where the + * guest can reprogram the PLL registers to downclock the CPU, and the + * systick device needs to react accordingly. Possibly this should + * be deferred until we have a good API for modelling clock trees. + */ +extern int system_clock_scale; + #endif From patchwork Thu May 23 14:23:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 165018 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2265383ili; Thu, 23 May 2019 07:27:21 -0700 (PDT) X-Google-Smtp-Source: APXvYqzWtIxu88QfZ2BdeFKsEW6AUZvFTl2R5+WAMp3lZKMsEsSkuKwQJP1ktQ/l5DWVCZuIgnxB X-Received: by 2002:a17:906:4244:: with SMTP id r4mr61785574ejl.211.1558621641000; Thu, 23 May 2019 07:27:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558621640; cv=none; d=google.com; s=arc-20160816; b=HBrF0FStHLdSAhLq8JO/LaSvhKyhylxbymAYp3KcGTGM1vqY9aGrNWZLM+G06FTkaH 7uuhAun7E2crvyVt/cX26LC8Hn+PWqxoe27KmPOVnU615RfMDNAziaQg8bSSDilZMXGN OORWHCmV+hKawdSx5VvYe1XzMZ73Sv/ddCp/cgJQ6OkEx82KzQO7ZMUpgXVd3Sit+flC Eekq12dPVF0wwkUt3SdWnhtuhda/PU1qqzoWyb7bNFXk0LeqXYypYFdhQN3UsthAPGOd 1iGzkzysD6b4fdi8g0JA7Smfpu7ZCSFqmqwVwumWSt0N+pyxf8FsQETWiMUBUVIZ+0eL qgVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=aPHvP77EG+2v9a9J5aEUYg8t8lA/BUnM+q643Wx7cho=; b=LpmFFvhSbp1BOesx8xAohRkAiWZCaaDl+oe1p+kv6SC/EwaFfqP7djlDQ01KKzS1fn 4mT0FrNEebFBnL3gweIhqyjIZ3Dah4if9w9tV1hrTkrh6XeGDPfSE5CItymH5/Kqo0R7 W2CsLIIcdDLtCefkPlAJ0n06HTqSM701m21uGqSPPIqAz0R1C7AbDxTF1tdExwoI1e7T lBgXtJ+rXXVkoOWbNxTLXYnuNlD7KV/3SSzXKlEJOB2l/VlYRbCsyJpB1iyrdvIj96CY BXVPFmI62KgGj+OlL90vd4p4S5Oimb+p4px9sPymE1pmF3NoEgFPpO9RcwsGiJXL6vMz 9ZHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vACYtOFu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z5sm9700617wmi.34.2019.05.23.07.24.04 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 May 2019 07:24:04 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 23 May 2019 15:23:50 +0100 Message-Id: <20190523142357.5175-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190523142357.5175-1-peter.maydell@linaro.org> References: <20190523142357.5175-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PULL 05/12] arm: Remove unnecessary includes of hw/arm/arm.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The hw/arm/arm.h header now only includes declarations relating to boot.c code, so it is only needed by Arm board or SoC code. Remove some unnecessary inclusions of it from target/arm files and from hw/intc/armv7m_nvic.c. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Message-id: 20190516163857.6430-3-peter.maydell@linaro.org --- hw/intc/armv7m_nvic.c | 1 - target/arm/arm-semi.c | 1 - target/arm/cpu.c | 1 - target/arm/cpu64.c | 1 - target/arm/kvm.c | 1 - target/arm/kvm32.c | 1 - target/arm/kvm64.c | 1 - 7 files changed, 7 deletions(-) -- 2.20.1 diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 3a346a682a3..815e720cfab 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -16,7 +16,6 @@ #include "cpu.h" #include "hw/sysbus.h" #include "qemu/timer.h" -#include "hw/arm/arm.h" #include "hw/intc/armv7m_nvic.h" #include "target/arm/cpu.h" #include "exec/exec-all.h" diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c index 8b5fd7bc6e3..ddb94e0aba0 100644 --- a/target/arm/arm-semi.c +++ b/target/arm/arm-semi.c @@ -29,7 +29,6 @@ #else #include "qemu-common.h" #include "exec/gdbstub.h" -#include "hw/arm/arm.h" #include "qemu/cutils.h" #endif diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8eee1d8c59a..9b23ac2c935 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -30,7 +30,6 @@ #if !defined(CONFIG_USER_ONLY) #include "hw/loader.h" #endif -#include "hw/arm/arm.h" #include "sysemu/sysemu.h" #include "sysemu/hw_accel.h" #include "kvm_arm.h" diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 835f73cceb5..0ec8cd41f19 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -25,7 +25,6 @@ #if !defined(CONFIG_USER_ONLY) #include "hw/loader.h" #endif -#include "hw/arm/arm.h" #include "sysemu/sysemu.h" #include "sysemu/kvm.h" #include "kvm_arm.h" diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 59956346126..fe4f461d4ef 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -23,7 +23,6 @@ #include "cpu.h" #include "trace.h" #include "internals.h" -#include "hw/arm/arm.h" #include "hw/pci/pci.h" #include "exec/memattrs.h" #include "exec/address-spaces.h" diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index 327375f6252..4e54e372a66 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -20,7 +20,6 @@ #include "sysemu/kvm.h" #include "kvm_arm.h" #include "internals.h" -#include "hw/arm/arm.h" #include "qemu/log.h" static inline void set_feature(uint64_t *features, int feature) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index e3ba1492482..998d21f399f 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -26,7 +26,6 @@ #include "sysemu/kvm.h" #include "kvm_arm.h" #include "internals.h" -#include "hw/arm/arm.h" static bool have_guest_debug; From patchwork Thu May 23 14:23:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 165023 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2272596ili; Thu, 23 May 2019 07:32:40 -0700 (PDT) X-Google-Smtp-Source: APXvYqxNrEOst0gn+K7nRiuQlMZBYKOJP3Xz0Vriey4enE4NxQFrjYvK6wpvDHscOkK/1elblRi6 X-Received: by 2002:a17:906:265b:: with SMTP id i27mr35595144ejc.147.1558621960556; Thu, 23 May 2019 07:32:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558621960; cv=none; d=google.com; s=arc-20160816; b=f1WTAl5mCjUQEXc/WzZM9z5jZusjYb2Plg9ri53Dq2idQ55SIJcDAIzffZ7rplK6tS VOCRn6IjOIycL4FE2Ubk7LYd8+pybLm4YzJSd9jYMRZy6buHJUDuDn9+QURdQ1RcqWgJ qP0l1xSPnsquf5g5RMrzjir/NwNdhZMzpAwhBDlyqm7RByiIlhrvGxdl+wAw6VjFXCg1 d+4Ilh206mSbxXBOhexg8JzXc5ssihTbffXg6gHGPIuQzc33X3VvN/I9deQ5/PcXzRRS xwUOISwPHOYQD0KmWTmgIPJqIvTL4tCfktITJdRzbpceEaArasELGJutaG+Qeg0fe6MX fw6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=AApmP8aPCfH0hCSDFDOPzm0TWmC/u1RASs9C6mJHQzM=; b=V5vcmGtCMmuoyM7z8t2n4yyMeZjH4NNg4gD8V0rvZ1Xrm+LSjp0K4JfZsto2WE6Xad +Z66jyLZ06YmZ9Qh5GBHSBeW2qAgSPiUM/cWuOcXXz4uqEP886dFYTxcfG6fEzvJ8DhN z30YEl70B7EfhodN4kBwQ9f+UplgZNTZs3Gnx95l+jCbx2qztx8DQEoaE6d0J2XEj4dy 7Q9Fxkrfo70MQmLIwpB1Sa7rBtSbyJ9W1HDD543JbuSErDhp7sku2UOFdQtY1vqwiSEJ jz4/EhMPBqHUQHd2PawXtkop5rV3v32hwn0wxI3E9+RHCxIPQ7TmwiVeg3Ity55ijBGl +xxw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fqsgv3uH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z5sm9700617wmi.34.2019.05.23.07.24.05 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 May 2019 07:24:06 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 23 May 2019 15:23:51 +0100 Message-Id: <20190523142357.5175-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190523142357.5175-1-peter.maydell@linaro.org> References: <20190523142357.5175-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PULL 06/12] arm: Rename hw/arm/arm.h to hw/arm/boot.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The header file hw/arm/arm.h now includes only declarations relating to hw/arm/boot.c functionality. Rename it accordingly, and adjust its header comment. The bulk of this commit was created via perl -pi -e 's|hw/arm/arm.h|hw/arm/boot.h|' hw/arm/*.c include/hw/arm/*.h In a few cases we can just delete the #include: hw/arm/msf2-soc.c, include/hw/arm/aspeed_soc.h and include/hw/arm/bcm2836.h did not require it. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Message-id: 20190516163857.6430-4-peter.maydell@linaro.org --- include/hw/arm/allwinner-a10.h | 2 +- include/hw/arm/aspeed_soc.h | 1 - include/hw/arm/bcm2836.h | 1 - include/hw/arm/{arm.h => boot.h} | 8 ++++---- include/hw/arm/fsl-imx25.h | 2 +- include/hw/arm/fsl-imx31.h | 2 +- include/hw/arm/fsl-imx6.h | 2 +- include/hw/arm/fsl-imx6ul.h | 2 +- include/hw/arm/fsl-imx7.h | 2 +- include/hw/arm/virt.h | 2 +- include/hw/arm/xlnx-versal.h | 2 +- include/hw/arm/xlnx-zynqmp.h | 2 +- hw/arm/armsse.c | 2 +- hw/arm/armv7m.c | 2 +- hw/arm/aspeed.c | 2 +- hw/arm/boot.c | 2 +- hw/arm/collie.c | 2 +- hw/arm/exynos4210.c | 2 +- hw/arm/exynos4_boards.c | 2 +- hw/arm/highbank.c | 2 +- hw/arm/integratorcp.c | 2 +- hw/arm/mainstone.c | 2 +- hw/arm/microbit.c | 2 +- hw/arm/mps2-tz.c | 2 +- hw/arm/mps2.c | 2 +- hw/arm/msf2-soc.c | 1 - hw/arm/msf2-som.c | 2 +- hw/arm/musca.c | 2 +- hw/arm/musicpal.c | 2 +- hw/arm/netduino2.c | 2 +- hw/arm/nrf51_soc.c | 2 +- hw/arm/nseries.c | 2 +- hw/arm/omap1.c | 2 +- hw/arm/omap2.c | 2 +- hw/arm/omap_sx1.c | 2 +- hw/arm/palm.c | 2 +- hw/arm/raspi.c | 2 +- hw/arm/realview.c | 2 +- hw/arm/spitz.c | 2 +- hw/arm/stellaris.c | 2 +- hw/arm/stm32f205_soc.c | 2 +- hw/arm/strongarm.c | 2 +- hw/arm/tosa.c | 2 +- hw/arm/versatilepb.c | 2 +- hw/arm/vexpress.c | 2 +- hw/arm/virt.c | 2 +- hw/arm/xilinx_zynq.c | 2 +- hw/arm/xlnx-versal.c | 2 +- hw/arm/z2.c | 2 +- 49 files changed, 49 insertions(+), 52 deletions(-) rename include/hw/arm/{arm.h => boot.h} (98%) -- 2.20.1 diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h index 389e128d0fc..6305b9c586f 100644 --- a/include/hw/arm/allwinner-a10.h +++ b/include/hw/arm/allwinner-a10.h @@ -3,7 +3,7 @@ #include "qemu-common.h" #include "qemu/error-report.h" #include "hw/char/serial.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "hw/timer/allwinner-a10-pit.h" #include "hw/intc/allwinner-a10-pic.h" #include "hw/net/allwinner_emac.h" diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 11ec0179db5..836b2ba8bf1 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -12,7 +12,6 @@ #ifndef ASPEED_SOC_H #define ASPEED_SOC_H -#include "hw/arm/arm.h" #include "hw/intc/aspeed_vic.h" #include "hw/misc/aspeed_scu.h" #include "hw/misc/aspeed_sdmc.h" diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h index 93248399ba0..a2cb8454dea 100644 --- a/include/hw/arm/bcm2836.h +++ b/include/hw/arm/bcm2836.h @@ -11,7 +11,6 @@ #ifndef BCM2836_H #define BCM2836_H -#include "hw/arm/arm.h" #include "hw/arm/bcm2835_peripherals.h" #include "hw/intc/bcm2836_control.h" diff --git a/include/hw/arm/arm.h b/include/hw/arm/boot.h similarity index 98% rename from include/hw/arm/arm.h rename to include/hw/arm/boot.h index ba3a9b41422..c48cc4c2bca 100644 --- a/include/hw/arm/arm.h +++ b/include/hw/arm/boot.h @@ -1,5 +1,5 @@ /* - * Misc ARM declarations + * ARM kernel loader. * * Copyright (c) 2006 CodeSourcery. * Written by Paul Brook @@ -8,8 +8,8 @@ * */ -#ifndef HW_ARM_H -#define HW_ARM_H +#ifndef HW_ARM_BOOT_H +#define HW_ARM_BOOT_H #include "exec/memory.h" #include "target/arm/cpu-qom.h" @@ -167,4 +167,4 @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, const struct arm_boot_info *info, hwaddr mvbar_addr); -#endif /* HW_ARM_H */ +#endif /* HW_ARM_BOOT_H */ diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h index 65a73714efe..3280ab1fb05 100644 --- a/include/hw/arm/fsl-imx25.h +++ b/include/hw/arm/fsl-imx25.h @@ -17,7 +17,7 @@ #ifndef FSL_IMX25_H #define FSL_IMX25_H -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "hw/intc/imx_avic.h" #include "hw/misc/imx25_ccm.h" #include "hw/char/imx_serial.h" diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h index d408abbba0d..e68a81efd75 100644 --- a/include/hw/arm/fsl-imx31.h +++ b/include/hw/arm/fsl-imx31.h @@ -17,7 +17,7 @@ #ifndef FSL_IMX31_H #define FSL_IMX31_H -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "hw/intc/imx_avic.h" #include "hw/misc/imx31_ccm.h" #include "hw/char/imx_serial.h" diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h index 06f8aaeda42..1265a55c3b0 100644 --- a/include/hw/arm/fsl-imx6.h +++ b/include/hw/arm/fsl-imx6.h @@ -17,7 +17,7 @@ #ifndef FSL_IMX6_H #define FSL_IMX6_H -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "hw/cpu/a9mpcore.h" #include "hw/misc/imx6_ccm.h" #include "hw/misc/imx6_src.h" diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h index 58972171943..9e94e98f8ee 100644 --- a/include/hw/arm/fsl-imx6ul.h +++ b/include/hw/arm/fsl-imx6ul.h @@ -17,7 +17,7 @@ #ifndef FSL_IMX6UL_H #define FSL_IMX6UL_H -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "hw/cpu/a15mpcore.h" #include "hw/misc/imx6ul_ccm.h" #include "hw/misc/imx6_src.h" diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h index d848262bfdd..4101f80251e 100644 --- a/include/hw/arm/fsl-imx7.h +++ b/include/hw/arm/fsl-imx7.h @@ -19,7 +19,7 @@ #ifndef FSL_IMX7_H #define FSL_IMX7_H -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "hw/cpu/a15mpcore.h" #include "hw/intc/imx_gpcv2.h" #include "hw/misc/imx7_ccm.h" diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 424070924ed..73005f05ae8 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -34,7 +34,7 @@ #include "exec/hwaddr.h" #include "qemu/notify.h" #include "hw/boards.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "hw/block/flash.h" #include "sysemu/kvm.h" #include "hw/intc/arm_gicv3_common.h" diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index ec7c859d08c..14405c1465d 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -13,7 +13,7 @@ #define XLNX_VERSAL_H #include "hw/sysbus.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "hw/intc/arm_gicv3.h" #define TYPE_XLNX_VERSAL "xlnx-versal" diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 591515c7600..cd90b04310c 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -18,7 +18,7 @@ #ifndef XLNX_ZYNQMP_H #include "qemu-common.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "hw/intc/arm_gic.h" #include "hw/net/cadence_gem.h" #include "hw/char/cadence_uart.h" diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 76cc6905798..83b920334d5 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -17,7 +17,7 @@ #include "hw/sysbus.h" #include "hw/registerfields.h" #include "hw/arm/armsse.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" /* Format of the System Information block SYS_CONFIG register */ typedef enum SysConfigFormat { diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index c4b2a9a1f5c..029572258f0 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -13,7 +13,7 @@ #include "qemu-common.h" #include "cpu.h" #include "hw/sysbus.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "hw/loader.h" #include "elf.h" #include "sysemu/qtest.h" diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 29d225ed140..415cff7a015 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -14,7 +14,7 @@ #include "qemu-common.h" #include "cpu.h" #include "exec/address-spaces.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "hw/arm/aspeed.h" #include "hw/arm/aspeed_soc.h" #include "hw/boards.h" diff --git a/hw/arm/boot.c b/hw/arm/boot.c index a830655e1af..7279185bd94 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -12,7 +12,7 @@ #include "qapi/error.h" #include #include "hw/hw.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "hw/arm/linux-boot-if.h" #include "sysemu/kvm.h" #include "sysemu/sysemu.h" diff --git a/hw/arm/collie.c b/hw/arm/collie.c index d12604c5739..3db3c560048 100644 --- a/hw/arm/collie.c +++ b/hw/arm/collie.c @@ -14,7 +14,7 @@ #include "hw/sysbus.h" #include "hw/boards.h" #include "strongarm.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "hw/block/flash.h" #include "exec/address-spaces.h" #include "cpu.h" diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index af82e955421..0bf61134550 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -30,7 +30,7 @@ #include "hw/boards.h" #include "sysemu/sysemu.h" #include "hw/sysbus.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "hw/loader.h" #include "hw/arm/exynos4210.h" #include "hw/sd/sdhci.h" diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c index ea8100f65a8..71f0af3bdbb 100644 --- a/hw/arm/exynos4_boards.c +++ b/hw/arm/exynos4_boards.c @@ -29,7 +29,7 @@ #include "sysemu/sysemu.h" #include "hw/sysbus.h" #include "net/net.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "exec/address-spaces.h" #include "hw/arm/exynos4210.h" #include "hw/net/lan9118.h" diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index 96ccf18d863..a89a1d3a7c1 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/sysbus.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "hw/loader.h" #include "net/net.h" #include "sysemu/kvm.h" diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c index 0b6f24465e4..d18caab8bdd 100644 --- a/hw/arm/integratorcp.c +++ b/hw/arm/integratorcp.c @@ -13,7 +13,7 @@ #include "cpu.h" #include "hw/sysbus.h" #include "hw/boards.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "hw/misc/arm_integrator_debug.h" #include "hw/net/smc91c111.h" #include "net/net.h" diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c index c1cec590379..cd1f904c6c9 100644 --- a/hw/arm/mainstone.c +++ b/hw/arm/mainstone.c @@ -16,7 +16,7 @@ #include "qapi/error.h" #include "hw/hw.h" #include "hw/arm/pxa.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "net/net.h" #include "hw/net/smc91c111.h" #include "hw/boards.h" diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c index da67bf6d9d1..e9a891f7d37 100644 --- a/hw/arm/microbit.c +++ b/hw/arm/microbit.c @@ -11,7 +11,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/boards.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "sysemu/sysemu.h" #include "exec/address-spaces.h" diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 7832408bb70..c167a5fa593 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -40,7 +40,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/error-report.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "hw/arm/armv7m.h" #include "hw/or-irq.h" #include "hw/boards.h" diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 54b7395849f..b74f1378c90 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -25,7 +25,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/error-report.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "hw/arm/armv7m.h" #include "hw/or-irq.h" #include "hw/boards.h" diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c index 2702e90b453..d700b212f8d 100644 --- a/hw/arm/msf2-soc.c +++ b/hw/arm/msf2-soc.c @@ -26,7 +26,6 @@ #include "qemu/units.h" #include "qapi/error.h" #include "qemu-common.h" -#include "hw/arm/arm.h" #include "exec/address-spaces.h" #include "hw/char/serial.h" #include "hw/boards.h" diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c index 2432b5e9352..8c550a8bddc 100644 --- a/hw/arm/msf2-som.c +++ b/hw/arm/msf2-som.c @@ -27,7 +27,7 @@ #include "qapi/error.h" #include "qemu/error-report.h" #include "hw/boards.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "exec/address-spaces.h" #include "hw/arm/msf2-soc.h" #include "cpu.h" diff --git a/hw/arm/musca.c b/hw/arm/musca.c index 23aff43f4bc..825d80e75a4 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -24,7 +24,7 @@ #include "qapi/error.h" #include "exec/address-spaces.h" #include "sysemu/sysemu.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "hw/arm/armsse.h" #include "hw/boards.h" #include "hw/char/pl011.h" diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index 93ec3c5698f..5645997b56f 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -14,7 +14,7 @@ #include "qemu-common.h" #include "cpu.h" #include "hw/sysbus.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "net/net.h" #include "sysemu/sysemu.h" #include "hw/boards.h" diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c index f936017d4a7..f57fc38f920 100644 --- a/hw/arm/netduino2.c +++ b/hw/arm/netduino2.c @@ -27,7 +27,7 @@ #include "hw/boards.h" #include "qemu/error-report.h" #include "hw/arm/stm32f205_soc.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" static void netduino2_init(MachineState *machine) { diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index 3e633d160ea..ce618edc7b3 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -11,7 +11,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu-common.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "hw/sysbus.h" #include "hw/boards.h" #include "hw/misc/unimp.h" diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c index 303f7a31e1c..4a79f5c88b4 100644 --- a/hw/arm/nseries.c +++ b/hw/arm/nseries.c @@ -25,7 +25,7 @@ #include "qemu/bswap.h" #include "sysemu/sysemu.h" #include "hw/arm/omap.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "hw/irq.h" #include "ui/console.h" #include "hw/boards.h" diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c index 539d29ef9ce..28fbe275a88 100644 --- a/hw/arm/omap1.c +++ b/hw/arm/omap1.c @@ -24,7 +24,7 @@ #include "cpu.h" #include "hw/boards.h" #include "hw/hw.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "hw/arm/omap.h" #include "sysemu/sysemu.h" #include "hw/arm/soc_dma.h" diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c index 446223906e4..23e72db79ef 100644 --- a/hw/arm/omap2.c +++ b/hw/arm/omap2.c @@ -26,7 +26,7 @@ #include "sysemu/qtest.h" #include "hw/boards.h" #include "hw/hw.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "hw/arm/omap.h" #include "sysemu/sysemu.h" #include "qemu/timer.h" diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c index 95a4fe7e7f0..cae78d0a368 100644 --- a/hw/arm/omap_sx1.c +++ b/hw/arm/omap_sx1.c @@ -31,7 +31,7 @@ #include "ui/console.h" #include "hw/arm/omap.h" #include "hw/boards.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "hw/block/flash.h" #include "sysemu/qtest.h" #include "exec/address-spaces.h" diff --git a/hw/arm/palm.c b/hw/arm/palm.c index 139d27d1cc0..9eb9612bce9 100644 --- a/hw/arm/palm.c +++ b/hw/arm/palm.c @@ -25,7 +25,7 @@ #include "ui/console.h" #include "hw/arm/omap.h" #include "hw/boards.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "hw/input/tsc2xxx.h" #include "hw/loader.h" #include "exec/address-spaces.h" diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index fe2bb511b98..2b5fe10e2f0 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -20,7 +20,7 @@ #include "qemu/error-report.h" #include "hw/boards.h" #include "hw/loader.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "sysemu/sysemu.h" #define SMPBOOT_ADDR 0x300 /* this should leave enough space for ATAGS */ diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 05a244df255..d42a76e7a1c 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -12,7 +12,7 @@ #include "qemu-common.h" #include "cpu.h" #include "hw/sysbus.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "hw/arm/primecell.h" #include "hw/net/lan9118.h" #include "hw/net/smc91c111.h" diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index 22f5958b9da..723cf5d5929 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -14,7 +14,7 @@ #include "qapi/error.h" #include "hw/hw.h" #include "hw/arm/pxa.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "sysemu/sysemu.h" #include "hw/pcmcia.h" #include "hw/i2c/i2c.h" diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 5059aedbaa2..499035f5c8f 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -11,7 +11,7 @@ #include "qapi/error.h" #include "hw/sysbus.h" #include "hw/ssi/ssi.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "qemu/timer.h" #include "hw/i2c/i2c.h" #include "net/net.h" diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c index 980e5af13c5..a5b6f7bda2b 100644 --- a/hw/arm/stm32f205_soc.c +++ b/hw/arm/stm32f205_soc.c @@ -25,7 +25,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu-common.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "exec/address-spaces.h" #include "hw/arm/stm32f205_soc.h" diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c index 644a9c45b4e..a1ecbddaab9 100644 --- a/hw/arm/strongarm.c +++ b/hw/arm/strongarm.c @@ -33,7 +33,7 @@ #include "hw/sysbus.h" #include "strongarm.h" #include "qemu/error-report.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "chardev/char-fe.h" #include "chardev/char-serial.h" #include "sysemu/sysemu.h" diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c index 9a1247797fe..7843d68d465 100644 --- a/hw/arm/tosa.c +++ b/hw/arm/tosa.c @@ -15,7 +15,7 @@ #include "qapi/error.h" #include "hw/hw.h" #include "hw/arm/pxa.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "hw/arm/sharpsl.h" #include "hw/pcmcia.h" #include "hw/boards.h" diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c index 25166e15171..f471fb70255 100644 --- a/hw/arm/versatilepb.c +++ b/hw/arm/versatilepb.c @@ -12,7 +12,7 @@ #include "qemu-common.h" #include "cpu.h" #include "hw/sysbus.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "hw/net/smc91c111.h" #include "net/net.h" #include "sysemu/sysemu.h" diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index d8634f3dd29..2b3b0c2334e 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -26,7 +26,7 @@ #include "qemu-common.h" #include "cpu.h" #include "hw/sysbus.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "hw/arm/primecell.h" #include "hw/net/lan9118.h" #include "hw/i2c/i2c.h" diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 5331ab71e22..bf54f10b515 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -33,7 +33,7 @@ #include "qemu/option.h" #include "qapi/error.h" #include "hw/sysbus.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "hw/arm/primecell.h" #include "hw/arm/virt.h" #include "hw/block/flash.h" diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index b3b82157597..198e3f97634 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -20,7 +20,7 @@ #include "qemu-common.h" #include "cpu.h" #include "hw/sysbus.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "net/net.h" #include "exec/address-spaces.h" #include "sysemu/sysemu.h" diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 5ee58c09be8..e8e4278eb3b 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -17,7 +17,7 @@ #include "net/net.h" #include "sysemu/sysemu.h" #include "sysemu/kvm.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "kvm_arm.h" #include "hw/misc/unimp.h" #include "hw/intc/arm_gicv3_common.h" diff --git a/hw/arm/z2.c b/hw/arm/z2.c index 1f906ef20bc..44aa748d39d 100644 --- a/hw/arm/z2.c +++ b/hw/arm/z2.c @@ -14,7 +14,7 @@ #include "qemu/osdep.h" #include "hw/hw.h" #include "hw/arm/pxa.h" -#include "hw/arm/arm.h" +#include "hw/arm/boot.h" #include "hw/i2c/i2c.h" #include "hw/ssi/ssi.h" #include "hw/boards.h" From patchwork Thu May 23 14:23:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 165016 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2265091ili; Thu, 23 May 2019 07:27:08 -0700 (PDT) X-Google-Smtp-Source: APXvYqzWgNUwAUOTQMr2/xl8jnS37CYtDU2T9w/xXkLq+O5EYlR8LRASNhsP8LKQuXzwDdE+nQo7 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z5sm9700617wmi.34.2019.05.23.07.24.06 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 May 2019 07:24:07 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 23 May 2019 15:23:52 +0100 Message-Id: <20190523142357.5175-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190523142357.5175-1-peter.maydell@linaro.org> References: <20190523142357.5175-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::334 Subject: [Qemu-devel] [PULL 07/12] hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1} X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In ich_vmcr_write() we enforce "writes of BPR fields to less than their minimum sets them to the minimum" by doing a "read vbpr and write it back" operation. A typo here meant that we weren't handling writes to these fields correctly, because we were reading from VBPR0 but writing to VBPR1. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20190520162809.2677-4-peter.maydell@linaro.org --- hw/intc/arm_gicv3_cpuif.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.20.1 diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index cbad6037f19..000bdbd6247 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -2366,7 +2366,7 @@ static void ich_vmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, /* Enforce "writing BPRs to less than minimum sets them to the minimum" * by reading and writing back the fields. */ - write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G0)); + write_vbpr(cs, GICV3_G0, read_vbpr(cs, GICV3_G0)); write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G1)); gicv3_cpuif_virt_update(cs); From patchwork Thu May 23 14:23:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 165024 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2275208ili; Thu, 23 May 2019 07:34:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqwxhJBVgkI+k7DxnYBVrUiqYWpsKKvSIv7QSQ6gpCvsmdIurDoPJefHx/WtDBov3LJZCp3C X-Received: by 2002:a17:906:774e:: with SMTP id o14mr51495018ejn.175.1558622078374; Thu, 23 May 2019 07:34:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558622078; cv=none; d=google.com; s=arc-20160816; b=QZOXWUBwvmN5YrHu3leozHnTDzRYD9G6zYRMbDBXfLKxwWC4gHOeqnyh+810FeZ/GC O3kl9G7FDvZkiQYeBeWXVL9oA66VZpVj5Str4QIw3SAElyJHRhkk1J71JARNwsS9kdT2 NxAGLGZLcxr9Jkf0rmqPP6U+kN1CgFevBrE7GToIOkL8mYv3nDb/SKRNPKTV6ZMoHNNS qZleWAh64QzI8FORmWQnzrjphao6woxJCYeMwyXV/C6PPIOFhK75vWu/93gz58Tqb4+O XLfezr2Z2m1SylsqdYQe1cvoWyvqs1UrFAOyxColflAMLRRIePKJWlRjlFQtlbCOawRg XWeA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=0a+RF8S0YvjE+0k16KJTj/Qgw1ZTceu2oeIc7kE90J8=; b=ED6zdGiL9ygr1BLaIBoOaM3fIgfak1ftzGmlVi15AEPydZXFbl1h5Y/GDi5gi8BXc1 UHIDj0BUFG0ZCKC12AGPsUpFrSWfN6qm2eYDuhXiqLUK4LHiNLmhwscIYHXG6cvJKoiU 8JkkQ1Cj0MDalnsdwQLBBQxcQuWkZ7LR/d69pZGRmihtuD/TanbaXhl7mz41nJH/BZTQ u/JuthN4Wg0QUzib/6IvsA5Tupdue95IHKxqy6XuUqB3rV1yR1rpVkG1blpbHYcrD8Ha MiXk4GRT08qduGTTrp6zdOcHe/Q6VXXRpga4jWDKA+xK4UM3tcqYL4RbT8M3H8PERv6r YjyQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=s36ruKot; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z5sm9700617wmi.34.2019.05.23.07.24.07 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 May 2019 07:24:08 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 23 May 2019 15:23:53 +0100 Message-Id: <20190523142357.5175-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190523142357.5175-1-peter.maydell@linaro.org> References: <20190523142357.5175-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PULL 08/12] hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The ICC_CTLR_EL3 register includes some bits which are aliases of bits in the ICC_CTLR_EL1(S) and (NS) registers. QEMU chooses to keep those bits in the cs->icc_ctlr_el1[] struct fields. Unfortunately a missing '~' in the code to update the bits in those fields meant that writing to ICC_CTLR_EL3 would corrupt the ICC_CLTR_EL1 register values. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20190520162809.2677-5-peter.maydell@linaro.org --- hw/intc/arm_gicv3_cpuif.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.20.1 diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 000bdbd6247..3b212d91c8f 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -1856,7 +1856,7 @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri, trace_gicv3_icc_ctlr_el3_write(gicv3_redist_affid(cs), value); /* *_EL1NS and *_EL1S bits are aliases into the ICC_CTLR_EL1 bits. */ - cs->icc_ctlr_el1[GICV3_NS] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); + cs->icc_ctlr_el1[GICV3_NS] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); if (value & ICC_CTLR_EL3_EOIMODE_EL1NS) { cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE; } @@ -1864,7 +1864,7 @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri, cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_CBPR; } - cs->icc_ctlr_el1[GICV3_S] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); + cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); if (value & ICC_CTLR_EL3_EOIMODE_EL1S) { cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_EOIMODE; } From patchwork Thu May 23 14:23:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 165026 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2275652ili; Thu, 23 May 2019 07:34:59 -0700 (PDT) X-Google-Smtp-Source: APXvYqzjcYJfcpeDfE5jG76xDmDwE0U6Bo0IofPm5TrZR0Dxx9NVEiPuCP4OmniTTH8LJpCS7Y2r X-Received: by 2002:a17:906:a3d7:: with SMTP id ca23mr44874928ejb.23.1558622099614; Thu, 23 May 2019 07:34:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558622099; cv=none; d=google.com; s=arc-20160816; b=c2znds/ozQtJVFlyXiakRSaKylHlgNrlGNbQTyLl73aJvwjZZ3kWDKmkHo1E33blCA G32UwLyENW2gvv7cBRycSJwpkRebIS4QTJubtObg0FCoQjIL/Z8wuFTql0nHciybia4P BCyWkPMsSawhnyB6SeiZZQ4NAElj5ee4Sn70X7B81MIreeTJLOa1b7rkbEgoKduttU+I lDuHSMza2sTcPKCH19ACvKEUGhhYmrE3B7FMb/ytzsrGOAqk8U0I4QyJBVd7TljHyrrX xMJ4j5tWedKfGiLGY/kLkVTdwApoqHiupf/TRtqmQ/0rYqx9B1dZ6l89ixXlMxoeIicB 5e3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=r8KGu8IeOBjMN2NrTnfDSqKnNbY/WeWtTXuKw6y5tUs=; b=F8udXrEsllazPYKmH2t3bej2QB2AnqQJVT8ueE1UhT0oEhbtpaUl+Q0X3+DqVBwZVK +WWzVeBSlWhdxGsO0MQ10Obq6ofVe+lapxl6VbR9WO2+KiXvvGy9ARbmBa4hzSX258t0 F9bYzfrQSIF3fUt6L1I7RJ4UygvIT+R+9+csVAsLXaGLh7s4Xnt4xqjOW6xpSbQAFWPi iVRhzAT+VnOIidrCJMq4nMUo1VxMz0itFQii3+WIQODlbf2lpKCaGv8Xe+MsizoyZcM5 ywLvfRtCb2EtdesTwTxrFt27UMMjFKMEYspPiwWMnbQYNKKC/zXsKw4lMW8BleZ7omff 5KfQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=VLvgCR18; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z5sm9700617wmi.34.2019.05.23.07.24.08 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 May 2019 07:24:08 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 23 May 2019 15:23:54 +0100 Message-Id: <20190523142357.5175-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190523142357.5175-1-peter.maydell@linaro.org> References: <20190523142357.5175-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42d Subject: [Qemu-devel] [PULL 09/12] hw/arm/exynos4: Remove unuseful debug code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-id: 20190520214342.13709-2-philmd@redhat.com Signed-off-by: Peter Maydell --- hw/arm/exynos4_boards.c | 24 ------------------------ 1 file changed, 24 deletions(-) -- 2.20.1 diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c index 71f0af3bdbb..1b82bce2f4d 100644 --- a/hw/arm/exynos4_boards.c +++ b/hw/arm/exynos4_boards.c @@ -35,20 +35,6 @@ #include "hw/net/lan9118.h" #include "hw/boards.h" -#undef DEBUG - -//#define DEBUG - -#ifdef DEBUG - #undef PRINT_DEBUG - #define PRINT_DEBUG(fmt, args...) \ - do { \ - fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ - } while (0) -#else - #define PRINT_DEBUG(fmt, args...) do {} while (0) -#endif - #define SMDK_LAN9118_BASE_ADDR 0x05000000 typedef enum Exynos4BoardType { @@ -140,16 +126,6 @@ exynos4_boards_init_common(MachineState *machine, exynos4_board_binfo.gic_cpu_if_addr = EXYNOS4210_SMP_PRIVATE_BASE_ADDR + 0x100; - PRINT_DEBUG("\n ram_size: %luMiB [0x%08lx]\n" - " kernel_filename: %s\n" - " kernel_cmdline: %s\n" - " initrd_filename: %s\n", - exynos4_board_ram_size[board_type] / 1048576, - exynos4_board_ram_size[board_type], - machine->kernel_filename, - machine->kernel_cmdline, - machine->initrd_filename); - exynos4_boards_init_ram(s, get_system_memory(), exynos4_board_ram_size[board_type]); From patchwork Thu May 23 14:23:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 165025 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2275543ili; Thu, 23 May 2019 07:34:55 -0700 (PDT) X-Google-Smtp-Source: APXvYqzEQzpAr1+8P7aTN9Zmvx80HCJCNr/vwnsu/ZkBviUY9gNn4dxiaSXGgfUMPug970Yfye8V X-Received: by 2002:a50:ac3a:: with SMTP id v55mr97482023edc.96.1558622094917; Thu, 23 May 2019 07:34:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558622094; cv=none; d=google.com; s=arc-20160816; b=AGcai6cuWro0i3VzMDqR/dx9F1lXwa7mP7K2IKffAS1c3YMR0t6LcJ3qLccbq6J/WA srHQtg1A0+HDPg/OmamPEgAuJQYQwITP43El3KWUHxoeEjv1ffZ5938QaW/QZoqKgDBe UXqVZoar+MFkvSH5KuwNbbQbHHVVK6mN77TdEMAsEmYJoxDfPtnwLlk45HGOFXyiOA0q tyQR6OHOLbitkcIBMxoXs09TfWKwGTJrBhb+3bPw2/GUZdr9aDVXBxaiAZdKluZZr/j2 yVrm3GB+eA4KFJJeeCdWaLv/Sqk9GxA13NxDoieLZh6z9vQnC53lLRMZjTi7Aj5PdXwk Q/wQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=azbgycPFZ1DsGwmKdNJoyt5+e00qL8Rz3KbWhOofhPo=; b=dgIxQG35c6Z8U+gYYLYAdga6QOFZZQwBSqptAi5uacCgCX2doo8GfbgvyrLO8vKhFk A4ZhFwSePraJksjiJ1D1T05omifzujN1oNtwuljQJhBjm89WcY4GOcpGGPYp9yfXsLaq Fiv+gRTqcvbFxth/spl4P1ulXkFTsa/fki2YdJAPyxRksvDM9SDH9o1T0gIkv7DkJAkZ MDxyZbcVRXEJ7uPrqJSxJhvJ3KUCVjA0cgUmpOkcVwHSm7vrBDDLanNXMDeGg9eQfQ6f uz791yfqe4pjyEnzOKgBnBJaPu4NUtQff52lmtYtP/GLyUqsaF6ESfc375FLamghjohv cWyA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vycBGIs8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z5sm9700617wmi.34.2019.05.23.07.24.09 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 May 2019 07:24:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 23 May 2019 15:23:55 +0100 Message-Id: <20190523142357.5175-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190523142357.5175-1-peter.maydell@linaro.org> References: <20190523142357.5175-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::430 Subject: [Qemu-devel] [PULL 10/12] hw/arm/exynos4: Use the IEC binary prefix definitions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé It eases code review, unit is explicit. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-id: 20190520214342.13709-3-philmd@redhat.com Signed-off-by: Peter Maydell --- hw/arm/exynos4_boards.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.20.1 diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c index 1b82bce2f4d..fa0d7016413 100644 --- a/hw/arm/exynos4_boards.c +++ b/hw/arm/exynos4_boards.c @@ -22,6 +22,7 @@ */ #include "qemu/osdep.h" +#include "qemu/units.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "qemu-common.h" @@ -60,8 +61,8 @@ static int exynos4_board_smp_bootreg_addr[EXYNOS4_NUM_OF_BOARDS] = { }; static unsigned long exynos4_board_ram_size[EXYNOS4_NUM_OF_BOARDS] = { - [EXYNOS4_BOARD_NURI] = 0x40000000, - [EXYNOS4_BOARD_SMDKC210] = 0x40000000, + [EXYNOS4_BOARD_NURI] = 1 * GiB, + [EXYNOS4_BOARD_SMDKC210] = 1 * GiB, }; static struct arm_boot_info exynos4_board_binfo = { From patchwork Thu May 23 14:23:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 165020 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2268984ili; Thu, 23 May 2019 07:30:06 -0700 (PDT) X-Google-Smtp-Source: APXvYqxb8dh1wtI/pv4zNgcEKknkTttwKNeksghCmrrt9E11E70R6j8jtY8SpMkhOAlRdO0SH8v+ X-Received: by 2002:a17:906:f84a:: with SMTP id ks10mr59196736ejb.65.1558621805988; Thu, 23 May 2019 07:30:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558621805; cv=none; d=google.com; s=arc-20160816; b=XYaRmdIMeBo/+/vdT9JeUD7/78MBYtP/oJX9GCyBuEb8kBSPbQL2kZrSJebLfggCJ8 lPOLcy7ADMbZevZJEFmVJmZl5DB7lIeEG1SMuzscFGCkhubCfAmgANfqgwobiXcI4QDy ObdjbXIC2uTUAE/3Itw56YKmuufb0lGKqF4qnJNG0mq39wqK/aVXLW0vwr1J37r0snMO XxwYAy59y0DHTY/nfi+gMZQoAiODgDDfyFbzoAgdSuK6qDPPKpoLUQWnwDiz431zGvc/ dYLFPlMwNFmolfVMpgfOaLazbAsk6kDtRDJv4GeRkFiBtYB08+kHP7hQPqHwhlh/HLbV ij1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=joq0WIkgIgBccOnX/tw/4BR0pXLnjvJzCw5NVsq1dWQ=; b=JN8far+1tPwxgaZQ2aRALuSDrpYa8Une+2GjHJ1whF3wWQZlLeVTVAx90U1QwfeK8J D0vUsaFCPuARSMRC/0XVAQId2kkdE9pssbDnTeDCBzDuBVF1v23NVuYl80wi480bYI0w HSX5gZ046P8/Uxdlpwrq3EgoOIGGE1peepWA21z7LUKYtMif9zfrf/RelMQ/5yBe5K+f GBO2BuZT39/xKNDBK3O5FuYlGFBDMSIVCFncWz2SRUb7SGs40xw8hi+9eGZUWlaKJNRq QC2NmUTmxa1hpq9QbE5WLECXcL3Ut0INHPDGCGPbKSkqQ+i4ihUzbpsGCwJ9WVVYPUYp OUog== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="u/WfZjtM"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z5sm9700617wmi.34.2019.05.23.07.24.10 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 May 2019 07:24:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 23 May 2019 15:23:56 +0100 Message-Id: <20190523142357.5175-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190523142357.5175-1-peter.maydell@linaro.org> References: <20190523142357.5175-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PULL 11/12] hw/arm/exynos4210: Add DMA support for the Exynos4210 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Guenter Roeck QEMU already supports pl330. Instantiate it for Exynos4210. Relevant part of Linux arch/arm/boot/dts/exynos4.dtsi: / { soc: soc { amba { pdma0: pdma@12680000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12680000 0x1000>; interrupts = ; clocks = <&clock CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <32>; }; pdma1: pdma@12690000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12690000 0x1000>; interrupts = ; clocks = <&clock CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <32>; }; mdma1: mdma@12850000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12850000 0x1000>; interrupts = ; clocks = <&clock CLK_MDMA>; clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <1>; }; }; }; }; Signed-off-by: Guenter Roeck Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daudé Message-id: 20190520214342.13709-4-philmd@redhat.com [PMD: Do not set default qdev properties, create the controllers in the SoC rather than the board (Peter Maydell), add dtsi in commit message] Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/exynos4210.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) -- 2.20.1 diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 0bf61134550..f942ed2be96 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -96,6 +96,11 @@ /* EHCI */ #define EXYNOS4210_EHCI_BASE_ADDR 0x12580000 +/* DMA */ +#define EXYNOS4210_PL330_BASE0_ADDR 0x12680000 +#define EXYNOS4210_PL330_BASE1_ADDR 0x12690000 +#define EXYNOS4210_PL330_BASE2_ADDR 0x12850000 + static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, 0x09, 0x00, 0x00, 0x00 }; @@ -160,6 +165,19 @@ static uint64_t exynos4210_calc_affinity(int cpu) return (0x9 << ARM_AFF1_SHIFT) | cpu; } +static void pl330_create(uint32_t base, qemu_irq irq, int nreq) +{ + SysBusDevice *busdev; + DeviceState *dev; + + dev = qdev_create(NULL, "pl330"); + qdev_prop_set_uint8(dev, "num_periph_req", nreq); + qdev_init_nofail(dev); + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, base); + sysbus_connect_irq(busdev, 0, irq); +} + Exynos4210State *exynos4210_init(MemoryRegion *system_mem) { Exynos4210State *s = g_new0(Exynos4210State, 1); @@ -410,5 +428,13 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem) sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR, s->irq_table[exynos4210_get_irq(28, 3)]); + /*** DMA controllers ***/ + pl330_create(EXYNOS4210_PL330_BASE0_ADDR, + qemu_irq_invert(s->irq_table[exynos4210_get_irq(35, 1)]), 32); + pl330_create(EXYNOS4210_PL330_BASE1_ADDR, + qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32); + pl330_create(EXYNOS4210_PL330_BASE2_ADDR, + qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1); 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z5sm9700617wmi.34.2019.05.23.07.24.11 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 May 2019 07:24:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 23 May 2019 15:23:57 +0100 Message-Id: <20190523142357.5175-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190523142357.5175-1-peter.maydell@linaro.org> References: <20190523142357.5175-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PULL 12/12] hw/arm/exynos4210: QOM'ify the Exynos4210 SoC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-id: 20190520214342.13709-5-philmd@redhat.com Signed-off-by: Peter Maydell --- include/hw/arm/exynos4210.h | 9 +++++++-- hw/arm/exynos4210.c | 28 ++++++++++++++++++++++++---- hw/arm/exynos4_boards.c | 9 ++++++--- 3 files changed, 37 insertions(+), 9 deletions(-) -- 2.20.1 diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h index 098a69ec73d..27c684e851d 100644 --- a/include/hw/arm/exynos4210.h +++ b/include/hw/arm/exynos4210.h @@ -85,6 +85,9 @@ typedef struct Exynos4210Irq { } Exynos4210Irq; typedef struct Exynos4210State { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ ARMCPU *cpu[EXYNOS4210_NCPUS]; Exynos4210Irq irqs; qemu_irq *irq_table; @@ -98,11 +101,13 @@ typedef struct Exynos4210State { I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER]; } Exynos4210State; +#define TYPE_EXYNOS4210_SOC "exynos4210" +#define EXYNOS4210_SOC(obj) \ + OBJECT_CHECK(Exynos4210State, obj, TYPE_EXYNOS4210_SOC) + void exynos4210_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info); -Exynos4210State *exynos4210_init(MemoryRegion *system_mem); - /* Initialize exynos4210 IRQ subsystem stub */ qemu_irq *exynos4210_init_irq(Exynos4210Irq *env); diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index f942ed2be96..e99e9cd11bd 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -178,9 +178,10 @@ static void pl330_create(uint32_t base, qemu_irq irq, int nreq) sysbus_connect_irq(busdev, 0, irq); } -Exynos4210State *exynos4210_init(MemoryRegion *system_mem) +static void exynos4210_realize(DeviceState *socdev, Error **errp) { - Exynos4210State *s = g_new0(Exynos4210State, 1); + Exynos4210State *s = EXYNOS4210_SOC(socdev); + MemoryRegion *system_mem = get_system_memory(); qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS]; SysBusDevice *busdev; DeviceState *dev; @@ -435,6 +436,25 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem) qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32); pl330_create(EXYNOS4210_PL330_BASE2_ADDR, qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1); - - return s; } + +static void exynos4210_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = exynos4210_realize; +} + +static const TypeInfo exynos4210_info = { + .name = TYPE_EXYNOS4210_SOC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(Exynos4210State), + .class_init = exynos4210_class_init, +}; + +static void exynos4210_register_types(void) +{ + type_register_static(&exynos4210_info); +} + +type_init(exynos4210_register_types) diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c index fa0d7016413..71f58586c14 100644 --- a/hw/arm/exynos4_boards.c +++ b/hw/arm/exynos4_boards.c @@ -45,7 +45,7 @@ typedef enum Exynos4BoardType { } Exynos4BoardType; typedef struct Exynos4BoardState { - Exynos4210State *soc; + Exynos4210State soc; MemoryRegion dram0_mem; MemoryRegion dram1_mem; } Exynos4BoardState; @@ -130,7 +130,10 @@ exynos4_boards_init_common(MachineState *machine, exynos4_boards_init_ram(s, get_system_memory(), exynos4_board_ram_size[board_type]); - s->soc = exynos4210_init(get_system_memory()); + object_initialize(&s->soc, sizeof(s->soc), TYPE_EXYNOS4210_SOC); + qdev_set_parent_bus(DEVICE(&s->soc), sysbus_get_default()); + object_property_set_bool(OBJECT(&s->soc), true, "realized", + &error_fatal); return s; } @@ -148,7 +151,7 @@ static void smdkc210_init(MachineState *machine) EXYNOS4_BOARD_SMDKC210); lan9215_init(SMDK_LAN9118_BASE_ADDR, - qemu_irq_invert(s->soc->irq_table[exynos4210_get_irq(37, 1)])); + qemu_irq_invert(s->soc.irq_table[exynos4210_get_irq(37, 1)])); arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo); }