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[83.9.1.37]) by smtp.gmail.com with ESMTPSA id u4-20020a2e9b04000000b00295a3a64816sm2777299lji.2.2023.04.05.03.48.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Apr 2023 03:48:37 -0700 (PDT) From: Konrad Dybcio Date: Wed, 05 Apr 2023 12:48:34 +0200 Subject: [PATCH v2 1/2] dt-bindings: interrupt-controller: mpm: Pass MSG RAM slice through phandle MIME-Version: 1.0 Message-Id: <20230328-topic-msgram_mpm-v2-1-e24a48e57f0d@linaro.org> References: <20230328-topic-msgram_mpm-v2-0-e24a48e57f0d@linaro.org> In-Reply-To: <20230328-topic-msgram_mpm-v2-0-e24a48e57f0d@linaro.org> To: Andy Gross , Bjorn Andersson , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Shawn Guo Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680691715; l=2113; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=R+nl9I6wuHXVSNu7ub0x4qWS9SfiNOhOzZJ7YrNBpgo=; b=nkKf8A9vZ3gv5c16oKZQlCBsfqwPAK9cloJD47Af9w4oLjF/q/kjJyT9Hl4zHElrEPnSKgSNhvrx izmgdvb9B9gxIw16BlNtjyjYEqwTaT7Nulq0JppAGtU2sjuLOcj/ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Due to the wild nature of the Qualcomm RPM Message RAM, we can't really use 'reg' to point to the MPM's slice of Message RAM without cutting into an already-defined RPM MSG RAM node used for GLINK and SMEM. Document passing the register space as a slice of SRAM through the qcom,rpm-msg-ram property. This also makes 'reg' deprecated. Signed-off-by: Konrad Dybcio --- .../devicetree/bindings/interrupt-controller/qcom,mpm.yaml | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml index 509d20c091af..61fc5b1b74dc 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml @@ -29,6 +29,12 @@ properties: maxItems: 1 description: Specifies the base address and size of vMPM registers in RPM MSG RAM. + deprecated: true + + qcom,rpm-msg-ram: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the APSS MPM slice of the RPM Message RAM interrupts: maxItems: 1 @@ -64,23 +70,22 @@ properties: required: - compatible - - reg - interrupts - mboxes - interrupt-controller - '#interrupt-cells' - qcom,mpm-pin-count - qcom,mpm-pin-map + - qcom,rpm-msg-ram additionalProperties: false examples: - | #include - mpm: interrupt-controller@45f01b8 { + mpm: interrupt-controller { compatible = "qcom,mpm"; interrupts = ; - reg = <0x45f01b8 0x1000>; mboxes = <&apcs_glb 1>; interrupt-controller; #interrupt-cells = <2>; @@ -93,4 +98,5 @@ examples: <86 183>, <90 260>, <91 260>; + qcom,rpm-msg-ram = <&apss_mpm>; };