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Signed-off-by: Brad Larson Reviewed-by: Rob Herring --- .../devicetree/bindings/arm/amd,pensando.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/amd,pensando.yaml diff --git a/Documentation/devicetree/bindings/arm/amd,pensando.yaml b/Documentation/devicetree/bindings/arm/amd,pensando.yaml new file mode 100644 index 000000000000..e5c2591834a8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amd,pensando.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/amd,pensando.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Pensando SoC Platforms + +maintainers: + - Brad Larson + +properties: + $nodename: + const: "/" + compatible: + oneOf: + + - description: Boards with Pensando Elba SoC + items: + - enum: + - amd,pensando-elba-ortano + - const: amd,pensando-elba + +additionalProperties: true + +... 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2023 18:46:17.6947 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 232cf6d4-9d3e-4a13-102e-08db39f3de9d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT014.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8315 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the cadence qspi controller compatible for AMD Pensando Elba SoC boards. The Elba qspi fifo size is 1024. Signed-off-by: Brad Larson Reviewed-by: Krzysztof Kozlowski --- v11 changes: - Removed redundant if/then for amd,pensando-elba-qspi v10 changes: - Fix cdns,fifo-depth, only amd,pensando-elba-qspi is 1024 bytes v9 changes: - Add 1024 to cdns,fifo-depth property to resolve dtbs_check error --- .../bindings/spi/cdns,qspi-nor.yaml | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index 5c01db128be0..6e67de9da293 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -20,11 +20,28 @@ allOf: required: - power-domains + - if: + properties: + compatible: + contains: + const: amd,pensando-elba-qspi + then: + properties: + cdns,fifo-depth: + enum: [ 128, 256, 1024 ] + default: 1024 + else: + properties: + cdns,fifo-depth: + enum: [ 128, 256 ] + default: 128 + properties: compatible: oneOf: - items: - enum: + - amd,pensando-elba-qspi - ti,k2g-qspi - ti,am654-ospi - intel,lgm-qspi @@ -48,8 +65,6 @@ properties: description: Size of the data FIFO in words. $ref: /schemas/types.yaml#/definitions/uint32 - enum: [ 128, 256 ] - default: 128 cdns,fifo-width: $ref: /schemas/types.yaml#/definitions/uint32 From patchwork Mon Apr 10 18:45:16 2023 Content-Type: text/plain; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2023 18:46:32.7641 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bc221dac-1306-4a5c-db6c-08db39f3e79a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT052.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6630 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Support the AMD Pensando Elba SoC Controller which is a SPI connected device providing a miscellaneous set of essential board control/status registers. This device is present in all Pensando SoC based designs. Signed-off-by: Brad Larson Reviewed-by: Krzysztof Kozlowski --- v11 changes: - Fixed the compatible which should have stayed as 'amd,pensando-elba-ctrl', the commit message, and the filename - Reference spi-peripheral-props - Delete spi-max-frequency - Remove num-cs from example v10 changes: - Property renamed to amd,pensando-ctrl - Driver is renamed and moved to soc/drivers/amd affecting binding - Delete cs property, driver handles device node creation from parent num-cs fixing schema reg error in a different way v9 changes: - Instead of four nodes, one per chip-select, a single node is used with reset-cells in the parent. - No MFD API is used anymore in the driver so it made sense to move this to drivers/spi. - This driver is common for all Pensando SoC based designs so changed the name to pensando-sr.c to not make it Elba SoC specific. - Added property cs for the chip-select number which is used by the driver to create /dev/pensr0. --- .../soc/amd/amd,pensando-elba-ctrl.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/amd/amd,pensando-elba-ctrl.yaml diff --git a/Documentation/devicetree/bindings/soc/amd/amd,pensando-elba-ctrl.yaml b/Documentation/devicetree/bindings/soc/amd/amd,pensando-elba-ctrl.yaml new file mode 100644 index 000000000000..f1d3ed4f519b --- /dev/null +++ b/Documentation/devicetree/bindings/soc/amd/amd,pensando-elba-ctrl.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/amd/amd,pensando-elba-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Pensando Elba SoC Controller + +description: + The AMD Pensando Elba SoC Controller is a SPI connected device with essential + control/status registers accessed on chip select 0. This device is present + in all Pensando SoC based designs. + +maintainers: + - Brad Larson + +properties: + compatible: + enum: + - amd,pensando-elba-ctrl + + reg: + maxItems: 1 + + '#reset-cells': + const: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - '#reset-cells' + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + system-controller@0 { + compatible = "amd,pensando-elba-ctrl"; + reg = <0>; + spi-max-frequency = <12000000>; + interrupt-parent = <&porta>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + #reset-cells = <1>; + }; + }; + +... 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2023 18:46:52.0102 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 733c75f8-1ec3-423b-334c-08db39f3f311 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT105.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8164 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add ARCH_PENSANDO configuration option for AMD Pensando SoC based platforms. Signed-off-by: Brad Larson --- arch/arm64/Kconfig.platforms | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 89a0b13b058d..3510daaabe27 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -236,6 +236,18 @@ config ARCH_NPCM General support for NPCM8xx BMC (Arbel). Nuvoton NPCM8xx BMC based on the Cortex A35. +config ARCH_PENSANDO + bool "AMD Pensando Platforms" + help + This enables support for the ARMv8 based AMD Pensando SoC + family to include the Elba SoC. + + AMD Pensando SoCs support a range of Distributed Services + Cards in PCIe format installed into servers. The Elba + SoC includes 16 A-72 CPU cores, 144 programmable P4 + cores for a minimal latency/jitter datapath, and network + interfaces up to 200 Gb/s. + config ARCH_QCOM bool "Qualcomm Platforms" select GPIOLIB From patchwork Mon Apr 10 18:45:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 672121 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F1C7C76196 for ; Mon, 10 Apr 2023 18:47:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229971AbjDJSrZ (ORCPT ); Mon, 10 Apr 2023 14:47:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229995AbjDJSrT (ORCPT ); Mon, 10 Apr 2023 14:47:19 -0400 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2040.outbound.protection.outlook.com [40.107.236.40]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 11A8E1737; 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Mon, 10 Apr 2023 18:47:09 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT032.mail.protection.outlook.com (10.13.173.93) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6298.20 via Frontend Transport; Mon, 10 Apr 2023 18:47:09 +0000 Received: from platform-dev1.pensando.io (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 10 Apr 2023 13:47:06 -0500 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v13 09/15] spi: cadence-quadspi: Add compatible for AMD Pensando Elba SoC Date: Mon, 10 Apr 2023 11:45:20 -0700 Message-ID: <20230410184526.15990-10-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230410184526.15990-1-blarson@amd.com> References: <20230410184526.15990-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT032:EE_|SA1PR12MB8724:EE_ X-MS-Office365-Filtering-Correlation-Id: bfa20993-3530-46d4-acbb-08db39f3fd85 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2023 18:47:09.5508 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bfa20993-3530-46d4-acbb-08db39f3fd85 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT032.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8724 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The AMD Pensando Elba SoC has the Cadence QSPI controller integrated. The quirk CQSPI_NEEDS_APB_AHB_HAZARD_WAR is added and if enabled a dummy readback from the controller is performed to ensure synchronization. Signed-off-by: Brad Larson --- v9 changes: - Rebase to linux-next 6.2.0-rc1 --- drivers/spi/spi-cadence-quadspi.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 64b6a460d739..ad82d2ab3442 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -40,6 +40,7 @@ #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) #define CQSPI_SLOW_SRAM BIT(4) +#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5) /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) @@ -90,6 +91,7 @@ struct cqspi_st { u32 pd_dev_id; bool wr_completion; bool slow_sram; + bool apb_ahb_hazard; }; struct cqspi_driver_platdata { @@ -1004,6 +1006,13 @@ static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, if (cqspi->wr_delay) ndelay(cqspi->wr_delay); + /* + * If a hazard exists between the APB and AHB interfaces, perform a + * dummy readback from the controller to ensure synchronization. + */ + if (cqspi->apb_ahb_hazard) + readl(reg_base + CQSPI_REG_INDIRECTWR); + while (remaining > 0) { size_t write_words, mod_bytes; @@ -1734,6 +1743,8 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->wr_completion = false; if (ddata->quirks & CQSPI_SLOW_SRAM) cqspi->slow_sram = true; + if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) + cqspi->apb_ahb_hazard = true; if (of_device_is_compatible(pdev->dev.of_node, "xlnx,versal-ospi-1.0")) @@ -1859,6 +1870,10 @@ static const struct cqspi_driver_platdata versal_ospi = { .get_dma_status = cqspi_get_versal_dma_status, }; +static const struct cqspi_driver_platdata pensando_cdns_qspi = { + .quirks = CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE, +}; + static const struct of_device_id cqspi_dt_ids[] = { { .compatible = "cdns,qspi-nor", @@ -1884,6 +1899,10 @@ static const struct of_device_id cqspi_dt_ids[] = { .compatible = "intel,socfpga-qspi", .data = &socfpga_qspi, }, + { + .compatible = "amd,pensando-elba-qspi", + .data = &pensando_cdns_qspi, + }, { /* end of table */ } }; From patchwork Mon Apr 10 18:45:22 2023 Content-Type: text/plain; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2023 18:47:31.6101 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9df2f4cd-d3fa-490a-a878-08db39f40aab X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT038.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR12MB5425 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org SoCs with device specific Cadence implementation, such as setting byte-enables before the write, need to override writel(). Add a callback where the default is writel() for all existing chips. Signed-off-by: Brad Larson Acked-by: Adrian Hunter --- v10 changes: - The 1st patch adding private writel() is unchanged. The 2nd patch is split into two patches to provide for device specific init in one patch with no effect on existing designs. Then add the pensando support into the next patch. Then the 4th patch is mmc hardware reset support which is unchanged. v9 changes: - No change to this patch but as some patches are deleted and this is a respin the three successive patches to sdhci-cadence.c are patches 12, 13, and 14 which do the following: 1. Add ability for Cadence specific design to have priv writel(). 2. Add Elba SoC support that requires its own priv writel() for byte-lane control . 3. Add support for mmc hardware reset. --- drivers/mmc/host/sdhci-cadence.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c index 6f2de54a5987..708d4297f241 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -67,6 +67,7 @@ struct sdhci_cdns_phy_param { struct sdhci_cdns_priv { void __iomem *hrs_addr; bool enhanced_strobe; + void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg); unsigned int nr_phy_params; struct sdhci_cdns_phy_param phy_params[]; }; @@ -90,6 +91,12 @@ static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = { { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, }, }; +static inline void cdns_writel(struct sdhci_cdns_priv *priv, u32 val, + void __iomem *reg) +{ + writel(val, reg); +} + static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv, u8 addr, u8 data) { @@ -104,17 +111,17 @@ static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv, tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) | FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr); - writel(tmp, reg); + priv->priv_writel(priv, tmp, reg); tmp |= SDHCI_CDNS_HRS04_WR; - writel(tmp, reg); + priv->priv_writel(priv, tmp, reg); ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10); if (ret) return ret; tmp &= ~SDHCI_CDNS_HRS04_WR; - writel(tmp, reg); + priv->priv_writel(priv, tmp, reg); ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS04_ACK), 0, 10); @@ -191,7 +198,7 @@ static void sdhci_cdns_set_emmc_mode(struct sdhci_cdns_priv *priv, u32 mode) tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06); tmp &= ~SDHCI_CDNS_HRS06_MODE; tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode); - writel(tmp, priv->hrs_addr + SDHCI_CDNS_HRS06); + priv->priv_writel(priv, tmp, priv->hrs_addr + SDHCI_CDNS_HRS06); } static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv) @@ -223,7 +230,7 @@ static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val) */ for (i = 0; i < 2; i++) { tmp |= SDHCI_CDNS_HRS06_TUNE_UP; - writel(tmp, reg); + priv->priv_writel(priv, tmp, reg); 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Mon, 10 Apr 2023 13:47:46 -0500 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v13 13/15] mmc: sdhci-cadence: Add AMD Pensando Elba SoC support Date: Mon, 10 Apr 2023 11:45:24 -0700 Message-ID: <20230410184526.15990-14-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230410184526.15990-1-blarson@amd.com> References: <20230410184526.15990-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT103:EE_|DS7PR12MB5935:EE_ X-MS-Office365-Filtering-Correlation-Id: ac6a6a63-7dac-47e8-aa11-08db39f41594 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: IGUCWk+08nxlOIEwIu1fPzjOSgQL84fHP1Q2OmEdr9IaSPRG0HGDLKyD/A4RrN85W2XgNln5u4dq2mYZ/120KgPSlOZIqbQIboJC3wu5F28RROCbMH4EZ/3mpPCD81XfWjRh7j3jqxlpKlkE9pr5Burag5CRzKCDHnTWQc1IcTwR2yUDzA8oLDgzkq9GVVbJCs2xDVMB8G1/uikFVcEdMPChXc2WBAP1vput8yq6uBueOO0TEFKeia7WJh1SpzhZFYYXfU+lq0xnBL06KNjqgzKhYyec2s42BpzNBEo7Q8dXEWNAKN+I+QM3egxAORu3mDQSAJMC6k3I5YaPlVh1UviRAQUvAsrnvTT2DGsjWE7Ph4Cw+i3KLLqZZkZzsRovYbOHWegBX9DO6b74ScFo/LcJ6VADUlniKhhwdVMaUcXqKEQgxDEiTWRIa+MR88HoljfF1GcSw8SjJ+d6VuonvpUhYAyrPZUzsV7a0St09kStlLoqDfvpIZ5Aqgcct3BKzZqKmTLY3HFYMjvOr+85mSftp5O8PxMNfRsoM9H6zodOQg1tlXEAO7FOS4GHRNKq5T4ds6atPRyBYlmHzOXtGij9L1WGhfbO2yQqSjg3KsiUS5EVXTeklk38B/VGM4xLVhDcuT06Ju2n+tiefe/O9f69Dav2pj/8JKtjcLPxvYVizODFpeo1J5GeKFAFrLdM8gGIKPhyAIQK/2eoy5XwqeImwf/exrMRfEkoZcEUhxc= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230028)(4636009)(39860400002)(396003)(136003)(346002)(376002)(451199021)(36840700001)(46966006)(40470700004)(40460700003)(6916009)(7416002)(8676002)(4326008)(70586007)(82310400005)(82740400003)(70206006)(2906002)(316002)(81166007)(356005)(36756003)(5660300002)(8936002)(41300700001)(36860700001)(478600001)(7406005)(40480700001)(54906003)(426003)(336012)(2616005)(1076003)(26005)(186003)(16526019)(6666004)(83380400001)(47076005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2023 18:47:49.9143 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ac6a6a63-7dac-47e8-aa11-08db39f41594 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT103.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5935 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for AMD Pensando Elba SoC which explicitly controls byte-lane enables on writes. Select MMC_SDHCI_IO_ACCESSORS for MMC_SDHCI_CADENCE which allows Elba SoC sdhci_elba_ops to overwrite the SDHCI IO memory accessors Signed-off-by: Brad Larson Acked-by: Adrian Hunter --- v13 changes: - Use GENMASK(7, 3) in elba_priv_writel() to set all byte enables - Add a variable 'shift' with GENMASK(1, 0) in elba_write_w() and elba_write_b() to set the byte enable variable. v11 changes: - Remove elba-drv_init() call to platform_get_resource() since that check is done inside devm_platform_ioremap_resource() - Move spin_lock_init() before error check - Remove extra parentheses v10 changes: - Add Elba specific support into this 3rd patch. This builds on the private writel() enabled in patch 1 followed by platform specific init() in patch 2. - Specify when first used the reason for the spinlock use to order byte-enable prior to write data. --- drivers/mmc/host/Kconfig | 1 + drivers/mmc/host/sdhci-cadence.c | 98 ++++++++++++++++++++++++++++++++ 2 files changed, 99 insertions(+) diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 4745fe217ade..9f793892123c 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -255,6 +255,7 @@ config MMC_SDHCI_CADENCE tristate "SDHCI support for the Cadence SD/SDIO/eMMC controller" depends on MMC_SDHCI_PLTFM depends on OF + select MMC_SDHCI_IO_ACCESSORS help This selects the Cadence SD/SDIO/eMMC driver. diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c index c528a25f48b8..5d1e9cef74f5 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -66,6 +66,8 @@ struct sdhci_cdns_phy_param { struct sdhci_cdns_priv { void __iomem *hrs_addr; + void __iomem *ctl_addr; /* write control */ + spinlock_t wrlock; /* write lock */ bool enhanced_strobe; void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg); unsigned int nr_phy_params; @@ -321,6 +323,91 @@ static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host, sdhci_set_uhs_signaling(host, timing); } +/* Elba control register bits [6:3] are byte-lane enables */ +#define ELBA_BYTE_ENABLE_MASK(x) ((x) << 3) + +/* + * The Pensando Elba SoC explicitly controls byte-lane enabling on writes + * which includes writes to the HRS registers. The write lock (wrlock) + * is used to ensure byte-lane enable, using write control (ctl_addr), + * occurs before the data write. + */ +static void elba_priv_writel(struct sdhci_cdns_priv *priv, u32 val, + void __iomem *reg) +{ + unsigned long flags; + + spin_lock_irqsave(&priv->wrlock, flags); + writel(GENMASK(7, 3), priv->ctl_addr); + writel(val, reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static void elba_write_l(struct sdhci_host *host, u32 val, int reg) +{ + elba_priv_writel(sdhci_cdns_priv(host), val, host->ioaddr + reg); +} + +static void elba_write_w(struct sdhci_host *host, u16 val, int reg) +{ + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + u32 shift = reg & GENMASK(1, 0); + unsigned long flags; + u32 byte_enables; + + byte_enables = GENMASK(1, 0) << shift; + spin_lock_irqsave(&priv->wrlock, flags); + writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr); + writew(val, host->ioaddr + reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static void elba_write_b(struct sdhci_host *host, u8 val, int reg) +{ + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + u32 shift = reg & GENMASK(1, 0); + unsigned long flags; + u32 byte_enables; + + byte_enables = BIT(0) << shift; + spin_lock_irqsave(&priv->wrlock, flags); + writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr); + writeb(val, host->ioaddr + reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static const struct sdhci_ops sdhci_elba_ops = { + .write_l = elba_write_l, + .write_w = elba_write_w, + .write_b = elba_write_b, + .set_clock = sdhci_set_clock, + .get_timeout_clock = sdhci_cdns_get_timeout_clock, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_cdns_set_uhs_signaling, +}; + +static int elba_drv_init(struct platform_device *pdev) +{ + struct sdhci_host *host = platform_get_drvdata(pdev); + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + void __iomem *ioaddr; + + host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA; + spin_lock_init(&priv->wrlock); + + /* Byte-lane control register */ + ioaddr = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(ioaddr)) + return PTR_ERR(ioaddr); + + priv->ctl_addr = ioaddr; + priv->priv_writel = elba_priv_writel; + writel(ELBA_BYTE_ENABLE_MASK(0xf), priv->ctl_addr); + + return 0; +} + static const struct sdhci_ops sdhci_cdns_ops = { .set_clock = sdhci_set_clock, .get_timeout_clock = sdhci_cdns_get_timeout_clock, @@ -337,6 +424,13 @@ static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data = { }, }; +static const struct sdhci_cdns_drv_data sdhci_elba_drv_data = { + .init = elba_drv_init, + .pltfm_data = { + .ops = &sdhci_elba_ops, + }, +}; + static const struct sdhci_cdns_drv_data sdhci_cdns_drv_data = { .pltfm_data = { .ops = &sdhci_cdns_ops, @@ -477,6 +571,10 @@ static const struct of_device_id sdhci_cdns_match[] = { .compatible = "socionext,uniphier-sd4hc", .data = &sdhci_cdns_uniphier_drv_data, }, + { + .compatible = "amd,pensando-elba-sd4hc", + .data = &sdhci_elba_drv_data, + }, { .compatible = "cdns,sd4hc" }, { /* sentinel */ } }; From patchwork Mon Apr 10 18:45:26 2023 Content-Type: text/plain; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2023 18:48:10.5799 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 96715424-a04b-4e32-fab0-08db39f421e5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT085.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8419 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Pensando SoC controller is a SPI connected companion device that is present in all Pensando SoC board designs. The essential board management registers are accessed on chip select 0 with board mgmt IO support accessed using additional chip selects. Signed-off-by: Brad Larson --- v13 changes: - Update include list in pensando-ctrl.c - Change variable spi_dev to spi throughout - Removed unneeded variable initialization, simplification of error checks, remove extra castings, and use dev_err_probe() - Sort the includes in amd-pensando-ctrl.h - Updates to cleanup if there is an error in penctrl_spi_probe() v12 changes: - Fix gcc-12.1.0 warning: Reported-by: kernel test robot Link: https://lore.kernel.org/oe-kbuild-all/202303120925.SxLjwOd2-lkp@intel.com/ v11 changes: - Fix the compatible to be specific 'amd,pensando-elba-ctrl' v10 changes: - Different driver implementation specific to this Pensando controller device. - Moved to soc/amd directory under new name based on guidance. This driver is of no use to any design other than all Pensando SoC based cards. - Removed use of builtin_driver, can be built as a module. v9 changes: - Previously patch 14/17 - After the change to the device tree node and squashing reset-cells into the parent simplified this to not use any MFD API and move it to drivers/spi/pensando-sr.c. - Change the naming to remove elba since this driver is common for all Pensando SoC designs . - Default yes SPI_PENSANDO_SR for ARCH_PENSANDO --- drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/amd/Kconfig | 16 ++ drivers/soc/amd/Makefile | 2 + drivers/soc/amd/pensando-ctrl.c | 373 +++++++++++++++++++++++++ include/uapi/linux/amd-pensando-ctrl.h | 30 ++ 6 files changed, 423 insertions(+) create mode 100644 drivers/soc/amd/Kconfig create mode 100644 drivers/soc/amd/Makefile create mode 100644 drivers/soc/amd/pensando-ctrl.c create mode 100644 include/uapi/linux/amd-pensando-ctrl.h diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 4e176280113a..9e023f74e47c 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -2,6 +2,7 @@ menu "SOC (System On Chip) specific Drivers" source "drivers/soc/actions/Kconfig" +source "drivers/soc/amd/Kconfig" source "drivers/soc/amlogic/Kconfig" source "drivers/soc/apple/Kconfig" source "drivers/soc/aspeed/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 3b0f9fb3b5c8..8914530f2721 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -4,6 +4,7 @@ # obj-$(CONFIG_ARCH_ACTIONS) += actions/ +obj-y += amd/ obj-y += apple/ obj-y += aspeed/ obj-$(CONFIG_ARCH_AT91) += atmel/ diff --git a/drivers/soc/amd/Kconfig b/drivers/soc/amd/Kconfig new file mode 100644 index 000000000000..011d5339d14e --- /dev/null +++ b/drivers/soc/amd/Kconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-only +menu "AMD Pensando SoC drivers" + +config AMD_PENSANDO_CTRL + tristate "AMD Pensando SoC Controller" + depends on SPI_MASTER=y + depends on (ARCH_PENSANDO && OF) || COMPILE_TEST + default ARCH_PENSANDO + select REGMAP_SPI + select MFD_SYSCON + help + Enables AMD Pensando SoC controller device support. This is a SPI + attached companion device in all Pensando SoC board designs which + provides essential board control/status registers and management IO + support. +endmenu diff --git a/drivers/soc/amd/Makefile b/drivers/soc/amd/Makefile new file mode 100644 index 000000000000..a2de0424f68d --- /dev/null +++ b/drivers/soc/amd/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_AMD_PENSANDO_CTRL) += pensando-ctrl.o diff --git a/drivers/soc/amd/pensando-ctrl.c b/drivers/soc/amd/pensando-ctrl.c new file mode 100644 index 000000000000..6e4066564684 --- /dev/null +++ b/drivers/soc/amd/pensando-ctrl.c @@ -0,0 +1,373 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * AMD Pensando SoC Controller + * + * Userspace interface and reset driver support for SPI connected Pensando SoC + * controller device. This device is present in all Pensando SoC designs and + * contains board control/status registers and management IO support. + * + * Copyright 2023 Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct penctrl_device { + struct spi_device *spi; + struct reset_controller_dev rcdev; +}; + +static DEFINE_MUTEX(spi_lock); +static dev_t penctrl_devt; +static struct penctrl_device *penctrl; +static struct class *penctrl_class; + +static long +penctrl_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + void __user *in_arg = (void __user *)arg; + struct penctrl_device *penctrl; + u8 tx_buf[PENCTRL_MAX_MSG_LEN]; + u8 rx_buf[PENCTRL_MAX_MSG_LEN]; + struct spi_transfer t[2] = {}; + struct penctrl_spi_xfer *msg; + struct spi_device *spi; + unsigned int num_msgs; + struct spi_message m; + u32 size; + int ret; + + /* Check for a valid command */ + if (_IOC_TYPE(cmd) != PENCTRL_IOC_MAGIC) + return -ENOTTY; + + if (_IOC_NR(cmd) > PENCTRL_IOC_MAXNR) + return -ENOTTY; + + if (_IOC_DIR(cmd) & _IOC_READ) + ret = !access_ok(in_arg, _IOC_SIZE(cmd)); + else if (_IOC_DIR(cmd) & _IOC_WRITE) + ret = !access_ok(in_arg, _IOC_SIZE(cmd)); + + if (ret) + return -EFAULT; + + /* Get a reference to the SPI device */ + penctrl = filp->private_data; + if (!penctrl) + return -ESHUTDOWN; + + spi = spi_dev_get(penctrl->spi); + if (!spi) + return -ESHUTDOWN; + + /* Verify and prepare SPI message */ + size = _IOC_SIZE(cmd); + num_msgs = size / sizeof(struct penctrl_spi_xfer); + if (size == 0 || size % sizeof(struct penctrl_spi_xfer)) { + ret = -EINVAL; + goto done; + } + msg = memdup_user((struct penctrl_spi_xfer *)arg, size); + if (!msg) { + ret = PTR_ERR(msg); + goto done; + } + if (msg->len > PENCTRL_MAX_MSG_LEN) { + ret = -EINVAL; + goto done; + } + + t[0].tx_buf = tx_buf; + t[0].len = msg->len; + if (copy_from_user(tx_buf, (void __user *)msg->tx_buf, msg->len)) { + ret = -EFAULT; + goto done; + } + if (num_msgs > 1) { + msg++; + if (msg->len > PENCTRL_MAX_MSG_LEN) { + ret = -EINVAL; + goto done; + } + t[1].rx_buf = rx_buf; + t[1].len = msg->len; + } + spi_message_init_with_transfers(&m, t, num_msgs); + + /* Perform the transfer */ + mutex_lock(&spi_lock); + ret = spi_sync(spi, &m); + mutex_unlock(&spi_lock); + + if (ret || (num_msgs == 1)) + goto done; + + if (copy_to_user((void __user *)msg->rx_buf, rx_buf, msg->len)) + ret = -EFAULT; + +done: + spi_dev_put(spi); + return ret; +} + +static int penctrl_open(struct inode *inode, struct file *filp) +{ + struct spi_device *spi; + u8 current_cs; + + if (!penctrl) + return -ENODEV; + + filp->private_data = penctrl; + current_cs = iminor(inode); + spi = penctrl->spi; + spi->chip_select = current_cs; + spi->cs_gpiod = spi->controller->cs_gpiods[current_cs]; + spi_setup(spi); + return stream_open(inode, filp); +} + +static int penctrl_release(struct inode *inode, struct file *filp) +{ + filp->private_data = NULL; + return 0; +} + +static const struct file_operations penctrl_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = penctrl_ioctl, + .open = penctrl_open, + .release = penctrl_release, + .llseek = no_llseek, +}; + +static int penctrl_regs_read(struct penctrl_device *penctrl, u32 reg, u32 *val) +{ + struct spi_device *spi = penctrl->spi; + struct spi_transfer t[2] = {}; + struct spi_message m; + u8 txbuf[3]; + u8 rxbuf[1]; + int ret; + + txbuf[0] = PENCTRL_SPI_CMD_REGRD; + txbuf[1] = reg; + txbuf[2] = 0; + t[0].tx_buf = txbuf; + t[0].len = 3; + + rxbuf[0] = 0; + t[1].rx_buf = rxbuf; + t[1].len = 1; + + spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t)); + ret = spi_sync(spi, &m); + if (ret == 0) + *val = rxbuf[0]; + + return ret; +} + +static int penctrl_regs_write(struct penctrl_device *penctrl, u32 reg, u32 val) +{ + struct spi_device *spi = penctrl->spi; + struct spi_transfer t; + struct spi_message m; + u8 txbuf[4]; + + txbuf[0] = PENCTRL_SPI_CMD_REGWR; + txbuf[1] = reg; + txbuf[2] = val; + txbuf[3] = 0; + + t.tx_buf = txbuf; + t.len = 4; + spi_message_init_with_transfers(&m, &t, 1); + return spi_sync(spi, &m); +} + +static int penctrl_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct penctrl_device *penctrl = + container_of(rcdev, struct penctrl_device, rcdev); + struct spi_device *spi = penctrl->spi; + unsigned int val; + int ret; + + mutex_lock(&spi_lock); + spi->chip_select = 0; + spi->cs_gpiod = spi->controller->cs_gpiods[0]; + spi_setup(spi); + ret = penctrl_regs_read(penctrl, PENCTRL_REG_CTRL0, &val); + if (ret) { + dev_err(&spi->dev, "error reading ctrl0 reg\n"); + goto done; + } + + val |= BIT(6); + ret = penctrl_regs_write(penctrl, PENCTRL_REG_CTRL0, val); + if (ret) + dev_err(&spi->dev, "error writing ctrl0 reg\n"); + +done: + mutex_unlock(&spi_lock); + return ret; +} + +static int penctrl_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct penctrl_device *penctrl = + container_of(rcdev, struct penctrl_device, rcdev); + struct spi_device *spi = penctrl->spi; + unsigned int val; + int ret; + + mutex_lock(&spi_lock); + spi->chip_select = 0; + spi->cs_gpiod = spi->controller->cs_gpiods[0]; + spi_setup(spi); + ret = penctrl_regs_read(penctrl, PENCTRL_REG_CTRL0, &val); + if (ret) { + dev_err(&spi->dev, "error reading ctrl0 reg\n"); + goto done; + } + + val &= ~BIT(6); + ret = penctrl_regs_write(penctrl, PENCTRL_REG_CTRL0, val); + if (ret) + dev_err(&spi->dev, "error writing ctrl0 reg\n"); + +done: + mutex_unlock(&spi_lock); + return ret; +} + +static const struct reset_control_ops penctrl_reset_ops = { + .assert = penctrl_reset_assert, + .deassert = penctrl_reset_deassert, +}; + +static int penctrl_spi_probe(struct spi_device *spi) +{ + struct device *dev; + struct cdev *cdev; + u32 num_cs; + int ret; + u32 cs; + + ret = device_property_read_u32(spi->dev.parent, "num-cs", &num_cs); + if (ret) + return dev_err_probe(&spi->dev, ret, + "number of chip-selects not defined\n"); + + ret = alloc_chrdev_region(&penctrl_devt, 0, num_cs, "penctrl"); + if (ret) + return dev_err_probe(&spi->dev, ret, + "failed to alloc chrdev region\n"); + + penctrl_class = class_create(THIS_MODULE, "penctrl"); + if (IS_ERR(penctrl_class)) { + ret = dev_err_probe(&spi->dev, PTR_ERR(penctrl_class), + "failed to create class\n"); + goto unregister_chrdev; + } + + cdev = cdev_alloc(); + if (!cdev) { + ret = dev_err_probe(&spi->dev, -ENOMEM, + "allocation of cdev failed\n"); + goto destroy_class; + } + cdev->owner = THIS_MODULE; + cdev_init(cdev, &penctrl_fops); + + ret = cdev_add(cdev, penctrl_devt, num_cs); + if (ret) { + ret = dev_err_probe(&spi->dev, ret, + "register of cdev failed\n"); + goto free_cdev; + } + + /* Allocate driver data */ + penctrl = kzalloc(sizeof(*penctrl), GFP_KERNEL); + if (!penctrl) { + ret = -ENOMEM; + goto free_cdev; + } + penctrl->spi = spi; + mutex_init(&spi_lock); + + /* Create a device for each chip select */ + for (cs = 0; cs < num_cs; cs++) { + dev = device_create(penctrl_class, + &spi->dev, + MKDEV(MAJOR(penctrl_devt), cs), + penctrl, + "penctrl0.%d", + cs); + if (IS_ERR(dev)) { + ret = dev_err_probe(&spi->dev, PTR_ERR(dev), + "error creating device\n"); + goto destroy_device; + } + dev_dbg(&spi->dev, "created device major %u, minor %d\n", + MAJOR(penctrl_devt), cs); + } + + /* Register emmc hardware reset */ + penctrl->rcdev.nr_resets = 1; + penctrl->rcdev.owner = THIS_MODULE; + penctrl->rcdev.dev = &spi->dev; + penctrl->rcdev.ops = &penctrl_reset_ops; + penctrl->rcdev.of_node = spi->dev.of_node; + device_set_node(&spi->dev, dev_fwnode(dev)); + + ret = reset_controller_register(&penctrl->rcdev); + if (ret) + return dev_err_probe(&spi->dev, ret, + "failed to register reset controller\n"); + return 0; + +destroy_device: + for (cs = 0; cs < num_cs; cs++) + device_destroy(penctrl_class, MKDEV(MAJOR(penctrl_devt), cs)); + kfree(penctrl); +free_cdev: + cdev_del(cdev); +destroy_class: + class_destroy(penctrl_class); +unregister_chrdev: + unregister_chrdev(MAJOR(penctrl_devt), "penctrl"); + + return ret; +} + +static const struct of_device_id penctrl_dt_match[] = { + { .compatible = "amd,pensando-elba-ctrl" }, + { /* sentinel */ } +}; + +static struct spi_driver penctrl_spi_driver = { + .probe = penctrl_spi_probe, + .driver = { + .name = "pensando-ctrl", + .of_match_table = penctrl_dt_match, + }, +}; +module_spi_driver(penctrl_spi_driver); + +MODULE_AUTHOR("Brad Larson "); +MODULE_DESCRIPTION("AMD Pensando SoC Controller via SPI"); +MODULE_LICENSE("GPL"); diff --git a/include/uapi/linux/amd-pensando-ctrl.h b/include/uapi/linux/amd-pensando-ctrl.h new file mode 100644 index 000000000000..2508a1aef22c --- /dev/null +++ b/include/uapi/linux/amd-pensando-ctrl.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* + * Userspace interface for /dev/penctrl + * + * This file can be used by applications that need to communicate + * with the AMD Pensando SoC controller device via the ioctl interface. + */ +#ifndef _UAPI_LINUX_AMD_PENSANDO_CTRL_H +#define _UAPI_LINUX_AMD_PENSANDO_CTRL_H + +#include +#include + +#define PENCTRL_SPI_CMD_REGRD 0x0b +#define PENCTRL_SPI_CMD_REGWR 0x02 +#define PENCTRL_IOC_MAGIC 'k' +#define PENCTRL_IOC_MAXNR 0 +#define PENCTRL_MAX_MSG_LEN 16 +#define PENCTRL_MAX_REG 0xff +#define PENCTRL_REG_CTRL0 0x10 + +struct penctrl_spi_xfer { + __u64 tx_buf; + __u64 rx_buf; + __u32 len; + __u32 speed_hz; + __u64 compat; +}; + +#endif /* _UAPI_LINUX_AMD_PENSANDO_CTRL_H */