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Ip=[20.160.56.81]; Helo=[inpost-eu.tmcas.trendmicro.com] X-MS-Exchange-CrossTenant-AuthSource: AM6EUR05FT009.eop-eur05.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR03MB10109 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds a binding for the SerDes module found on QorIQ processors. Each phy is a subnode of the top-level device, possibly supporting multiple lanes and protocols. This "thick" #phy-cells is used due to allow for better organization of parameters. Note that the particular parameters necessary to select a protocol-controller/lane combination vary across different SoCs, and even within different SerDes on the same SoC. The driver is designed to be able to completely reconfigure lanes at runtime. Generally, the phy consumer can select the appropriate protocol using set_mode. There are two PLLs, each of which can be used as the master clock for each lane. Each PLL has its own reference. For the moment they are required, because it simplifies the driver implementation. Absent reference clocks can be modeled by a fixed-clock with a rate of 0. Signed-off-by: Sean Anderson Reviewed-by: Rob Herring --- (no changes since v9) Changes in v9: - Add fsl,unused-lanes-reserved to allow for a gradual transition between firmware and Linux control of the SerDes - Change phy-type back to fsl,type, as I was getting the error '#phy-cells' is a dependency of 'phy-type' Changes in v7: - Use double quotes everywhere in yaml Changes in v6: - fsl,type -> phy-type Changes in v4: - Use subnodes to describe lane configuration, instead of describing PCCRs. This is the same style used by phy-cadence-sierra et al. Changes in v3: - Manually expand yaml references - Add mode configuration to device tree Changes in v2: - Rename to fsl,lynx-10g.yaml - Refer to the device in the documentation, rather than the binding - Move compatible first - Document phy cells in the description - Allow a value of 1 for phy-cells. This allows for compatibility with the similar (but according to Ioana Ciornei different enough) lynx-28g binding. - Remove minItems - Use list for clock-names - Fix example binding having too many cells in regs - Add #clock-cells. This will allow using assigned-clocks* to configure the PLLs. - Document the structure of the compatible strings .../devicetree/bindings/phy/fsl,lynx-10g.yaml | 248 ++++++++++++++++++ 1 file changed, 248 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml diff --git a/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml b/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml new file mode 100644 index 000000000000..7c364f7de85c --- /dev/null +++ b/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml @@ -0,0 +1,248 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/fsl,lynx-10g.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP Lynx 10G SerDes + +maintainers: + - Sean Anderson + +description: | + These Lynx "SerDes" devices are found in NXP's QorIQ line of processors. The + SerDes provides up to eight lanes. Each lane may be configured individually, + or may be combined with adjacent lanes for a multi-lane protocol. The SerDes + supports a variety of protocols, including up to 10G Ethernet, PCIe, SATA, and + others. The specific protocols supported for each lane depend on the + particular SoC. + +properties: + compatible: + items: + - enum: + - fsl,ls1046a-serdes + - fsl,ls1088a-serdes + - const: fsl,lynx-10g + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + "#clock-cells": + const: 1 + description: | + The cell contains an ID as described in dt-bindings/clock/fsl,lynx-10g.h. + Note that when assigning a rate to a PLL, the PLL's rate is divided by + 1000 to avoid overflow. A rate of 5000000 corresponds to 5GHz. + + clocks: + maxItems: 2 + description: | + Clock for each PLL reference clock input. + + clock-names: + minItems: 2 + maxItems: 2 + items: + enum: + - ref0 + - ref1 + + fsl,unused-lanes-reserved: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Unused lanes are reserved for firmware use, and should not be disabled. + Normally, groups containing unused lanes may be reconfigured or disabled + to save power. However, when this property is present, unused lanes will + not be touched until they are used by another driver. This allows + migrating from firmware control of lanes to driver control. + + Lanes not present in any group will never be modified, regardless of the + presence of this property. + + reg: + maxItems: 1 + +patternProperties: + "^phy@": + type: object + + description: | + A contiguous group of lanes which will be configured together. Each group + corresponds to one phy device. Lanes not described by any group will be + left as-is. + + properties: + "#phy-cells": + const: 0 + + reg: + minItems: 1 + maxItems: 8 + description: + The lanes in the group. These must be listed in order. The first lane + will have the FIRST_LANE bit set in GCR0. The order of lanes also + determines the reset order (TRSTDIR). + + patternProperties: + "^(q?sgmii|xfi)": + type: object + + description: | + A protocol controller which may control the group of lanes. Each + controller is selected through the PCCRs. In addition to protocols + desired for use by the OS, protocols which may have been configured + by the bootloader must also be described. This ensures that only one + protocol controller is attached to a group of lanes at once. + + properties: + fsl,pccr: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + The index of the PCCR which configures this protocol controller. + This is the same as the register name suffix. For example, PCCR8 + would use a value of 8 for an offset of 0x220 (0x200 + 4 * 8). + + fsl,index: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + The index of the protocol controller. This corresponds to the + suffix in the documentation. For example, PEXa would be 0, PEXb + 1, etc. Generally, higher fields occupy lower bits. + + fsl,cfg: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + description: | + The configuration value to program into the protocol controller + field. + + fsl,type: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 8 # PHY_TYPE_SGMII + - 9 # PHY_TYPE_QSGMII + - 13 # PHY_TYPE_2500BASEX + - 14 # PHY_TYPE_10GBASER + description: | + The category of protocols supported by this controller. See + "dt-bindings/phy/phy.h" for the relevant definitions. Individual + protocols are selected by the phy consumer. The availability of + 1000BASE-KX and 10GBASE-KR depends on the SoC. + + - PHY_TYPE_SGMII: 1000BASE-X, SGMII, and 1000BASE-KX + - PHY_TYPE_2500BASEX: 2500BASE-X, 1000BASE-X, SGMII, and + 1000BASE-KX + - PHY_TYPE_QSGMII: QSGMII + - PHY_TYPE_10GBASER: 10GBASE-R and 10GBASE-KR + + required: + - fsl,pccr + - fsl,index + - fsl,cfg + - fsl,type + + additionalProperties: false + + required: + - "#phy-cells" + - reg + + additionalProperties: false + +required: + - "#address-cells" + - "#clock-cells" + - "#size-cells" + - compatible + - clocks + - clock-names + - reg + +additionalProperties: false + +examples: + - | + #include + + serdes1: serdes@1ea0000 { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + compatible = "fsl,ls1046a-serdes", "fsl,lynx-10g"; + reg = <0x1ea0000 0x2000>; + clocks = <&clk_100mhz>, <&clk_156mhz>; + clock-names = "ref0", "ref1"; + + serdes1_0: phy@0 { + #phy-cells = <0>; + reg = <0>; + + /* SGMII.6 */ + sgmii-0 { + fsl,pccr = <0x8>; + fsl,index = <0>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + }; + + serdes1_1: phy@1 { + #phy-cells = <0>; + reg = <1>; + + /* SGMII.5 */ + sgmii-1 { + fsl,pccr = <0x8>; + fsl,index = <1>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + }; + + serdes1_2: phy@2 { + #phy-cells = <0>; + reg = <2>; + + /* SGMII.10 */ + sgmii-2 { + fsl,pccr = <0x8>; + fsl,index = <2>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + + /* XFI.10 */ + xfi-0 { + fsl,pccr = <0xb>; + fsl,index = <0>; + fsl,cfg = <0x2>; + fsl,type = ; + }; + }; + + serdes1_3: phy@3 { + #phy-cells = <0>; + reg = <3>; + + /* SGMII.9 */ + sgmii-3 { + fsl,pccr = <0x8>; + fsl,index = <3>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + + /* XFI.9 */ + xfi-1 { + fsl,pccr = <0xb>; + fsl,index = <1>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + }; + }; +... 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Ip=[20.160.56.80]; Helo=[inpost-eu.tmcas.trendmicro.com] X-MS-Exchange-CrossTenant-AuthSource: AM6EUR05FT004.eop-eur05.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR03MB8347 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This is a generic binding for simple MMIO GPIO controllers. Although we have a single driver for these controllers, they were previously spread over several files. Consolidate them. The register descriptions are adapted from the comments in the source. There is no set order for the registers, and some registers may be omitted. Because of this, reg-names is mandatory, and no order is specified. Rename brcm,bcm6345-gpio to brcm,bcm63xx-gpio to reflect that bcm6345 has moved. Signed-off-by: Sean Anderson Reviewed-by: Linus Walleij --- Linus or Bartosz, feel free to pick this up as the rest of this series may not be merged any time soon. Changes in v13: - Fix references to brcm,bcm63xx-gpio.yaml (neé brcm,bcm6345-gpio) Changes in v12: - Put compatible first - Keep gpio-controller to one line - Add little-endian property - Alphabetize compatibles - Remove some comments - Remove some examples with insufficient novelty Changes in v11: - Keep empty (or almost-empty) properties on a single line - Don't use | unnecessarily - Use gpio as the node name for examples - Rename brcm,bcm6345-gpio.yaml to brcm,bcm63xx-gpio.yaml Changes in v10: - New ...m6345-gpio.yaml => brcm,bcm63xx-gpio.yaml} | 16 +-- .../devicetree/bindings/gpio/gpio-mmio.yaml | 117 ++++++++++++++++++ .../bindings/gpio/ni,169445-nand-gpio.txt | 38 ------ .../devicetree/bindings/gpio/wd,mbl-gpio.txt | 38 ------ .../mfd/brcm,bcm6318-gpio-sysctl.yaml | 4 +- .../mfd/brcm,bcm63268-gpio-sysctl.yaml | 4 +- .../mfd/brcm,bcm6328-gpio-sysctl.yaml | 4 +- .../mfd/brcm,bcm6358-gpio-sysctl.yaml | 4 +- .../mfd/brcm,bcm6362-gpio-sysctl.yaml | 4 +- .../mfd/brcm,bcm6368-gpio-sysctl.yaml | 4 +- 10 files changed, 130 insertions(+), 103 deletions(-) rename Documentation/devicetree/bindings/gpio/{brcm,bcm6345-gpio.yaml => brcm,bcm63xx-gpio.yaml} (78%) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-mmio.yaml delete mode 100644 Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt delete mode 100644 Documentation/devicetree/bindings/gpio/wd,mbl-gpio.txt diff --git a/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml b/Documentation/devicetree/bindings/gpio/brcm,bcm63xx-gpio.yaml similarity index 78% rename from Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml rename to Documentation/devicetree/bindings/gpio/brcm,bcm63xx-gpio.yaml index 4d69f79df859..e11f4af49c52 100644 --- a/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/brcm,bcm63xx-gpio.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/gpio/brcm,bcm6345-gpio.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Broadcom BCM6345 GPIO controller +title: Broadcom BCM63xx GPIO controller maintainers: - Álvaro Fernández Rojas @@ -18,8 +18,6 @@ description: |+ BCM6338 have 8-bit data and dirout registers, where GPIO state can be read and/or written, and the direction changed from input to output. - BCM6345 have 16-bit data and dirout registers, where GPIO state can be read - and/or written, and the direction changed from input to output. BCM6318, BCM6328, BCM6358, BCM6362, BCM6368 and BCM63268 have 32-bit data and dirout registers, where GPIO state can be read and/or written, and the direction changed from input to output. @@ -29,7 +27,6 @@ properties: enum: - brcm,bcm6318-gpio - brcm,bcm6328-gpio - - brcm,bcm6345-gpio - brcm,bcm6358-gpio - brcm,bcm6362-gpio - brcm,bcm6368-gpio @@ -63,17 +60,6 @@ required: additionalProperties: false examples: - - | - gpio@fffe0406 { - compatible = "brcm,bcm6345-gpio"; - reg-names = "dirout", "dat"; - reg = <0xfffe0406 2>, <0xfffe040a 2>; - native-endian; - - gpio-controller; - #gpio-cells = <2>; - }; - - | gpio@0 { compatible = "brcm,bcm63268-gpio"; diff --git a/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml b/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml new file mode 100644 index 000000000000..b394e058256e --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml @@ -0,0 +1,117 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic MMIO GPIO + +maintainers: + - Linus Walleij + - Bartosz Golaszewski + +description: + Some simple GPIO controllers may consist of a single data register or a pair + of set/clear-bit registers. Such controllers are common for glue logic in + FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped + NAND-style parallel busses. + +properties: + compatible: + enum: + - brcm,bcm6345-gpio + - ni,169445-nand-gpio + - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller + + big-endian: true + + '#gpio-cells': + const: 2 + + gpio-controller: true + + little-endian: true + + reg: + minItems: 1 + description: + A list of registers in the controller. The width of each register is + determined by its size. All registers must have the same width. The number + of GPIOs is set by the width, with bit 0 corresponding to GPIO 0. + items: + - description: + Register to READ the value of the GPIO lines. If GPIO line is high, + the bit will be set. If the GPIO line is low, the bit will be cleared. + This register may also be used to drive GPIOs if the SET register is + omitted. + - description: + Register to SET the value of the GPIO lines. Setting a bit in this + register will drive the GPIO line high. + - description: + Register to CLEAR the value of the GPIO lines. Setting a bit in this + register will drive the GPIO line low. If this register is omitted, + the SET register will be used to clear the GPIO lines as well, by + actively writing the line with 0. + - description: + Register to set the line as OUTPUT. Setting a bit in this register + will turn that line into an output line. Conversely, clearing a bit + will turn that line into an input. + - description: + Register to set this line as INPUT. Setting a bit in this register + will turn that line into an input line. Conversely, clearing a bit + will turn that line into an output. + + reg-names: + minItems: 1 + maxItems: 5 + items: + enum: + - dat + - set + - clr + - dirout + - dirin + + native-endian: true + + no-output: + $ref: /schemas/types.yaml#/definitions/flag + description: + If this property is present, the controller cannot drive the GPIO lines. + +required: + - compatible + - reg + - reg-names + - '#gpio-cells' + - gpio-controller + +additionalProperties: false + +examples: + - | + gpio@1f300010 { + compatible = "ni,169445-nand-gpio"; + reg = <0x1f300010 0x4>; + reg-names = "dat"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@e0100000 { + compatible = "wd,mbl-gpio"; + reg-names = "dat"; + reg = <0xe0100000 0x1>; + #gpio-cells = <2>; + gpio-controller; + no-output; + }; + + gpio@fffe0406 { + compatible = "brcm,bcm6345-gpio"; + reg-names = "dirout", "dat"; + reg = <0xfffe0406 2>, <0xfffe040a 2>; + native-endian; + gpio-controller; + #gpio-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt b/Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt deleted file mode 100644 index ca2f8c745a27..000000000000 --- a/Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt +++ /dev/null @@ -1,38 +0,0 @@ -Bindings for the National Instruments 169445 GPIO NAND controller - -The 169445 GPIO NAND controller has two memory mapped GPIO registers, one -for input (the ready signal) and one for output (control signals). It is -intended to be used with the GPIO NAND driver. - -Required properties: - - compatible: should be "ni,169445-nand-gpio" - - reg-names: must contain - "dat" - data register - - reg: address + size pairs describing the GPIO register sets; - order must correspond with the order of entries in reg-names - - #gpio-cells: must be set to 2. The first cell is the pin number and - the second cell is used to specify the gpio polarity: - 0 = active high - 1 = active low - - gpio-controller: Marks the device node as a gpio controller. - -Optional properties: - - no-output: disables driving output on the pins - -Examples: - gpio1: nand-gpio-out@1f300010 { - compatible = "ni,169445-nand-gpio"; - reg = <0x1f300010 0x4>; - reg-names = "dat"; - gpio-controller; - #gpio-cells = <2>; - }; - - gpio2: nand-gpio-in@1f300014 { - compatible = "ni,169445-nand-gpio"; - reg = <0x1f300014 0x4>; - reg-names = "dat"; - gpio-controller; - #gpio-cells = <2>; - no-output; - }; diff --git a/Documentation/devicetree/bindings/gpio/wd,mbl-gpio.txt b/Documentation/devicetree/bindings/gpio/wd,mbl-gpio.txt deleted file mode 100644 index 038c3a6a1f4d..000000000000 --- a/Documentation/devicetree/bindings/gpio/wd,mbl-gpio.txt +++ /dev/null @@ -1,38 +0,0 @@ -Bindings for the Western Digital's MyBook Live memory-mapped GPIO controllers. - -The Western Digital MyBook Live has two memory-mapped GPIO controllers. -Both GPIO controller only have a single 8-bit data register, where GPIO -state can be read and/or written. - -Required properties: - - compatible: should be "wd,mbl-gpio" - - reg-names: must contain - "dat" - data register - - reg: address + size pairs describing the GPIO register sets; - order must correspond with the order of entries in reg-names - - #gpio-cells: must be set to 2. The first cell is the pin number and - the second cell is used to specify the gpio polarity: - 0 = active high - 1 = active low - - gpio-controller: Marks the device node as a gpio controller. - -Optional properties: - - no-output: GPIOs are read-only. - -Examples: - gpio0: gpio0@e0000000 { - compatible = "wd,mbl-gpio"; - reg-names = "dat"; - reg = <0xe0000000 0x1>; - #gpio-cells = <2>; - gpio-controller; - }; - - gpio1: gpio1@e0100000 { - compatible = "wd,mbl-gpio"; - reg-names = "dat"; - reg = <0xe0100000 0x1>; - #gpio-cells = <2>; - gpio-controller; - no-output; - }; diff --git a/Documentation/devicetree/bindings/mfd/brcm,bcm6318-gpio-sysctl.yaml b/Documentation/devicetree/bindings/mfd/brcm,bcm6318-gpio-sysctl.yaml index 148f1da47603..9f9a14af875e 100644 --- a/Documentation/devicetree/bindings/mfd/brcm,bcm6318-gpio-sysctl.yaml +++ b/Documentation/devicetree/bindings/mfd/brcm,bcm6318-gpio-sysctl.yaml @@ -35,11 +35,11 @@ patternProperties: "^gpio@[0-9a-f]+$": # Child node type: object - $ref: "../gpio/brcm,bcm6345-gpio.yaml" + $ref: "../gpio/brcm,bcm63xx-gpio.yaml" description: GPIO controller for the SoC GPIOs. This child node definition should follow the bindings specified in - Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml. + Documentation/devicetree/bindings/gpio/brcm,bcm63xx-gpio.yaml. "^pinctrl@[0-9a-f]+$": # Child node diff --git a/Documentation/devicetree/bindings/mfd/brcm,bcm63268-gpio-sysctl.yaml b/Documentation/devicetree/bindings/mfd/brcm,bcm63268-gpio-sysctl.yaml index 7e582243ea76..803277dd2725 100644 --- a/Documentation/devicetree/bindings/mfd/brcm,bcm63268-gpio-sysctl.yaml +++ b/Documentation/devicetree/bindings/mfd/brcm,bcm63268-gpio-sysctl.yaml @@ -35,11 +35,11 @@ patternProperties: "^gpio@[0-9a-f]+$": # Child node type: object - $ref: "../gpio/brcm,bcm6345-gpio.yaml" + $ref: "../gpio/brcm,bcm63xx-gpio.yaml" description: GPIO controller for the SoC GPIOs. This child node definition should follow the bindings specified in - Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml. + Documentation/devicetree/bindings/gpio/brcm,bcm63xx-gpio.yaml. "^pinctrl@[0-9a-f]+$": # Child node diff --git a/Documentation/devicetree/bindings/mfd/brcm,bcm6328-gpio-sysctl.yaml b/Documentation/devicetree/bindings/mfd/brcm,bcm6328-gpio-sysctl.yaml index 2230848e11c3..b9a6856ce970 100644 --- a/Documentation/devicetree/bindings/mfd/brcm,bcm6328-gpio-sysctl.yaml +++ b/Documentation/devicetree/bindings/mfd/brcm,bcm6328-gpio-sysctl.yaml @@ -35,11 +35,11 @@ patternProperties: "^gpio@[0-9a-f]+$": # Child node type: object - $ref: "../gpio/brcm,bcm6345-gpio.yaml" + $ref: "../gpio/brcm,bcm63xx-gpio.yaml" description: GPIO controller for the SoC GPIOs. This child node definition should follow the bindings specified in - Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml. + Documentation/devicetree/bindings/gpio/brcm,bcm63xx-gpio.yaml. "^pinctrl@[0-9a-f]+$": # Child node diff --git a/Documentation/devicetree/bindings/mfd/brcm,bcm6358-gpio-sysctl.yaml b/Documentation/devicetree/bindings/mfd/brcm,bcm6358-gpio-sysctl.yaml index c06693b6f7aa..4651fe4dde07 100644 --- a/Documentation/devicetree/bindings/mfd/brcm,bcm6358-gpio-sysctl.yaml +++ b/Documentation/devicetree/bindings/mfd/brcm,bcm6358-gpio-sysctl.yaml @@ -35,11 +35,11 @@ patternProperties: "^gpio@[0-9a-f]+$": # Child node type: object - $ref: "../gpio/brcm,bcm6345-gpio.yaml" + $ref: "../gpio/brcm,bcm63xx-gpio.yaml" description: GPIO controller for the SoC GPIOs. This child node definition should follow the bindings specified in - Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml. + Documentation/devicetree/bindings/gpio/brcm,bcm63xx-gpio.yaml. "^pinctrl@[0-9a-f]+$": # Child node diff --git a/Documentation/devicetree/bindings/mfd/brcm,bcm6362-gpio-sysctl.yaml b/Documentation/devicetree/bindings/mfd/brcm,bcm6362-gpio-sysctl.yaml index c560bede0e37..0330b621fd38 100644 --- a/Documentation/devicetree/bindings/mfd/brcm,bcm6362-gpio-sysctl.yaml +++ b/Documentation/devicetree/bindings/mfd/brcm,bcm6362-gpio-sysctl.yaml @@ -35,11 +35,11 @@ patternProperties: "^gpio@[0-9a-f]+$": # Child node type: object - $ref: "../gpio/brcm,bcm6345-gpio.yaml" + $ref: "../gpio/brcm,bcm63xx-gpio.yaml" description: GPIO controller for the SoC GPIOs. This child node definition should follow the bindings specified in - Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml. + Documentation/devicetree/bindings/gpio/brcm,bcm63xx-gpio.yaml. "^pinctrl@[0-9a-f]+$": # Child node diff --git a/Documentation/devicetree/bindings/mfd/brcm,bcm6368-gpio-sysctl.yaml b/Documentation/devicetree/bindings/mfd/brcm,bcm6368-gpio-sysctl.yaml index c534f5f2404e..82d3e4415bda 100644 --- a/Documentation/devicetree/bindings/mfd/brcm,bcm6368-gpio-sysctl.yaml +++ b/Documentation/devicetree/bindings/mfd/brcm,bcm6368-gpio-sysctl.yaml @@ -35,11 +35,11 @@ patternProperties: "^gpio@[0-9a-f]+$": # Child node type: object - $ref: "../gpio/brcm,bcm6345-gpio.yaml" + $ref: "../gpio/brcm,bcm63xx-gpio.yaml" description: GPIO controller for the SoC GPIOs. This child node definition should follow the bindings specified in - Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml. + Documentation/devicetree/bindings/gpio/brcm,bcm63xx-gpio.yaml. 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Ip=[20.160.56.80]; Helo=[inpost-eu.tmcas.trendmicro.com] X-MS-Exchange-CrossTenant-AuthSource: AM6EUR05FT047.eop-eur05.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR03MB9648 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org NXP has a "QIXIS" FPGA on several of their reference design boards. On the LS1088ARDB there are several registers which control GPIOs. These can be modeled with the MMIO GPIO driver. Signed-off-by: Sean Anderson Reviewed-by: Rob Herring --- (no changes since v10) Changes in v10: - New .../devicetree/bindings/gpio/gpio-mmio.yaml | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml b/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml index b394e058256e..5abf3dabcf39 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml @@ -18,10 +18,16 @@ description: properties: compatible: - enum: - - brcm,bcm6345-gpio - - ni,169445-nand-gpio - - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller + oneOf: + - enum: + - brcm,bcm6345-gpio + - ni,169445-nand-gpio + - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller + - items: + - enum: + - fsl,fpga-qixis-los-stat + - fsl,fpga-qixis-brdcfg9 + - const: ni,169445-nand-gpio big-endian: true From patchwork Tue Apr 11 18:43:03 2023 Content-Type: text/plain; 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Ip=[20.160.56.80]; Helo=[inpost-eu.tmcas.trendmicro.com] X-MS-Exchange-CrossTenant-AuthSource: VI1EUR05FT009.eop-eur05.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR03MB9984 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds support for the PLLs found in Lynx 10G "SerDes" devices found on various NXP QorIQ SoCs. There are two PLLs in each SerDes. This driver has been split from the main PHY driver to allow for better review, even though these PLLs are not present anywhere else besides the SerDes. An auxiliary device is not used as it offers no benefits over a function call (and there is no need to have a separate device). The PLLs are modeled as clocks proper to let us take advantage of the existing clock infrastructure. I have not given the same treatment to the per-lane clocks because they need to be programmed in-concert with the rest of the lane settings. One tricky thing is that the VCO (PLL) rate exceeds 2^32 (maxing out at around 5GHz). This will be a problem on 32-bit platforms, since clock rates are stored as unsigned longs. To work around this, the pll clock rate is generally treated in units of kHz. The PLLs are configured rather interestingly. Instead of the usual direct programming of the appropriate divisors, the input and output clock rates are selected directly. Generally, the only restriction is that the input and output must be integer multiples of each other. This suggests some kind of internal look-up table. The datasheets generally list out the supported combinations explicitly, and not all input/output combinations are documented. I'm not sure if this is due to lack of support, or due to an oversight. If this becomes an issue, then some combinations can be blacklisted (or whitelisted). This may also be necessary for other SoCs which have more stringent clock requirements. Signed-off-by: Sean Anderson --- (no changes since v10) Changes in v10: - Remove unnecessary inclusion of clk.h - Don't gate clocks in compatibility mode Changes in v9: - Convert some u32s to unsigned long to match arguments - Switch from round_rate to determine_rate - Drop explicit reference to reference clock - Use .parent_names when requesting parents - Use devm_clk_hw_get_clk to pass clocks back to serdes - Fix indentation - Split off from following patch to allow for better review MAINTAINERS | 7 + drivers/clk/Makefile | 1 + drivers/clk/clk-fsl-lynx-10g.c | 510 +++++++++++++++++++++++++++++++++ drivers/phy/freescale/Kconfig | 6 + include/linux/phy/lynx-10g.h | 16 ++ 5 files changed, 540 insertions(+) create mode 100644 drivers/clk/clk-fsl-lynx-10g.c create mode 100644 include/linux/phy/lynx-10g.h diff --git a/MAINTAINERS b/MAINTAINERS index fce67b74e4a2..8da893681de6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12195,6 +12195,13 @@ S: Maintained W: http://linux-test-project.github.io/ T: git https://github.com/linux-test-project/ltp.git +LYNX 10G SERDES DRIVER +M: Sean Anderson +S: Maintained +F: drivers/clk/clk-fsl-lynx-10g.c +F: include/dt-bindings/clock/fsl,lynx-10g.h +F: include/linux/phy/lynx-10g.h + LYNX 28G SERDES PHY DRIVER M: Ioana Ciornei L: netdev@vger.kernel.org diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index e3ca0d058a25..eebed69f6c58 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_ARCH_SPARX5) += clk-sparx5.o obj-$(CONFIG_COMMON_CLK_EN7523) += clk-en7523.o obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o obj-$(CONFIG_COMMON_CLK_FSL_FLEXSPI) += clk-fsl-flexspi.o +obj-$(CONFIG_PHY_FSL_LYNX_10G) += clk-fsl-lynx-10g.o obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o diff --git a/drivers/clk/clk-fsl-lynx-10g.c b/drivers/clk/clk-fsl-lynx-10g.c new file mode 100644 index 000000000000..78357303b578 --- /dev/null +++ b/drivers/clk/clk-fsl-lynx-10g.c @@ -0,0 +1,510 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Sean Anderson + * + * This file contains the implementation for the PLLs found on Lynx 10G phys. + * + * XXX: The VCO rate of the PLLs can exceed ~4GHz, which is the maximum rate + * expressable in an unsigned long. To work around this, rates are specified in + * kHz. This is as if there was a division by 1000 in the PLL. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PLL_STRIDE 0x20 +#define PLLa(a, off) ((a) * PLL_STRIDE + (off)) +#define PLLaRSTCTL(a) PLLa(a, 0x00) +#define PLLaCR0(a) PLLa(a, 0x04) + +#define PLLaRSTCTL_RSTREQ BIT(31) +#define PLLaRSTCTL_RST_DONE BIT(30) +#define PLLaRSTCTL_RST_ERR BIT(29) +#define PLLaRSTCTL_PLLRST_B BIT(7) +#define PLLaRSTCTL_SDRST_B BIT(6) +#define PLLaRSTCTL_SDEN BIT(5) + +#define PLLaRSTCTL_ENABLE_SET (PLLaRSTCTL_RST_DONE | PLLaRSTCTL_PLLRST_B | \ + PLLaRSTCTL_SDRST_B | PLLaRSTCTL_SDEN) +#define PLLaRSTCTL_ENABLE_MASK (PLLaRSTCTL_ENABLE_SET | PLLaRSTCTL_RST_ERR) + +#define PLLaCR0_POFF BIT(31) +#define PLLaCR0_RFCLK_SEL GENMASK(30, 28) +#define PLLaCR0_PLL_LCK BIT(23) +#define PLLaCR0_FRATE_SEL GENMASK(19, 16) +#define PLLaCR0_DLYDIV_SEL GENMASK(1, 0) + +#define PLLaCR0_DLYDIV_SEL_16 0b01 + +/** + * struct lynx_clk - Driver data for the PLLs + * @pll: The PLL clock + * @ex_dly: The "PLLa_ex_dly_clk" clock + * @dev: The serdes device + * @regmap: Our registers + * @idx: Which PLL this clock is for + */ +struct lynx_clk { + struct clk_hw pll, ex_dly; + struct device *dev; + struct regmap *regmap; + unsigned int idx; +}; + +static u32 lynx_read(struct lynx_clk *clk, u32 reg) +{ + unsigned int ret = 0; + + WARN_ON_ONCE(regmap_read(clk->regmap, reg, &ret)); + return ret; +} + +static void lynx_write(struct lynx_clk *clk, u32 val, u32 reg) +{ + WARN_ON_ONCE(regmap_write(clk->regmap, reg, val)); +} + +static struct lynx_clk *lynx_pll_to_clk(struct clk_hw *hw) +{ + return container_of(hw, struct lynx_clk, pll); +} + +static struct lynx_clk *lynx_ex_dly_to_clk(struct clk_hw *hw) +{ + return container_of(hw, struct lynx_clk, ex_dly); +} + +static void lynx_pll_stop(struct lynx_clk *clk) +{ + u32 rstctl; + + rstctl = lynx_read(clk, PLLaRSTCTL(clk->idx)); + rstctl &= ~PLLaRSTCTL_SDRST_B; + lynx_write(clk, rstctl, PLLaRSTCTL(clk->idx)); + + ndelay(50); + + rstctl = lynx_read(clk, PLLaRSTCTL(clk->idx)); + rstctl &= ~(PLLaRSTCTL_SDEN | PLLaRSTCTL_PLLRST_B); + lynx_write(clk, rstctl, PLLaRSTCTL(clk->idx)); + + ndelay(100); +} + +static void lynx_pll_disable(struct clk_hw *hw) +{ + struct lynx_clk *clk = lynx_pll_to_clk(hw); + u32 cr0; + + dev_dbg(clk->dev, "disable pll%d\n", clk->idx); + + lynx_pll_stop(clk); + + cr0 = lynx_read(clk, PLLaCR0(clk->idx)); + cr0 |= PLLaCR0_POFF; + lynx_write(clk, cr0, PLLaCR0(clk->idx)); +} + +static int lynx_pll_reset(struct lynx_clk *clk) +{ + int ret; + u32 rstctl = lynx_read(clk, PLLaRSTCTL(clk->idx)); + + rstctl |= PLLaRSTCTL_RSTREQ; + lynx_write(clk, rstctl, PLLaRSTCTL(clk->idx)); + ret = read_poll_timeout(lynx_read, rstctl, + rstctl & (PLLaRSTCTL_RST_DONE | PLLaRSTCTL_RST_ERR), + 100, 5000, true, clk, PLLaRSTCTL(clk->idx)); + if (rstctl & PLLaRSTCTL_RST_ERR) + ret = -EIO; + if (ret) { + dev_err(clk->dev, "pll%d reset failed\n", clk->idx); + return ret; + } + + rstctl |= PLLaRSTCTL_SDEN | PLLaRSTCTL_PLLRST_B | PLLaRSTCTL_SDRST_B; + lynx_write(clk, rstctl, PLLaRSTCTL(clk->idx)); + return 0; +} + +static int lynx_pll_prepare(struct clk_hw *hw) +{ + struct lynx_clk *clk = lynx_pll_to_clk(hw); + u32 rstctl = lynx_read(clk, PLLaRSTCTL(clk->idx)); + u32 cr0 = lynx_read(clk, PLLaCR0(clk->idx)); + + /* + * "Enabling" the PLL involves resetting it (and all attached lanes). + * Avoid doing this if we are already enabled. + */ + if (!(cr0 & PLLaCR0_POFF) && + (rstctl & PLLaRSTCTL_ENABLE_MASK) == PLLaRSTCTL_ENABLE_SET) { + dev_dbg(clk->dev, "pll%d already prepared\n", clk->idx); + return 0; + } + + dev_dbg(clk->dev, "prepare pll%d\n", clk->idx); + + cr0 &= ~PLLaCR0_POFF; + lynx_write(clk, cr0, PLLaCR0(clk->idx)); + + return lynx_pll_reset(clk); +} + +static int lynx_pll_is_enabled(struct clk_hw *hw) +{ + struct lynx_clk *clk = lynx_pll_to_clk(hw); + u32 cr0 = lynx_read(clk, PLLaCR0(clk->idx)); + bool enabled = !(cr0 & PLLaCR0_POFF); + + dev_dbg(clk->dev, "pll%d %s enabled\n", clk->idx, + enabled ? "is" : "is not"); + + return enabled; +} + +static const unsigned long rfclk_sel_map[8] = { + [0b000] = 100000000, + [0b001] = 125000000, + [0b010] = 156250000, + [0b011] = 150000000, +}; + +/** + * lynx_rfclk_to_sel() - Convert a reference clock rate to a selector + * @rate: The reference clock rate + * + * To allow for some variation in the reference clock rate, up to 100ppm of + * error is allowed. + * + * Return: An appropriate selector for @rate, or -%EINVAL. + */ +static int lynx_rfclk_to_sel(unsigned long rate) +{ + int ret; + + for (ret = 0; ret < ARRAY_SIZE(rfclk_sel_map); ret++) { + unsigned long rfclk_rate = rfclk_sel_map[ret]; + /* Allow an error of 100ppm */ + unsigned long error = rfclk_rate / 10000; + + if (abs(rate - rfclk_rate) < error) + return ret; + } + + return -EINVAL; +} + +static const unsigned long frate_sel_map[16] = { + [0b0000] = 5000000, + [0b0101] = 3750000, + [0b0110] = 5156250, + [0b0111] = 4000000, + [0b1001] = 3125000, + [0b1010] = 3000000, +}; + +/** + * lynx_frate_to_sel() - Convert a VCO clock rate to a selector + * @rate_khz: The VCO frequency, in kHz + * + * Return: An appropriate selector for @rate_khz, or -%EINVAL. + */ +static int lynx_frate_to_sel(unsigned long rate_khz) +{ + int ret; + + for (ret = 0; ret < ARRAY_SIZE(frate_sel_map); ret++) + if (frate_sel_map[ret] == rate_khz) + return ret; + + return -EINVAL; +} + +static u32 lynx_pll_ratio(u32 frate_sel, u32 rfclk_sel) +{ + u64 frate; + u32 rfclk, error, ratio; + + frate = frate_sel_map[frate_sel] * (u64)HZ_PER_KHZ; + rfclk = rfclk_sel_map[rfclk_sel]; + + if (!frate || !rfclk) + return 0; + + ratio = div_u64_rem(frate, rfclk, &error); + if (!error) + return ratio; + return 0; +} + +static unsigned long lynx_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct lynx_clk *clk = lynx_pll_to_clk(hw); + u32 cr0 = lynx_read(clk, PLLaCR0(clk->idx)); + u32 frate_sel = FIELD_GET(PLLaCR0_FRATE_SEL, cr0); + u32 rfclk_sel = FIELD_GET(PLLaCR0_RFCLK_SEL, cr0); + u32 ratio = lynx_pll_ratio(frate_sel, rfclk_sel); + unsigned long ret; + + /* Ensure that the parent matches our rfclk selector */ + if (rfclk_sel == lynx_rfclk_to_sel(parent_rate)) + ret = mult_frac(parent_rate, ratio, HZ_PER_KHZ); + else + ret = 0; + + dev_dbg(clk->dev, "recalc pll%d new=%llu parent=%lu\n", clk->idx, + (u64)ret * HZ_PER_KHZ, parent_rate); + return ret; +} + +static int lynx_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + int frate_sel, rfclk_sel; + struct lynx_clk *clk = lynx_pll_to_clk(hw); + u32 ratio; + + dev_dbg(clk->dev, "round pll%d new=%llu parent=%lu\n", clk->idx, + (u64)req->rate * HZ_PER_KHZ, req->best_parent_rate); + + frate_sel = lynx_frate_to_sel(req->rate); + if (frate_sel < 0) + return frate_sel; + + /* Try the current parent rate */ + rfclk_sel = lynx_rfclk_to_sel(req->best_parent_rate); + if (rfclk_sel >= 0) { + ratio = lynx_pll_ratio(frate_sel, rfclk_sel); + if (ratio) { + req->rate = mult_frac(req->best_parent_rate, ratio, + HZ_PER_KHZ); + return 0; + } + } + + /* Try all possible parent rates */ + for (rfclk_sel = 0; + rfclk_sel < ARRAY_SIZE(rfclk_sel_map); + rfclk_sel++) { + unsigned long new_parent_rate; + + ratio = lynx_pll_ratio(frate_sel, rfclk_sel); + if (!ratio) + continue; + + /* Ensure the reference clock can produce this rate */ + new_parent_rate = rfclk_sel_map[rfclk_sel]; + new_parent_rate = clk_hw_round_rate(req->best_parent_hw, + new_parent_rate); + if (rfclk_sel != lynx_rfclk_to_sel(new_parent_rate)) + continue; + + req->rate = mult_frac(new_parent_rate, ratio, HZ_PER_KHZ); + req->best_parent_rate = new_parent_rate; + return 0; + } + + return -EINVAL; +} + +static int lynx_pll_set_rate(struct clk_hw *hw, unsigned long rate_khz, + unsigned long parent_rate) +{ + int frate_sel, rfclk_sel; + struct lynx_clk *clk = lynx_pll_to_clk(hw); + u32 ratio, cr0 = lynx_read(clk, PLLaCR0(clk->idx)); + + dev_dbg(clk->dev, "set rate pll%d new=%llu parent=%lu\n", clk->idx, + (u64)rate_khz * HZ_PER_KHZ, parent_rate); + + frate_sel = lynx_frate_to_sel(rate_khz); + if (frate_sel < 0) + return frate_sel; + + rfclk_sel = lynx_rfclk_to_sel(parent_rate); + if (rfclk_sel < 0) + return rfclk_sel; + + ratio = lynx_pll_ratio(frate_sel, rfclk_sel); + if (!ratio) + return -EINVAL; + + lynx_pll_stop(clk); + cr0 &= ~(PLLaCR0_RFCLK_SEL | PLLaCR0_FRATE_SEL); + cr0 |= FIELD_PREP(PLLaCR0_RFCLK_SEL, rfclk_sel); + cr0 |= FIELD_PREP(PLLaCR0_FRATE_SEL, frate_sel); + lynx_write(clk, cr0, PLLaCR0(clk->idx)); + /* Don't bother resetting if it's off */ + if (cr0 & PLLaCR0_POFF) + return 0; + return lynx_pll_reset(clk); +} + +static const struct clk_ops lynx_pll_clk_ops = { + .prepare = lynx_pll_prepare, + .disable = lynx_pll_disable, + .is_enabled = lynx_pll_is_enabled, + .recalc_rate = lynx_pll_recalc_rate, + .determine_rate = lynx_pll_determine_rate, + .set_rate = lynx_pll_set_rate, +}; + +static void lynx_ex_dly_disable(struct clk_hw *hw) +{ + struct lynx_clk *clk = lynx_ex_dly_to_clk(hw); + u32 cr0 = lynx_read(clk, PLLaCR0(clk->idx)); + + cr0 &= ~PLLaCR0_DLYDIV_SEL; + lynx_write(clk, PLLaCR0(clk->idx), cr0); +} + +static int lynx_ex_dly_enable(struct clk_hw *hw) +{ + struct lynx_clk *clk = lynx_ex_dly_to_clk(hw); + u32 cr0 = lynx_read(clk, PLLaCR0(clk->idx)); + + cr0 &= ~PLLaCR0_DLYDIV_SEL; + cr0 |= FIELD_PREP(PLLaCR0_DLYDIV_SEL, PLLaCR0_DLYDIV_SEL_16); + lynx_write(clk, PLLaCR0(clk->idx), cr0); + return 0; +} + +static int lynx_ex_dly_is_enabled(struct clk_hw *hw) +{ + struct lynx_clk *clk = lynx_ex_dly_to_clk(hw); + + return lynx_read(clk, PLLaCR0(clk->idx)) & PLLaCR0_DLYDIV_SEL; +} + +static unsigned long lynx_ex_dly_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return parent_rate / 16; +} + +static const struct clk_ops lynx_ex_dly_clk_ops = { + .enable = lynx_ex_dly_enable, + .disable = lynx_ex_dly_disable, + .is_enabled = lynx_ex_dly_is_enabled, + .recalc_rate = lynx_ex_dly_recalc_rate, +}; + +static int lynx_clk_init(struct clk_hw_onecell_data *hw_data, + struct device *dev, struct regmap *regmap, + unsigned int index, bool compat) +{ + const struct clk_hw *ex_dly_parents; + struct clk_parent_data pll_parents[1] = { }; + struct clk_init_data pll_init = { + .ops = &lynx_pll_clk_ops, + .parent_data = pll_parents, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT | + CLK_OPS_PARENT_ENABLE, + }; + struct clk_init_data ex_dly_init = { + .ops = &lynx_ex_dly_clk_ops, + .parent_hws = &ex_dly_parents, + .num_parents = 1, + }; + struct lynx_clk *clk; + int ret; + + clk = devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL); + if (!clk) + return -ENOMEM; + + clk->dev = dev; + clk->regmap = regmap; + clk->idx = index; + + pll_parents[0].fw_name = kasprintf(GFP_KERNEL, "ref%d", index); + pll_init.name = kasprintf(GFP_KERNEL, "%s.pll%d_khz", dev_name(dev), + index); + ex_dly_init.name = kasprintf(GFP_KERNEL, "%s.pll%d_ex_dly_khz", + dev_name(dev), index); + if (!pll_parents[0].fw_name || !pll_init.name || !ex_dly_init.name) { + ret = -ENOMEM; + goto out; + } + + if (compat) + pll_init.flags |= CLK_IGNORE_UNUSED; + clk->pll.init = &pll_init; + ret = devm_clk_hw_register(dev, &clk->pll); + if (ret) { + dev_err_probe(dev, ret, "could not register %s\n", + pll_init.name); + goto out; + } + + ex_dly_parents = &clk->pll; + clk->ex_dly.init = &ex_dly_init; + ret = devm_clk_hw_register(dev, &clk->ex_dly); + if (ret) + dev_err_probe(dev, ret, "could not register %s\n", + ex_dly_init.name); + + hw_data->hws[LYNX10G_PLLa(index)] = &clk->pll; + hw_data->hws[LYNX10G_PLLa_EX_DLY(index)] = &clk->ex_dly; + +out: + kfree(pll_parents[0].fw_name); + kfree(pll_init.name); + kfree(ex_dly_init.name); + return ret; +} + +#define NUM_PLLS 2 +#define NUM_CLKS (NUM_PLLS * LYNX10G_CLKS_PER_PLL) + +int lynx_clks_init(struct device *dev, struct regmap *regmap, + struct clk *plls[2], struct clk *ex_dlys[2], bool compat) +{ + int ret, i; + struct clk_hw_onecell_data *hw_data; + + hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, NUM_CLKS), + GFP_KERNEL); + if (!hw_data) + return -ENOMEM; + hw_data->num = NUM_CLKS; + + for (i = 0; i < NUM_PLLS; i++) { + ret = lynx_clk_init(hw_data, dev, regmap, i, compat); + if (ret) + return ret; + + plls[i] = devm_clk_hw_get_clk(dev, + hw_data->hws[LYNX10G_PLLa(i)], + NULL); + if (IS_ERR(plls[i])) + return PTR_ERR(plls[i]); + + ex_dlys[i] = devm_clk_hw_get_clk(dev, + hw_data->hws[LYNX10G_PLLa_EX_DLY(i)], + NULL); + if (IS_ERR(ex_dlys[i])) + return PTR_ERR(plls[i]); + } + + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, hw_data); + if (ret) + dev_err_probe(dev, ret, "could not register clock provider\n"); + + return ret; +} +EXPORT_SYMBOL_GPL(lynx_clks_init); + +MODULE_AUTHOR("Sean Anderson "); +MODULE_DESCRIPTION("Lynx 10G PLL driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig index 853958fb2c06..5d461232276f 100644 --- a/drivers/phy/freescale/Kconfig +++ b/drivers/phy/freescale/Kconfig @@ -47,3 +47,9 @@ config PHY_FSL_LYNX_28G found on NXP's Layerscape platforms such as LX2160A. Used to change the protocol running on SerDes lanes at runtime. Only useful for a restricted set of Ethernet protocols. + +config PHY_FSL_LYNX_10G + tristate + depends on COMMON_CLK + depends on ARCH_LAYERSCAPE || PPC || COMPILE_TEST + select REGMAP_MMIO diff --git a/include/linux/phy/lynx-10g.h b/include/linux/phy/lynx-10g.h new file mode 100644 index 000000000000..b7b80b3ee988 --- /dev/null +++ b/include/linux/phy/lynx-10g.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022 Sean Anderson + */ + +#ifndef LYNX_10G +#define LYNX_10G + +struct clk; +struct device; +struct regmap; + +int lynx_clks_init(struct device *dev, struct regmap *regmap, + struct clk *plls[2], struct clk *ex_dlys[2], bool compat); + +#endif /* LYNX 10G */ From patchwork Tue Apr 11 18:43:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 672436 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDF7AC77B72 for ; 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Ip=[20.160.56.87]; Helo=[inpost-eu.tmcas.trendmicro.com] X-MS-Exchange-CrossTenant-AuthSource: VI1EUR05FT047.eop-eur05.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV2PR03MB8584 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds nodes for the SerDes devices. They are disabled by default to prevent any breakage on existing boards. Signed-off-by: Sean Anderson --- (no changes since v10) Changes in v10: - Move serdes bindings to SoC dtsi - Add support for all (ethernet) serdes modes - Refer to "nodes" instead of "bindings" - Move compatible/reg first Changes in v4: - Convert to new bindings Changes in v3: - Describe modes in device tree Changes in v2: - Use one phy cell for SerDes1, since no lanes can be grouped - Disable SerDes by default to prevent breaking boards inadvertently. .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 111 ++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index a01e3cfec77f..f6361fafaef7 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include / { compatible = "fsl,ls1046a"; @@ -424,6 +425,116 @@ sfp: efuse@1e80000 { clock-names = "sfp"; }; + serdes1: serdes@1ea0000 { + compatible = "fsl,ls1046a-serdes", "fsl,lynx-10g"; + reg = <0x0 0x1ea0000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + status = "disabled"; + + /* + * XXX: Lane A uses pins SD1_RX3_P/N! That is, the lane + * numbers and pin numbers are _reversed_. In addition, + * the PCCR documentation is _inconsistent_ in its + * usage of these terms! + * + * PCCR "Lane 0" refers to... + * ==== ===================== + * 0 Lane A + * 2 Lane A + * 8 Lane A + * 9 Lane A + * B Lane D! + */ + serdes1_A: phy@0 { + #phy-cells = <0>; + reg = <0>; + + /* SGMII.6 */ + sgmii-0 { + fsl,pccr = <0x8>; + fsl,index = <0>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + }; + + serdes1_B: phy@1 { + #phy-cells = <0>; + reg = <1>; + + /* SGMII.5 */ + sgmii-1 { + fsl,pccr = <0x8>; + fsl,index = <1>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + + /* QSGMII.6,5,10,1 */ + qsgmii-1 { + fsl,pccr = <0x9>; + fsl,index = <1>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + + /* TODO: PCIe.1 */ + }; + + serdes1_C: phy@2 { + #phy-cells = <0>; + reg = <2>; + + /* SGMII.10 */ + sgmii-2 { + fsl,pccr = <0x8>; + fsl,index = <2>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + + /* XFI.10 */ + xfi-0 { + fsl,pccr = <0xb>; + fsl,index = <0>; + fsl,cfg = <0x2>; + fsl,type = ; + }; + }; + + serdes1_D: phy@3 { + #phy-cells = <0>; + reg = <3>; + + /* SGMII.9 */ + sgmii-3 { + fsl,pccr = <0x8>; + fsl,index = <3>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + + /* XFI.9 */ + xfi-1 { + fsl,pccr = <0xb>; + fsl,index = <1>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + }; + }; + + serdes2: serdes@1eb0000 { + compatible = "fsl,ls1046a-serdes", "fsl,lynx-10g"; + reg = <0x0 0x1eb0000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + status = "disabled"; + }; + dcfg: dcfg@1ee0000 { compatible = "fsl,ls1046a-dcfg", "syscon"; reg = <0x0 0x1ee0000 0x0 0x1000>; From patchwork Tue Apr 11 18:43:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 672435 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E11EC77B75 for ; Tue, 11 Apr 2023 18:45:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229931AbjDKSpZ (ORCPT ); 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Ip=[20.160.56.84]; Helo=[inpost-eu.tmcas.trendmicro.com] X-MS-Exchange-CrossTenant-AuthSource: VI1EUR05FT018.eop-eur05.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR03MB7409 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds nodes for the SerDes devices. They are disabled by default to prevent any breakage on existing boards. Signed-off-by: Sean Anderson --- (no changes since v10) Changes in v10: - Move serdes bindings to SoC dtsi - Add support for all (ethernet) serdes modes - Refer to "nodes" instead of "bindings" - Move compatible/reg first Changes in v4: - Convert to new bindings Changes in v3: - New .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 126 ++++++++++++++++++ 1 file changed, 126 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index e5fb137ac02b..59b401daad4d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -9,6 +9,7 @@ */ #include #include +#include #include / { @@ -238,6 +239,131 @@ reset: syscon@1e60000 { reg = <0x0 0x1e60000 0x0 0x10000>; }; + serdes1: serdes@1ea0000 { + compatible = "fsl,ls1088a-serdes", "fsl,lynx-10g"; + reg = <0x0 0x1ea0000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + status = "disabled"; + + /* + * XXX: Lane A uses pins SD1_RX3_P/N! That is, the lane + * numbers and pin numbers are _reversed_. + */ + serdes1_A: phy@0 { + #phy-cells = <0>; + reg = <0>; + + /* SG3 */ + sgmii-0 { + fsl,pccr = <0x8>; + fsl,index = <0>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + + /* QSGb */ + qsgmii-0 { + fsl,pccr = <0x9>; + fsl,index = <0>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + }; + + serdes1_B: phy@1 { + #phy-cells = <0>; + reg = <1>; + + /* SG7 */ + sgmii-1 { + fsl,pccr = <0x8>; + fsl,index = <1>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + + /* QSGa */ + qsgmii-1 { + fsl,pccr = <0x9>; + fsl,index = <1>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + + /* TODO: PCIe1 */ + }; + + serdes1_C: phy@2 { + #phy-cells = <0>; + reg = <2>; + + /* SG1 */ + sgmii-2 { + fsl,pccr = <0x8>; + fsl,index = <2>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + + /* + * XFI1 + * Table 23-1 and section 23.5.16.4 disagree; + * this reflects the table. + * + * fsl,cfg is documented as 1, but it is set to + * 2 by the RCW! This is the same as the + * LS1046A. + */ + xfi-0 { + fsl,pccr = <0xb>; + fsl,index = <0>; + fsl,cfg = <0x2>; + fsl,type = ; + }; + }; + + serdes1_D: phy@3 { + #phy-cells = <0>; + reg = <3>; + + /* SG2 */ + sgmii-3 { + fsl,pccr = <0x8>; + fsl,index = <3>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + + /* QSGb */ + qsgmii-0 { + fsl,pccr = <0x9>; + fsl,index = <0>; + fsl,cfg = <0x2>; + fsl,type = ; + }; + + /* XFI2 */ + xfi-1 { + fsl,pccr = <0xb>; + fsl,index = <1>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + }; + + }; + + serdes2: serdes@1eb0000 { + compatible = "fsl,ls1088a-serdes", "fsl,lynx-10g"; + reg = <0x0 0x1eb0000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + status = "disabled"; + }; + isc: syscon@1f70000 { compatible = "fsl,ls1088a-isc", "syscon"; reg = <0x0 0x1f70000 0x0 0x10000>; From patchwork Tue Apr 11 18:43:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 672437 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D357DC77B73 for ; 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Received: from DB9PR03MB8847.eurprd03.prod.outlook.com (2603:10a6:10:3dd::13) by DB4PR03MB9433.eurprd03.prod.outlook.com (2603:10a6:10:3fa::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6277.38; Tue, 11 Apr 2023 18:45:00 +0000 Received: from DB9PR03MB8847.eurprd03.prod.outlook.com ([fe80::2226:eb03:a8c:a7e5]) by DB9PR03MB8847.eurprd03.prod.outlook.com ([fe80::2226:eb03:a8c:a7e5%2]) with mapi id 15.20.6277.035; Tue, 11 Apr 2023 18:45:00 +0000 From: Sean Anderson To: Vinod Koul , Kishon Vijay Abraham I , linux-phy@lists.infradead.org Cc: Camelia Alexandra Groza , Bagas Sanjaya , Ioana Ciornei , linux-arm-kernel@lists.infradead.org, Madalin Bucur , devicetree@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , linuxppc-dev@lists.ozlabs.org, Sean Anderson , Li Yang , Shawn Guo Subject: [PATCH v13 12/15] arm64: dts: ls1088a: Prevent PCSs from probing as phys Date: Tue, 11 Apr 2023 14:43:09 -0400 Message-Id: <20230411184313.3679145-13-sean.anderson@seco.com> X-Mailer: git-send-email 2.35.1.1320.gc452695387.dirty In-Reply-To: <20230411184313.3679145-1-sean.anderson@seco.com> References: <20230411184313.3679145-1-sean.anderson@seco.com> X-ClientProxiedBy: BL1PR13CA0350.namprd13.prod.outlook.com (2603:10b6:208:2c6::25) To DB9PR03MB8847.eurprd03.prod.outlook.com (2603:10a6:10:3dd::13) MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: DB9PR03MB8847:EE_|DB4PR03MB9433:EE_|DB8EUR05FT021:EE_|AM7PR03MB6546:EE_ X-MS-Office365-Filtering-Correlation-Id: 1c22ca68-be6e-4ee1-665f-08db3abce35f X-TrendMicro-CAS-OUT-LOOP-IDENTIFIER: 656f966764b7fb185830381c646b41a1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; 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CTRY:NL; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:inpost-eu.tmcas.trendmicro.com; PTR:inpost-eu.tmcas.trendmicro.com; CAT:NONE; SFS:(13230028)(396003)(39850400004)(136003)(376002)(346002)(5400799015)(451199021)(46966006)(36840700001)(47076005)(86362001)(7596003)(7636003)(478600001)(40480700001)(356005)(6486002)(110136005)(2906002)(54906003)(83380400001)(7416002)(2616005)(186003)(82310400005)(336012)(34070700002)(8676002)(36756003)(8936002)(41300700001)(5660300002)(82740400003)(36860700001)(6512007)(1076003)(26005)(6506007)(316002)(44832011)(70586007)(4326008)(70206006)(12100799027); DIR:OUT; SFP:1501; X-OriginatorOrg: seco.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Apr 2023 18:45:14.5062 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1c22ca68-be6e-4ee1-665f-08db3abce35f X-MS-Exchange-CrossTenant-Id: bebe97c3-6438-442e-ade3-ff17aa50e733 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=bebe97c3-6438-442e-ade3-ff17aa50e733; Ip=[20.160.56.87]; Helo=[inpost-eu.tmcas.trendmicro.com] X-MS-Exchange-CrossTenant-AuthSource: DB8EUR05FT021.eop-eur05.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM7PR03MB6546 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The internal PCSs are not always accessible during boot (such as if the serdes has deselected the appropriate link mode). Give them appropriate compatible strings so they don't automatically (fail to) probe as genphys. Signed-off-by: Sean Anderson --- (no changes since v8) Changes in v8: - New .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 30 ++++++++++++------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 59b401daad4d..bbc714f84577 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -932,7 +932,8 @@ pcs_mdio1: mdio@8c07000 { #size-cells = <0>; status = "disabled"; - pcs1: ethernet-phy@0 { + pcs1: ethernet-pcs@0 { + compatible = "fsl,lynx-pcs"; reg = <0>; }; }; @@ -945,7 +946,8 @@ pcs_mdio2: mdio@8c0b000 { #size-cells = <0>; status = "disabled"; - pcs2: ethernet-phy@0 { + pcs2: ethernet-pcs@0 { + compatible = "fsl,lynx-pcs"; reg = <0>; }; }; @@ -958,19 +960,23 @@ pcs_mdio3: mdio@8c0f000 { #size-cells = <0>; status = "disabled"; - pcs3_0: ethernet-phy@0 { + pcs3_0: ethernet-pcs@0 { + compatible = "fsl,lynx-pcs"; reg = <0>; }; - pcs3_1: ethernet-phy@1 { + pcs3_1: ethernet-pcs@1 { + compatible = "fsl,lynx-pcs"; reg = <1>; }; - pcs3_2: ethernet-phy@2 { + pcs3_2: ethernet-pcs@2 { + compatible = "fsl,lynx-pcs"; reg = <2>; }; - pcs3_3: ethernet-phy@3 { + pcs3_3: ethernet-pcs@3 { + compatible = "fsl,lynx-pcs"; reg = <3>; }; }; @@ -983,19 +989,23 @@ pcs_mdio7: mdio@8c1f000 { #size-cells = <0>; status = "disabled"; - pcs7_0: ethernet-phy@0 { + pcs7_0: ethernet-pcs@0 { + compatible = "fsl,lynx-pcs"; reg = <0>; }; - pcs7_1: ethernet-phy@1 { + pcs7_1: ethernet-pcs@1 { + compatible = "fsl,lynx-pcs"; reg = <1>; }; - pcs7_2: ethernet-phy@2 { + pcs7_2: ethernet-pcs@2 { + compatible = "fsl,lynx-pcs"; reg = <2>; }; - pcs7_3: ethernet-phy@3 { + pcs7_3: ethernet-pcs@3 { + compatible = "fsl,lynx-pcs"; reg = <3>; }; }; From patchwork Tue Apr 11 18:43:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 672434 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44FC7C7619A for ; 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Ip=[20.160.56.80]; Helo=[inpost-eu.tmcas.trendmicro.com] X-MS-Exchange-CrossTenant-AuthSource: DB8EUR05FT025.eop-eur05.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR03MB8806 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org dpmac1 defaults to a fixed link. However, it has an SFP cage, so we can determine more about the link (such as whether it's up/down) by describing it. The GPIOs are part of the "QIXIS" FPGA. For now, just model them as individual registers. Signed-off-by: Sean Anderson --- Changes in v13: - Split off SFP addition from serdes support .../boot/dts/freescale/fsl-ls1088a-rdb.dts | 51 ++++++++++++++++++- 1 file changed, 50 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts index 391c2b8afa81..9fb1960f1258 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts @@ -10,11 +10,27 @@ /dts-v1/; +#include + #include "fsl-ls1088a.dtsi" / { model = "LS1088A RDB Board"; compatible = "fsl,ls1088a-rdb", "fsl,ls1088a"; + + sfp_slot: sfp { + compatible = "sff,sfp"; + i2c-bus = <&sfp_i2c>; + los-gpios = <&los_stat 5 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&los_stat 4 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&brdcfg9 4 GPIO_ACTIVE_HIGH>; + }; +}; + +&dpmac1 { + managed = "in-band-status"; + pcs-handle = <&pcs1>; + sfp = <&sfp_slot>; }; &dpmac2 { @@ -170,6 +186,12 @@ rtc@51 { interrupts-extended = <&extirq 0 IRQ_TYPE_LEVEL_LOW>; }; }; + + sfp_i2c: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; }; }; @@ -184,8 +206,31 @@ nand@0,0 { }; fpga: board-control@2,0 { - compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis"; + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis", + "simple-bus"; reg = <0x2 0x0 0x0000100>; + ranges = <0x0 0x2 0x0 0x0000100>; + + los_stat: gpio-controller@1d { + #gpio-cells = <2>; + compatible = "fsl,fpga-qixis-los-stat", + "ni,169445-nand-gpio"; + reg = <0x1d 0x1>; + reg-names = "dat"; + gpio-controller; + no-output; + }; + + brdcfg9: gpio-controller@59 { + #gpio-cells = <2>; + compatible = "fsl,fpga-qixis-brdcfg9", + "ni,169445-nand-gpio"; + reg = <0x59 0x1>; + reg-names = "dat"; + gpio-controller; + }; }; }; @@ -202,6 +247,10 @@ &esdhc { status = "okay"; }; +&pcs_mdio1 { + status = "okay"; +}; + &pcs_mdio2 { status = "okay"; };