From patchwork Tue Apr 11 12:59:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 672461 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00AB7C77B70 for ; Tue, 11 Apr 2023 12:59:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230201AbjDKM7g (ORCPT ); Tue, 11 Apr 2023 08:59:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54060 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230174AbjDKM7c (ORCPT ); Tue, 11 Apr 2023 08:59:32 -0400 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 32D8849C2 for ; Tue, 11 Apr 2023 05:59:21 -0700 (PDT) Received: by mail-wm1-x335.google.com with SMTP id v14-20020a05600c470e00b003f06520825fso9529794wmo.0 for ; Tue, 11 Apr 2023 05:59:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20210112.gappssmtp.com; s=20210112; t=1681217959; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TuLAeQGEV5K3iInBKoewzkhME+2oUBqCQOoUHj0zOJc=; b=PyPA+z9wzuCADbJtJNpxfh193DbvsBKQKRFsnEfdj2lux9LDV4aSpKu/Sl/j/gaY6D ff1p7jAPq70oW11rHUG0e/JHYABUvaI5p6p9GAY8Ed6gQvH3EyelCkOXAmD0OLsu5IvE 3On13qxxWDP8hytuA7PMIGBmRRi3Ajv35irx15owRr11QSYeL1uZ/S+ci5YMEt25UfFz J3jUc7nvNQGsFxBDwZgQVmuwS1wEMY75SVRm9ZLYiWMgtw5rXZ9grW2MwCw+D6srA522 d17sR+X/yCvaFxX6XaJ+jMVpEjFuaX3+dTC4FAUqWUG8Co7PMz4BS3urZXyS0wJGih8n 2Idg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681217959; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TuLAeQGEV5K3iInBKoewzkhME+2oUBqCQOoUHj0zOJc=; b=tPriDdnZoG+VvdWtYPortBV5V5OM8yykLl5v+cVhgJmcxF7fufs2/Gd9Ute81TyHb9 ghnuDOXf0eLaDfCXJ6bQcv/lFt4q23aX8LsVzEAEon9INm/OVeQvGi/f3VKXq1UIh1vn szuR8TtGzAocA3tgM4i/gZGhbR9diRALk2MV80XC+pPxs1af3S5VHXw2aCWJLgG3y1C5 rc7TNqnaMBGF4sfhAMnDBuJ7OQqHJHNCtS76PoQt66EX8+UvL0Cf1IM1wljXSaixZEGl znmzCuSgjv266HNN987qLtwgUv8O/t3g5qiCz2rDJlGNHedn9PNm3VKcXvF7YZCnAl6D 8WbA== X-Gm-Message-State: AAQBX9fHHqXHDreHWp5qzm3WVuTMz82Nvmu0sHkPtQjpIpss0QDWc8EG A+RyvMQFKh23ohYvp1PzJg+9Zg== X-Google-Smtp-Source: AKy350bBn4WjRe9oZZ13H+/2ZdNlHiC6u5ndF+nHtCFdwE/SHGsCimjWqVYVI8eMvSCk4yMuQkOmNw== X-Received: by 2002:a05:600c:2189:b0:3ed:5d41:f95c with SMTP id e9-20020a05600c218900b003ed5d41f95cmr10128112wme.11.1681217959220; Tue, 11 Apr 2023 05:59:19 -0700 (PDT) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:a099:fc1d:c99a:bfc3]) by smtp.gmail.com with ESMTPSA id e24-20020a05600c219800b003eae73f0fc1sm16944591wme.18.2023.04.11.05.59.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Apr 2023 05:59:18 -0700 (PDT) From: Bartosz Golaszewski To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Will Deacon , Robin Murphy , Joerg Roedel , Catalin Marinas , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Bartosz Golaszewski Subject: [PATCH v3 4/7] arm64: dts: qcom: sa8775p: add the pcie smmu node Date: Tue, 11 Apr 2023 14:59:07 +0200 Message-Id: <20230411125910.401075-5-brgl@bgdev.pl> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230411125910.401075-1-brgl@bgdev.pl> References: <20230411125910.401075-1-brgl@bgdev.pl> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Bartosz Golaszewski Add the PCIe SMMU node for sa8775p platforms. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 74 +++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 2343df7e0ea4..a23175352a20 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -809,6 +809,80 @@ apps_smmu: iommu@15000000 { ; }; + pcie_smmu: iommu@15200000 { + compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x15200000 0x0 0x80000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ From patchwork Tue Apr 11 12:59:08 2023 Content-Type: text/plain; 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Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index a23175352a20..191b510b5a1a 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -591,6 +591,20 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + gpucc: clock-controller@3d90000 { + compatible = "qcom,sa8775p-gpucc"; + reg = <0x0 0x03d90000 0x0 0xa000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sa8775p-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x30000>, From patchwork Tue Apr 11 12:59:10 2023 Content-Type: text/plain; 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Signed-off-by: Bartosz Golaszewski --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 37 +++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 191b510b5a1a..11f3d80dd869 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -605,6 +606,42 @@ gpucc: clock-controller@3d90000 { #power-domain-cells = <1>; }; + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu", + "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x20000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + dma-coherent; + power-domains = <&gpucc GPU_CC_CX_GDSC>; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HUB_AON_CLK>; + clock-names = "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gpu_cc_ahb_clk", + "gpu_cc_hlos1_vote_gpu_smmu_clk", + "gpu_cc_cx_gmu_clk", + "gpu_cc_hub_cx_int_clk", + "gpu_cc_hub_aon_clk"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sa8775p-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x30000>,