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Wed, 29 May 2019 08:44:04 +0000 Received: from MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::7c9a:f3bf:fe2e:fe4a]) by MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::7c9a:f3bf:fe2e:fe4a%4]) with mapi id 15.20.1922.021; Wed, 29 May 2019 08:44:04 +0000 From: Robert Richter To: Borislav Petkov , Tony Luck , "James Morse" , Mauro Carvalho Chehab CC: "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Robert Richter Subject: [PATCH 01/21] EDAC, mc: Fix edac_mc_find() in case no device is found Thread-Topic: [PATCH 01/21] EDAC, mc: Fix edac_mc_find() in case no device is found Thread-Index: AQHVFfqrQ8tilup7g0mWUbmqRMwOlw== Date: Wed, 29 May 2019 08:44:03 +0000 Message-ID: <20190529084344.28562-2-rrichter@marvell.com> References: <20190529084344.28562-1-rrichter@marvell.com> In-Reply-To: <20190529084344.28562-1-rrichter@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM6PR01CA0046.eurprd01.prod.exchangelabs.com (2603:10a6:20b:e0::23) To MN2PR18MB3408.namprd18.prod.outlook.com (2603:10b6:208:16c::25) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.20.1 x-originating-ip: [78.54.13.57] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: ca3f281f-db7b-4160-6ec9-08d6e411cd51 x-microsoft-antispam: BCL:0; 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FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: TTpPqP9c+BjDwGAftqAxjwosStakAdzNeHv8CwYMsfabjU6fxIIeUMsUL7M5a0ZxBEK27Xw/yCRAFOP4gWSuxBNGwO5VUUumritp09YTSpDo34BbxZ+cdp6EwYPkmNi5QVc7QAlD87mRj3nM9DVQfZgSRsxWbxp295Brsi9HROuOZ0GKtpTYNf/IjhbC+JXXkzKKNOwOgYJggxVkK7ZmKAvzuy+p63beKDtAU0sgdrGGh3fCVatVv+sRF9kNI0tUjOQ0fee4zPEJFObYUmz/PTvFcz7jbao2MyytZ/saaLKQan7hEDYG61/eiqBrrH4o/MUVRTeTY/rAUfQctXVX/8WaKpG1pnDAM/qk9e92LnH81R6w7PRmPE2twVx73iJ0tcnUmeZ+TJaAHtjin1knztDY5EExc/R98DBMxftE3XY= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: ca3f281f-db7b-4160-6ec9-08d6e411cd51 X-MS-Exchange-CrossTenant-originalarrivaltime: 29 May 2019 08:44:03.8523 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: rrichter@marvell.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR18MB3437 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-05-29_05:, , signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The function should return NULL in case no device is found, but it always returns the last checked mc device from the list even if the index did not match. This patch fixes this. I did some analysis why this did not raise any issues for about 3 years and the reason is that edac_mc_find() is mostly used to search for existing devices. Thus, the bug is not triggered. Fixes: c73e8833bec5 ("EDAC, mc: Fix locking around mc_devices list") Signed-off-by: Robert Richter --- drivers/edac/edac_mc.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) -- 2.20.1 diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index 13594ffadcb3..64922c8fa7e3 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -679,22 +679,18 @@ static int del_mc_from_global_list(struct mem_ctl_info *mci) struct mem_ctl_info *edac_mc_find(int idx) { - struct mem_ctl_info *mci = NULL; + struct mem_ctl_info *mci; struct list_head *item; mutex_lock(&mem_ctls_mutex); list_for_each(item, &mc_devices) { mci = list_entry(item, struct mem_ctl_info, link); - - if (mci->mc_idx >= idx) { - if (mci->mc_idx == idx) { - goto unlock; - } - break; - } + if (mci->mc_idx == idx) + goto unlock; } + mci = NULL; unlock: mutex_unlock(&mem_ctls_mutex); return mci; From patchwork Wed May 29 08:44:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 165350 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp9581041ili; Wed, 29 May 2019 01:45:56 -0700 (PDT) X-Google-Smtp-Source: APXvYqy8D8lsEqM/3UB4Yz1at+lbDmnuYIkHfFuw4BuvTxRRQOyq54TF9Ibn6aYPAzPjoKcsKGv3 X-Received: by 2002:a17:90a:cf18:: with SMTP id h24mr10591176pju.63.1559119555946; Wed, 29 May 2019 01:45:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559119555; cv=none; d=google.com; s=arc-20160816; b=w2VDSS6ZokT3Up8vgvm9vs1WRulussZoqZjP2PGsezssQ9dXdca7l6i8ETyJTiUf6c 8mOBR2IjVe0Zy5wfujoqQyzM2ks0LFmqX0G1HhnB4KGV8m18L5uw/+GVfvudxrWMY1Q3 s/0+N5NlnSdptMX1+L2r58ufUIQY42drMWoQRnT795eZPSC8Iiv2UbtjvyMawT+vH+a7 l7y+ZVxPAZiasnR3OBN1Mm4eG3SoXvEqjmKTnlplynlV4AlPzHLIEpFPTjtg7K5BR0Mn uVVZ25vCR/ONUEqebFTAmZ9deey3rUM3OM7WXLV7NPkyu85BCVk5Zz5cMLMpmXh3Just 0twQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:cc:to:from:dkim-signature :dkim-signature; bh=lQoZq7loVV5pKhsOJFBMbaakQmiE1B08uig6ldsAt6M=; b=mhJRu8OMLhYLEmwda/IrNx5kEvoG9P1FWWw4zuc4P/Okzp1KGos2nRVY+5nhBcaf2W NSLzLzxMlJOY4HwXsQHGRTOTG473wBboMaGSfx/5ho3Cr21tKAKbc1jMTlQaUGX/ddBi k8YF0BTaEEf+XhbIvIn1Q+Xe1CiUt2IVSosyFyjoh55aM+JvsU+cCeBggRt4uiQPq4in 05s7I1CWz3jeyMNbpWkgCJXqdkLhVVfFBqXgsN8b9ZYGhMnPEa4bGW7ZlHxFp0igE7Xp dQ49daMnhddQVAtRXNkMxM84mlnlUcjr0Qc9NRw8LhWs806iK1iRPmzkWBviMYvjPZj/ g7FA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0818 header.b="qFaeIO0/"; dkim=pass header.i=@marvell.onmicrosoft.com header.s=selector2-marvell-onmicrosoft-com header.b=nYyzid2i; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=marvell.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Wed, 29 May 2019 08:44:05 +0000 Received: from MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::7c9a:f3bf:fe2e:fe4a]) by MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::7c9a:f3bf:fe2e:fe4a%4]) with mapi id 15.20.1922.021; Wed, 29 May 2019 08:44:05 +0000 From: Robert Richter To: Borislav Petkov , Tony Luck , "James Morse" , Mauro Carvalho Chehab CC: "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Robert Richter Subject: [PATCH 02/21] EDAC: Fixes to use put_device() after device_add() errors Thread-Topic: [PATCH 02/21] EDAC: Fixes to use put_device() after device_add() errors Thread-Index: AQHVFfqscON641zZekePQqJCvaQr+Q== Date: Wed, 29 May 2019 08:44:05 +0000 Message-ID: <20190529084344.28562-3-rrichter@marvell.com> References: <20190529084344.28562-1-rrichter@marvell.com> In-Reply-To: <20190529084344.28562-1-rrichter@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM6PR01CA0046.eurprd01.prod.exchangelabs.com (2603:10a6:20b:e0::23) To MN2PR18MB3408.namprd18.prod.outlook.com (2603:10b6:208:16c::25) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.20.1 x-originating-ip: [78.54.13.57] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: ff4239af-1494-4fd7-a0a2-08d6e411ceda x-microsoft-antispam: BCL:0; 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Signed-off-by: Robert Richter --- drivers/edac/edac_mc_sysfs.c | 36 +++++++++++++++++++----------------- 1 file changed, 19 insertions(+), 17 deletions(-) -- 2.20.1 diff --git a/drivers/edac/edac_mc_sysfs.c b/drivers/edac/edac_mc_sysfs.c index 464174685589..dbef699162a8 100644 --- a/drivers/edac/edac_mc_sysfs.c +++ b/drivers/edac/edac_mc_sysfs.c @@ -404,6 +404,8 @@ static inline int nr_pages_per_csrow(struct csrow_info *csrow) static int edac_create_csrow_object(struct mem_ctl_info *mci, struct csrow_info *csrow, int index) { + int err; + csrow->dev.type = &csrow_attr_type; csrow->dev.groups = csrow_dev_groups; device_initialize(&csrow->dev); @@ -415,7 +417,11 @@ static int edac_create_csrow_object(struct mem_ctl_info *mci, edac_dbg(0, "creating (virtual) csrow node %s\n", dev_name(&csrow->dev)); - return device_add(&csrow->dev); + err = device_add(&csrow->dev); + if (err) + put_device(&csrow->dev); + + return err; } /* Create a CSROW object under specifed edac_mc_device */ @@ -646,8 +652,11 @@ static int edac_create_dimm_object(struct mem_ctl_info *mci, pm_runtime_forbid(&mci->dev); err = device_add(&dimm->dev); - - edac_dbg(0, "creating rank/dimm device %s\n", dev_name(&dimm->dev)); + if (err) + put_device(&dimm->dev); + else + edac_dbg(0, "creating rank/dimm device %s\n", + dev_name(&dimm->dev)); return err; } @@ -927,8 +936,9 @@ int edac_create_sysfs_mci_device(struct mem_ctl_info *mci, edac_dbg(0, "creating device %s\n", dev_name(&mci->dev)); err = device_add(&mci->dev); if (err < 0) { + put_device(&mci->dev); edac_dbg(1, "failure: create device %s\n", dev_name(&mci->dev)); - goto out; + return err; } /* @@ -977,7 +987,6 @@ int edac_create_sysfs_mci_device(struct mem_ctl_info *mci, } device_unregister(&mci->dev); -out: return err; } @@ -1034,10 +1043,8 @@ int __init edac_mc_sysfs_init(void) int err; mci_pdev = kzalloc(sizeof(*mci_pdev), GFP_KERNEL); - if (!mci_pdev) { - err = -ENOMEM; - goto out; - } + if (!mci_pdev) + return -ENOMEM; mci_pdev->bus = edac_get_sysfs_subsys(); mci_pdev->type = &mc_attr_type; @@ -1046,15 +1053,10 @@ int __init edac_mc_sysfs_init(void) err = device_add(mci_pdev); if (err < 0) - goto out_put_device; - - edac_dbg(0, "device %s created\n", dev_name(mci_pdev)); - - return 0; + put_device(mci_pdev); + else + edac_dbg(0, "device %s created\n", dev_name(mci_pdev)); - out_put_device: - put_device(mci_pdev); - out: return err; } From patchwork Wed May 29 08:44:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 165331 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp9579829ili; Wed, 29 May 2019 01:44:35 -0700 (PDT) X-Google-Smtp-Source: APXvYqwIAI4kaOnnqU2OYphWY8CYQsimtNJTuSF5A/eCjPyhUUF8HXZAiVowumt8puqySMWnTzC7 X-Received: by 2002:a63:eb50:: with SMTP id b16mr62808011pgk.150.1559119475480; Wed, 29 May 2019 01:44:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559119475; cv=none; d=google.com; s=arc-20160816; b=mnb8HoPBU+HIDai/ZbQCEh18celwcur1G3IrK+sVBQxoO2J0mOpmp8m5XzCXpOy6Oq A9irkUqEZLAo85lv6EosTKAbUa3153W2galYxx+NUdiOLNbgQOgRnSnBteceLkC99NLC P30JJJCPfCpijR43PYe+v6Xw78G+3PNVCeCw3yPblJt6U5YUXPrP47wdDBnUs++JQdsU KvvNbQgvTFuLUO99zw/+ndXrcrmvB/5jkyhv/evkNOrtSkYMLZmWzgGB3Up6ce4KYWxj v7s9jX/PlWp+N6RBQiG3dun48BbMo0GzO3zqT0b6LriFbpdflA7B5ALgvOL2kM/OzcTE JgfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:cc:to:from:dkim-signature :dkim-signature; bh=vGqf9qtafHxeR6/co378KEK8dLyYIV4i6j5Du4cXTz8=; b=QnHEfSFIe0TZjAdCakKF5fTevr5vBG6xZNIgZL5i2JX0hG3Xs1aDkVzLEcXmunjPF/ jMQ+eFj8b5ktW4kHS3qYLIHhKwN54BER8X3m7SMSWlioEpCn19K5R3TOr+vPi+Jzb6et PtI6iRcPo8TU71VxTJ8y6mbbsn9gYsqqcU7pFRytZrB5/Y56NI0QCaBawc7NtmW0zrOk ryjb9VK+8vhBjXGNmCI0iNZAVxwEocFTJJ/ME5EQMMEtvvBret18gXFLHzMISADx4mQz C2UmZ2GvH1tRKWsnX2fsRFnIQKcPPmGXKxZa5B7NAjghyXHPCcyFYYrJnT3kCd7kUifp 6qoA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0818 header.b=bgI6po2y; dkim=pass header.i=@marvell.onmicrosoft.com header.s=selector2-marvell-onmicrosoft-com header.b=HR77H30o; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=marvell.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Wed, 29 May 2019 08:44:10 +0000 Received: from MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::7c9a:f3bf:fe2e:fe4a]) by MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::7c9a:f3bf:fe2e:fe4a%4]) with mapi id 15.20.1922.021; Wed, 29 May 2019 08:44:10 +0000 From: Robert Richter To: Borislav Petkov , Tony Luck , "James Morse" , Mauro Carvalho Chehab , Jason Baron , Qiuxu Zhuo , "Tero Kristo" CC: "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Robert Richter Subject: [PATCH 03/21] EDAC: Kill EDAC_DIMM_PTR() macro Thread-Topic: [PATCH 03/21] EDAC: Kill EDAC_DIMM_PTR() macro Thread-Index: AQHVFfqvtHJHBX/ovUG+VmPPDrz2CQ== Date: Wed, 29 May 2019 08:44:10 +0000 Message-ID: <20190529084344.28562-4-rrichter@marvell.com> References: <20190529084344.28562-1-rrichter@marvell.com> In-Reply-To: <20190529084344.28562-1-rrichter@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM6PR01CA0046.eurprd01.prod.exchangelabs.com (2603:10a6:20b:e0::23) To MN2PR18MB3408.namprd18.prod.outlook.com (2603:10b6:208:16c::25) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.20.1 x-originating-ip: [78.54.13.57] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 33e64680-c615-48fd-3485-08d6e411d18c x-microsoft-antispam: BCL:0; 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Also introduce the edac_get_dimm_by_index() function for later use. Semantic patch used: @@ expression mci, a, b,c; @@ -EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, a, b, c) +edac_get_dimm(mci, a, b, c) Signed-off-by: Robert Richter --- drivers/edac/edac_mc.c | 1 + drivers/edac/ghes_edac.c | 8 ++-- drivers/edac/i10nm_base.c | 3 +- drivers/edac/i3200_edac.c | 3 +- drivers/edac/i5000_edac.c | 5 +-- drivers/edac/i5100_edac.c | 3 +- drivers/edac/i5400_edac.c | 4 +- drivers/edac/i7300_edac.c | 3 +- drivers/edac/i7core_edac.c | 3 +- drivers/edac/ie31200_edac.c | 7 +--- drivers/edac/pnd2_edac.c | 4 +- drivers/edac/sb_edac.c | 2 +- drivers/edac/skx_base.c | 3 +- drivers/edac/ti_edac.c | 2 +- include/linux/edac.h | 84 +++++++++++++++++++++++-------------- 15 files changed, 73 insertions(+), 62 deletions(-) -- 2.20.1 diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index 64922c8fa7e3..5f565e5949b3 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -439,6 +439,7 @@ struct mem_ctl_info *edac_mc_alloc(unsigned mc_num, goto error; mci->dimms[off] = dimm; dimm->mci = mci; + dimm->idx = off; /* * Copy DIMM location and initialize it. diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c index 49396bf6ad88..42afa2604db3 100644 --- a/drivers/edac/ghes_edac.c +++ b/drivers/edac/ghes_edac.c @@ -100,9 +100,8 @@ static void ghes_edac_dmidecode(const struct dmi_header *dh, void *arg) if (dh->type == DMI_ENTRY_MEM_DEVICE) { struct memdev_dmi_entry *entry = (struct memdev_dmi_entry *)dh; - struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, - mci->n_layers, - dimm_fill->count, 0, 0); + struct dimm_info *dimm = edac_get_dimm(mci, dimm_fill->count, + 0, 0); u16 rdr_mask = BIT(7) | BIT(13); if (entry->size == 0xffff) { @@ -529,8 +528,7 @@ int ghes_edac_register(struct ghes *ghes, struct device *dev) dimm_fill.mci = mci; dmi_walk(ghes_edac_dmidecode, &dimm_fill); } else { - struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, - mci->n_layers, 0, 0, 0); + struct dimm_info *dimm = edac_get_dimm(mci, 0, 0, 0); dimm->nr_pages = 1; dimm->grain = 128; diff --git a/drivers/edac/i10nm_base.c b/drivers/edac/i10nm_base.c index c334fb7c63df..bc7c990b57a5 100644 --- a/drivers/edac/i10nm_base.c +++ b/drivers/edac/i10nm_base.c @@ -152,8 +152,7 @@ static int i10nm_get_dimm_config(struct mem_ctl_info *mci) ndimms = 0; for (j = 0; j < I10NM_NUM_DIMMS; j++) { - dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, - mci->n_layers, i, j, 0); + dimm = edac_get_dimm(mci, i, j, 0); mtr = I10NM_GET_DIMMMTR(imc, i, j); mcddrtcfg = I10NM_GET_MCDDRTCFG(imc, i, j); edac_dbg(1, "dimmmtr 0x%x mcddrtcfg 0x%x (mc%d ch%d dimm%d)\n", diff --git a/drivers/edac/i3200_edac.c b/drivers/edac/i3200_edac.c index 299b441647cd..432b375a4075 100644 --- a/drivers/edac/i3200_edac.c +++ b/drivers/edac/i3200_edac.c @@ -392,8 +392,7 @@ static int i3200_probe1(struct pci_dev *pdev, int dev_idx) unsigned long nr_pages; for (j = 0; j < nr_channels; j++) { - struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, - mci->n_layers, i, j, 0); + struct dimm_info *dimm = edac_get_dimm(mci, i, j, 0); nr_pages = drb_to_nr_pages(drbs, stacked, j, i); if (nr_pages == 0) diff --git a/drivers/edac/i5000_edac.c b/drivers/edac/i5000_edac.c index 078a7351bf05..1a6f69c859ab 100644 --- a/drivers/edac/i5000_edac.c +++ b/drivers/edac/i5000_edac.c @@ -1275,9 +1275,8 @@ static int i5000_init_csrows(struct mem_ctl_info *mci) if (!MTR_DIMMS_PRESENT(mtr)) continue; - dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, - channel / MAX_BRANCHES, - channel % MAX_BRANCHES, slot); + dimm = edac_get_dimm(mci, channel / MAX_BRANCHES, + channel % MAX_BRANCHES, slot); csrow_megs = pvt->dimm_info[slot][channel].megabytes; dimm->grain = 8; diff --git a/drivers/edac/i5100_edac.c b/drivers/edac/i5100_edac.c index b506eef6b146..39ba7f2414ae 100644 --- a/drivers/edac/i5100_edac.c +++ b/drivers/edac/i5100_edac.c @@ -858,8 +858,7 @@ static void i5100_init_csrows(struct mem_ctl_info *mci) if (!npages) continue; - dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, - chan, rank, 0); + dimm = edac_get_dimm(mci, chan, rank, 0); dimm->nr_pages = npages; dimm->grain = 32; diff --git a/drivers/edac/i5400_edac.c b/drivers/edac/i5400_edac.c index 6f8bcdb9256a..a50a8707337b 100644 --- a/drivers/edac/i5400_edac.c +++ b/drivers/edac/i5400_edac.c @@ -1196,8 +1196,8 @@ static int i5400_init_dimms(struct mem_ctl_info *mci) if (!MTR_DIMMS_PRESENT(mtr)) continue; - dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, - channel / 2, channel % 2, slot); + dimm = edac_get_dimm(mci, channel / 2, channel % 2, + slot); size_mb = pvt->dimm_info[slot][channel].megabytes; diff --git a/drivers/edac/i7300_edac.c b/drivers/edac/i7300_edac.c index 6b5a554ba8e4..b76be69f0d74 100644 --- a/drivers/edac/i7300_edac.c +++ b/drivers/edac/i7300_edac.c @@ -796,8 +796,7 @@ static int i7300_init_csrows(struct mem_ctl_info *mci) for (ch = 0; ch < max_channel; ch++) { int channel = to_channel(ch, branch); - dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, - mci->n_layers, branch, ch, slot); + dimm = edac_get_dimm(mci, branch, ch, slot); dinfo = &pvt->dimm_info[slot][channel]; diff --git a/drivers/edac/i7core_edac.c b/drivers/edac/i7core_edac.c index 40297550313a..4d7afcd55626 100644 --- a/drivers/edac/i7core_edac.c +++ b/drivers/edac/i7core_edac.c @@ -587,8 +587,7 @@ static int get_dimm_config(struct mem_ctl_info *mci) if (!DIMM_PRESENT(dimm_dod[j])) continue; - dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, - i, j, 0); + dimm = edac_get_dimm(mci, i, j, 0); banks = numbank(MC_DOD_NUMBANK(dimm_dod[j])); ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j])); rows = numrow(MC_DOD_NUMROW(dimm_dod[j])); diff --git a/drivers/edac/ie31200_edac.c b/drivers/edac/ie31200_edac.c index aac9b9b360b8..a2b4d80ddc57 100644 --- a/drivers/edac/ie31200_edac.c +++ b/drivers/edac/ie31200_edac.c @@ -467,9 +467,7 @@ static int ie31200_probe1(struct pci_dev *pdev, int dev_idx) if (dimm_info[j][i].dual_rank) { nr_pages = nr_pages / 2; - dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, - mci->n_layers, (i * 2) + 1, - j, 0); + dimm = edac_get_dimm(mci, (i * 2) + 1, j, 0); dimm->nr_pages = nr_pages; edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages); dimm->grain = 8; /* just a guess */ @@ -480,8 +478,7 @@ static int ie31200_probe1(struct pci_dev *pdev, int dev_idx) dimm->dtype = DEV_UNKNOWN; dimm->edac_mode = EDAC_UNKNOWN; } - dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, - mci->n_layers, i * 2, j, 0); + dimm = edac_get_dimm(mci, i * 2, j, 0); dimm->nr_pages = nr_pages; edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages); dimm->grain = 8; /* same guess */ diff --git a/drivers/edac/pnd2_edac.c b/drivers/edac/pnd2_edac.c index 903a4f1fadcc..2f7dcafd84b1 100644 --- a/drivers/edac/pnd2_edac.c +++ b/drivers/edac/pnd2_edac.c @@ -1234,7 +1234,7 @@ static void apl_get_dimm_config(struct mem_ctl_info *mci) if (!(chan_mask & BIT(i))) continue; - dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, i, 0, 0); + dimm = edac_get_dimm(mci, i, 0, 0); if (!dimm) { edac_dbg(0, "No allocated DIMM for channel %d\n", i); continue; @@ -1314,7 +1314,7 @@ static void dnv_get_dimm_config(struct mem_ctl_info *mci) if (!ranks_of_dimm[j]) continue; - dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, i, j, 0); + dimm = edac_get_dimm(mci, i, j, 0); if (!dimm) { edac_dbg(0, "No allocated DIMM for channel %d DIMM %d\n", i, j); continue; diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c index 9353c3fc7c05..5dfa9ba1c252 100644 --- a/drivers/edac/sb_edac.c +++ b/drivers/edac/sb_edac.c @@ -1623,7 +1623,7 @@ static int __populate_dimms(struct mem_ctl_info *mci, } for (j = 0; j < max_dimms_per_channel; j++) { - dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, i, j, 0); + dimm = edac_get_dimm(mci, i, j, 0); if (pvt->info.type == KNIGHTS_LANDING) { pci_read_config_dword(pvt->knl.pci_channel[i], knl_mtr_reg, &mtr); diff --git a/drivers/edac/skx_base.c b/drivers/edac/skx_base.c index adae4c848ca1..6a828d6c0852 100644 --- a/drivers/edac/skx_base.c +++ b/drivers/edac/skx_base.c @@ -177,8 +177,7 @@ static int skx_get_dimm_config(struct mem_ctl_info *mci) pci_read_config_dword(imc->chan[i].cdev, 0x8C, &amap); pci_read_config_dword(imc->chan[i].cdev, 0x400, &mcddrtcfg); for (j = 0; j < SKX_NUM_DIMMS; j++) { - dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, - mci->n_layers, i, j, 0); + dimm = edac_get_dimm(mci, i, j, 0); pci_read_config_dword(imc->chan[i].cdev, 0x80 + 4 * j, &mtr); if (IS_DIMM_PRESENT(mtr)) { diff --git a/drivers/edac/ti_edac.c b/drivers/edac/ti_edac.c index 6ac26d1b929f..8be3e89a510e 100644 --- a/drivers/edac/ti_edac.c +++ b/drivers/edac/ti_edac.c @@ -135,7 +135,7 @@ static void ti_edac_setup_dimm(struct mem_ctl_info *mci, u32 type) u32 val; u32 memsize; - dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, 0, 0, 0); + dimm = edac_get_dimm(mci, 0, 0, 0); val = ti_edac_readl(edac, EMIF_SDRAM_CONFIG); diff --git a/include/linux/edac.h b/include/linux/edac.h index 342dabda9c7e..1367a3fc544f 100644 --- a/include/linux/edac.h +++ b/include/linux/edac.h @@ -403,37 +403,6 @@ struct edac_mc_layer { __i; \ }) -/** - * EDAC_DIMM_PTR - Macro responsible to get a pointer inside a pointer array - * for the element given by [layer0,layer1,layer2] position - * - * @layers: a struct edac_mc_layer array, describing how many elements - * were allocated for each layer - * @var: name of the var where we want to get the pointer - * (like mci->dimms) - * @nlayers: Number of layers at the @layers array - * @layer0: layer0 position - * @layer1: layer1 position. Unused if n_layers < 2 - * @layer2: layer2 position. Unused if n_layers < 3 - * - * For 1 layer, this macro returns "var[layer0]"; - * - * For 2 layers, this macro is similar to allocate a bi-dimensional array - * and to return "var[layer0][layer1]"; - * - * For 3 layers, this macro is similar to allocate a tri-dimensional array - * and to return "var[layer0][layer1][layer2]"; - */ -#define EDAC_DIMM_PTR(layers, var, nlayers, layer0, layer1, layer2) ({ \ - typeof(*var) __p; \ - int ___i = EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2); \ - if (___i < 0) \ - __p = NULL; \ - else \ - __p = (var)[___i]; \ - __p; \ -}) - struct dimm_info { struct device dev; @@ -443,6 +412,7 @@ struct dimm_info { unsigned location[EDAC_MAX_LAYERS]; struct mem_ctl_info *mci; /* the parent */ + int idx; /* index within the parent dimm array */ u32 grain; /* granularity of reported error in bytes */ enum dev_type dtype; /* memory device type */ @@ -669,4 +639,56 @@ struct mem_ctl_info { bool fake_inject_ue; u16 fake_inject_count; }; + +/** + * edac_get_dimm_by_index - Get DIMM info from a memory controller + * given by an index + * + * @mci: a struct mem_ctl_info + * @index: index in the memory controller's DIMM array + * + * Returns a struct dimm_info*. + */ +static inline struct dimm_info * +edac_get_dimm_by_index(struct mem_ctl_info *mci, int index) +{ + if (index < 0 || index >= mci->tot_dimms) + return NULL; + + if (WARN_ON_ONCE(mci->dimms[index]->idx != index)) + return NULL; + + return mci->dimms[index]; +} + +/** + * edac_get_dimm - Get DIMM info from a memory controller given by + * [layer0,layer1,layer2] position + * + * @mci: a struct mem_ctl_info + * @layer0: layer0 position + * @layer1: layer1 position. Unused if n_layers < 2 + * @layer2: layer2 position. Unused if n_layers < 3 + * + * For 1 layer, this macro returns "dimms[layer0]"; + * + * For 2 layers, this macro is similar to allocate a bi-dimensional array + * and to return "dimms[layer0][layer1]"; + * + * For 3 layers, this macro is similar to allocate a tri-dimensional array + * and to return "dimms[layer0][layer1][layer2]"; + */ +static inline struct dimm_info * +edac_get_dimm(struct mem_ctl_info *mci, int layer0, int layer1, int layer2) +{ + int index = layer0; + + if (index >= 0 && mci->n_layers > 1) + index = index * mci->layers[1].size + layer1; + if (index >= 0 && mci->n_layers > 2) + index = index * mci->layers[2].size + layer2; + + return edac_get_dimm_by_index(mci, index); +} + #endif From patchwork Wed May 29 08:44:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 165332 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp9579876ili; Wed, 29 May 2019 01:44:37 -0700 (PDT) X-Google-Smtp-Source: APXvYqySVks0dnIo+JtFDdQ0Fwyg9tO3kr1FNZL4Kkrx7qHi6N3KrYlFZ52hctK4bwMbcMnPAb/E X-Received: by 2002:a17:902:f81:: with SMTP id 1mr90527496plz.242.1559119477737; Wed, 29 May 2019 01:44:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559119477; cv=none; d=google.com; s=arc-20160816; b=xOMmNdCacgrvB1yUzdI5j9gZKmh/CwpM+h2yc385mDzuEGxnTCyAamJRXHluPXV47d wAy5ymTHZfPUjXq5wxLjv08ZAklOYIUzoMTV3I4sU0BJ8UH1rRDkvMlCF0+ZDbHmr9y+ O/qc6VRFVhRkm94rNukqI962zgH3wKOscl1cQczS3dxC15k5gI3yT3T2P8JlQYcdPV2c OID2UIwjry+JfiYzUcOpPobZ0BF1sf7OBpZTBWMfklVEn6ql9kJardD1dhEnO6fPfH/w Z4gxXJz4a4y6MeUyafJNtS4BAZfCKOCqfWx8nZ5BWM8fOCSg4az/5snn0NQg4PB66GcP 1yAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:cc:to:from:dkim-signature :dkim-signature; bh=aMNfwpkrfZlAQGOhWkeFqTQ7b5LUQt+8tswNsduhmqQ=; b=H1NaoEKaDRKG5TAB02mRUmG+tJHUEatg8+SoJw3LuOyimCAkC0YR9YmrLySfhSFsOa xTmO6xhzKFGwF1vtKH+hPYAUCbMeIl5ap0qAtN0FZir0Cl6p7hZsRPWD0ePZlpP6GfPQ oZs6hJisJn/bTWfyDsZQHGnamsipPZQrDKcCxf26NPkT/KrSv4igIsztpifKcbFlmnP0 bXrfCyasOfUOtVTdEWa/7ygNA4OlXc+b7EuO1CJp+gVorAyonteZjg8esQm3hVJhsWJr NAiC1xTZ7/IZxVSqCNre2IOc2M7PsYM8sk7xBsclZNpGiYmmZH2K7dc4vLel3E0LZAwS InCQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0818 header.b=KIrs5vXX; dkim=pass header.i=@marvell.onmicrosoft.com header.s=selector2-marvell-onmicrosoft-com header.b=wioOTkbe; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=marvell.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Robert Richter --- drivers/edac/edac_mc.c | 13 ++++-------- drivers/edac/edac_mc_sysfs.c | 20 ++++-------------- include/linux/edac.h | 41 ------------------------------------ 3 files changed, 8 insertions(+), 66 deletions(-) -- 2.20.1 diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index 5f565e5949b3..07edbd80af07 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -318,7 +318,7 @@ struct mem_ctl_info *edac_mc_alloc(unsigned mc_num, unsigned size, tot_dimms = 1, count = 1; unsigned tot_csrows = 1, tot_channels = 1, tot_errcount = 0; void *pvt, *p, *ptr = NULL; - int i, j, row, chn, n, len, off; + int idx, i, j, row, chn, n, len; bool per_rank = false; BUG_ON(n_layers > EDAC_MAX_LAYERS || n_layers == 0); @@ -426,20 +426,15 @@ struct mem_ctl_info *edac_mc_alloc(unsigned mc_num, memset(&pos, 0, sizeof(pos)); row = 0; chn = 0; - for (i = 0; i < tot_dimms; i++) { + for (idx = 0; idx < tot_dimms; idx++) { chan = mci->csrows[row]->channels[chn]; - off = EDAC_DIMM_OFF(layer, n_layers, pos[0], pos[1], pos[2]); - if (off < 0 || off >= tot_dimms) { - edac_mc_printk(mci, KERN_ERR, "EDAC core bug: EDAC_DIMM_OFF is trying to do an illegal data access\n"); - goto error; - } dimm = kzalloc(sizeof(**mci->dimms), GFP_KERNEL); if (!dimm) goto error; - mci->dimms[off] = dimm; + mci->dimms[idx] = dimm; dimm->mci = mci; - dimm->idx = off; + dimm->idx = idx; /* * Copy DIMM location and initialize it. diff --git a/drivers/edac/edac_mc_sysfs.c b/drivers/edac/edac_mc_sysfs.c index dbef699162a8..8beefa699a49 100644 --- a/drivers/edac/edac_mc_sysfs.c +++ b/drivers/edac/edac_mc_sysfs.c @@ -558,14 +558,8 @@ static ssize_t dimmdev_ce_count_show(struct device *dev, { struct dimm_info *dimm = to_dimm(dev); u32 count; - int off; - - off = EDAC_DIMM_OFF(dimm->mci->layers, - dimm->mci->n_layers, - dimm->location[0], - dimm->location[1], - dimm->location[2]); - count = dimm->mci->ce_per_layer[dimm->mci->n_layers-1][off]; + + count = dimm->mci->ce_per_layer[dimm->mci->n_layers-1][dimm->idx]; return sprintf(data, "%u\n", count); } @@ -575,14 +569,8 @@ static ssize_t dimmdev_ue_count_show(struct device *dev, { struct dimm_info *dimm = to_dimm(dev); u32 count; - int off; - - off = EDAC_DIMM_OFF(dimm->mci->layers, - dimm->mci->n_layers, - dimm->location[0], - dimm->location[1], - dimm->location[2]); - count = dimm->mci->ue_per_layer[dimm->mci->n_layers-1][off]; + + count = dimm->mci->ue_per_layer[dimm->mci->n_layers-1][dimm->idx]; return sprintf(data, "%u\n", count); } diff --git a/include/linux/edac.h b/include/linux/edac.h index 1367a3fc544f..2ee9b8598ae0 100644 --- a/include/linux/edac.h +++ b/include/linux/edac.h @@ -362,47 +362,6 @@ struct edac_mc_layer { */ #define EDAC_MAX_LAYERS 3 -/** - * EDAC_DIMM_OFF - Macro responsible to get a pointer offset inside a pointer - * array for the element given by [layer0,layer1,layer2] - * position - * - * @layers: a struct edac_mc_layer array, describing how many elements - * were allocated for each layer - * @nlayers: Number of layers at the @layers array - * @layer0: layer0 position - * @layer1: layer1 position. Unused if n_layers < 2 - * @layer2: layer2 position. Unused if n_layers < 3 - * - * For 1 layer, this macro returns "var[layer0] - var"; - * - * For 2 layers, this macro is similar to allocate a bi-dimensional array - * and to return "var[layer0][layer1] - var"; - * - * For 3 layers, this macro is similar to allocate a tri-dimensional array - * and to return "var[layer0][layer1][layer2] - var". - * - * A loop could be used here to make it more generic, but, as we only have - * 3 layers, this is a little faster. - * - * By design, layers can never be 0 or more than 3. If that ever happens, - * a NULL is returned, causing an OOPS during the memory allocation routine, - * with would point to the developer that he's doing something wrong. - */ -#define EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2) ({ \ - int __i; \ - if ((nlayers) == 1) \ - __i = layer0; \ - else if ((nlayers) == 2) \ - __i = (layer1) + ((layers[1]).size * (layer0)); \ - else if ((nlayers) == 3) \ - __i = (layer2) + ((layers[2]).size * ((layer1) + \ - ((layers[1]).size * (layer0)))); \ - else \ - __i = -EINVAL; \ - __i; \ -}) - struct dimm_info { struct device dev; From patchwork Wed May 29 08:44:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 165349 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp9580993ili; Wed, 29 May 2019 01:45:52 -0700 (PDT) X-Google-Smtp-Source: APXvYqzrij3SyyrRIwYhZ8SPPu90u01KgycCaYVV6UWqLCfVhm1h2mGyBC15sXqh9bSeVIuc0k+O X-Received: by 2002:a17:902:2a68:: with SMTP id i95mr2668220plb.167.1559119552479; Wed, 29 May 2019 01:45:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559119552; cv=none; d=google.com; s=arc-20160816; b=RzLnkrDaJE3oGfQb92QHq1TdOQdLTGMbU3FkMmuLZT4srZ4CJHsJYoXcpx1gr9/iot /K5n3HmLz2D1mtuHpcrbR23yXn2truljfzSvEK/nv0S5Q63X24AL6U0qLBaioZiPLsPd bnz6TBChhcuQLxiIRgZs21rlfWZbMvGvx9IdaRcM3xTDaYuBWpg65IIiFPzahYrkOcSH GDj6If5lzUej0rJvhZSZ4nZYgzA2Hj3lhH+gn24/VBYdw1lL+OIYZIpV5qKMFVx68Etw /klcxVdOmu3iRvsE/YorwythTlucr669grK5say+phQ/yejrrAaxKk1imUJyzKEWAVOa CpCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:cc:to:from:dkim-signature :dkim-signature; bh=wzWksusEaTyX0Xqg/yKi2uWhEhxqWz63CbuF6f9E0Qk=; b=TQNJ7sAz9GC7RsWgXGBw1555S5ik5jcJfEcEFsfb4tdw3rB+vOZSWPmPEiD1iq+xgy U2hLUH9Xjn/H0HX8glXn6557AmZzOcxyyuUY+CUWnWt7szHPel+sD9beX8PN9VE9WxIJ XKM5VjIN/t+0CK0htEsf3I81E8CbI5m5y8FNHpS0e9t5nHN490AZPnKyjboBS12hkEuX Bq2iAMiMmu4xoxr38d49SXeZcNkUDQMomr3VHy/VZgVaW2nRx43i7Pwrc88oXsaoCFUT yyZnsqF9oBHk/1kzv90I0Mg7yxXa2gJ3UpcSS+YQ9MH2ThnUVrpWzaejmciI/ki5WD3Y FxYg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0818 header.b=PeclCnA6; dkim=pass header.i=@marvell.onmicrosoft.com header.s=selector2-marvell-onmicrosoft-com header.b=HQhogKUj; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=marvell.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Wed, 29 May 2019 08:44:15 +0000 Received: from MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::7c9a:f3bf:fe2e:fe4a]) by MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::7c9a:f3bf:fe2e:fe4a%4]) with mapi id 15.20.1922.021; Wed, 29 May 2019 08:44:15 +0000 From: Robert Richter To: Borislav Petkov , Tony Luck , "James Morse" , Mauro Carvalho Chehab CC: "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Robert Richter Subject: [PATCH 05/21] EDAC: Introduce mci_for_each_dimm() iterator Thread-Topic: [PATCH 05/21] EDAC: Introduce mci_for_each_dimm() iterator Thread-Index: AQHVFfqyZ42X6bVw40qQR+81APMGEQ== Date: Wed, 29 May 2019 08:44:15 +0000 Message-ID: <20190529084344.28562-6-rrichter@marvell.com> References: <20190529084344.28562-1-rrichter@marvell.com> In-Reply-To: <20190529084344.28562-1-rrichter@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM6PR01CA0046.eurprd01.prod.exchangelabs.com (2603:10a6:20b:e0::23) To MN2PR18MB3408.namprd18.prod.outlook.com (2603:10b6:208:16c::25) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.20.1 x-originating-ip: [78.54.13.57] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 6d80d6cc-c981-41cc-d3ab-08d6e411d489 x-microsoft-antispam: BCL:0; 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Now, we just get a pointer to a struct dimm_info. Direct array access using an index is no longer needed to iterate. Signed-off-by: Robert Richter --- drivers/edac/edac_mc.c | 18 ++++++++++-------- drivers/edac/edac_mc_sysfs.c | 34 +++++++++++++++------------------- drivers/edac/ghes_edac.c | 8 ++++---- drivers/edac/i5100_edac.c | 11 +++++------ include/linux/edac.h | 7 +++++++ 5 files changed, 41 insertions(+), 37 deletions(-) -- 2.20.1 diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index 07edbd80af07..a6b34ccce3d4 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -145,15 +145,18 @@ static void edac_mc_dump_channel(struct rank_info *chan) edac_dbg(4, " channel->dimm = %p\n", chan->dimm); } -static void edac_mc_dump_dimm(struct dimm_info *dimm, int number) +static void edac_mc_dump_dimm(struct dimm_info *dimm) { char location[80]; + if (!dimm->nr_pages) + return; + edac_dimm_info_location(dimm, location, sizeof(location)); edac_dbg(4, "%s%i: %smapped as virtual row %d, chan %d\n", dimm->mci->csbased ? "rank" : "dimm", - number, location, dimm->csrow, dimm->cschannel); + dimm->idx, location, dimm->csrow, dimm->cschannel); edac_dbg(4, " dimm = %p\n", dimm); edac_dbg(4, " dimm->label = '%s'\n", dimm->label); edac_dbg(4, " dimm->nr_pages = 0x%x\n", dimm->nr_pages); @@ -703,6 +706,7 @@ EXPORT_SYMBOL_GPL(edac_get_owner); int edac_mc_add_mc_with_groups(struct mem_ctl_info *mci, const struct attribute_group **groups) { + struct dimm_info *dimm; int ret = -EINVAL; edac_dbg(0, "\n"); @@ -727,9 +731,8 @@ int edac_mc_add_mc_with_groups(struct mem_ctl_info *mci, if (csrow->channels[j]->dimm->nr_pages) edac_mc_dump_channel(csrow->channels[j]); } - for (i = 0; i < mci->tot_dimms; i++) - if (mci->dimms[i]->nr_pages) - edac_mc_dump_dimm(mci->dimms[i], i); + mci_for_each_dimm(mci, dimm) + edac_mc_dump_dimm(dimm); } #endif mutex_lock(&mem_ctls_mutex); @@ -1087,6 +1090,7 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, const char *msg, const char *other_detail) { + struct dimm_info *dimm; char *p; int row = -1, chan = -1; int pos[EDAC_MAX_LAYERS] = { top_layer, mid_layer, low_layer }; @@ -1147,9 +1151,7 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, p = e->label; *p = '\0'; - for (i = 0; i < mci->tot_dimms; i++) { - struct dimm_info *dimm = mci->dimms[i]; - + mci_for_each_dimm(mci, dimm) { if (top_layer >= 0 && top_layer != dimm->location[0]) continue; if (mid_layer >= 0 && mid_layer != dimm->location[1]) diff --git a/drivers/edac/edac_mc_sysfs.c b/drivers/edac/edac_mc_sysfs.c index 8beefa699a49..75cba0812a16 100644 --- a/drivers/edac/edac_mc_sysfs.c +++ b/drivers/edac/edac_mc_sysfs.c @@ -622,8 +622,7 @@ static const struct device_type dimm_attr_type = { /* Create a DIMM object under specifed memory controller device */ static int edac_create_dimm_object(struct mem_ctl_info *mci, - struct dimm_info *dimm, - int index) + struct dimm_info *dimm) { int err; dimm->mci = mci; @@ -633,9 +632,9 @@ static int edac_create_dimm_object(struct mem_ctl_info *mci, dimm->dev.parent = &mci->dev; if (mci->csbased) - dev_set_name(&dimm->dev, "rank%d", index); + dev_set_name(&dimm->dev, "rank%d", dimm->idx); else - dev_set_name(&dimm->dev, "dimm%d", index); + dev_set_name(&dimm->dev, "dimm%d", dimm->idx); dev_set_drvdata(&dimm->dev, dimm); pm_runtime_forbid(&mci->dev); @@ -909,7 +908,8 @@ static const struct device_type mci_attr_type = { int edac_create_sysfs_mci_device(struct mem_ctl_info *mci, const struct attribute_group **groups) { - int i, err; + struct dimm_info *dimm; + int err; /* get the /sys/devices/system/edac subsys reference */ mci->dev.type = &mci_attr_type; @@ -932,14 +932,13 @@ int edac_create_sysfs_mci_device(struct mem_ctl_info *mci, /* * Create the dimm/rank devices */ - for (i = 0; i < mci->tot_dimms; i++) { - struct dimm_info *dimm = mci->dimms[i]; + mci_for_each_dimm(mci, dimm) { /* Only expose populated DIMMs */ if (!dimm->nr_pages) continue; #ifdef CONFIG_EDAC_DEBUG - edac_dbg(1, "creating dimm%d, located at ", i); + edac_dbg(1, "creating dimm%d, located at ", dimm->idx); if (edac_debug_level >= 1) { int lay; for (lay = 0; lay < mci->n_layers; lay++) @@ -949,9 +948,10 @@ int edac_create_sysfs_mci_device(struct mem_ctl_info *mci, printk(KERN_CONT "\n"); } #endif - err = edac_create_dimm_object(mci, dimm, i); + err = edac_create_dimm_object(mci, dimm); if (err) { - edac_dbg(1, "failure: create dimm %d obj\n", i); + edac_dbg(1, "failure: create dimm %d obj\n", + dimm->idx); goto fail_unregister_dimm; } } @@ -966,12 +966,9 @@ int edac_create_sysfs_mci_device(struct mem_ctl_info *mci, return 0; fail_unregister_dimm: - for (i--; i >= 0; i--) { - struct dimm_info *dimm = mci->dimms[i]; - if (!dimm->nr_pages) - continue; - - device_unregister(&dimm->dev); + mci_for_each_dimm(mci, dimm) { + if (device_is_registered(&dimm->dev)) + device_unregister(&dimm->dev); } device_unregister(&mci->dev); @@ -983,7 +980,7 @@ int edac_create_sysfs_mci_device(struct mem_ctl_info *mci, */ void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci) { - int i; + struct dimm_info *dimm; edac_dbg(0, "\n"); @@ -994,8 +991,7 @@ void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci) edac_delete_csrow_objects(mci); #endif - for (i = 0; i < mci->tot_dimms; i++) { - struct dimm_info *dimm = mci->dimms[i]; + mci_for_each_dimm(mci, dimm) { if (dimm->nr_pages == 0) continue; edac_dbg(0, "removing device %s\n", dev_name(&dimm->dev)); diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c index 42afa2604db3..fe45392f0c3e 100644 --- a/drivers/edac/ghes_edac.c +++ b/drivers/edac/ghes_edac.c @@ -84,11 +84,11 @@ static void ghes_edac_count_dimms(const struct dmi_header *dh, void *arg) static int get_dimm_smbios_index(u16 handle) { struct mem_ctl_info *mci = ghes_pvt->mci; - int i; + struct dimm_info *dimm; - for (i = 0; i < mci->tot_dimms; i++) { - if (mci->dimms[i]->smbios_handle == handle) - return i; + mci_for_each_dimm(mci, dimm) { + if (dimm->smbios_handle == handle) + return dimm->idx; } return -1; } diff --git a/drivers/edac/i5100_edac.c b/drivers/edac/i5100_edac.c index 39ba7f2414ae..7ec42b26a716 100644 --- a/drivers/edac/i5100_edac.c +++ b/drivers/edac/i5100_edac.c @@ -846,14 +846,13 @@ static void i5100_init_interleaving(struct pci_dev *pdev, static void i5100_init_csrows(struct mem_ctl_info *mci) { - int i; struct i5100_priv *priv = mci->pvt_info; + struct dimm_info *dimm; - for (i = 0; i < mci->tot_dimms; i++) { - struct dimm_info *dimm; - const unsigned long npages = i5100_npages(mci, i); - const unsigned chan = i5100_csrow_to_chan(mci, i); - const unsigned rank = i5100_csrow_to_rank(mci, i); + mci_for_each_dimm(mci, dimm) { + const unsigned long npages = i5100_npages(mci, dimm->idx); + const unsigned chan = i5100_csrow_to_chan(mci, dimm->idx); + const unsigned rank = i5100_csrow_to_rank(mci, dimm->idx); if (!npages) continue; diff --git a/include/linux/edac.h b/include/linux/edac.h index 2ee9b8598ae0..20a04f48616c 100644 --- a/include/linux/edac.h +++ b/include/linux/edac.h @@ -599,6 +599,13 @@ struct mem_ctl_info { u16 fake_inject_count; }; +#define mci_for_each_dimm(mci, dimm) \ + for ((dimm) = (mci)->dimms[0]; \ + (dimm); \ + (dimm) = (dimm)->idx < (mci)->tot_dimms \ + ? (mci)->dimms[(dimm)->idx + 1] \ + : NULL) + /** * edac_get_dimm_by_index - Get DIMM info from a memory controller * given by an index From patchwork Wed May 29 08:44:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 165348 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp9580872ili; Wed, 29 May 2019 01:45:45 -0700 (PDT) X-Google-Smtp-Source: APXvYqzlpLPyq6Ca3KbWtovT7fBscnXWHFHgfjW7en137vC1T56kCzksBJvID900uQ8nSvQQSlb+ X-Received: by 2002:a63:fe51:: with SMTP id x17mr26353653pgj.339.1559119544997; Wed, 29 May 2019 01:45:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559119544; cv=none; d=google.com; s=arc-20160816; b=xria5QO79r+2dtnko+NNYO4+tBDk0+QN01UhACLoiuGitLt8fmvbSQv92m0CFqLXAQ jhLIBwpbGDoJggYbVAMFhZ0PXuuUTGngy+oM1bj2ghuBHmIFaVbAeGhH6H0Ffmrwpp3J lnXIi8aIFqqW5RgsTiS1wxjg0QZQW+8JcFS9lbCvEg7SFvyAULSp7UXlP9q/lKl18dum NfoOXuLop8ZzEojIvZv3CqU8kQOGFehtGSHF0r25JhTxUqKNyMd0KfkMSJsOByay3AZq nkGg7ssQFNEX5Nkpe2m1qhoSJjQE3U0lylSgZ2ThAgdz80wkzvuE/88IVxzPFgmzw0WL 2CGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:cc:to:from:dkim-signature :dkim-signature; bh=6Fc5EB71Mh+CRL6fzdDB56EnuIF+olOEmhQM0dUtWPc=; b=xVSPeUpLXzVVdGdvw0o5zKo40eEUte3uRr6Adv+Wdj0i/vLCoKWr/RdMT2+f4bnjtv hUpP77eFNAxRM6ljOwTW8OrCY6e4+Xs/BOmQUbWpKNHpcXD4ETy47pzco+/KWHPP+mnB FgcvYs5J0WaOfG39Uzpy85UU8DgMb82D0YXI8+sKQibF2QUYv8s6xk+Oq2EI/zdVr8UK vSTENYGlfA6chAlEput2KG4xijrOUmeEGzPt0d6NX7T9FVyFbOkYSle6ptWvCB9mtfqS SfeprDYcZKIgMmp/NujEw8OvhDmNH435zTgSgRqfjNF1ADL38Qy3tGPfSr7OHPnAe9LE YImw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0818 header.b=OWXBNleg; dkim=pass header.i=@marvell.onmicrosoft.com header.s=selector2-marvell-onmicrosoft-com header.b=bVjEhSPf; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=marvell.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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No functional changes. Signed-off-by: Robert Richter --- drivers/edac/edac_mc.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) -- 2.20.1 diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index a6b34ccce3d4..a849993a8dcd 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -280,26 +280,23 @@ static void _edac_mc_free(struct mem_ctl_info *mci) { int i, chn, row; struct csrow_info *csr; - const unsigned int tot_dimms = mci->tot_dimms; - const unsigned int tot_channels = mci->num_cschannel; - const unsigned int tot_csrows = mci->nr_csrows; if (mci->dimms) { - for (i = 0; i < tot_dimms; i++) + for (i = 0; i < mci->tot_dimms; i++) kfree(mci->dimms[i]); kfree(mci->dimms); } if (mci->csrows) { - for (row = 0; row < tot_csrows; row++) { + for (row = 0; row < mci->nr_csrows; row++) { csr = mci->csrows[row]; - if (csr) { - if (csr->channels) { - for (chn = 0; chn < tot_channels; chn++) - kfree(csr->channels[chn]); - kfree(csr->channels); - } - kfree(csr); + if (!csr) + continue; + if (csr->channels) { + for (chn = 0; chn < mci->num_cschannel; chn++) + kfree(csr->channels[chn]); + kfree(csr->channels); } + kfree(csr); } kfree(mci->csrows); } From patchwork Wed May 29 08:44:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 165347 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp9580768ili; Wed, 29 May 2019 01:45:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqxsx4rMlsqId7dbb69bNUfx0YjaLgyW9GQXT5ZOTUh9jthe97ZOnyCyvTe2SI03/4rWH+oq X-Received: by 2002:a17:90a:5d15:: with SMTP id s21mr10352541pji.126.1559119538725; Wed, 29 May 2019 01:45:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559119538; cv=none; d=google.com; s=arc-20160816; b=XaY3f95pzFiV1ayYihp/DHAw3mGzj1V3YbUGP3wIhEavLRz1xJuNMY0gGFqAa+1UU6 fLQHQ2Jtf3LGSMqsiaPTNsLKcRjr0zz6VnaKW6Xl6ntWH88OIeP3s9jWJKqrDVUyt0Qt Ysg+U2/FVnE8hZ8eQ3amGTYPs9LaX8iMMrwgdL0hA/rlmlfcWpymiLF4IeH0fBIzJUTS ZHePAztorku93LD/lo5FXxscW+K/vhM+k8kc65NB0z1mSVQe3HMi7766+6+DS9lVbvZ9 fnOtuJM4LKc8JngmCBuYvB9b0Bc0qN9dp1tYAaTdCuMnfVKEgAStkF5ffa9kKU5rCAAf 91QQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:cc:to:from:dkim-signature :dkim-signature; bh=4wF3SPUyGPHoCx3EBCyYWxuZWb/bDs+k4pi0b8sR4Mg=; b=KrwcCu0IByo4/QttAAoo9znOCTNsim+Q1VTYO8u0sTfL8tdo8wW8qOR9uUiV4JwMxe tqYugVgnbrspWBmccZ24Tb5ijd1JaUM9dnmSgP84tRKohPtpp4xOVjo/2w4/iagUMB8B 1KZmBrhAXdsSMG3572DlDTWob+rQrGKBfh66ejoquhVb7jxOi6kyjb3JSN2/xeKi80Gc K0971a6LsAQu7p4SytYpSzlof8ZBprpn3E3C6MQmjG/j/kuE5AvaG+Qn236RmlsPvC3C BzOtmX4r94ANXIRi0hvqnFz/gmFfKPlOu95gkbD+1g/40re8YYWoqKgSh5wW1WfDRhZf 39ww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0818 header.b=qcn5VQM2; dkim=pass header.i=@marvell.onmicrosoft.com header.s=selector2-marvell-onmicrosoft-com header.b=Uou4UDHg; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=marvell.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Wed, 29 May 2019 08:44:20 +0000 Received: from MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::7c9a:f3bf:fe2e:fe4a]) by MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::7c9a:f3bf:fe2e:fe4a%4]) with mapi id 15.20.1922.021; Wed, 29 May 2019 08:44:20 +0000 From: Robert Richter To: Borislav Petkov , Tony Luck , "James Morse" , Mauro Carvalho Chehab CC: "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Robert Richter Subject: [PATCH 07/21] EDAC, mc: Remove per layer counters Thread-Topic: [PATCH 07/21] EDAC, mc: Remove per layer counters Thread-Index: AQHVFfq1pJPJBRznJ0WhfJ4esVhWBA== Date: Wed, 29 May 2019 08:44:20 +0000 Message-ID: <20190529084344.28562-8-rrichter@marvell.com> References: <20190529084344.28562-1-rrichter@marvell.com> In-Reply-To: <20190529084344.28562-1-rrichter@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM6PR01CA0046.eurprd01.prod.exchangelabs.com (2603:10a6:20b:e0::23) To MN2PR18MB3408.namprd18.prod.outlook.com (2603:10b6:208:16c::25) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.20.1 x-originating-ip: [78.54.13.57] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 78148fda-38bc-437a-1a2e-08d6e411d74f x-microsoft-antispam: BCL:0; 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FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 4jymGFlb2MBTHG/rOt+bDNyOf4L17044qxN/P2kopUnvygTY2GqcWNMDEYzV1HsnWC0CkzR1GpZynpA6deNTI6rj0lDQrBin7K2mgzCQ/J+YrslDZEetIIgO94ciSnrk1P4Nhs6oWVa4hhsqXpb2KO9hVj123UK5Vvf8snMHzzUnQxukDALmYS+fVGx+9Im3DZEjKita4ERDn0wUTu4H6T8an0LX5TzyRsVErxLVZ/4vgomAtt3KfzTzxoXoGZgK0G1xNop3bOcFHGqSdt/w5GStwNZvbLBUcucruGdRLWi12UGqBZm9cZYG6Pvp3SSaKs6W7OIEXwo/ogA+u2hvq+i+OlU4DMbGB6EVB57oq9Zf5sC3U+Xie0lqKzdgFusBhu7NCsukA34eyN7g7sHT2AhDiUtBsr1uW0UPRH8v7B8= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 78148fda-38bc-437a-1a2e-08d6e411d74f X-MS-Exchange-CrossTenant-originalarrivaltime: 29 May 2019 08:44:20.1929 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: rrichter@marvell.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR18MB3437 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-05-29_05:, , signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Looking at how mci->{ue,ce}_per_layer[EDAC_MAX_LAYERS] is used, it turns out that only the leaves in the memory hierarchy are consumed (in sysfs), but not the intermediate layers, e.g.: count = dimm->mci->ce_per_layer[dimm->mci->n_layers-1][dimm->idx]; So let's get rid of the unused counters that just add complexity. Error counter values are directly stored in struct dimm_info now. Signed-off-by: Robert Richter --- drivers/edac/edac_mc.c | 98 ++++++++++++------------------------ drivers/edac/edac_mc_sysfs.c | 17 ++----- drivers/edac/ghes_edac.c | 5 +- include/linux/edac.h | 7 ++- 4 files changed, 39 insertions(+), 88 deletions(-) -- 2.20.1 diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index a849993a8dcd..2e461c9e1a89 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -313,10 +313,9 @@ struct mem_ctl_info *edac_mc_alloc(unsigned mc_num, struct csrow_info *csr; struct rank_info *chan; struct dimm_info *dimm; - u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS]; unsigned pos[EDAC_MAX_LAYERS]; - unsigned size, tot_dimms = 1, count = 1; - unsigned tot_csrows = 1, tot_channels = 1, tot_errcount = 0; + unsigned size, tot_dimms = 1; + unsigned tot_csrows = 1, tot_channels = 1; void *pvt, *p, *ptr = NULL; int idx, i, j, row, chn, n, len; bool per_rank = false; @@ -342,19 +341,10 @@ struct mem_ctl_info *edac_mc_alloc(unsigned mc_num, * stringent as what the compiler would provide if we could simply * hardcode everything into a single struct. */ - mci = edac_align_ptr(&ptr, sizeof(*mci), 1); - layer = edac_align_ptr(&ptr, sizeof(*layer), n_layers); - for (i = 0; i < n_layers; i++) { - count *= layers[i].size; - edac_dbg(4, "errcount layer %d size %d\n", i, count); - ce_per_layer[i] = edac_align_ptr(&ptr, sizeof(u32), count); - ue_per_layer[i] = edac_align_ptr(&ptr, sizeof(u32), count); - tot_errcount += 2 * count; - } - - edac_dbg(4, "allocating %d error counters\n", tot_errcount); - pvt = edac_align_ptr(&ptr, sz_pvt, 1); - size = ((unsigned long)pvt) + sz_pvt; + mci = edac_align_ptr(&ptr, sizeof(*mci), 1); + layer = edac_align_ptr(&ptr, sizeof(*layer), n_layers); + pvt = edac_align_ptr(&ptr, sz_pvt, 1); + size = ((unsigned long)pvt) + sz_pvt; edac_dbg(1, "allocating %u bytes for mci data (%d %s, %d csrows/channels)\n", size, @@ -370,10 +360,6 @@ struct mem_ctl_info *edac_mc_alloc(unsigned mc_num, * rather than an imaginary chunk of memory located at address 0. */ layer = (struct edac_mc_layer *)(((char *)mci) + ((unsigned long)layer)); - for (i = 0; i < n_layers; i++) { - mci->ce_per_layer[i] = (u32 *)((char *)mci + ((unsigned long)ce_per_layer[i])); - mci->ue_per_layer[i] = (u32 *)((char *)mci + ((unsigned long)ue_per_layer[i])); - } pvt = sz_pvt ? (((char *)mci) + ((unsigned long)pvt)) : NULL; /* setup index and various internal pointers */ @@ -903,53 +889,31 @@ const char *edac_layer_name[] = { EXPORT_SYMBOL_GPL(edac_layer_name); static void edac_inc_ce_error(struct mem_ctl_info *mci, - bool enable_per_layer_report, const int pos[EDAC_MAX_LAYERS], const u16 count) { - int i, index = 0; + struct dimm_info *dimm = edac_get_dimm(mci, pos[0], pos[1], pos[2]); mci->ce_mc += count; - if (!enable_per_layer_report) { + if (dimm) + dimm->ce_count += count; + else mci->ce_noinfo_count += count; - return; - } - - for (i = 0; i < mci->n_layers; i++) { - if (pos[i] < 0) - break; - index += pos[i]; - mci->ce_per_layer[i][index] += count; - - if (i < mci->n_layers - 1) - index *= mci->layers[i + 1].size; - } } static void edac_inc_ue_error(struct mem_ctl_info *mci, - bool enable_per_layer_report, const int pos[EDAC_MAX_LAYERS], const u16 count) { - int i, index = 0; + struct dimm_info *dimm = edac_get_dimm(mci, pos[0], pos[1], pos[2]); mci->ue_mc += count; - if (!enable_per_layer_report) { + if (dimm) + dimm->ue_count += count; + else mci->ue_noinfo_count += count; - return; - } - - for (i = 0; i < mci->n_layers; i++) { - if (pos[i] < 0) - break; - index += pos[i]; - mci->ue_per_layer[i][index] += count; - - if (i < mci->n_layers - 1) - index *= mci->layers[i + 1].size; - } } static void edac_ce_error(struct mem_ctl_info *mci, @@ -960,7 +924,6 @@ static void edac_ce_error(struct mem_ctl_info *mci, const char *label, const char *detail, const char *other_detail, - const bool enable_per_layer_report, const unsigned long page_frame_number, const unsigned long offset_in_page, long grain) @@ -983,7 +946,7 @@ static void edac_ce_error(struct mem_ctl_info *mci, error_count, msg, msg_aux, label, location, detail); } - edac_inc_ce_error(mci, enable_per_layer_report, pos, error_count); + edac_inc_ce_error(mci, pos, error_count); if (mci->scrub_mode == SCRUB_SW_SRC) { /* @@ -1013,8 +976,7 @@ static void edac_ue_error(struct mem_ctl_info *mci, const char *location, const char *label, const char *detail, - const char *other_detail, - const bool enable_per_layer_report) + const char *other_detail) { char *msg_aux = ""; @@ -1043,7 +1005,7 @@ static void edac_ue_error(struct mem_ctl_info *mci, msg, msg_aux, label, location, detail); } - edac_inc_ue_error(mci, enable_per_layer_report, pos, error_count); + edac_inc_ue_error(mci, pos, error_count); } void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type, @@ -1059,16 +1021,16 @@ void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type, "page:0x%lx offset:0x%lx grain:%ld syndrome:0x%lx", e->page_frame_number, e->offset_in_page, e->grain, e->syndrome); - edac_ce_error(mci, e->error_count, pos, e->msg, e->location, e->label, - detail, e->other_detail, e->enable_per_layer_report, + edac_ce_error(mci, e->error_count, pos, e->msg, e->location, + e->label, detail, e->other_detail, e->page_frame_number, e->offset_in_page, e->grain); } else { snprintf(detail, sizeof(detail), "page:0x%lx offset:0x%lx grain:%ld", e->page_frame_number, e->offset_in_page, e->grain); - edac_ue_error(mci, e->error_count, pos, e->msg, e->location, e->label, - detail, e->other_detail, e->enable_per_layer_report); + edac_ue_error(mci, e->error_count, pos, e->msg, e->location, + e->label, detail, e->other_detail); } @@ -1094,6 +1056,7 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, int i, n_labels = 0; u8 grain_bits; struct edac_raw_error_desc *e = &mci->error_desc; + bool per_layer_report = false; edac_dbg(3, "MC%d\n", mci->mc_idx); @@ -1111,9 +1074,9 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, /* * Check if the event report is consistent and if the memory - * location is known. If it is known, enable_per_layer_report will be - * true, the DIMM(s) label info will be filled and the per-layer - * error counters will be incremented. + * location is known. If it is known, the DIMM(s) label info + * will be filled and the per-layer error counters will be + * incremented. */ for (i = 0; i < mci->n_layers; i++) { if (pos[i] >= (int)mci->layers[i].size) { @@ -1131,7 +1094,7 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, pos[i] = -1; } if (pos[i] >= 0) - e->enable_per_layer_report = true; + per_layer_report = true; } /* @@ -1160,15 +1123,18 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, if (dimm->grain > e->grain) e->grain = dimm->grain; + if (!per_layer_report) + continue; + /* * If the error is memory-controller wide, there's no need to * seek for the affected DIMMs because the whole * channel/memory controller/... may be affected. * Also, don't show errors for empty DIMM slots. */ - if (e->enable_per_layer_report && dimm->nr_pages) { + if (dimm->nr_pages) { if (n_labels >= EDAC_MAX_LABELS) { - e->enable_per_layer_report = false; + per_layer_report = false; break; } n_labels++; @@ -1199,7 +1165,7 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, } } - if (!e->enable_per_layer_report) { + if (!per_layer_report) { strcpy(e->label, "any memory"); } else { edac_dbg(4, "csrow/channel to increment: (%d,%d)\n", row, chan); diff --git a/drivers/edac/edac_mc_sysfs.c b/drivers/edac/edac_mc_sysfs.c index 75cba0812a16..55357d243fca 100644 --- a/drivers/edac/edac_mc_sysfs.c +++ b/drivers/edac/edac_mc_sysfs.c @@ -557,10 +557,8 @@ static ssize_t dimmdev_ce_count_show(struct device *dev, char *data) { struct dimm_info *dimm = to_dimm(dev); - u32 count; - count = dimm->mci->ce_per_layer[dimm->mci->n_layers-1][dimm->idx]; - return sprintf(data, "%u\n", count); + return sprintf(data, "%u\n", dimm->ce_count); } static ssize_t dimmdev_ue_count_show(struct device *dev, @@ -568,10 +566,8 @@ static ssize_t dimmdev_ue_count_show(struct device *dev, char *data) { struct dimm_info *dimm = to_dimm(dev); - u32 count; - count = dimm->mci->ue_per_layer[dimm->mci->n_layers-1][dimm->idx]; - return sprintf(data, "%u\n", count); + return sprintf(data, "%u\n", dimm->ue_count); } /* dimm/rank attribute files */ @@ -659,7 +655,7 @@ static ssize_t mci_reset_counters_store(struct device *dev, const char *data, size_t count) { struct mem_ctl_info *mci = to_mci(dev); - int cnt, row, chan, i; + int row, chan; mci->ue_mc = 0; mci->ce_mc = 0; mci->ue_noinfo_count = 0; @@ -675,13 +671,6 @@ static ssize_t mci_reset_counters_store(struct device *dev, ri->channels[chan]->ce_count = 0; } - cnt = 1; - for (i = 0; i < mci->n_layers; i++) { - cnt *= mci->layers[i].size; - memset(mci->ce_per_layer[i], 0, cnt * sizeof(u32)); - memset(mci->ue_per_layer[i], 0, cnt * sizeof(u32)); - } - mci->start_time = jiffies; return count; } diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c index fe45392f0c3e..2c8f816c2cc7 100644 --- a/drivers/edac/ghes_edac.c +++ b/drivers/edac/ghes_edac.c @@ -350,11 +350,8 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) mem_err->mem_dev_handle); index = get_dimm_smbios_index(mem_err->mem_dev_handle); - if (index >= 0) { + if (index >= 0) e->top_layer = index; - e->enable_per_layer_report = true; - } - } if (p > e->location) *(p - 1) = '\0'; diff --git a/include/linux/edac.h b/include/linux/edac.h index 20a04f48616c..4dcf075e9dff 100644 --- a/include/linux/edac.h +++ b/include/linux/edac.h @@ -383,6 +383,9 @@ struct dimm_info { unsigned csrow, cschannel; /* Points to the old API data */ u16 smbios_handle; /* Handle for SMBIOS type 17 */ + + u32 ce_count; + u32 ue_count; }; /** @@ -453,8 +456,6 @@ struct errcount_attribute_data { * @location: location of the error * @label: label of the affected DIMM(s) * @other_detail: other driver-specific detail about the error - * @enable_per_layer_report: if false, the error affects all layers - * (typically, a memory controller error) */ struct edac_raw_error_desc { /* @@ -475,7 +476,6 @@ struct edac_raw_error_desc { unsigned long syndrome; const char *msg; const char *other_detail; - bool enable_per_layer_report; }; /* MEMORY controller information structure @@ -565,7 +565,6 @@ struct mem_ctl_info { */ u32 ce_noinfo_count, ue_noinfo_count; u32 ue_mc, ce_mc; - u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS]; struct completion complete; From patchwork Wed May 29 08:44:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 165333 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp9579951ili; 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Signed-off-by: Robert Richter --- drivers/edac/edac_mc.c | 28 +++++++++++++--------------- drivers/edac/edac_mc.h | 2 ++ drivers/edac/ghes_edac.c | 6 +++++- 3 files changed, 20 insertions(+), 16 deletions(-) -- 2.20.1 diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index 2e461c9e1a89..b1bd0a23d02b 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -889,11 +889,9 @@ const char *edac_layer_name[] = { EXPORT_SYMBOL_GPL(edac_layer_name); static void edac_inc_ce_error(struct mem_ctl_info *mci, - const int pos[EDAC_MAX_LAYERS], + struct dimm_info *dimm, const u16 count) { - struct dimm_info *dimm = edac_get_dimm(mci, pos[0], pos[1], pos[2]); - mci->ce_mc += count; if (dimm) @@ -903,11 +901,9 @@ static void edac_inc_ce_error(struct mem_ctl_info *mci, } static void edac_inc_ue_error(struct mem_ctl_info *mci, - const int pos[EDAC_MAX_LAYERS], - const u16 count) + struct dimm_info *dimm, + const u16 count) { - struct dimm_info *dimm = edac_get_dimm(mci, pos[0], pos[1], pos[2]); - mci->ue_mc += count; if (dimm) @@ -917,8 +913,8 @@ static void edac_inc_ue_error(struct mem_ctl_info *mci, } static void edac_ce_error(struct mem_ctl_info *mci, + struct dimm_info *dimm, const u16 error_count, - const int pos[EDAC_MAX_LAYERS], const char *msg, const char *location, const char *label, @@ -946,7 +942,7 @@ static void edac_ce_error(struct mem_ctl_info *mci, error_count, msg, msg_aux, label, location, detail); } - edac_inc_ce_error(mci, pos, error_count); + edac_inc_ce_error(mci, dimm, error_count); if (mci->scrub_mode == SCRUB_SW_SRC) { /* @@ -970,8 +966,8 @@ static void edac_ce_error(struct mem_ctl_info *mci, } static void edac_ue_error(struct mem_ctl_info *mci, + struct dimm_info *dimm, const u16 error_count, - const int pos[EDAC_MAX_LAYERS], const char *msg, const char *location, const char *label, @@ -1005,15 +1001,15 @@ static void edac_ue_error(struct mem_ctl_info *mci, msg, msg_aux, label, location, detail); } - edac_inc_ue_error(mci, pos, error_count); + edac_inc_ue_error(mci, dimm, error_count); } void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type, struct mem_ctl_info *mci, + struct dimm_info *dimm, struct edac_raw_error_desc *e) { char detail[80]; - int pos[EDAC_MAX_LAYERS] = { e->top_layer, e->mid_layer, e->low_layer }; /* Memory type dependent details about the error */ if (type == HW_EVENT_ERR_CORRECTED) { @@ -1021,7 +1017,7 @@ void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type, "page:0x%lx offset:0x%lx grain:%ld syndrome:0x%lx", e->page_frame_number, e->offset_in_page, e->grain, e->syndrome); - edac_ce_error(mci, e->error_count, pos, e->msg, e->location, + edac_ce_error(mci, dimm, e->error_count, e->msg, e->location, e->label, detail, e->other_detail, e->page_frame_number, e->offset_in_page, e->grain); } else { @@ -1029,7 +1025,7 @@ void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type, "page:0x%lx offset:0x%lx grain:%ld", e->page_frame_number, e->offset_in_page, e->grain); - edac_ue_error(mci, e->error_count, pos, e->msg, e->location, + edac_ue_error(mci, dimm, e->error_count, e->msg, e->location, e->label, detail, e->other_detail); } @@ -1206,6 +1202,8 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page, grain_bits, e->syndrome, e->other_detail); - edac_raw_mc_handle_error(type, mci, e); + dimm = edac_get_dimm(mci, top_layer, mid_layer, low_layer); + + edac_raw_mc_handle_error(type, mci, dimm, e); } EXPORT_SYMBOL_GPL(edac_mc_handle_error); diff --git a/drivers/edac/edac_mc.h b/drivers/edac/edac_mc.h index 4165e15995ad..b816cf3caaee 100644 --- a/drivers/edac/edac_mc.h +++ b/drivers/edac/edac_mc.h @@ -214,6 +214,7 @@ extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, * * @type: severity of the error (CE/UE/Fatal) * @mci: a struct mem_ctl_info pointer + * @dimm: a struct dimm_info pointer * @e: error description * * This raw function is used internally by edac_mc_handle_error(). It should @@ -222,6 +223,7 @@ extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, */ void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type, struct mem_ctl_info *mci, + struct dimm_info *dimm, struct edac_raw_error_desc *e); /** diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c index 2c8f816c2cc7..4a13c394fa66 100644 --- a/drivers/edac/ghes_edac.c +++ b/drivers/edac/ghes_edac.c @@ -196,6 +196,7 @@ static void ghes_edac_dmidecode(const struct dmi_header *dh, void *arg) void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) { + struct dimm_info *dimm_info; enum hw_event_mc_err_type type; struct edac_raw_error_desc *e; struct mem_ctl_info *mci; @@ -440,7 +441,10 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page, grain_bits, e->syndrome, pvt->detail_location); - edac_raw_mc_handle_error(type, mci, e); + dimm_info = edac_get_dimm_by_index(mci, e->top_layer); + + edac_raw_mc_handle_error(type, mci, dimm_info, e); + spin_unlock_irqrestore(&ghes_lock, flags); } From patchwork Wed May 29 08:44:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 165344 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp9580601ili; Wed, 29 May 2019 01:45:29 -0700 (PDT) X-Google-Smtp-Source: APXvYqxWrd41InmC/rxfwXj7kZxn+bh5xOQ5g23RON4OTtpPO8XdPVjVlraZ7QVlAmLSiSUF3oYK X-Received: by 2002:a63:43c2:: with SMTP id q185mr27617142pga.280.1559119529247; Wed, 29 May 2019 01:45:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559119529; cv=none; d=google.com; s=arc-20160816; b=ZPzgauIaIWiFMvGa+0l4FshdB+FZCJmgm4AiYJ8qvtlgM8Jp5HZiOPdPD4k7s73gLN Di0fjKOSyWCMOey6z/HC08OAfrRNCdRISNaX0sloLlXO+6SseHO+5Z4s5G6a9vx0gXbm Ho9XKdk8PsHSmR2b5zyn3offjI0NEPbmT2BuU0du75Uj6OsG1T8xGWsHCdGOfqyUmBsy lGpvKp1Xaj+lj7EGYfoeKzNx1nfC4Q5widrPl6TSofycm0Y4qgJ2XLAceW7PuT2V9oVo ROinLaNjrZcp9ISSx9f3Nfy3QgyyenY6kkdDM5ZHj5ha1BYZ4RAwD3SGpatG9xsZZ6Y0 oUJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:cc:to:from:dkim-signature :dkim-signature; bh=8mmEpGetGTGsC8KH3eiVJJd5ql01Z6s/28f7cnxCY4o=; b=vYiw+2VhYtWCvwwcV8aWGzG0SeovF2/lzKYJV3JVjkg9alvEspm9s2xBKpETHmxthT nkqBCOetf9kWYNw6JNi8Vnx6P7rtdjpzc0xb0nrRutLtz+TKO7GgnnLGBBcH6CpFouHi i+dsO1Rb/1j22SXnkOr3qxuyyk+zAEomaUlzNEJTFRAn/bjcs3XRnJNrfBIezPN7CbpH jhIuFIgzOVbB7d4wr4X1hNl6RLTmDgwKWbIJpAtJK3+w2du6G5RAzPsIwYxQF0Gnkvgy ghuQsGa+g91xtbC1CcNyTpt28TIdWkN5KkurAS5lJsddDdQYPrPTDWH/2aVrde3fKYzT QmlQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0818 header.b=ouk4ig5p; dkim=pass header.i=@marvell.onmicrosoft.com header.s=selector2-marvell-onmicrosoft-com header.b=YEqVFC44; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=marvell.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Robert Richter --- drivers/edac/ghes_edac.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.20.1 Reviewed-by: James Morse diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c index 4a13c394fa66..39702bac5eaf 100644 --- a/drivers/edac/ghes_edac.c +++ b/drivers/edac/ghes_edac.c @@ -313,8 +313,8 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) /* Error address */ if (mem_err->validation_bits & CPER_MEM_VALID_PA) { - e->page_frame_number = mem_err->physical_addr >> PAGE_SHIFT; - e->offset_in_page = mem_err->physical_addr & ~PAGE_MASK; + e->page_frame_number = PHYS_PFN(mem_err->physical_addr); + e->offset_in_page = offset_in_page(mem_err->physical_addr); } /* Error grain */ From patchwork Wed May 29 08:44:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 165334 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp9579983ili; Wed, 29 May 2019 01:44:45 -0700 (PDT) X-Google-Smtp-Source: APXvYqwsV4u8bim3Yre88qWeZ0XfbgCFsUCorReGiUTYZmsbgaMTwKWOQoYPVt6pwaEr9PplnDY3 X-Received: by 2002:aa7:880f:: with SMTP id c15mr53373869pfo.100.1559119485534; Wed, 29 May 2019 01:44:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559119485; cv=none; d=google.com; s=arc-20160816; b=g88XWkFpHM7AgfyEvnkgEbiYV02wuKWDi+nOXEPbehhcZk1nJZD9+MOPU6Uk4WCNo6 taPE8LMBXhXnp5Hke70JyPUkZz5H+7zvILgicXlwuApnq3mWWw8ZCHs/m/oUSzGmnKOg 6sE1vdUQe97MWO/G3CJu3x+6EQRKDhiGfpDBFK+PIVF0ui++75ToFC/AAYrI/SbfvwbU gD7bv33vBsAFJxtv8B19D6v36Ywko8Kzuu2aiE2F/GfE3ijZm9B2Z9/DbQhbM2KKLjbv uFStLaMcqdOp1kIzF2vtrcDL1wjF6DZd7gxqW9cjx+LI57ck24pU8/n/Ds3HOx3nN0Au j7tw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:cc:to:from:dkim-signature :dkim-signature; bh=D+Hh1I02195DBSaaVB19Bw/6l1Ypo9lTWFbg/cO3BOM=; b=NngSGTd33hrMj042zTsjs9RoUA/ED4T61Nx/rW5WDv5/B72u0Agscn8MrzHsZM53YV bDOGOZW9IgfkyWlLUgOOrQd5tuykxCjR3d0u0ymgxnVpVcrxjiWfkHQqRwZwQRKlaqQH wHxNlk+dVvovKgxGiX5LIgSxphtel/WrVPZxjmVx1BbAiqhmuMAzT0JJFWE0Z1OGvgyt ChThyKFLUsgiG5cAKKtXe9NUeJ3DW6t+KsM+ebGmRFaI/XVcXw8r694QP9RhZDg5pyGB IGukqpwMyY3Br6ogwoJZ9i49lq/CbmRMpEjlvwYbOwLiVrPKCysSX6S2/agveYqNf80B HxGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0818 header.b="HQFp/8Rh"; dkim=pass header.i=@marvell.onmicrosoft.com header.s=selector2-marvell-onmicrosoft-com header.b=Y9x4sspU; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=marvell.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: HPUbDVvqvHYkKiwxI6UOkB+QXMt1At4nsJjuNs8E9VFi02BGlMGpkObRNNfatPnYItpsHMBjEWoFol2wJ/0rzxnGyqUY6raQRUkq4vP/N/wJaRWBwf1uGOowPa+eiebUJ/36OnSN5qKhBYJGnScdlrUIh4M/zcWBypvqlZL3PXkZXvCMFMiyhk1AspVfWveUUr7EFKjiBAbL1Qs94R9KRh6FAbI2XTBQYWbgnCH7PKbNu+w5HmxR3UM00/THahwX3oEdt2US6hVjNE88E6lbDupyZJq/2xDlFPgW7hu++Swc4TNu8X75/16IrHT8DuWvTH7oIWd8jyN9clQqKZdZfYqP8+Fa+CE7JojnlIqVsCQ7D4Km4UCPDMY406mEp/MZNWuRXE1urdjgtkPpm63a29fdmtaLipJhV8DsvDcUw+0= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: fdb97f67-9b3d-43ec-224b-08d6e411db2a X-MS-Exchange-CrossTenant-originalarrivaltime: 29 May 2019 08:44:26.4914 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: rrichter@marvell.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR18MB3437 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-05-29_05:, , signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The detail_location[] string in struct ghes_edac_pvt is complete useless and data is just copied around. Put everything into e->other_detail from the beginning. Signed-off-by: Robert Richter --- drivers/edac/ghes_edac.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) -- 2.20.1 Reviewed-by: James Morse diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c index 39702bac5eaf..c18f16bc9e4d 100644 --- a/drivers/edac/ghes_edac.c +++ b/drivers/edac/ghes_edac.c @@ -23,8 +23,7 @@ struct ghes_edac_pvt { struct mem_ctl_info *mci; /* Buffers for the error handling routine */ - char detail_location[240]; - char other_detail[160]; + char other_detail[400]; char msg[80]; }; @@ -225,13 +224,14 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) memset(e, 0, sizeof (*e)); e->error_count = 1; strcpy(e->label, "unknown label"); - e->msg = pvt->msg; - e->other_detail = pvt->other_detail; e->top_layer = -1; e->mid_layer = -1; e->low_layer = -1; - *pvt->other_detail = '\0'; + e->msg = pvt->msg; + e->other_detail = pvt->other_detail; + *pvt->msg = '\0'; + *pvt->other_detail = '\0'; switch (sev) { case GHES_SEV_CORRECTED: @@ -359,6 +359,8 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) /* All other fields are mapped on e->other_detail */ p = pvt->other_detail; + p += snprintf(p, sizeof(pvt->other_detail), + "APEI location: %s ", e->location); if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_STATUS) { u64 status = mem_err->error_status; @@ -434,12 +436,11 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) /* Generate the trace event */ grain_bits = fls_long(e->grain); - snprintf(pvt->detail_location, sizeof(pvt->detail_location), - "APEI location: %s %s", e->location, e->other_detail); + trace_mc_event(type, e->msg, e->label, e->error_count, mci->mc_idx, e->top_layer, e->mid_layer, e->low_layer, (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page, - grain_bits, e->syndrome, pvt->detail_location); + grain_bits, e->syndrome, e->other_detail); dimm_info = edac_get_dimm_by_index(mci, e->top_layer); From patchwork Wed May 29 08:44:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 165346 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp9580824ili; Wed, 29 May 2019 01:45:41 -0700 (PDT) X-Google-Smtp-Source: APXvYqyIUJiUKAcjPk46/qddSAMGX/bO7f+WjnTlz1qe+npyWOGyejHJeBITvpLWpicLfdMvuHnk X-Received: by 2002:a62:e217:: with SMTP id a23mr103456255pfi.128.1559119541804; Wed, 29 May 2019 01:45:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559119541; cv=none; d=google.com; s=arc-20160816; b=RbOoVuEJhMGIAPS5reQM+qtMC0dB9GO1rC1aX2G/TyLdR9wBlgjiEd8ekXh5LSwiCY kvX+mcImiKgD792zygcMJVsYZTWA1Qi5AScblmFb1MurqqlRh5VhPWzi9glr6ITArzrp NH3qAHWxQ3reF0OM34D/IL5JM8/38IS7tFC1WChK7JtmnEfAjLw1OycUu5aKdP5jfVYy 7rpLRFJHJZupwAolW7kRRT/nWUWMlWFcA5r6OWSThpKWc8L5cDzP1oTfx0mMaWJH3kuK QTSczTs8B17PLKNj18idpqd4WQ6lwaC/RauVJ3MlVL0w0EfmT5kjIQNFeCdvMHn/DBIv gWxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:cc:to:from:dkim-signature :dkim-signature; bh=nKwZxi1myEspKdU3HROV4Me4eokbwIVj/uTY/R3dhxo=; b=LWr4Atm9458eI2iQl3g/IBQqVWx5YTvYE0tu1YxFFCV7zO2ddEElIx8cYIngyttBgo w9/FP0Dsc5URcGfZt6V/v2z3d2TGjTsVs4Pnyrxpcpyf8ePbP1cVOb1B/Ju6+tH5ty3s C8ZzCLgzrwLl5VvPEm0WTyICGc6WbT8lxHR4uy0nBhoZpUo8eCcvRiyqVKp4bE7TYlpg XuFyhEEc2hyTvpOhrPU8yunwtQGrQ4Ih7Ww2bwc7k1RwhfDS1XebEAC3uTEa1ZKNMKED uYrFgVI7UoVv56RYRw3HFnsefvYG/1j1I6MW9A6zJX4FoaFoEPWfF5Uw0Q8yKf8Zc9mG AOAg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0818 header.b=w3AdXKDR; dkim=pass header.i=@marvell.onmicrosoft.com header.s=selector2-marvell-onmicrosoft-com header.b=eLIH9LfL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=marvell.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Wed, 29 May 2019 08:44:28 +0000 Received: from MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::7c9a:f3bf:fe2e:fe4a]) by MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::7c9a:f3bf:fe2e:fe4a%4]) with mapi id 15.20.1922.021; Wed, 29 May 2019 08:44:28 +0000 From: Robert Richter To: Borislav Petkov , Tony Luck , "James Morse" , Mauro Carvalho Chehab CC: "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Robert Richter Subject: [PATCH 11/21] EDAC, ghes: Unify trace_mc_event() code with edac_mc driver Thread-Topic: [PATCH 11/21] EDAC, ghes: Unify trace_mc_event() code with edac_mc driver Thread-Index: AQHVFfq6gjLVec/X00qyYoFkU9EVEg== Date: Wed, 29 May 2019 08:44:28 +0000 Message-ID: <20190529084344.28562-12-rrichter@marvell.com> References: <20190529084344.28562-1-rrichter@marvell.com> In-Reply-To: <20190529084344.28562-1-rrichter@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM6PR01CA0046.eurprd01.prod.exchangelabs.com (2603:10a6:20b:e0::23) To MN2PR18MB3408.namprd18.prod.outlook.com (2603:10b6:208:16c::25) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.20.1 x-originating-ip: [78.54.13.57] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 5eff7721-877f-4761-eb6a-08d6e411dc6e x-microsoft-antispam: BCL:0; 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FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: oyoSj9ed3P8VMy8lFG/zguykNKkF1mut9QjgzKskcy2fO9/v2Yf7Uc/SpZp1GrcTiN5Y9wOeMJiSQC1ZKvcoTmtdWdfD0Vzth7XaSGZj0jORqmZloU60Jf3yWruyE62uiazvqtp4U2M3gKT+Xy01fRfxu5zgSzGy8KI+VbmmklFoxixH1dVQq6IQMEU0AM14xcOUzEZaSpOjKuemMWLUc2UDXKAAvd+hNcNmEZ4DUuTBhAjne5h/h4YlaEo1D3nuhMJuI4qpNf3gafKCu/ZjZFgS3SlLeyX7B7Tbt3f3DTwzu4Onszw6Rqt4FW8ahFhZjzXZUCRFVxZFVQ5LW3n3bRvP8soIA63loHT9A0muVsGSQEHWLhbKFUtCPk0ZztuuOSckflYCrp35ryyJPTfGQJr7B9XRu3c9zM/a4tqD+QA= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 5eff7721-877f-4761-eb6a-08d6e411dc6e X-MS-Exchange-CrossTenant-originalarrivaltime: 29 May 2019 08:44:28.6169 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: rrichter@marvell.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR18MB3437 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-05-29_05:, , signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Almost duplicate code, remove it. Note: there is a difference in the calculation of the grain_bits, using the edac_mc's version here. Signed-off-by: Robert Richter --- drivers/edac/edac_mc.c | 22 +++++++++++----------- drivers/edac/ghes_edac.c | 9 --------- 2 files changed, 11 insertions(+), 20 deletions(-) -- 2.20.1 diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index b1bd0a23d02b..8613a31dc86c 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -1010,6 +1010,17 @@ void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type, struct edac_raw_error_desc *e) { char detail[80]; + u8 grain_bits; + + /* Report the error via the trace interface */ + grain_bits = fls_long(e->grain) + 1; + + if (IS_ENABLED(CONFIG_RAS)) + trace_mc_event(type, e->msg, e->label, e->error_count, + mci->mc_idx, e->top_layer, e->mid_layer, + e->low_layer, + (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page, + grain_bits, e->syndrome, e->other_detail); /* Memory type dependent details about the error */ if (type == HW_EVENT_ERR_CORRECTED) { @@ -1050,7 +1061,6 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, int row = -1, chan = -1; int pos[EDAC_MAX_LAYERS] = { top_layer, mid_layer, low_layer }; int i, n_labels = 0; - u8 grain_bits; struct edac_raw_error_desc *e = &mci->error_desc; bool per_layer_report = false; @@ -1192,16 +1202,6 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, if (p > e->location) *(p - 1) = '\0'; - /* Report the error via the trace interface */ - grain_bits = fls_long(e->grain) + 1; - - if (IS_ENABLED(CONFIG_RAS)) - trace_mc_event(type, e->msg, e->label, e->error_count, - mci->mc_idx, e->top_layer, e->mid_layer, - e->low_layer, - (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page, - grain_bits, e->syndrome, e->other_detail); - dimm = edac_get_dimm(mci, top_layer, mid_layer, low_layer); edac_raw_mc_handle_error(type, mci, dimm, e); diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c index c18f16bc9e4d..f6ea4b070bfe 100644 --- a/drivers/edac/ghes_edac.c +++ b/drivers/edac/ghes_edac.c @@ -202,7 +202,6 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) struct ghes_edac_pvt *pvt = ghes_pvt; unsigned long flags; char *p; - u8 grain_bits; if (!pvt) return; @@ -434,14 +433,6 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) if (p > pvt->other_detail) *(p - 1) = '\0'; - /* Generate the trace event */ - grain_bits = fls_long(e->grain); - - trace_mc_event(type, e->msg, e->label, e->error_count, - mci->mc_idx, e->top_layer, e->mid_layer, e->low_layer, - (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page, - grain_bits, e->syndrome, e->other_detail); - dimm_info = edac_get_dimm_by_index(mci, e->top_layer); edac_raw_mc_handle_error(type, mci, dimm_info, e); From patchwork Wed May 29 08:44:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 165335 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp9580057ili; Wed, 29 May 2019 01:44:50 -0700 (PDT) X-Google-Smtp-Source: APXvYqweyGP3QWrPLif0Aelx2T5lgWY4gZE78KQK7+rTSjDE5LXNWSbXSUsKnX1qo3R2dOqA2smi X-Received: by 2002:a63:6cc5:: with SMTP id h188mr76528842pgc.105.1559119490535; Wed, 29 May 2019 01:44:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559119490; cv=none; d=google.com; s=arc-20160816; b=NnX6rEbGuSC2Jr6ayhv/NG+LUTHA0ZI+EtfinApyhdl/TXp/HZio774L3V42KZr7iX a1/1Kojp6my4vLoaZz7KdI0Pej/869a2jkY1JkTicGjxj5cHex9Oai31MfmwcOBBLapL LhAKm9T49KsbVf/GlR0maRz3R8Uphw26FO61MzZeJ8vs55UARw0HOIkUsgY+PIWIw4tE eH3PElbqjgbn+azGlPBLHD3b79Pi4+0EDwyKtYhgt2gwe/y/eCOsuM7fqxYQW+NXS6tr 2yVFVza+ejhH6kO+G4c+/tB5nfMJELGf+qxwXsrx15ZYA+egVbuLEZqqT6B8ogTmYLgL DCnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:cc:to:from:dkim-signature :dkim-signature; bh=gH07SKJSQPdDv/5bA0/8ymvQicLgvr2M4038/DDZ8dk=; b=y6by+S8T72AQb3I4GQfOrjI/L/AYq0Y0sa4PEhrysXPTLX1/c6yt4JhY7ZIL9zC50m IvwpfQY8BjPoRz1qxirzyhogP5CA+9RRiZJuY5lNCwwZ6VOJgfTig4pBwWqvXbzRfQEA YTSIzz1h15016/efbP4XWPuCFDcGsc8WcZTHHIGrZ3KHbj3+qYm+QEjRx3UkmK1L/abb IfzXm1QQC+j61kPChRfIH60XAF1Cfl+nn56EIYHFNW0lQwPFiI2Jo0rxpBYeYZvM4K2q qOlJSjgIxijhmUHFl2W4VOO29vH2hA3AwnfiZ/oL3qmabnDTDI5LAJZYnj9Sh5HDu/sM mwew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0818 header.b=NpnlqoVt; dkim=pass header.i=@marvell.onmicrosoft.com header.s=selector2-marvell-onmicrosoft-com header.b=MBUDhLvr; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=marvell.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Wed, 29 May 2019 08:44:31 +0000 Received: from MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::7c9a:f3bf:fe2e:fe4a]) by MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::7c9a:f3bf:fe2e:fe4a%4]) with mapi id 15.20.1922.021; Wed, 29 May 2019 08:44:31 +0000 From: Robert Richter To: Borislav Petkov , Tony Luck , "James Morse" , Mauro Carvalho Chehab CC: "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Robert Richter Subject: [PATCH 12/21] EDAC, ghes: Add support for legacy API counters Thread-Topic: [PATCH 12/21] EDAC, ghes: Add support for legacy API counters Thread-Index: AQHVFfq76DACswz/0kCLO71UP6WlZA== Date: Wed, 29 May 2019 08:44:30 +0000 Message-ID: <20190529084344.28562-13-rrichter@marvell.com> References: <20190529084344.28562-1-rrichter@marvell.com> In-Reply-To: <20190529084344.28562-1-rrichter@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM6PR01CA0046.eurprd01.prod.exchangelabs.com (2603:10a6:20b:e0::23) To MN2PR18MB3408.namprd18.prod.outlook.com (2603:10b6:208:16c::25) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.20.1 x-originating-ip: [78.54.13.57] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 48f98d83-122d-4b5f-9855-08d6e411ddcc x-microsoft-antispam: BCL:0; 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FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 9SzTuwoWv3Pxe8JuELv0nAxIYrMSoVIhI6s8ASrtx7oAtTq9hRunlQeQhACxPjf+7HqPuBvNFPmveXQcqQVx3RcUuskRA+lQWIW1bpGkZLUGy5qIsXBq3E5A0DwWO7B6jzetBrFA15v4720636HueMJ5GibrRyM1tMNp3KqAlGeeZBbbeRD8plEFSIF7rJtHRrd89AuaHC5r/+RRnEZk7CTeXqdMneTtFgcc82niifFI1HnfwQXK8KrIfLDxTmuxtINWOaBEaowua3uBR/sMlA8utDtvO0scMqoLTZ7NjEPwqjNovSgizsCSiuZfypkJYXlpcXUf5JcbcciiR48H5iulYTQKGLHBn2vAfRZn0nh+Y0V6SySZo3msDcAm/KA6owmigQLLm5VgjUqAZ0R6/7BGdIEd8EQyoBFMAet1XEU= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 48f98d83-122d-4b5f-9855-08d6e411ddcc X-MS-Exchange-CrossTenant-originalarrivaltime: 29 May 2019 08:44:30.8855 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: rrichter@marvell.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR18MB3437 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-05-29_05:, , signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ghes driver is not able yet to count legacy API counters in sysfs, e.g.: /sys/devices/system/edac/mc/mc0/csrow2/ce_count /sys/devices/system/edac/mc/mc0/csrow2/ch0_ce_count /sys/devices/system/edac/mc/mc0/csrow2/ch1_ce_count Make counting csrows/channels generic so that the ghes driver can use it too. Signed-off-by: Robert Richter --- drivers/edac/edac_mc.c | 39 ++++++++++++++++++++++----------------- drivers/edac/edac_mc.h | 7 ++++++- drivers/edac/ghes_edac.c | 2 +- 3 files changed, 29 insertions(+), 19 deletions(-) -- 2.20.1 diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index 8613a31dc86c..f7e6a751f309 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -1007,7 +1007,8 @@ static void edac_ue_error(struct mem_ctl_info *mci, void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type, struct mem_ctl_info *mci, struct dimm_info *dimm, - struct edac_raw_error_desc *e) + struct edac_raw_error_desc *e, + int row, int chan) { char detail[80]; u8 grain_bits; @@ -1040,7 +1041,23 @@ void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type, e->label, detail, e->other_detail); } + /* old API's counters */ + if (dimm) { + row = dimm->csrow; + chan = dimm->cschannel; + } + + if (row >= 0) { + if (type == HW_EVENT_ERR_CORRECTED) { + mci->csrows[row]->ce_count += e->error_count; + if (chan >= 0) + mci->csrows[row]->channels[chan]->ce_count += e->error_count; + } else { + mci->csrows[row]->ue_count += e->error_count; + } + } + edac_dbg(4, "csrow/channel to increment: (%d,%d)\n", row, chan); } EXPORT_SYMBOL_GPL(edac_raw_mc_handle_error); @@ -1171,22 +1188,10 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, } } - if (!per_layer_report) { + if (!per_layer_report) strcpy(e->label, "any memory"); - } else { - edac_dbg(4, "csrow/channel to increment: (%d,%d)\n", row, chan); - if (p == e->label) - strcpy(e->label, "unknown memory"); - if (type == HW_EVENT_ERR_CORRECTED) { - if (row >= 0) { - mci->csrows[row]->ce_count += error_count; - if (chan >= 0) - mci->csrows[row]->channels[chan]->ce_count += error_count; - } - } else - if (row >= 0) - mci->csrows[row]->ue_count += error_count; - } + else if (!*e->label) + strcpy(e->label, "unknown memory"); /* Fill the RAM location data */ p = e->location; @@ -1204,6 +1209,6 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, dimm = edac_get_dimm(mci, top_layer, mid_layer, low_layer); - edac_raw_mc_handle_error(type, mci, dimm, e); + edac_raw_mc_handle_error(type, mci, dimm, e, row, chan); } EXPORT_SYMBOL_GPL(edac_mc_handle_error); diff --git a/drivers/edac/edac_mc.h b/drivers/edac/edac_mc.h index b816cf3caaee..c4ddd5c1e24c 100644 --- a/drivers/edac/edac_mc.h +++ b/drivers/edac/edac_mc.h @@ -216,6 +216,10 @@ extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, * @mci: a struct mem_ctl_info pointer * @dimm: a struct dimm_info pointer * @e: error description + * @row: csrow hint if there is no dimm info (<0 if + * unknown) + * @chan: cschannel hint if there is no dimm info (<0 if + * unknown) * * This raw function is used internally by edac_mc_handle_error(). It should * only be called directly when the hardware error come directly from BIOS, @@ -224,7 +228,8 @@ extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type, struct mem_ctl_info *mci, struct dimm_info *dimm, - struct edac_raw_error_desc *e); + struct edac_raw_error_desc *e, + int row, int chan); /** * edac_mc_handle_error() - Reports a memory event to userspace. diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c index f6ea4b070bfe..ea4d53043199 100644 --- a/drivers/edac/ghes_edac.c +++ b/drivers/edac/ghes_edac.c @@ -435,7 +435,7 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) dimm_info = edac_get_dimm_by_index(mci, e->top_layer); - edac_raw_mc_handle_error(type, mci, dimm_info, e); + edac_raw_mc_handle_error(type, mci, dimm_info, e, -1, -1); spin_unlock_irqrestore(&ghes_lock, flags); } From patchwork Wed May 29 08:44:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 165336 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp9580094ili; Wed, 29 May 2019 01:44:53 -0700 (PDT) X-Google-Smtp-Source: APXvYqypqeV0+Noc4jp/y2K5HEWLVv9KfG0dmIN6JSipFQ0be0Ctsx+JJoR1qXueRLayURX5gANS X-Received: by 2002:a65:48c3:: with SMTP id o3mr30225909pgs.351.1559119493251; Wed, 29 May 2019 01:44:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559119493; cv=none; d=google.com; s=arc-20160816; b=W6AO04sHVX3r/ZZEbo6zCptKjIXibA9oPcCENRx+zF2ojlIqAa4PzeqCSpT+pireLv l7BNrwloH/a3cBJleobMl1h6y106JbOWQjZSqG0u7bRqJzMA5hBUE1bSrYY7VW5sBJGz nlm8qUHimFYV42jBw7KIw3KOLby9l7L2B2cM/v6TaTOS5sIJP6euOPhe8VEVfOAVJItj uNdA/43lynOWTMcnCoTIgnzkdKr2nLFz3kb/OgSAsiShxtJ0ZtH6V1hL77kbRLQnHG0F +aar7c2/amrDC+U/VGmqCAL2Rc5JSg+ZVhmP5i+uo9lETVaCk1bS8qVN5Mv3USq3WTLB 5ciA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:cc:to:from:dkim-signature :dkim-signature; bh=yHYwU54umMELZAQMIPMJ37PnFVJnG63kxP1wbyaS+CM=; b=jZQeET17xR4FJ6tqg66mrL9Ef1wkIYyxHdP0Qb8XtnzWmo9BaORBLUvrIqDn85gynJ SeZo+25BXurF/daFuUTqBaawtF8JRX0cStUXoS10bOmI05FFrkwzijXLeHACngJl8kL/ C5XzkCZXGZlmnZ8YH5YJLvzSDXDc7Y9vSjqBF5JubxBcYhgqN5rGQ5J7MhRSaTgocVFx y1WVG0nOwQ7qgqk9eitMkw1p5qDp0/J2ofUIOui6LSPwzrx2n57o6vNorM8P03f1qlpj vRRqHQAHdklTmw8kWbKF2dZ3lj+HhB3ChCK2TqLP2uMWPFyFKXowZiXfvV+kXrbWIk69 vBqg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0818 header.b=OduGwTVW; dkim=pass header.i=@marvell.onmicrosoft.com header.s=selector2-marvell-onmicrosoft-com header.b=THK+d77n; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=marvell.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Wed, 29 May 2019 08:44:33 +0000 Received: from MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::7c9a:f3bf:fe2e:fe4a]) by MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::7c9a:f3bf:fe2e:fe4a%4]) with mapi id 15.20.1922.021; Wed, 29 May 2019 08:44:33 +0000 From: Robert Richter To: Borislav Petkov , Tony Luck , "James Morse" , Mauro Carvalho Chehab CC: "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Robert Richter Subject: [PATCH 13/21] EDAC, ghes: Rework memory hierarchy detection Thread-Topic: [PATCH 13/21] EDAC, ghes: Rework memory hierarchy detection Thread-Index: AQHVFfq8/D/t80TYn0adLRIpgQ6mjA== Date: Wed, 29 May 2019 08:44:32 +0000 Message-ID: <20190529084344.28562-14-rrichter@marvell.com> References: <20190529084344.28562-1-rrichter@marvell.com> In-Reply-To: <20190529084344.28562-1-rrichter@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM6PR01CA0046.eurprd01.prod.exchangelabs.com (2603:10a6:20b:e0::23) To MN2PR18MB3408.namprd18.prod.outlook.com (2603:10b6:208:16c::25) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.20.1 x-originating-ip: [78.54.13.57] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 2743c187-3161-48a1-4158-08d6e411def9 x-microsoft-antispam: BCL:0; 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Rework memory hierarchy detection to make the code extendable for this. The general approach is roughly like: mem_info_setup(); for_each_node(nid) { mci = edac_mc_alloc(nid); mci_add_dimm_info(mci); edac_mc_add_mc(mci); }; This patch introduces mem_info_setup() and mci_add_dimm_info(). All data of the memory hierarchy is collected in a local struct ghes_mem_info. Note: Per (NUMA) node registration will be implemented in a later patch. Signed-off-by: Robert Richter --- drivers/edac/ghes_edac.c | 166 +++++++++++++++++++++++++++++---------- 1 file changed, 126 insertions(+), 40 deletions(-) -- 2.20.1 diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c index ea4d53043199..50f4ee36b755 100644 --- a/drivers/edac/ghes_edac.c +++ b/drivers/edac/ghes_edac.c @@ -67,17 +67,38 @@ struct memdev_dmi_entry { u16 conf_mem_clk_speed; } __attribute__((__packed__)); -struct ghes_edac_dimm_fill { - struct mem_ctl_info *mci; - unsigned count; +struct ghes_dimm_info { + struct dimm_info dimm_info; + int idx; +}; + +struct ghes_mem_info { + int num_dimm; + struct ghes_dimm_info *dimms; }; +struct ghes_mem_info mem_info; + +#define for_each_dimm(dimm) \ + for (dimm = mem_info.dimms; \ + dimm < mem_info.dimms + mem_info.num_dimm; \ + dimm++) + static void ghes_edac_count_dimms(const struct dmi_header *dh, void *arg) { - int *num_dimm = arg; - if (dh->type == DMI_ENTRY_MEM_DEVICE) - (*num_dimm)++; + mem_info.num_dimm++; +} + +static void ghes_dimm_info_init(void) +{ + struct ghes_dimm_info *dimm; + int idx = 0; + + for_each_dimm(dimm) { + dimm->idx = idx; + idx++; + } } static int get_dimm_smbios_index(u16 handle) @@ -94,18 +115,17 @@ static int get_dimm_smbios_index(u16 handle) static void ghes_edac_dmidecode(const struct dmi_header *dh, void *arg) { - struct ghes_edac_dimm_fill *dimm_fill = arg; - struct mem_ctl_info *mci = dimm_fill->mci; - if (dh->type == DMI_ENTRY_MEM_DEVICE) { + int *idx = arg; struct memdev_dmi_entry *entry = (struct memdev_dmi_entry *)dh; - struct dimm_info *dimm = edac_get_dimm(mci, dimm_fill->count, - 0, 0); + struct ghes_dimm_info *mi = &mem_info.dimms[*idx]; + struct dimm_info *dimm = &mi->dimm_info; u16 rdr_mask = BIT(7) | BIT(13); + mi->phys_handle = entry->phys_mem_array_handle; + if (entry->size == 0xffff) { - pr_info("Can't get DIMM%i size\n", - dimm_fill->count); + pr_info("Can't get DIMM%i size\n", mi->idx); dimm->nr_pages = MiB_TO_PAGES(32);/* Unknown */ } else if (entry->size == 0x7fff) { dimm->nr_pages = MiB_TO_PAGES(entry->extended_size); @@ -179,7 +199,7 @@ static void ghes_edac_dmidecode(const struct dmi_header *dh, void *arg) if (dimm->nr_pages) { edac_dbg(1, "DIMM%i: %s size = %d MB%s\n", - dimm_fill->count, edac_mem_types[dimm->mtype], + mi->idx, edac_mem_types[dimm->mtype], PAGES_TO_MiB(dimm->nr_pages), (dimm->edac_mode != EDAC_NONE) ? "(ECC)" : ""); edac_dbg(2, "\ttype %d, detail 0x%02x, width %d(total %d)\n", @@ -189,8 +209,83 @@ static void ghes_edac_dmidecode(const struct dmi_header *dh, void *arg) dimm->smbios_handle = entry->handle; - dimm_fill->count++; + (*idx)++; + } +} + +static int mem_info_setup(void) +{ + int idx = 0; + + memset(&mem_info, 0, sizeof(mem_info)); + + /* Get the number of DIMMs */ + dmi_walk(ghes_edac_count_dimms, NULL); + if (!mem_info.num_dimm) + return -EINVAL; + + mem_info.dimms = kcalloc(mem_info.num_dimm, + sizeof(*mem_info.dimms), GFP_KERNEL); + if (!mem_info.dimms) + return -ENOMEM; + + ghes_dimm_info_init(); + dmi_walk(ghes_edac_dmidecode, &idx); + + return 0; +} + +static int mem_info_setup_fake(void) +{ + struct ghes_dimm_info *ghes_dimm; + struct dimm_info *dimm; + + memset(&mem_info, 0, sizeof(mem_info)); + + ghes_dimm = kzalloc(sizeof(*mem_info.dimms), GFP_KERNEL); + if (!ghes_dimm) + return -ENOMEM; + + mem_info.num_dimm = 1; + mem_info.dimms = ghes_dimm; + + ghes_dimm_info_init(); + + dimm = &ghes_dimm->dimm_info; + dimm->nr_pages = 1; + dimm->grain = 128; + dimm->mtype = MEM_UNKNOWN; + dimm->dtype = DEV_UNKNOWN; + dimm->edac_mode = EDAC_SECDED; + + return 0; +} + +static void mci_add_dimm_info(struct mem_ctl_info *mci) +{ + struct dimm_info *mci_dimm, *dmi_dimm; + struct ghes_dimm_info *dimm; + int index = 0; + + for_each_dimm(dimm) { + dmi_dimm = &dimm->dimm_info; + mci_dimm = edac_get_dimm_by_index(mci, index); + + index++; + if (index > mci->tot_dimms) + break; + + mci_dimm->nr_pages = dmi_dimm->nr_pages; + mci_dimm->mtype = dmi_dimm->mtype; + mci_dimm->edac_mode = dmi_dimm->edac_mode; + mci_dimm->dtype = dmi_dimm->dtype; + mci_dimm->grain = dmi_dimm->grain; + mci_dimm->smbios_handle = dmi_dimm->smbios_handle; } + + if (index != mci->tot_dimms) + pr_warn("Unexpected number of DIMMs: %d (exp. %d)\n", + index, mci->tot_dimms); } void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) @@ -451,10 +546,9 @@ static struct acpi_platform_list plat_list[] = { int ghes_edac_register(struct ghes *ghes, struct device *dev) { bool fake = false; - int rc, num_dimm = 0; + int rc; struct mem_ctl_info *mci; struct edac_mc_layer layers[1]; - struct ghes_edac_dimm_fill dimm_fill; int idx = -1; if (IS_ENABLED(CONFIG_X86)) { @@ -472,22 +566,24 @@ int ghes_edac_register(struct ghes *ghes, struct device *dev) if (atomic_inc_return(&ghes_init) > 1) return 0; - /* Get the number of DIMMs */ - dmi_walk(ghes_edac_count_dimms, &num_dimm); - - /* Check if we've got a bogus BIOS */ - if (num_dimm == 0) { + rc = mem_info_setup(); + if (rc == -EINVAL) { + /* we've got a bogus BIOS */ fake = true; - num_dimm = 1; + rc = mem_info_setup_fake(); + } + if (rc < 0) { + pr_err("Can't allocate memory for DIMM data\n"); + return rc; } layers[0].type = EDAC_MC_LAYER_ALL_MEM; - layers[0].size = num_dimm; + layers[0].size = mem_info.num_dimm; layers[0].is_virt_csrow = true; mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(struct ghes_edac_pvt)); if (!mci) { - pr_info("Can't allocate memory for EDAC data\n"); + pr_err("Can't allocate memory for EDAC data\n"); return -ENOMEM; } @@ -513,26 +609,14 @@ int ghes_edac_register(struct ghes *ghes, struct device *dev) pr_info("So, the end result of using this driver varies from vendor to vendor.\n"); pr_info("If you find incorrect reports, please contact your hardware vendor\n"); pr_info("to correct its BIOS.\n"); - pr_info("This system has %d DIMM sockets.\n", num_dimm); + pr_info("This system has %d DIMM sockets.\n", mem_info.num_dimm); } - if (!fake) { - dimm_fill.count = 0; - dimm_fill.mci = mci; - dmi_walk(ghes_edac_dmidecode, &dimm_fill); - } else { - struct dimm_info *dimm = edac_get_dimm(mci, 0, 0, 0); - - dimm->nr_pages = 1; - dimm->grain = 128; - dimm->mtype = MEM_UNKNOWN; - dimm->dtype = DEV_UNKNOWN; - dimm->edac_mode = EDAC_SECDED; - } + mci_add_dimm_info(mci); rc = edac_mc_add_mc(mci); if (rc < 0) { - pr_info("Can't register at EDAC core\n"); + pr_err("Can't register at EDAC core\n"); edac_mc_free(mci); return -ENODEV; } @@ -549,4 +633,6 @@ void ghes_edac_unregister(struct ghes *ghes) mci = ghes_pvt->mci; edac_mc_del_mc(mci->pdev); edac_mc_free(mci); + + kfree(mem_info.dimms); } From patchwork Wed May 29 08:44:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 165337 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp9580152ili; Wed, 29 May 2019 01:44:57 -0700 (PDT) X-Google-Smtp-Source: APXvYqyO+51P6n0ox6TYfjInnxdCT7OMgZ8nzqClzjL+sel59QbD5tUEKywP67VCLDCxNEFMVMTs X-Received: by 2002:a65:638a:: with SMTP id h10mr69569911pgv.64.1559119496959; Wed, 29 May 2019 01:44:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559119496; cv=none; d=google.com; s=arc-20160816; b=VgaO5LNKqp2GYEQEdldyM5YQGbzYx2hpdFcDgwmrlw0LEtgkxeuo0FTk857NBZ96u4 myfyXE5IDDgJkag+gFuysk1N6rL6iAr0ryvxrhunq3vX3XIeZS87WYbXejRQ5dbSoG1V N8wonTAxH7e55KoeSrHh56dVJEV7homh49NIQVJQGCwhWdqVQUn43K7/P2EvQsHvevNY 4TOGVhlSp47l88CNgJiquUVRT6yet1t/4ttUZSnF1PbLAsAcafDb18GcEWaM1uR2Zhgv zO12DHGQUFRVVOzlMi2Gp24V6WGfdD6U9Ws3Uf64ZyYeVOpE/1RFbRNnbJ3qbJufKOpO hGWw== ARC-Message-Signature: i=1; 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Wed, 29 May 2019 08:44:35 +0000 Received: from MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::7c9a:f3bf:fe2e:fe4a]) by MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::7c9a:f3bf:fe2e:fe4a%4]) with mapi id 15.20.1922.021; Wed, 29 May 2019 08:44:35 +0000 From: Robert Richter To: Borislav Petkov , Tony Luck , "James Morse" , Mauro Carvalho Chehab CC: "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Robert Richter Subject: [PATCH 14/21] EDAC, ghes: Extract numa node information for each dimm Thread-Topic: [PATCH 14/21] EDAC, ghes: Extract numa node information for each dimm Thread-Index: AQHVFfq9sPfT7Zt2PE+R3bvTGIYDig== Date: Wed, 29 May 2019 08:44:35 +0000 Message-ID: <20190529084344.28562-15-rrichter@marvell.com> References: <20190529084344.28562-1-rrichter@marvell.com> In-Reply-To: <20190529084344.28562-1-rrichter@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM6PR01CA0046.eurprd01.prod.exchangelabs.com (2603:10a6:20b:e0::23) To MN2PR18MB3408.namprd18.prod.outlook.com (2603:10b6:208:16c::25) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.20.1 x-originating-ip: [78.54.13.57] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: ac202288-64fa-4567-8f08-08d6e411e036 x-microsoft-antispam: BCL:0; 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FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: oCcwaQG/Xey/h8j1hSSXI/fQ8xAcXr2cpgAnOoNpFKvtN3pgu8FcvsH7YFIdXo0W1zgTCm7eYB+bXPsqV5lnqkDFfqTlAFOv119nG6qpScL7OIMS/QE4Ku0ITLf3avziQ8ITVfOkIR6D0U/Mp7bYLEr7QkOUheDUOBzxJMTMPYyezuFHZweW2ejBhwY/ywWf9bGnkbAwh9hG2wykC6d1GPDPLCN3w4Fw/s0UxA+NWk/1rH9CfM7mrSCawMKZ3HchXm+tQvJ1a0cZaTJ+vE4Tb8JpzyTpmSVBAyIjXoOlg9aa3RB4FJo/zZVHyUuM7juwN2xf25Y4crRhIabVN6eYeqXrvmAx8y3w+oasD7AjyPmDC6VdRpnj//OZyh+C4abObZuVJ0yPMcVuU85N8kTlzZGRbdyRjLpR8oGmYxAhkIA= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: ac202288-64fa-4567-8f08-08d6e411e036 X-MS-Exchange-CrossTenant-originalarrivaltime: 29 May 2019 08:44:35.0325 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: rrichter@marvell.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR18MB3437 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-05-29_05:, , signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In a later patch we want to have one mc device per node. This patch extracts the numa node information for each dimm. This is done by collecting the physical address ranges from the DMI table (Memory Array Mapped Address - Type 19 of SMBIOS spec). The node information for a physical address is already know to a numa aware system (e.g. by using the ACPI _PXM method or the ACPI SRAT table), so based on the PA we can assign the node id to the dimms. A fallback that disables numa is implemented in case the node information is inconsistent. E.g., on a ThunderX2 system the following node mappings are found based on the DMI table: EDAC DEBUG: mem_info_setup: DIMM0: Found mem range [0x0000008800000000-0x0000009ffcffffff] on node 0 EDAC DEBUG: mem_info_setup: DIMM1: Found mem range [0x0000008800000000-0x0000009ffcffffff] on node 0 EDAC DEBUG: mem_info_setup: DIMM2: Found mem range [0x0000008800000000-0x0000009ffcffffff] on node 0 EDAC DEBUG: mem_info_setup: DIMM3: Found mem range [0x0000008800000000-0x0000009ffcffffff] on node 0 EDAC DEBUG: mem_info_setup: DIMM4: Found mem range [0x0000008800000000-0x0000009ffcffffff] on node 0 EDAC DEBUG: mem_info_setup: DIMM5: Found mem range [0x0000008800000000-0x0000009ffcffffff] on node 0 EDAC DEBUG: mem_info_setup: DIMM6: Found mem range [0x0000008800000000-0x0000009ffcffffff] on node 0 EDAC DEBUG: mem_info_setup: DIMM7: Found mem range [0x0000008800000000-0x0000009ffcffffff] on node 0 EDAC DEBUG: mem_info_setup: DIMM8: Found mem range [0x0000009ffd000000-0x000000bffcffffff] on node 1 EDAC DEBUG: mem_info_setup: DIMM9: Found mem range [0x0000009ffd000000-0x000000bffcffffff] on node 1 EDAC DEBUG: mem_info_setup: DIMM10: Found mem range [0x0000009ffd000000-0x000000bffcffffff] on node 1 EDAC DEBUG: mem_info_setup: DIMM11: Found mem range [0x0000009ffd000000-0x000000bffcffffff] on node 1 EDAC DEBUG: mem_info_setup: DIMM12: Found mem range [0x0000009ffd000000-0x000000bffcffffff] on node 1 EDAC DEBUG: mem_info_setup: DIMM13: Found mem range [0x0000009ffd000000-0x000000bffcffffff] on node 1 EDAC DEBUG: mem_info_setup: DIMM14: Found mem range [0x0000009ffd000000-0x000000bffcffffff] on node 1 EDAC DEBUG: mem_info_setup: DIMM15: Found mem range [0x0000009ffd000000-0x000000bffcffffff] on node 1 Signed-off-by: Robert Richter --- drivers/edac/ghes_edac.c | 104 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 103 insertions(+), 1 deletion(-) -- 2.20.1 diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c index 50f4ee36b755..083452a48b42 100644 --- a/drivers/edac/ghes_edac.c +++ b/drivers/edac/ghes_edac.c @@ -67,14 +67,34 @@ struct memdev_dmi_entry { u16 conf_mem_clk_speed; } __attribute__((__packed__)); +/* Memory Array Mapped Address - Type 19 of SMBIOS spec */ +struct memarr_dmi_entry { + u8 type; + u8 length; + u16 handle; + u32 start; + u32 end; + u16 phys_mem_array_handle; + u8 partition_width; + u64 ext_start; + u64 ext_end; +} __attribute__((__packed__)); + struct ghes_dimm_info { struct dimm_info dimm_info; int idx; + int numa_node; + phys_addr_t start; + phys_addr_t end; + u16 phys_handle; }; struct ghes_mem_info { - int num_dimm; + int num_dimm; struct ghes_dimm_info *dimms; + int num_nodes; + int num_per_node[MAX_NUMNODES]; + bool enable_numa; }; struct ghes_mem_info mem_info; @@ -97,10 +117,50 @@ static void ghes_dimm_info_init(void) for_each_dimm(dimm) { dimm->idx = idx; + dimm->numa_node = NUMA_NO_NODE; idx++; } } +static void ghes_edac_set_nid(const struct dmi_header *dh, void *arg) +{ + struct memarr_dmi_entry *entry = (struct memarr_dmi_entry *)dh; + struct ghes_dimm_info *dimm; + phys_addr_t start, end; + int nid; + + if (dh->type != DMI_ENTRY_MEM_ARRAY_MAPPED_ADDR) + return; + + /* only support SMBIOS 2.7+ */ + if (entry->length < sizeof(*entry)) + return; + + if (entry->start == 0xffffffff) + start = entry->ext_start; + else + start = entry->start; + if (entry->end == 0xffffffff) + end = entry->ext_end; + else + end = entry->end; + + if (!pfn_valid(PHYS_PFN(start))) + return; + + nid = pfn_to_nid(PHYS_PFN(start)); + if (nid < 0 || nid >= MAX_NUMNODES || !node_possible(nid)) + nid = NUMA_NO_NODE; + + for_each_dimm(dimm) { + if (entry->phys_mem_array_handle == dimm->phys_handle) { + dimm->numa_node = nid; + dimm->start = start; + dimm->end = end; + } + } +} + static int get_dimm_smbios_index(u16 handle) { struct mem_ctl_info *mci = ghes_pvt->mci; @@ -213,8 +273,25 @@ static void ghes_edac_dmidecode(const struct dmi_header *dh, void *arg) } } +static void mem_info_disable_numa(void) +{ + struct ghes_dimm_info *dimm; + + for_each_dimm(dimm) { + if (dimm->numa_node != NUMA_NO_NODE) + mem_info.num_per_node[dimm->numa_node] = 0; + dimm->numa_node = 0; + } + + mem_info.num_per_node[0] = mem_info.num_dimm; + mem_info.num_nodes = 1; + mem_info.enable_numa = false; +} + static int mem_info_setup(void) { + struct ghes_dimm_info *dimm; + bool enable_numa = true; int idx = 0; memset(&mem_info, 0, sizeof(mem_info)); @@ -231,6 +308,29 @@ static int mem_info_setup(void) ghes_dimm_info_init(); dmi_walk(ghes_edac_dmidecode, &idx); + dmi_walk(ghes_edac_set_nid, NULL); + + for_each_dimm(dimm) { + if (dimm->numa_node == NUMA_NO_NODE) { + enable_numa = false; + } else { + if (!mem_info.num_per_node[dimm->numa_node]) + mem_info.num_nodes++; + mem_info.num_per_node[dimm->numa_node]++; + } + + edac_dbg(1, "DIMM%i: Found mem range [%pa-%pa] on node %d\n", + dimm->idx, &dimm->start, &dimm->end, dimm->numa_node); + } + + mem_info.enable_numa = enable_numa; + if (enable_numa) + return 0; + + /* something went wrong, disable numa */ + if (num_possible_nodes() > 1) + pr_warn("Can't get numa info, disabling numa\n"); + mem_info_disable_numa(); return 0; } @@ -258,6 +358,8 @@ static int mem_info_setup_fake(void) dimm->dtype = DEV_UNKNOWN; dimm->edac_mode = EDAC_SECDED; + mem_info_disable_numa(); + return 0; } From patchwork Wed May 29 08:44:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 165345 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp9580632ili; Wed, 29 May 2019 01:45:31 -0700 (PDT) X-Google-Smtp-Source: APXvYqz18Pat5FEStytoxww4QV/z27txW+tMs17gSzCljrfmWLfHcc7WWEGfBPtVqddLtRwXNzS8 X-Received: by 2002:a63:24c1:: with SMTP id k184mr51208567pgk.120.1559119531473; Wed, 29 May 2019 01:45:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559119531; cv=none; d=google.com; s=arc-20160816; b=NxLyfj7ONukz8JlbOFaD++hjZaEJ8cXik94YPeGmTGWJYCF9bZBGFArbMmzfbRbN2I /j/SqtP1UwjGMeR22/tHxXfUepkNgGiWD9KRgwhS4G4af6v8h01f/gD7dqTXtQUh7EI7 HJBckj2rmdbGfrvrR4TS5FFlEjxYgJC6RXLj42rP70WYu8g674LGSMtDWIV5kUP26sah Zn7za4MKDcSIxAlYGRoRJ5WjUKqs+CuPV3R/YNebRsVwJuMis3v/RINa+bzbmw+4sbXO yAEXTUcUujRl10w6eXJZRZp/iy1oAuy1K+u0fg8gS9qja4GeAW8ZN+TTGCgZGRqNBW0A xyEw== ARC-Message-Signature: i=1; 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Signed-off-by: Robert Richter --- drivers/edac/ghes_edac.c | 97 ++++++++++++++++++++++------------------ 1 file changed, 53 insertions(+), 44 deletions(-) -- 2.20.1 diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c index 083452a48b42..c39cdfdfb8db 100644 --- a/drivers/edac/ghes_edac.c +++ b/drivers/edac/ghes_edac.c @@ -645,45 +645,19 @@ static struct acpi_platform_list plat_list[] = { { } /* End */ }; -int ghes_edac_register(struct ghes *ghes, struct device *dev) +static int +ghes_edac_register_one(int nid, struct ghes *ghes, struct device *parent) { - bool fake = false; int rc; struct mem_ctl_info *mci; struct edac_mc_layer layers[1]; - int idx = -1; - - if (IS_ENABLED(CONFIG_X86)) { - /* Check if safe to enable on this system */ - idx = acpi_match_platform_list(plat_list); - if (!force_load && idx < 0) - return -ENODEV; - } else { - idx = 0; - } - - /* - * We have only one logical memory controller to which all DIMMs belong. - */ - if (atomic_inc_return(&ghes_init) > 1) - return 0; - - rc = mem_info_setup(); - if (rc == -EINVAL) { - /* we've got a bogus BIOS */ - fake = true; - rc = mem_info_setup_fake(); - } - if (rc < 0) { - pr_err("Can't allocate memory for DIMM data\n"); - return rc; - } layers[0].type = EDAC_MC_LAYER_ALL_MEM; layers[0].size = mem_info.num_dimm; layers[0].is_virt_csrow = true; - mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(struct ghes_edac_pvt)); + mci = edac_mc_alloc(nid, ARRAY_SIZE(layers), layers, + sizeof(struct ghes_edac_pvt)); if (!mci) { pr_err("Can't allocate memory for EDAC data\n"); return -ENOMEM; @@ -693,7 +667,7 @@ int ghes_edac_register(struct ghes *ghes, struct device *dev) ghes_pvt->ghes = ghes; ghes_pvt->mci = mci; - mci->pdev = dev; + mci->pdev = parent; mci->mtype_cap = MEM_FLAG_EMPTY; mci->edac_ctl_cap = EDAC_FLAG_NONE; mci->edac_cap = EDAC_FLAG_NONE; @@ -701,19 +675,6 @@ int ghes_edac_register(struct ghes *ghes, struct device *dev) mci->ctl_name = "ghes_edac"; mci->dev_name = "ghes"; - if (fake) { - pr_info("This system has a very crappy BIOS: It doesn't even list the DIMMS.\n"); - pr_info("Its SMBIOS info is wrong. It is doubtful that the error report would\n"); - pr_info("work on such system. Use this driver with caution\n"); - } else if (idx < 0) { - pr_info("This EDAC driver relies on BIOS to enumerate memory and get error reports.\n"); - pr_info("Unfortunately, not all BIOSes reflect the memory layout correctly.\n"); - pr_info("So, the end result of using this driver varies from vendor to vendor.\n"); - pr_info("If you find incorrect reports, please contact your hardware vendor\n"); - pr_info("to correct its BIOS.\n"); - pr_info("This system has %d DIMM sockets.\n", mem_info.num_dimm); - } - mci_add_dimm_info(mci); rc = edac_mc_add_mc(mci); @@ -738,3 +699,51 @@ void ghes_edac_unregister(struct ghes *ghes) kfree(mem_info.dimms); } + +int ghes_edac_register(struct ghes *ghes, struct device *dev) +{ + bool fake = false; + int rc; + int idx = -1; + + if (IS_ENABLED(CONFIG_X86)) { + /* Check if safe to enable on this system */ + idx = acpi_match_platform_list(plat_list); + if (!force_load && idx < 0) + return -ENODEV; + } else { + idx = 0; + } + + /* We have only one ghes instance at a time. */ + if (atomic_inc_return(&ghes_init) > 1) + return 0; + + rc = mem_info_setup(); + if (rc == -EINVAL) { + /* we've got a bogus BIOS */ + fake = true; + rc = mem_info_setup_fake(); + } + if (rc < 0) { + pr_err("Can't allocate memory for DIMM data\n"); + return rc; + } + + if (fake) { + pr_info("This system has a very crappy BIOS: It doesn't even list the DIMMS.\n"); + pr_info("Its SMBIOS info is wrong. It is doubtful that the error report would\n"); + pr_info("work on such system. Use this driver with caution\n"); + } else if (idx < 0) { + pr_info("This EDAC driver relies on BIOS to enumerate memory and get error reports.\n"); + pr_info("Unfortunately, not all BIOSes reflect the memory layout correctly.\n"); + pr_info("So, the end result of using this driver varies from vendor to vendor.\n"); + pr_info("If you find incorrect reports, please contact your hardware vendor\n"); + pr_info("to correct its BIOS.\n"); + pr_info("This system has %d DIMM sockets.\n", mem_info.num_dimm); + } + + rc = ghes_edac_register_one(0, ghes, dev); + + return rc; +} From patchwork Wed May 29 08:44:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 165343 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp9580518ili; Wed, 29 May 2019 01:45:24 -0700 (PDT) X-Google-Smtp-Source: APXvYqxEpAlPCVAxdj214Brq94v26e3lpWnbENY+qGkkZySChOaey1Nn4K80wtwVKvrM4HwvYhnX X-Received: by 2002:a17:90a:f48a:: with SMTP id bx10mr900084pjb.118.1559119524143; Wed, 29 May 2019 01:45:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559119524; cv=none; d=google.com; s=arc-20160816; b=LvpCrrPHXVavf1EmnV8Bip5znFw7BiHb1pDtYorDP+nlFc7O4ESaIwOSv0+jmFRgJY E13D/D3RROcBtZ6xAKFNN0JBpAnZPu1YnUq2slPDorloJsGY6EJEHg3HpAGwQDB6xmEj XMuG71UG0Zq/Cqimx5/CwB7+48jQqaSqfwD34Q+xCOR4L13RZQmQOpah9p9+k7wBS7EB W7emCk5UO9DDeOqk714TCcUBiaK6+gMTknI4aYx6hARKtwKuRTgyS3FVpUNu9QirvVJo OVqvS6H59aypoGiQdjchKYWTSJFSIVw4tknSQVwxl+n8rTiN94ULH2IZP0kJ1SXJzZ2+ bE8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:cc:to:from:dkim-signature :dkim-signature; bh=coTN1R3U1d0hZvMbb9SooRv7f70/WoSqsGqWhWcV3SU=; b=UeJTw2F5pkHfZe2nn75RApb0vt3KKkDMvBcUM7ulBylFXz9npV1JK546RCpgB9swoC BUQWC7CE/iFgr1ZMa/lPnLB552+Sb32L5HhojT3kXFqgJw66enun24FymtST3RFx/e+f cRMasBn4ra/+CVj17Bcfq4+DS4i3m/+dIX+/3P9TPEkyKQERd3SagJ300S0qgcR4dxsr WUJds4rR/I7b/xrVXoSKHzd1JSs8uzcrE7FZAQCF2Px1OZVIbK/CCBQ9I/EmJkATycK3 CyaNja1m+qkBanCtNAz7vD9ZO/pHpHwriwn2FlSFIozgKLZwI8xIgy5PUgoJ+OrBnKjG BSdQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0818 header.b=QRD29DPs; dkim=pass header.i=@marvell.onmicrosoft.com header.s=selector2-marvell-onmicrosoft-com header.b="u0AZY9/Z"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=marvell.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: NXiANgjVcjSkLXNRgho/9DSFhyo48+LgRj6vA7ZL7IpjRIv4qlHM4PJ9IYDtg03Lcv2bYYqDlhaYkbnIpGyFdLj5QJFDT7KmV5tI6cV3Hj+44t4+9WCGsV9sjZr7cpxWL+d2CXXrbH/SYO/+nwrpraweuXXOzddZgz+sFmUGKwFQpSzyi/R2PCcQIj7OIeKUIHDwe7NcHpdMqzooiNAOMY5qur7R+qUQaMJRaEuZ1olJ/pvRuYqatBA0ZJD+7f7sMIkqOklTM1/ePaJ5mrnPxjXfYJO6eSdDPHXJEtiJ1sVCI3F0+sHIZZBmN4k4nuIqTuYHF+/FI6Yw+utKkZWCk9B20bsvwTiPoDokbG9KaP6RpgF7qgQSBmINE3zu9IWaHxg+xXzJWa+PQ0m0J3FzSWizwG9fcSVWWDLoD5n1cI8= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: aa590c18-ac00-49bd-1a43-08d6e411e2a5 X-MS-Exchange-CrossTenant-originalarrivaltime: 29 May 2019 08:44:39.0924 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: rrichter@marvell.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR18MB3437 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-05-29_05:, , signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Typically for most systems, there is one edac memory controller device per node. This patch implements the same for the ghes driver. Now, create multiple mc devices and map the dimms based on the node id. We need at least one node that is used as fallback if no node information is available in the error report. Here a complete and consistent error report from a ThunderX2 system (zero counter values dropped): # find /sys/devices/system/edac/mc/ -name \*count | sort -V | xargs grep . | sed -e '/:0/d' /sys/devices/system/edac/mc/mc0/ce_count:11 /sys/devices/system/edac/mc/mc0/ce_noinfo_count:1 /sys/devices/system/edac/mc/mc0/csrow2/ce_count:5 /sys/devices/system/edac/mc/mc0/csrow2/ch0_ce_count:5 /sys/devices/system/edac/mc/mc0/csrow3/ce_count:3 /sys/devices/system/edac/mc/mc0/csrow3/ch0_ce_count:3 /sys/devices/system/edac/mc/mc0/csrow4/ce_count:2 /sys/devices/system/edac/mc/mc0/csrow4/ch0_ce_count:2 /sys/devices/system/edac/mc/mc0/dimm2/dimm_ce_count:5 /sys/devices/system/edac/mc/mc0/dimm3/dimm_ce_count:3 /sys/devices/system/edac/mc/mc0/dimm4/dimm_ce_count:2 /sys/devices/system/edac/mc/mc1/ce_count:7 /sys/devices/system/edac/mc/mc1/csrow2/ce_count:4 /sys/devices/system/edac/mc/mc1/csrow2/ch0_ce_count:4 /sys/devices/system/edac/mc/mc1/csrow3/ce_count:1 /sys/devices/system/edac/mc/mc1/csrow3/ch0_ce_count:1 /sys/devices/system/edac/mc/mc1/csrow6/ce_count:2 /sys/devices/system/edac/mc/mc1/csrow6/ch0_ce_count:2 /sys/devices/system/edac/mc/mc1/dimm2/dimm_ce_count:4 /sys/devices/system/edac/mc/mc1/dimm3/dimm_ce_count:1 /sys/devices/system/edac/mc/mc1/dimm6/dimm_ce_count:2 Signed-off-by: Robert Richter --- drivers/edac/ghes_edac.c | 126 ++++++++++++++++++++++++++++++++------- 1 file changed, 104 insertions(+), 22 deletions(-) -- 2.20.1 diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c index c39cdfdfb8db..e5fa977bcfd9 100644 --- a/drivers/edac/ghes_edac.c +++ b/drivers/edac/ghes_edac.c @@ -18,6 +18,7 @@ #include struct ghes_edac_pvt { + struct device dev; struct list_head list; struct ghes *ghes; struct mem_ctl_info *mci; @@ -28,7 +29,7 @@ struct ghes_edac_pvt { }; static atomic_t ghes_init = ATOMIC_INIT(0); -static struct ghes_edac_pvt *ghes_pvt; +struct mem_ctl_info *fallback; /* * Sync with other, potentially concurrent callers of @@ -161,15 +162,15 @@ static void ghes_edac_set_nid(const struct dmi_header *dh, void *arg) } } -static int get_dimm_smbios_index(u16 handle) +static int get_dimm_smbios_index(struct mem_ctl_info *mci, u16 handle) { - struct mem_ctl_info *mci = ghes_pvt->mci; struct dimm_info *dimm; mci_for_each_dimm(mci, dimm) { if (dimm->smbios_handle == handle) return dimm->idx; } + return -1; } @@ -370,6 +371,9 @@ static void mci_add_dimm_info(struct mem_ctl_info *mci) int index = 0; for_each_dimm(dimm) { + if (mci->mc_idx != dimm->numa_node) + continue; + dmi_dimm = &dimm->dimm_info; mci_dimm = edac_get_dimm_by_index(mci, index); @@ -390,17 +394,35 @@ static void mci_add_dimm_info(struct mem_ctl_info *mci) index, mci->tot_dimms); } +static struct mem_ctl_info *get_mc_by_node(int nid) +{ + struct mem_ctl_info *mci = edac_mc_find(nid); + + if (mci) + return mci; + + if (num_possible_nodes() > 1) { + edac_mc_printk(fallback, KERN_WARNING, + "Invalid or no node information, falling back to first node: %s", + fallback->dev_name); + } + + return fallback; +} + void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) { struct dimm_info *dimm_info; enum hw_event_mc_err_type type; struct edac_raw_error_desc *e; struct mem_ctl_info *mci; - struct ghes_edac_pvt *pvt = ghes_pvt; + struct ghes_edac_pvt *pvt; unsigned long flags; char *p; + int nid = NUMA_NO_NODE; - if (!pvt) + /* We need at least one mc */ + if (WARN_ON_ONCE(!fallback)) return; /* @@ -413,7 +435,11 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) spin_lock_irqsave(&ghes_lock, flags); - mci = pvt->mci; + /* select the node's mc device */ + if (mem_err->validation_bits & CPER_MEM_VALID_NODE) + nid = mem_err->node; + mci = get_mc_by_node(nid); + pvt = mci->pvt_info; e = &mci->error_desc; /* Cleans the error report buffer */ @@ -546,7 +572,7 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) p += sprintf(p, "DIMM DMI handle: 0x%.4x ", mem_err->mem_dev_handle); - index = get_dimm_smbios_index(mem_err->mem_dev_handle); + index = get_dimm_smbios_index(mci, mem_err->mem_dev_handle); if (index >= 0) e->top_layer = index; } @@ -645,15 +671,29 @@ static struct acpi_platform_list plat_list[] = { { } /* End */ }; +void ghes_edac_release(struct device *dev) +{ + struct ghes_edac_pvt *ghes_pvt; + struct mem_ctl_info *mci; + + ghes_pvt = container_of(dev, struct ghes_edac_pvt, dev); + + mci = ghes_pvt->mci; + edac_mc_del_mc(mci->pdev); + edac_mc_free(mci); +} + static int ghes_edac_register_one(int nid, struct ghes *ghes, struct device *parent) { + struct device *dev; + struct ghes_edac_pvt *ghes_pvt; int rc; struct mem_ctl_info *mci; struct edac_mc_layer layers[1]; layers[0].type = EDAC_MC_LAYER_ALL_MEM; - layers[0].size = mem_info.num_dimm; + layers[0].size = mem_info.num_per_node[nid]; layers[0].is_virt_csrow = true; mci = edac_mc_alloc(nid, ARRAY_SIZE(layers), layers, @@ -667,43 +707,69 @@ ghes_edac_register_one(int nid, struct ghes *ghes, struct device *parent) ghes_pvt->ghes = ghes; ghes_pvt->mci = mci; - mci->pdev = parent; + dev = &ghes_pvt->dev; + dev->parent = parent; + dev->release = ghes_edac_release; + dev_set_name(dev, "ghes_mc%d", nid); + + rc = device_register(dev); + if (rc) { + pr_err("Can't create EDAC device (%d)\n", rc); + goto fail; + } + + mci->pdev = dev; mci->mtype_cap = MEM_FLAG_EMPTY; mci->edac_ctl_cap = EDAC_FLAG_NONE; mci->edac_cap = EDAC_FLAG_NONE; mci->mod_name = "ghes_edac.c"; - mci->ctl_name = "ghes_edac"; - mci->dev_name = "ghes"; + mci->ctl_name = "ghes_mc"; + mci->dev_name = dev_name(dev); mci_add_dimm_info(mci); rc = edac_mc_add_mc(mci); if (rc < 0) { - pr_err("Can't register at EDAC core\n"); - edac_mc_free(mci); - return -ENODEV; + pr_err("Can't register at EDAC core (%d)\n", rc); + goto fail; } + return 0; +fail: + put_device(dev); + return rc; +} + +static void ghes_edac_unregister_one(struct mem_ctl_info *mci) +{ + struct ghes_edac_pvt *pvt = mci->pvt_info; + + put_device(&pvt->dev); } void ghes_edac_unregister(struct ghes *ghes) { struct mem_ctl_info *mci; + int nid; - if (!ghes_pvt) - return; - - mci = ghes_pvt->mci; - edac_mc_del_mc(mci->pdev); - edac_mc_free(mci); + for_each_node(nid) { + mci = edac_mc_find(nid); + /* stop fallback at last */ + if (mci && mci != fallback) + ghes_edac_unregister_one(mci); + } + ghes_edac_unregister_one(fallback); + fallback = NULL; kfree(mem_info.dimms); + atomic_dec(&ghes_init); } int ghes_edac_register(struct ghes *ghes, struct device *dev) { bool fake = false; int rc; + int nid; int idx = -1; if (IS_ENABLED(CONFIG_X86)) { @@ -743,7 +809,23 @@ int ghes_edac_register(struct ghes *ghes, struct device *dev) pr_info("This system has %d DIMM sockets.\n", mem_info.num_dimm); } - rc = ghes_edac_register_one(0, ghes, dev); + for_each_node(nid) { + if (!mem_info.num_per_node[nid]) + continue; - return rc; + rc = ghes_edac_register_one(nid, ghes, dev); + if (rc) { + ghes_edac_unregister(ghes); + return rc; + } + + /* + * use the first node's mc as fallback in case we can + * not detect the node from the error information + */ + if (!fallback) + fallback = edac_mc_find(nid); + } + + return 0; } From patchwork Wed May 29 08:44:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 165338 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp9580196ili; Wed, 29 May 2019 01:45:00 -0700 (PDT) X-Google-Smtp-Source: APXvYqy4ms+718QWPat2QdIFppHszl3DUiYC4CAvJKbJOe+eES2PYxLUwkrTni33dBifQhbawyUN X-Received: by 2002:a17:90a:33c3:: with SMTP id n61mr10397977pjb.7.1559119499993; Wed, 29 May 2019 01:44:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559119499; cv=none; d=google.com; s=arc-20160816; b=AGXmEmdwk1ORPzSEtHPbzbM6fEe2gze4FlddPbfB+kJPqkNdKJFdS1IYc9GSqIva9k ZrVcDgkR7ZKntvuFGB+zHXcEBmWy7sHhpwxEyuGuL/OtBK3tJnYqlC+XDmlNwdKKNne2 iw6sxYge1XzQAVhQxqji+n7KDi20dIL6SNHoWbGqAzT/mjWCFBt4qdeC+2Ld5XJ6/76+ wKa/gxZFB2SXZtqAl+dOeiUv5ip2Z40i027l1jTV1XqdsIR0815Q/vPBHCJfzR+O3p0y belocMxHA7RqgBlSiAnZ8xFyWXO6VvOSWhE/5d6l7k04HoS1EZqA7TI9IavzFYLOfz6S juCg== ARC-Message-Signature: i=1; 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Wed, 29 May 2019 08:44:41 +0000 Received: from MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::7c9a:f3bf:fe2e:fe4a]) by MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::7c9a:f3bf:fe2e:fe4a%4]) with mapi id 15.20.1922.021; Wed, 29 May 2019 08:44:41 +0000 From: Robert Richter To: Borislav Petkov , Tony Luck , "James Morse" , Mauro Carvalho Chehab CC: "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Robert Richter Subject: [PATCH 17/21] EDAC, ghes: Fill sysfs with the DMI DIMM label information Thread-Topic: [PATCH 17/21] EDAC, ghes: Fill sysfs with the DMI DIMM label information Thread-Index: AQHVFfrBkFN+vkv8Z0OsrMgAzX4Eeg== Date: Wed, 29 May 2019 08:44:41 +0000 Message-ID: <20190529084344.28562-18-rrichter@marvell.com> References: <20190529084344.28562-1-rrichter@marvell.com> In-Reply-To: <20190529084344.28562-1-rrichter@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM6PR01CA0046.eurprd01.prod.exchangelabs.com (2603:10a6:20b:e0::23) To MN2PR18MB3408.namprd18.prod.outlook.com (2603:10b6:208:16c::25) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.20.1 x-originating-ip: [78.54.13.57] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 48a9e888-9069-4936-2955-08d6e411e3da x-microsoft-antispam: BCL:0; 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E.g. on a ThunderX2 system we found this now: # grep . /sys/devices/system/edac/mc/mc*/dimm*/dimm_label /sys/devices/system/edac/mc/mc0/dimm0/dimm_label:N0 DIMM_A0 /sys/devices/system/edac/mc/mc0/dimm1/dimm_label:N0 DIMM_B0 /sys/devices/system/edac/mc/mc0/dimm2/dimm_label:N0 DIMM_C0 /sys/devices/system/edac/mc/mc0/dimm3/dimm_label:N0 DIMM_D0 /sys/devices/system/edac/mc/mc0/dimm4/dimm_label:N0 DIMM_E0 /sys/devices/system/edac/mc/mc0/dimm5/dimm_label:N0 DIMM_F0 /sys/devices/system/edac/mc/mc0/dimm6/dimm_label:N0 DIMM_G0 /sys/devices/system/edac/mc/mc0/dimm7/dimm_label:N0 DIMM_H0 /sys/devices/system/edac/mc/mc1/dimm0/dimm_label:N1 DIMM_I0 /sys/devices/system/edac/mc/mc1/dimm1/dimm_label:N1 DIMM_J0 /sys/devices/system/edac/mc/mc1/dimm2/dimm_label:N1 DIMM_K0 /sys/devices/system/edac/mc/mc1/dimm3/dimm_label:N1 DIMM_L0 /sys/devices/system/edac/mc/mc1/dimm4/dimm_label:N1 DIMM_M0 /sys/devices/system/edac/mc/mc1/dimm5/dimm_label:N1 DIMM_N0 /sys/devices/system/edac/mc/mc1/dimm6/dimm_label:N1 DIMM_O0 /sys/devices/system/edac/mc/mc1/dimm7/dimm_label:N1 DIMM_P0 Signed-off-by: Robert Richter --- drivers/edac/ghes_edac.c | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) -- 2.20.1 diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c index e5fa977bcfd9..b8878ff498d1 100644 --- a/drivers/edac/ghes_edac.c +++ b/drivers/edac/ghes_edac.c @@ -254,10 +254,6 @@ static void ghes_edac_dmidecode(const struct dmi_header *dh, void *arg) dimm->dtype = DEV_UNKNOWN; dimm->grain = 128; /* Likely, worse case */ - /* - * FIXME: It shouldn't be hard to also fill the DIMM labels - */ - if (dimm->nr_pages) { edac_dbg(1, "DIMM%i: %s size = %d MB%s\n", mi->idx, edac_mem_types[dimm->mtype], @@ -293,6 +289,7 @@ static int mem_info_setup(void) { struct ghes_dimm_info *dimm; bool enable_numa = true; + const char *bank, *device; int idx = 0; memset(&mem_info, 0, sizeof(mem_info)); @@ -312,6 +309,17 @@ static int mem_info_setup(void) dmi_walk(ghes_edac_set_nid, NULL); for_each_dimm(dimm) { + bank = device = NULL; + dmi_memdev_name(dimm->dimm_info.smbios_handle, + &bank, &device); + if (bank && device) { + snprintf(dimm->dimm_info.label, + sizeof(dimm->dimm_info.label), + "%s %s", bank, device); + } else { + *dimm->dimm_info.label = '\0'; + } + if (dimm->numa_node == NUMA_NO_NODE) { enable_numa = false; } else { @@ -320,8 +328,11 @@ static int mem_info_setup(void) mem_info.num_per_node[dimm->numa_node]++; } - edac_dbg(1, "DIMM%i: Found mem range [%pa-%pa] on node %d\n", - dimm->idx, &dimm->start, &dimm->end, dimm->numa_node); + edac_dbg(1, "DIMM%i: Found mem range [%pa-%pa] on node %d, handle: 0x%.4x%s%s\n", + dimm->idx, &dimm->start, &dimm->end, dimm->numa_node, + dimm->dimm_info.smbios_handle, + *dimm->dimm_info.label ? ", label: " : "", + dimm->dimm_info.label); } mem_info.enable_numa = enable_numa; @@ -387,6 +398,9 @@ static void mci_add_dimm_info(struct mem_ctl_info *mci) mci_dimm->dtype = dmi_dimm->dtype; mci_dimm->grain = dmi_dimm->grain; mci_dimm->smbios_handle = dmi_dimm->smbios_handle; + + if (*dmi_dimm->label) + strcpy(mci_dimm->label, dmi_dimm->label); } if (index != mci->tot_dimms) From patchwork Wed May 29 08:44:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 165339 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp9580240ili; Wed, 29 May 2019 01:45:03 -0700 (PDT) X-Google-Smtp-Source: APXvYqzV/iVqGkQEMsiQH1gpIVfyas4NHoe9E+o2YmG/oCg5/zFcpH911a8z+UqHy7uEVGVqLiJ3 X-Received: by 2002:a17:902:b10f:: with SMTP id q15mr97774519plr.257.1559119503271; Wed, 29 May 2019 01:45:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559119503; cv=none; d=google.com; s=arc-20160816; b=qJKKF/BvIDHZwPKSDj6AV9R6rE4ArZX3WUaWuGKdgvpM+kEx4B+gS+ylVn2Gc2ZMde iIZ9qY/147sOda3VJX1FGiwtTa1XZjlwy86o+c5VopVJ3jxDyKg8q0HoVexuFUDec2iN oRMTXAEvtKAqpxfm7xYDgfkwaLKrS69uyqS3wuF1jn6OXzj8gk8A9OLqfWhjsH/00Pb8 peOx4hfdhrqK62RJ4xLkBfi8szUPqsni2WW65d/N/MpP5P1TesRRuAzOIlMGtpTFzCPr XmnG+X66U7evAF1JIaZB76WNp/cpoTQXpkZ5U1QgzjY2r/2z+Ae0MhEV7jE5nciwuJtL oR0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:cc:to:from:dkim-signature :dkim-signature; bh=P032/2mUDARC0KfBoQ1xOYrSE/a7RwcAnyqNMZPCrIY=; b=yHwNIrBxiOGdVHWwASNwFHdWT2UCxinaY1vULxVdLeD2IyELjvmvuqwMjyj1rBurg2 JV+3XaRLqppcpQNgada/mh9GCtb8Z9wyUdfkAkIMa+EIIKdzXozIEcMQa8xue4Mv45nx iWgAkIWbhe2OEXWUPY/46YfiCfm5FhAKZk72mM6NIcjxB7V452H6mZD1fLT/6qdHHXUa gRK+tIfenN3GFG8Q9Ng3p4AbeJ2tNWTiiiTzOwCTT4m0dYNLp8m2rA8TpBNLSlRwjeYV bSlDpFSu5BwjeK+38ASQtxO6MSpYNmOaqtQa/nf6TZy5xjjibYsd0CmwHlU7u/7RzeoF Ydig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0818 header.b=KjFFaJFJ; dkim=pass header.i=@marvell.onmicrosoft.com header.s=selector2-marvell-onmicrosoft-com header.b=MHkT7WyI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=marvell.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Wed, 29 May 2019 08:44:43 +0000 Received: from MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::7c9a:f3bf:fe2e:fe4a]) by MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::7c9a:f3bf:fe2e:fe4a%4]) with mapi id 15.20.1922.021; Wed, 29 May 2019 08:44:43 +0000 From: Robert Richter To: Borislav Petkov , Tony Luck , "James Morse" , Mauro Carvalho Chehab CC: "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Robert Richter Subject: [PATCH 18/21] EDAC, mc: Introduce edac_mc_alloc_by_dimm() for per dimm allocation Thread-Topic: [PATCH 18/21] EDAC, mc: Introduce edac_mc_alloc_by_dimm() for per dimm allocation Thread-Index: AQHVFfrDZJ6YG32qm0SpPdrScZiSnA== Date: Wed, 29 May 2019 08:44:43 +0000 Message-ID: <20190529084344.28562-19-rrichter@marvell.com> References: <20190529084344.28562-1-rrichter@marvell.com> In-Reply-To: <20190529084344.28562-1-rrichter@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM6PR01CA0046.eurprd01.prod.exchangelabs.com (2603:10a6:20b:e0::23) To MN2PR18MB3408.namprd18.prod.outlook.com (2603:10b6:208:16c::25) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.20.1 x-originating-ip: [78.54.13.57] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: e9fc6991-fcdb-46fd-175d-08d6e411e549 x-microsoft-antispam: BCL:0; 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Compared to other memory controller drivers the total size of each layer is unknown (card/module, channel/slot, etc.). But there is the total number of dimms. So add a function to allocate an mc device this way. The edac's driver uses internally a dimm index already for data access. Signed-off-by: Robert Richter --- drivers/edac/edac_mc.c | 83 ++++++++++++++++++++++++++++------------ drivers/edac/edac_mc.h | 17 ++++++-- drivers/edac/ghes_edac.c | 7 ++-- 3 files changed, 76 insertions(+), 31 deletions(-) -- 2.20.1 diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index f7e6a751f309..bdeb9fd08249 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -303,10 +303,11 @@ static void _edac_mc_free(struct mem_ctl_info *mci) kfree(mci); } -struct mem_ctl_info *edac_mc_alloc(unsigned mc_num, - unsigned n_layers, - struct edac_mc_layer *layers, - unsigned sz_pvt) +struct mem_ctl_info *__edac_mc_alloc(unsigned mc_num, + unsigned dimm_num, + unsigned n_layers, + struct edac_mc_layer *layers, + unsigned sz_pvt) { struct mem_ctl_info *mci; struct edac_mc_layer *layer; @@ -321,6 +322,7 @@ struct mem_ctl_info *edac_mc_alloc(unsigned mc_num, bool per_rank = false; BUG_ON(n_layers > EDAC_MAX_LAYERS || n_layers == 0); + /* * Calculate the total amount of dimms and csrows/cschannels while * in the old API emulation mode @@ -336,6 +338,26 @@ struct mem_ctl_info *edac_mc_alloc(unsigned mc_num, per_rank = true; } + /* allocate dimm_num DIMMS, layer size must be zero */ + if (dimm_num) { + if (dimm_num <= 0 || + layers[0].size || + (n_layers > 1 && layers[1].size) || + (n_layers > 2 && layers[2].size)) { + edac_printk(KERN_WARNING, EDAC_MC, + "invalid layer data\n"); + return NULL; + } + + /* + * Assume 1 csrow per dimm which also means 1 channel + * per csrow. + */ + tot_dimms = dimm_num; + tot_csrows = dimm_num; + tot_channels = 1; + } + /* Figure out the offsets of the various items from the start of an mc * structure. We want the alignment of each item to be at least as * stringent as what the compiler would provide if we could simply @@ -422,25 +444,10 @@ struct mem_ctl_info *edac_mc_alloc(unsigned mc_num, dimm->mci = mci; dimm->idx = idx; - /* - * Copy DIMM location and initialize it. - */ - len = sizeof(dimm->label); - p = dimm->label; - n = snprintf(p, len, "mc#%u", mc_num); - p += n; - len -= n; - for (j = 0; j < n_layers; j++) { - n = snprintf(p, len, "%s#%u", - edac_layer_name[layers[j].type], - pos[j]); - p += n; - len -= n; - dimm->location[j] = pos[j]; - - if (len <= 0) - break; - } + /* unknown location */ + dimm->location[0] = -1; + dimm->location[1] = -1; + dimm->location[2] = -1; /* Link it to the csrows old API data */ chan->dimm = dimm; @@ -462,6 +469,34 @@ struct mem_ctl_info *edac_mc_alloc(unsigned mc_num, } } + /* + * Copy DIMM location and initialize it. + */ + len = sizeof(dimm->label); + p = dimm->label; + n = snprintf(p, len, "mc#%u", mc_num); + p += n; + len -= n; + + if (dimm_num) { + n = snprintf(p, len, "dimm#%u", idx); + p += n; + len -= n; + continue; + } + + for (j = 0; j < n_layers; j++) { + n = snprintf(p, len, "%s#%u", + edac_layer_name[layers[j].type], + pos[j]); + p += n; + len -= n; + dimm->location[j] = pos[j]; + + if (len <= 0) + break; + } + /* Increment dimm location */ for (j = n_layers - 1; j >= 0; j--) { pos[j]++; @@ -480,7 +515,7 @@ struct mem_ctl_info *edac_mc_alloc(unsigned mc_num, return NULL; } -EXPORT_SYMBOL_GPL(edac_mc_alloc); +EXPORT_SYMBOL_GPL(__edac_mc_alloc); void edac_mc_free(struct mem_ctl_info *mci) { diff --git a/drivers/edac/edac_mc.h b/drivers/edac/edac_mc.h index c4ddd5c1e24c..e8215847f853 100644 --- a/drivers/edac/edac_mc.h +++ b/drivers/edac/edac_mc.h @@ -99,6 +99,10 @@ do { \ * edac_mc_alloc() - Allocate and partially fill a struct &mem_ctl_info. * * @mc_num: Memory controller number + * @dimm_num: Number of DIMMs to allocate. If non-zero the + * @layers' size parameter must be zero. Useful + * if the MC hierarchy is unknown but the number + * of DIMMs is known. * @n_layers: Number of MC hierarchy layers * @layers: Describes each layer as seen by the Memory Controller * @sz_pvt: size of private storage needed @@ -122,10 +126,15 @@ do { \ * On success, return a pointer to struct mem_ctl_info pointer; * %NULL otherwise */ -struct mem_ctl_info *edac_mc_alloc(unsigned mc_num, - unsigned n_layers, - struct edac_mc_layer *layers, - unsigned sz_pvt); +struct mem_ctl_info *__edac_mc_alloc(unsigned mc_num, + unsigned dimm_num, + unsigned n_layers, + struct edac_mc_layer *layers, + unsigned sz_pvt); +#define edac_mc_alloc(mc_num, n_layers, layers, sz_pvt) \ + __edac_mc_alloc(mc_num, 0, n_layers, layers, sz_pvt) +#define edac_mc_alloc_by_dimm(mc_num, dimm_num, n_layers, layers, sz_pvt) \ + __edac_mc_alloc(mc_num, dimm_num, n_layers, layers, sz_pvt) /** * edac_get_owner - Return the owner's mod_name of EDAC MC diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c index b8878ff498d1..4bac643d3404 100644 --- a/drivers/edac/ghes_edac.c +++ b/drivers/edac/ghes_edac.c @@ -707,11 +707,12 @@ ghes_edac_register_one(int nid, struct ghes *ghes, struct device *parent) struct edac_mc_layer layers[1]; layers[0].type = EDAC_MC_LAYER_ALL_MEM; - layers[0].size = mem_info.num_per_node[nid]; + layers[0].size = 0; layers[0].is_virt_csrow = true; - mci = edac_mc_alloc(nid, ARRAY_SIZE(layers), layers, - sizeof(struct ghes_edac_pvt)); + mci = edac_mc_alloc_by_dimm(nid, mem_info.num_per_node[nid], + ARRAY_SIZE(layers), layers, + sizeof(struct ghes_edac_pvt)); if (!mci) { pr_err("Can't allocate memory for EDAC data\n"); return -ENOMEM; From patchwork Wed May 29 08:44:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 165342 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp9580449ili; Wed, 29 May 2019 01:45:18 -0700 (PDT) X-Google-Smtp-Source: APXvYqwB1bVfAktLyAayfBEVQxdIQmq7SfzJp02fsORwx5yNwsstBsO8+W/0yRe0+ZZdXCg//9hZ X-Received: by 2002:a17:902:ac82:: with SMTP id h2mr80604535plr.303.1559119518819; Wed, 29 May 2019 01:45:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559119518; cv=none; d=google.com; s=arc-20160816; b=ANFFXRFHFLc9kLRYDvYhMWS/CWhLtCXlytG+eCbUMBwFvNj/f0BWiVESAYiDtqqIP3 bUedyUOWPtAAxXwMBP+ouXfYGosPj/T/ub7AS1BuQWuchIqRnxpU1T7pAXUtWXnvfaW3 x+WxSqfTtVJVcy8POmA/6HzZzWDbubaScpmEi9ocku9DTgQoxaWEBo1n6k43tfhJAkV1 NAP5BtFjHawdLzn66omI/7hVvtRgEwl3+nMs9Qdf8mpv+fsjQSpWwBQkhWrak3rHBOCl Iu4ACApNJgOeEUD88NmcdcaNM9VaBhs5L/oDs2IErifpXiT72gvNtqa4dTPzRxm8cWG3 vXDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:cc:to:from:dkim-signature :dkim-signature; bh=GUy40+DnrF6OKmv6P4tIQfRAjMx1FBjH2O7IeBlDwQA=; b=SxbHtWqHugFczT6NsQruSjYuJni4qE9kRbX+MlCKXbwVksnQvJs7xPDUgxRLreNp47 cZNKbymqXtuvu0fUWaOqJK25tx+7c0vdNcxk6EsQScIdQJ6tlK1YyJHRzqrVeOqXInuH /jIiDZi/FIkbzPZghZbE2hAbVTOps5ivIDImwfzz8/MogM0JKBKLJHYrvHLsGx68cZKH /eDlSw7KecKVprsR1aw5VOCqY6bihJQHrwS4Bhnp0Qf/qzf88Ilx0utNhQ2ROmgrguB9 S9SI4VeWzIXTvYzBn1ROyJTtgA0CKkEABvAn/nCA4oVderotgiVotJUFO1B7ID2LYJ+M mVjg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0818 header.b=AMUvekIg; dkim=pass header.i=@marvell.onmicrosoft.com header.s=selector2-marvell-onmicrosoft-com header.b=mAGOAFym; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=marvell.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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A module handle is used to map it to the dimms listed in the dmi table. Collect all those data from the error record and select the dimm accordingly. Inconsistent error records will be reported which is the case if the same dimm handle reports errors with different node, card or module. The change allows to enable per-layer reporting based on node, card and module in the next patch. Signed-off-by: Robert Richter --- drivers/edac/ghes_edac.c | 74 +++++++++++++++++++++++++++++++++------- 1 file changed, 62 insertions(+), 12 deletions(-) -- 2.20.1 diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c index 4bac643d3404..07c847ed7315 100644 --- a/drivers/edac/ghes_edac.c +++ b/drivers/edac/ghes_edac.c @@ -83,8 +83,11 @@ struct memarr_dmi_entry { struct ghes_dimm_info { struct dimm_info dimm_info; + struct dimm_info *dimm; int idx; int numa_node; + int card; + int module; phys_addr_t start; phys_addr_t end; u16 phys_handle; @@ -119,6 +122,8 @@ static void ghes_dimm_info_init(void) for_each_dimm(dimm) { dimm->idx = idx; dimm->numa_node = NUMA_NO_NODE; + dimm->card = -1; + dimm->module = -1; idx++; } } @@ -401,6 +406,13 @@ static void mci_add_dimm_info(struct mem_ctl_info *mci) if (*dmi_dimm->label) strcpy(mci_dimm->label, dmi_dimm->label); + + /* + * From here on do not use any longer &dimm.dimm_info. + * Instead switch to the mci's dimm info which might + * contain updated data, such as the label. + */ + dimm->dimm = mci_dimm; } if (index != mci->tot_dimms) @@ -408,24 +420,46 @@ static void mci_add_dimm_info(struct mem_ctl_info *mci) index, mci->tot_dimms); } -static struct mem_ctl_info *get_mc_by_node(int nid) +/* Requires ghes_lock being set. */ +static struct ghes_dimm_info * +get_and_prepare_dimm_info(int nid, int card, int module, int handle) { - struct mem_ctl_info *mci = edac_mc_find(nid); + static struct ghes_dimm_info *dimm; + struct dimm_info *di; - if (mci) - return mci; + /* + * We require smbios_handle being set in the error report for + * per layer reporting (SMBIOS handle for the Type 17 Memory + * Device Structure that represents the Memory Module) + */ + for_each_dimm(dimm) { + di = dimm->dimm; + if (di->smbios_handle == handle) + goto found; + } - if (num_possible_nodes() > 1) { - edac_mc_printk(fallback, KERN_WARNING, - "Invalid or no node information, falling back to first node: %s", - fallback->dev_name); + return NULL; +found: + if (dimm->card < 0 && card >= 0) + dimm->card = card; + if (dimm->module < 0 && module >= 0) + dimm->module = module; + + if ((num_possible_nodes() > 1 && di->mci->mc_idx != nid) || + (card >= 0 && card != dimm->card) || + (module >= 0 && module != dimm->module)) { + edac_mc_printk(di->mci, KERN_WARNING, + "Inconsistent error report (nid/card/module): %d/%d/%d (dimm%d: %d/%d/%d)", + nid, card, module, di->idx, + di->mci->mc_idx, dimm->card, dimm->module); } - return fallback; + return dimm; } void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) { + struct ghes_dimm_info *dimm; struct dimm_info *dimm_info; enum hw_event_mc_err_type type; struct edac_raw_error_desc *e; @@ -434,6 +468,9 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) unsigned long flags; char *p; int nid = NUMA_NO_NODE; + int card = -1; + int module = -1; + int handle = -1; /* We need at least one mc */ if (WARN_ON_ONCE(!fallback)) @@ -449,10 +486,23 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) spin_lock_irqsave(&ghes_lock, flags); - /* select the node's mc device */ if (mem_err->validation_bits & CPER_MEM_VALID_NODE) nid = mem_err->node; - mci = get_mc_by_node(nid); + if (mem_err->validation_bits & CPER_MEM_VALID_CARD) + card = mem_err->card; + if (mem_err->validation_bits & CPER_MEM_VALID_MODULE) + module = mem_err->module; + if (mem_err->validation_bits & CPER_MEM_VALID_MODULE_HANDLE) + handle = mem_err->mem_dev_handle; + + dimm = get_and_prepare_dimm_info(nid, card, module, handle); + if (dimm) + mci = dimm->dimm->mci; + else + mci = edac_mc_find(nid); + if (!mci) + mci = fallback; + pvt = mci->pvt_info; e = &mci->error_desc; @@ -670,7 +720,7 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) if (p > pvt->other_detail) *(p - 1) = '\0'; - dimm_info = edac_get_dimm_by_index(mci, e->top_layer); + dimm_info = dimm ? dimm->dimm : NULL; edac_raw_mc_handle_error(type, mci, dimm_info, e, -1, -1); From patchwork Wed May 29 08:44:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 165340 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp9580286ili; Wed, 29 May 2019 01:45:05 -0700 (PDT) X-Google-Smtp-Source: APXvYqxsINNrP0KhbGvrMq06Lx1C6LYQ/MDTtzGxz4JMvgYcCysnQB8EdHiSXeNIVQNF/k/CxpyP X-Received: by 2002:a17:90a:2401:: with SMTP id h1mr10532529pje.123.1559119505625; Wed, 29 May 2019 01:45:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559119505; cv=none; d=google.com; s=arc-20160816; b=oDdLQ0GW4eRHz3hhQSWfVtNwxJp4yGOb+gzJwIMTTvFs5TWpOvLCTyYVBxxIAFrdTV XMK7J+pppcJ8ozQ+G9TFveOn4KowUc9xm7CXU5EBebdvn+0tRyKV7JRFJiPkXyH8EQJD /jhEjXazRcJjR8W3FzChyxe6ScWXAs7SMj5xdCqYLs2y0r+aJneBzDQvYb/fSz7bHp4O nwZP1JBeCQesGfh1cetpr5aeabJrGYaY5BM6wn/olzZIRlk/5W2f79zuc6mUu3KdG+rZ kN82Nis0ms3F8YZoP3+zapfHij6K/iCLrAcMSdmIQREK4v7K33d+3bnD94Ae7ncEoZLS CtuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:cc:to:from:dkim-signature :dkim-signature; bh=dpQEqX+Tz0FmEJnIkWCsiP+ALItrYn6fkOWFHNnuN6I=; b=0TntxSV+z6GoU7Z6C/Q4Y+CrfJGWMwyTQP+UdalHOJqCprvEMDO8dGThJhCqiMMtJJ DJVolWm/4f3/UKqIZVaPyCZRDiBH2qFVPfDQzB2wIIfJAQr5wsEOwNoRVZrVEJlZHuYw 8pelKwSWyphYoO5MEitSJJMoDCsnfGCTKWQh8oadnxnpYXITfhohD+6d9HazQSkDNi40 i+EjxhjsMl2hi/oON5Qa/UcuRyCytRWgeDHk+rReM+PwwSnEnCBDNfmWOw4iMjLGCTvi gBGn2kcTpJFMORdOU4dv+fusXQFVkV1DKGlakoJ54s6p6YcKV9K7WYe26jWAPJD/L5tq C14A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0818 header.b=LK58nhB4; dkim=pass header.i=@marvell.onmicrosoft.com header.s=selector2-marvell-onmicrosoft-com header.b=RkXgIgXX; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=marvell.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Wed, 29 May 2019 08:44:48 +0000 Received: from MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::7c9a:f3bf:fe2e:fe4a]) by MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::7c9a:f3bf:fe2e:fe4a%4]) with mapi id 15.20.1922.021; Wed, 29 May 2019 08:44:48 +0000 From: Robert Richter To: Borislav Petkov , Tony Luck , "James Morse" , Mauro Carvalho Chehab CC: "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Robert Richter Subject: [PATCH 20/21] EDAC, ghes: Enable per-layer reporting based on card/module Thread-Topic: [PATCH 20/21] EDAC, ghes: Enable per-layer reporting based on card/module Thread-Index: AQHVFfrFZJH+3Ckua0Ku/1mj0fm9LA== Date: Wed, 29 May 2019 08:44:47 +0000 Message-ID: <20190529084344.28562-21-rrichter@marvell.com> References: <20190529084344.28562-1-rrichter@marvell.com> In-Reply-To: <20190529084344.28562-1-rrichter@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM6PR01CA0046.eurprd01.prod.exchangelabs.com (2603:10a6:20b:e0::23) To MN2PR18MB3408.namprd18.prod.outlook.com (2603:10b6:208:16c::25) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.20.1 x-originating-ip: [78.54.13.57] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: e12dfd8d-1c96-405b-9c9f-08d6e411e7e3 x-microsoft-antispam: BCL:0; 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A dimm can be uniquely identified by those 3 identifiers. The mc device is selected by the node id. Thus, each ghes edac memory controller device has a 2-dimensional layer hierarchy based on card and module in the same way as most other driver have. An error log looks as follows now: [ 8902.592060] {4}[Hardware Error]: Error 6, type: corrected [ 8902.597534] {4}[Hardware Error]: section_type: memory error [ 8902.603267] {4}[Hardware Error]: error_status: 0x0000000000000400 [ 8902.609522] {4}[Hardware Error]: physical_address: 0x000000b3bb7d3000 [ 8902.616126] {4}[Hardware Error]: node: 1 card: 3 module: 0 rank: 1 bank: 771 column: 14 bit_position: 16 [ 8902.625854] {4}[Hardware Error]: DIMM location: N1 DIMM_L0 [ 8902.807783] EDAC MC1: 1 CE ghes_mc on N1 DIMM_L0 (card:3 module:0 page:0xb3bb7d3 offset:0x0 grain:0 syndrome:0x0 - APEI location: node:1 card:3 module:0 rank:1 bank:771 col:14 bit_pos:16 handle:0x0052 status(0x0000000000000400): Storage error in DRAM memory) GHES error reports are now similar to edac_mc reports. This patch moves common code of ghes and edac_mc to edac_raw_mc_handle_error(). Signed-off-by: Robert Richter --- drivers/edac/edac_mc.c | 45 ++++++++++++++---------- drivers/edac/ghes_edac.c | 76 ++++++++++++++++++---------------------- include/linux/edac.h | 2 ++ 3 files changed, 63 insertions(+), 60 deletions(-) -- 2.20.1 diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index bdeb9fd08249..c159bb3c77e0 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -915,11 +915,13 @@ int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, unsigned long page) EXPORT_SYMBOL_GPL(edac_mc_find_csrow_by_page); const char *edac_layer_name[] = { - [EDAC_MC_LAYER_BRANCH] = "branch", - [EDAC_MC_LAYER_CHANNEL] = "channel", - [EDAC_MC_LAYER_SLOT] = "slot", - [EDAC_MC_LAYER_CHIP_SELECT] = "csrow", - [EDAC_MC_LAYER_ALL_MEM] = "memory", + [EDAC_MC_LAYER_BRANCH] = "branch", + [EDAC_MC_LAYER_CHANNEL] = "channel", + [EDAC_MC_LAYER_SLOT] = "slot", + [EDAC_MC_LAYER_CHIP_SELECT] = "csrow", + [EDAC_MC_LAYER_ALL_MEM] = "memory", + [EDAC_MC_LAYER_CARD] = "card", + [EDAC_MC_LAYER_MODULE] = "module", }; EXPORT_SYMBOL_GPL(edac_layer_name); @@ -1046,7 +1048,26 @@ void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type, int row, int chan) { char detail[80]; + int idx; + int pos[EDAC_MAX_LAYERS] = { e->top_layer, e->mid_layer, + e->low_layer }; u8 grain_bits; + char *p; + + /* Fill the RAM location data */ + p = e->location; + + for (idx = 0; idx < mci->n_layers; idx++) { + if (pos[idx] < 0) + continue; + + p += sprintf(p, "%s:%d ", + edac_layer_name[mci->layers[idx].type], + pos[idx]); + } + + if (p > e->location) + *(p - 1) = '\0'; /* Report the error via the trace interface */ grain_bits = fls_long(e->grain) + 1; @@ -1228,20 +1249,6 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, else if (!*e->label) strcpy(e->label, "unknown memory"); - /* Fill the RAM location data */ - p = e->location; - - for (i = 0; i < mci->n_layers; i++) { - if (pos[i] < 0) - continue; - - p += sprintf(p, "%s:%d ", - edac_layer_name[mci->layers[i].type], - pos[i]); - } - if (p > e->location) - *(p - 1) = '\0'; - dimm = edac_get_dimm(mci, top_layer, mid_layer, low_layer); edac_raw_mc_handle_error(type, mci, dimm, e, row, chan); diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c index 07c847ed7315..67e962159653 100644 --- a/drivers/edac/ghes_edac.c +++ b/drivers/edac/ghes_edac.c @@ -167,18 +167,6 @@ static void ghes_edac_set_nid(const struct dmi_header *dh, void *arg) } } -static int get_dimm_smbios_index(struct mem_ctl_info *mci, u16 handle) -{ - struct dimm_info *dimm; - - mci_for_each_dimm(mci, dimm) { - if (dimm->smbios_handle == handle) - return dimm->idx; - } - - return -1; -} - static void ghes_edac_dmidecode(const struct dmi_header *dh, void *arg) { if (dh->type == DMI_ENTRY_MEM_DEVICE) { @@ -506,10 +494,12 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) pvt = mci->pvt_info; e = &mci->error_desc; + edac_dbg(3, "MC%d\n", mci->mc_idx); + /* Cleans the error report buffer */ memset(e, 0, sizeof (*e)); + e->error_count = 1; - strcpy(e->label, "unknown label"); e->top_layer = -1; e->mid_layer = -1; e->low_layer = -1; @@ -519,6 +509,25 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) *pvt->msg = '\0'; *pvt->other_detail = '\0'; + if (dimm) { + /* The DIMM could be identified. */ + e->top_layer = dimm->card; + e->mid_layer = dimm->module; + strcpy(e->label, dimm->dimm->label); + } else if (nid >= 0 || card >= 0 || module >= 0 || handle >= 0) { + /* + * We have at least some information and can do a + * per-layer reporting, but the exact location is + * unknown. + */ + e->top_layer = card; + e->mid_layer = module; + strcpy(e->label, "unknown memory"); + } else { + /* No error location at all. */ + strcpy(e->label, "any memory"); + } + switch (sev) { case GHES_SEV_CORRECTED: type = HW_EVENT_ERR_CORRECTED; @@ -538,8 +547,10 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) (long long)mem_err->validation_bits); /* Error type, mapped on e->msg */ + p = pvt->msg; + p += sprintf(p, "%s", mci->ctl_name); if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_TYPE) { - p = pvt->msg; + p += sprintf(p, ": "); switch (mem_err->error_type) { case 0: p += sprintf(p, "Unknown"); @@ -593,8 +604,6 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) p += sprintf(p, "reserved error (%d)", mem_err->error_type); } - } else { - strcpy(pvt->msg, "unknown error"); } /* Error address */ @@ -607,8 +616,9 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) if (mem_err->validation_bits & CPER_MEM_VALID_PA_MASK) e->grain = ~(mem_err->physical_addr_mask & ~PAGE_MASK); - /* Memory error location, mapped on e->location */ - p = e->location; + /* Memory error location, mapped on e->other_detail */ + p = pvt->other_detail; + p += snprintf(p, sizeof(pvt->other_detail), "APEI location: "); if (mem_err->validation_bits & CPER_MEM_VALID_NODE) p += sprintf(p, "node:%d ", mem_err->node); if (mem_err->validation_bits & CPER_MEM_VALID_CARD) @@ -626,27 +636,8 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) if (mem_err->validation_bits & CPER_MEM_VALID_BIT_POSITION) p += sprintf(p, "bit_pos:%d ", mem_err->bit_pos); if (mem_err->validation_bits & CPER_MEM_VALID_MODULE_HANDLE) { - const char *bank = NULL, *device = NULL; - int index = -1; - - dmi_memdev_name(mem_err->mem_dev_handle, &bank, &device); - if (bank != NULL && device != NULL) - p += sprintf(p, "DIMM location:%s %s ", bank, device); - else - p += sprintf(p, "DIMM DMI handle: 0x%.4x ", - mem_err->mem_dev_handle); - - index = get_dimm_smbios_index(mci, mem_err->mem_dev_handle); - if (index >= 0) - e->top_layer = index; + p += sprintf(p, "handle:0x%.4x ", handle); } - if (p > e->location) - *(p - 1) = '\0'; - - /* All other fields are mapped on e->other_detail */ - p = pvt->other_detail; - p += snprintf(p, sizeof(pvt->other_detail), - "APEI location: %s ", e->location); if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_STATUS) { u64 status = mem_err->error_status; @@ -754,11 +745,14 @@ ghes_edac_register_one(int nid, struct ghes *ghes, struct device *parent) struct ghes_edac_pvt *ghes_pvt; int rc; struct mem_ctl_info *mci; - struct edac_mc_layer layers[1]; + struct edac_mc_layer layers[2]; - layers[0].type = EDAC_MC_LAYER_ALL_MEM; + layers[0].type = EDAC_MC_LAYER_CARD; layers[0].size = 0; - layers[0].is_virt_csrow = true; + layers[0].is_virt_csrow = false; + layers[1].type = EDAC_MC_LAYER_MODULE; + layers[1].size = 0; + layers[1].is_virt_csrow = false; mci = edac_mc_alloc_by_dimm(nid, mem_info.num_per_node[nid], ARRAY_SIZE(layers), layers, diff --git a/include/linux/edac.h b/include/linux/edac.h index 4dcf075e9dff..40e7da735e48 100644 --- a/include/linux/edac.h +++ b/include/linux/edac.h @@ -336,6 +336,8 @@ enum edac_mc_layer_type { EDAC_MC_LAYER_SLOT, EDAC_MC_LAYER_CHIP_SELECT, EDAC_MC_LAYER_ALL_MEM, + EDAC_MC_LAYER_CARD, /* SMBIOS Type 16 Memory Array */ + EDAC_MC_LAYER_MODULE, /* SMBIOS Type 17 Memory Device */ }; /** From patchwork Wed May 29 08:44:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 165341 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp9580378ili; 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Signed-off-by: Robert Richter --- Documentation/admin-guide/ras.rst | 31 +++++++++++++++++++------------ 1 file changed, 19 insertions(+), 12 deletions(-) -- 2.20.1 diff --git a/Documentation/admin-guide/ras.rst b/Documentation/admin-guide/ras.rst index c7495e42e6f4..4e2a01c77a9c 100644 --- a/Documentation/admin-guide/ras.rst +++ b/Documentation/admin-guide/ras.rst @@ -330,9 +330,12 @@ There can be multiple csrows and multiple channels. .. [#f4] Nowadays, the term DIMM (Dual In-line Memory Module) is widely used to refer to a memory module, although there are other memory - packaging alternatives, like SO-DIMM, SIMM, etc. Along this document, - and inside the EDAC system, the term "dimm" is used for all memory - modules, even when they use a different kind of packaging. + packaging alternatives, like SO-DIMM, SIMM, etc. The UEFI + specification (Version 2.7) defines a memory module in the Common + Platform Error Record (CPER) section to be an SMBIOS Memory Device + (Type 17). Along this document, and inside the EDAC system, the term + "dimm" is used for all memory modules, even when they use a + different kind of packaging. Memory controllers allow for several csrows, with 8 csrows being a typical value. Yet, the actual number of csrows depends on the layout of @@ -349,12 +352,14 @@ controllers. The following example will assume 2 channels: | | ``ch0`` | ``ch1`` | +============+===========+===========+ | ``csrow0`` | DIMM_A0 | DIMM_B0 | - +------------+ | | - | ``csrow1`` | | | + | | rank0 | rank0 | + +------------+ - | - | + | ``csrow1`` | rank1 | rank1 | +------------+-----------+-----------+ | ``csrow2`` | DIMM_A1 | DIMM_B1 | - +------------+ | | - | ``csrow3`` | | | + | | rank0 | rank0 | + +------------+ - | - | + | ``csrow3`` | rank1 | rank1 | +------------+-----------+-----------+ In the above example, there are 4 physical slots on the motherboard @@ -374,11 +379,13 @@ which the memory DIMM is placed. Thus, when 1 DIMM is placed in each Channel, the csrows cross both DIMMs. Memory DIMMs come single or dual "ranked". A rank is a populated csrow. -Thus, 2 single ranked DIMMs, placed in slots DIMM_A0 and DIMM_B0 above -will have just one csrow (csrow0). csrow1 will be empty. On the other -hand, when 2 dual ranked DIMMs are similarly placed, then both csrow0 -and csrow1 will be populated. The pattern repeats itself for csrow2 and -csrow3. +In the example above 2 dual ranked DIMMs are similarly placed. Thus, +both csrow0 and csrow1 are populated. On the other hand, when 2 single +ranked DIMMs are placed in slots DIMM_A0 and DIMM_B0, then they will +have just one csrow (csrow0) and csrow1 will be empty. The pattern +repeats itself for csrow2 and csrow3. Also note that some memory +controller doesn't have any logic to identify the memory module, see +``rankX`` directories below. The representation of the above is reflected in the directory tree in EDAC's sysfs interface. Starting in directory