From patchwork Thu Apr 13 18:23:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 672905 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0319C77B7A for ; Thu, 13 Apr 2023 18:23:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229881AbjDMSX5 (ORCPT ); Thu, 13 Apr 2023 14:23:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49338 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229636AbjDMSXy (ORCPT ); Thu, 13 Apr 2023 14:23:54 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3234E61BE; Thu, 13 Apr 2023 11:23:53 -0700 (PDT) Received: from jupiter.universe (dyndsl-091-248-212-251.ewe-ip-backbone.de [91.248.212.251]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id 4BE72660321C; Thu, 13 Apr 2023 19:23:51 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1681410231; bh=J/aAZ1smSAAsG9/uQ7OFDO0676ZcUa7ugt0BDTtD/es=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kSJI4qzgzI3qItD2MLXvZahzmwBLn0qhNZhGLmLdDvuSd6LVIZJI6sp4pWhNQ9v5Q RaxKQAo9l4cMm8NSykNz4Sxg1MW9s0katZv6t23gWLn3c2/SdkWsgPXWunpfXCHS1q /ycdgXHHFX4o9sjSSbaiwe2cOOdXHANFA4p06E1Fu15Uo6c7OXLn8nPf4njPbEZxcY R1i/ru+/GjqKed/HrgkC3/dCLG/wxy3/oONOGiAGk+NiQEFpExosbZJq9bwYrvwE+x rQLY98zPZR3SR9iOfGMCoa374HNhLmK3xLm39UF/8Fd7m+4mnkR3e8ejlSPFXg/5E6 6u5uNCtnkCdcg== Received: by jupiter.universe (Postfix, from userid 1000) id 89F3B4807E3; Thu, 13 Apr 2023 20:23:48 +0200 (CEST) From: Sebastian Reichel To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Damien Le Moal , Serge Semin , Vinod Koul , Kishon Vijay Abraham I , linux-ide@vger.kernel.org, linux-phy@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCHv1 1/5] dt-bindings: soc: rockchip: add rk3588 pipe-phy syscon Date: Thu, 13 Apr 2023 20:23:41 +0200 Message-Id: <20230413182345.92557-2-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230413182345.92557-1-sebastian.reichel@collabora.com> References: <20230413182345.92557-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The pipe-phy syscon is used by rockchip,rk3588-naneng-combphy, which in turn is the PHY for USB3, PCIe and SATA. Signed-off-by: Sebastian Reichel Acked-by: Rob Herring --- Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml index a873f74564f2..dda071b66813 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -24,6 +24,7 @@ properties: - rockchip,rk3588-bigcore1-grf - rockchip,rk3588-ioc - rockchip,rk3588-php-grf + - rockchip,rk3588-pipe-phy-grf - rockchip,rk3588-sys-grf - rockchip,rk3588-pcie3-phy-grf - rockchip,rk3588-pcie3-pipe-grf From patchwork Thu Apr 13 18:23:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 674210 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7A0AC77B6E for ; Thu, 13 Apr 2023 18:23:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229739AbjDMSXy (ORCPT ); Thu, 13 Apr 2023 14:23:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49326 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229479AbjDMSXx (ORCPT ); Thu, 13 Apr 2023 14:23:53 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E45BD59FF; Thu, 13 Apr 2023 11:23:52 -0700 (PDT) Received: from jupiter.universe (dyndsl-091-248-212-251.ewe-ip-backbone.de [91.248.212.251]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id 57910660321D; Thu, 13 Apr 2023 19:23:51 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1681410231; bh=KE/Qh2dz/391cip/CPeIBTyPxaiySIGR7XU//jF9HQ0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BLL+poNly6f3IBlk3AcHxjpOJ8gIQE2cGE4I6Xg1ZFICMpx1DyZUTlpHA+IUtO4hJ kCZbWdMjfXNjAgcx/JbDOatnmGbyWSZXPW5qG54p7HUJHRqE4deVIBld/FouDB2Ki0 M0uO0E06O/+8f+ROutsz3y42AeShpdj/HORVnBWjn/5K9k91zRQ/TC//tvP8w11COD HKG7PivvGp93lzC9lqw6xk+mIOIX7gaIG1/yBJQ3XVUWflmgBdxsASaN2clW4zfaq3 sxyPYMDcFM80u21UXU2UzLqLucuLRXRoCz2siDHI/1q5EvtMuOCp9dd4xROp6dRgGK 68pN6ewd0rHMA== Received: by jupiter.universe (Postfix, from userid 1000) id 8CA424807EF; Thu, 13 Apr 2023 20:23:48 +0200 (CEST) From: Sebastian Reichel To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Damien Le Moal , Serge Semin , Vinod Koul , Kishon Vijay Abraham I , linux-ide@vger.kernel.org, linux-phy@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCHv1 2/5] dt-bindings: ata: ahci: add RK3588 AHCI controller Date: Thu, 13 Apr 2023 20:23:42 +0200 Message-Id: <20230413182345.92557-3-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230413182345.92557-1-sebastian.reichel@collabora.com> References: <20230413182345.92557-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Just like RK3568, the RK3588 has a DWC based AHCI controller. Signed-off-by: Sebastian Reichel --- FWIW IDK what exactly the ASIC clock is. The TRM does not provide any details unfortunately. It is required for functional SATA, though. --- .../devicetree/bindings/ata/snps,dwc-ahci-common.yaml | 6 ++++-- Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml | 6 ++++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/ata/snps,dwc-ahci-common.yaml b/Documentation/devicetree/bindings/ata/snps,dwc-ahci-common.yaml index c1457910520b..0df8f49431eb 100644 --- a/Documentation/devicetree/bindings/ata/snps,dwc-ahci-common.yaml +++ b/Documentation/devicetree/bindings/ata/snps,dwc-ahci-common.yaml @@ -31,11 +31,11 @@ properties: PM-alive clock, RxOOB detection clock, embedded PHYs reference (Rx/Tx) clock, etc. minItems: 1 - maxItems: 4 + maxItems: 5 clock-names: minItems: 1 - maxItems: 4 + maxItems: 5 items: oneOf: - description: Application APB/AHB/AXI BIU clock @@ -50,6 +50,8 @@ properties: const: rxoob - description: SATA Ports reference clock const: ref + - description: Rockchip ASIC clock + const: asic resets: description: diff --git a/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml b/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml index 5afa4b57ce20..c6a0d6c8b62c 100644 --- a/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml +++ b/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml @@ -23,9 +23,11 @@ properties: const: snps,dwc-ahci - description: SPEAr1340 AHCI SATA device const: snps,spear-ahci - - description: Rockhip RK3568 AHCI controller + - description: Rockhip AHCI controller items: - - const: rockchip,rk3568-dwc-ahci + - enum: + - rockchip,rk3568-dwc-ahci + - rockchip,rk3588-dwc-ahci - const: snps,dwc-ahci patternProperties: From patchwork Thu Apr 13 18:23:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 674209 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8DCEDC77B78 for ; Thu, 13 Apr 2023 18:23:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229873AbjDMSX4 (ORCPT ); Thu, 13 Apr 2023 14:23:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49336 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229674AbjDMSXy (ORCPT ); Thu, 13 Apr 2023 14:23:54 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 126C06181; Thu, 13 Apr 2023 11:23:53 -0700 (PDT) Received: from jupiter.universe (dyndsl-091-248-212-251.ewe-ip-backbone.de [91.248.212.251]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id 6A0516603220; Thu, 13 Apr 2023 19:23:51 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1681410231; bh=zAjmL1BsGoOklDz1it3NJmReakUPeGQCam58Z7IsTXQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=G7ZQvrSFBMb0jXOSMCMBBP5lIgdeFmRUiJLqNmPe16V5VkkuL/e94NdSeKrbtxBhr C/dOfzTpPbuMCGuXA3YzTV1A5fKgFfqR0vAK48ytk1H1//LWADehUjHfuLfoqCyGK4 O5oaxj1juSox7QkYE7D1B4nPtfXLqNWBIys6qws3JUG6VDrvaLP2LBq/cM6j0A84Tu FOkYRDpK3BbxCmfxxeyycBgduMYc2/bf+kfNavs9KmiJruMxrlyn33L6pP0VuaaS3o BvCz1iiDZRYUrUl3nB7TAem6bKgrn3PNyRXkSViM30XrbaxvJZasGY/iIZb/6tDXVC sniDnVZACTxiw== Received: by jupiter.universe (Postfix, from userid 1000) id 8ED504807F0; Thu, 13 Apr 2023 20:23:48 +0200 (CEST) From: Sebastian Reichel To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Damien Le Moal , Serge Semin , Vinod Koul , Kishon Vijay Abraham I , linux-ide@vger.kernel.org, linux-phy@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCHv1 3/5] dt-bindings: phy: rockchip: rk3588 has two reset lines Date: Thu, 13 Apr 2023 20:23:43 +0200 Message-Id: <20230413182345.92557-4-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230413182345.92557-1-sebastian.reichel@collabora.com> References: <20230413182345.92557-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The RK3588 has two reset lines for the combphy. One for the APB interface and one for the actual PHY. Signed-off-by: Sebastian Reichel --- .../bindings/phy/phy-rockchip-naneng-combphy.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml index 9ae514fa7533..bac1aae07555 100644 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml @@ -31,8 +31,13 @@ properties: - const: pipe resets: + minItems: 1 + maxItems: 2 + + reset-names: items: - - description: exclusive PHY reset line + - const: phy + - const: apb rockchip,enable-ssc: type: boolean From patchwork Thu Apr 13 18:23:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 674208 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7BBFC77B71 for ; Thu, 13 Apr 2023 18:23:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229922AbjDMSX5 (ORCPT ); Thu, 13 Apr 2023 14:23:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49340 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229747AbjDMSXy (ORCPT ); Thu, 13 Apr 2023 14:23:54 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F32B61AE; Thu, 13 Apr 2023 11:23:53 -0700 (PDT) Received: from jupiter.universe (dyndsl-091-248-212-251.ewe-ip-backbone.de [91.248.212.251]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id 94AF86603221; Thu, 13 Apr 2023 19:23:51 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1681410231; bh=KpDLVmY7MLRSnWayLikD4zY8rROUxg2D6rCjRLznobU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FbhrVWG2OsHm7fJqsv6mJONTZF7mu8HIroXjj4b1nkr2ZMJD0FQxyyByntADT+ZjO YDoLBlrvgqS2Q3t18BLk60R90YlJbomF6IQKFMk9EptMhZ5HLEGGLt8RX1qmhsBcrb rpcYxIZahfATD/ww/UlfynrAo5NIK7DLotWsmXplAj4Nasxjvxx+D5+B5pSTzRDqd5 4jGkI6+dOzPkjCflw6eEh0vFH6vipziG/9f1Lxz0f1gx65EDF7pm/4StnzEvAx+x6Y ud4zP3Po7BzSBxMFhiatgWfB8dzexV2c2QqCG0BcsklApPwgNIATJRJDQwpibuTM8D a99yA40QCXRnQ== Received: by jupiter.universe (Postfix, from userid 1000) id 90FCD4807F1; Thu, 13 Apr 2023 20:23:48 +0200 (CEST) From: Sebastian Reichel To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Damien Le Moal , Serge Semin , Vinod Koul , Kishon Vijay Abraham I , linux-ide@vger.kernel.org, linux-phy@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCHv1 4/5] arm64: dts: rockchip: rk3588: add combo PHYs Date: Thu, 13 Apr 2023 20:23:44 +0200 Message-Id: <20230413182345.92557-5-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230413182345.92557-1-sebastian.reichel@collabora.com> References: <20230413182345.92557-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add all 3 combo PHYs that can be found in RK3588. They are used for SATA, PCIe or USB3. Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 21 ++++++++++++ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 42 +++++++++++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi index d085e57fbc4c..fe1866a3697a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -7,6 +7,11 @@ #include "rk3588-pinctrl.dtsi" / { + pipe_phy1_grf: syscon@fd5c0000 { + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5c0000 0x0 0x100>; + }; + gmac0: ethernet@fe1b0000 { compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; reg = <0x0 0xfe1b0000 0x0 0x10000>; @@ -55,4 +60,20 @@ gmac0_mtl_tx_setup: tx-queues-config { queue1 {}; }; }; + + combphy1_ps: phy@fee10000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee10000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, + <&cru PCLK_PHP_ROOT>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy1_grf>; + status = "disabled"; + }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 422b31e342ca..7227c918f825 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -944,6 +944,16 @@ php_grf: syscon@fd5b0000 { reg = <0x0 0xfd5b0000 0x0 0x1000>; }; + pipe_phy0_grf: syscon@fd5bc000 { + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5bc000 0x0 0x100>; + }; + + pipe_phy2_grf: syscon@fd5c4000 { + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5c4000 0x0 0x100>; + }; + ioc: syscon@fd5f0000 { compatible = "rockchip,rk3588-ioc", "syscon"; reg = <0x0 0xfd5f0000 0x0 0x10000>; @@ -2200,6 +2210,38 @@ dmac2: dma-controller@fed10000 { #dma-cells = <1>; }; + combphy0_ps: phy@fee00000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee00000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, + <&cru PCLK_PHP_ROOT>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy0_grf>; + status = "disabled"; + }; + + combphy2_psu: phy@fee20000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee20000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, + <&cru PCLK_PHP_ROOT>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy2_grf>; + status = "disabled"; + }; + system_sram2: sram@ff001000 { compatible = "mmio-sram"; reg = <0x0 0xff001000 0x0 0xef000>; From patchwork Thu Apr 13 18:23:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 672904 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 750EFC77B71 for ; Thu, 13 Apr 2023 18:24:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229479AbjDMSYB (ORCPT ); Thu, 13 Apr 2023 14:24:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229839AbjDMSX4 (ORCPT ); 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Thu, 13 Apr 2023 20:23:48 +0200 (CEST) From: Sebastian Reichel To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Damien Le Moal , Serge Semin , Vinod Koul , Kishon Vijay Abraham I , linux-ide@vger.kernel.org, linux-phy@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCHv1 5/5] arm64: dts: rockchip: rk3588: add SATA support Date: Thu, 13 Apr 2023 20:23:45 +0200 Message-Id: <20230413182345.92557-6-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230413182345.92557-1-sebastian.reichel@collabora.com> References: <20230413182345.92557-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add all three SATA IP blocks to the RK3588 DT. Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 23 +++++++++++ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 48 +++++++++++++++++++++++ 2 files changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi index fe1866a3697a..65d818964bff 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -61,6 +61,29 @@ gmac0_mtl_tx_setup: tx-queues-config { }; }; + sata1: sata@fe220000 { + compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfe220000 0 0x1000>; + clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, + <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>, + <&cru CLK_PIPEPHY1_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + interrupts = ; + ports-implemented = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata-port@0 { + reg = <0>; + hba-port-cap = ; + phys = <&combphy1_ps PHY_TYPE_SATA>; + phy-names = "sata-phy"; + snps,rx-ts-max = <32>; + snps,tx-ts-max = <32>; + }; + }; + combphy1_ps: phy@fee10000 { compatible = "rockchip,rk3588-naneng-combphy"; reg = <0x0 0xfee10000 0x0 0x100>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 7227c918f825..2124c654f665 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -9,6 +9,8 @@ #include #include #include +#include +#include / { compatible = "rockchip,rk3588"; @@ -1666,6 +1668,52 @@ gmac1_mtl_tx_setup: tx-queues-config { }; }; + sata0: sata@fe210000 { + compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfe210000 0 0x1000>; + clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, + <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, + <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + interrupts = ; + ports-implemented = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata-port@0 { + reg = <0>; + hba-port-cap = ; + phys = <&combphy0_ps PHY_TYPE_SATA>; + phy-names = "sata-phy"; + snps,rx-ts-max = <32>; + snps,tx-ts-max = <32>; + }; + }; + + sata2: sata@fe230000 { + compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfe230000 0 0x1000>; + clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, + <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, + <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + interrupts = ; + ports-implemented = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata-port@0 { + reg = <0>; + hba-port-cap = ; + phys = <&combphy2_psu PHY_TYPE_SATA>; + phy-names = "sata-phy"; + snps,rx-ts-max = <32>; + snps,tx-ts-max = <32>; + }; + }; + sdhci: mmc@fe2e0000 { compatible = "rockchip,rk3588-dwcmshc"; reg = <0x0 0xfe2e0000 0x0 0x10000>;