From patchwork Sun Apr 16 17:32:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Yang X-Patchwork-Id: 673664 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1082C77B77 for ; Sun, 16 Apr 2023 17:33:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229532AbjDPRdh (ORCPT ); Sun, 16 Apr 2023 13:33:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44466 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229446AbjDPRdh (ORCPT ); Sun, 16 Apr 2023 13:33:37 -0400 Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7217C26B2; Sun, 16 Apr 2023 10:33:32 -0700 (PDT) Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-63b4bf2d74aso929363b3a.2; Sun, 16 Apr 2023 10:33:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681666412; x=1684258412; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=y5kIOddp2BM0cA3ov6qyXIiq4ZLBnVdQ+km/uFDAHF0=; b=Eeo1XDbbRb9eKnyFHhcSuoLP/sYJbukWB80hLaDCj6j221CKAwA7xYo0eZEVYRONrw JlfulZdLJX0jxrkWEgqjZh2Uc1dagl9LHsOcntODS/5hOq+akb4rkb3VUNb1TgoRbrmo RR8VSmJ0GaW/m97F9MsE3SkqFn8IY+pmxaY4YYF3UMXoueCNVe7K/YzbLDTKAA28WK4c cOaJRyz4uQmNUVCbwoYu76GHpsnzNKy0QJWU1kybfk7F6AO+C1l+NUXEhRJTX+CG/D9J QF0CSh9RyhOhtAar7lwudUwjDY+UiUd3bKVhgi3+trt20oooBrYcgsn8YToTmp1aHdko TmZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681666412; x=1684258412; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=y5kIOddp2BM0cA3ov6qyXIiq4ZLBnVdQ+km/uFDAHF0=; b=GMUrrmDrMbWOM2FEROmSSdgUNn18SppJQGMn485UpPYCTndYI4Wk0BQGzIavX1mbp+ pzSBlhPB6B3cVFiuWSlnkwqjlozZsHZ454z1XF4Gnied32LrkpCLhXWjzuDyu0uUeosr bmqHMETUNBeKQrJ+jeSaVu84YZX3FO7/GwPT5ue+vPYvoCEFt/9/QwCnql7lbvzJP6lK 3lZYwruwTkIKJXzGC2rITCpVdTWtCOcWh1xfAAfsquaAXUDbY9pbtUPx0xMsSy59AN39 iJ1DAgA92zQvHa8wWFniMgkpdgguTBoSPr0ZVw5RRUXzQ3bUsqV4UEss0JjNA4ySVbUB 0brA== X-Gm-Message-State: AAQBX9cYK4p2QpojUVZeDxuwGhgNDbOb2S5vOgUfF0eW+iWWc6lNEwWA qUHiDwDm0pmbzqbX1zmxV/4d9J6/k/2tS0je5LA= X-Google-Smtp-Source: AKy350Y8vu47+r13CkiocfYLaqXrvC4pWA1zaDRkAZ+aTwSsGnTXZMzvHW+YaFLOOUl5PL4FG7cn0A== X-Received: by 2002:a05:6a00:228e:b0:633:afea:6b1a with SMTP id f14-20020a056a00228e00b00633afea6b1amr17811414pfe.19.1681666411698; Sun, 16 Apr 2023 10:33:31 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.245.200]) by smtp.gmail.com with ESMTPSA id j22-20020a62b616000000b0062d90f36d16sm6110973pff.88.2023.04.16.10.33.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Apr 2023 10:33:31 -0700 (PDT) From: David Yang To: linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org, David Yang , Michael Turquette , Stephen Boyd , Philipp Zabel , linux-kernel@vger.kernel.org, Rob Herring , Krzysztof Kozlowski Subject: [PATCH v2 1/4] dt-bindings: clock: Add simple-clock-controller Date: Mon, 17 Apr 2023 01:32:57 +0800 Message-Id: <20230416173302.1185683-2-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230416173302.1185683-1-mmyangfl@gmail.com> References: <20230416173302.1185683-1-mmyangfl@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT bindings documentation for simple-clock-controller, mutex controller for clocks. Signed-off-by: David Yang --- .../clock/simple-clock-controller.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/simple-clock-controller.yaml diff --git a/Documentation/devicetree/bindings/clock/simple-clock-controller.yaml b/Documentation/devicetree/bindings/clock/simple-clock-controller.yaml new file mode 100644 index 000000000000..17835aeddb1d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/simple-clock-controller.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/simple-clock-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Simple clock controller + +maintainers: + - David Yang + +description: | + Driver (lock provider) for real clocks. + + Usually one register controls more than one clocks. This controller avoids + write conflicts by imposing a write lock, so that two operations on the same + register will not happen at the same time. + +properties: + compatible: + items: + - oneOf: + - const: simple-clock-controller + - const: simple-clock-reset-controller + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + '#reset-cells': + const: 2 + +patternProperties: + "clock@.*": + type: object + description: Clock nodes. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + clock-controller@ffff000 { + compatible = "simple-clock-controller", "syscon", "simple-mfd"; + reg = <0xffff000 0x1000>; + }; From patchwork Sun Apr 16 17:32:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Yang X-Patchwork-Id: 673663 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A497DC77B73 for ; Sun, 16 Apr 2023 17:34:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229871AbjDPReY (ORCPT ); Sun, 16 Apr 2023 13:34:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45486 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229808AbjDPReV (ORCPT ); Sun, 16 Apr 2023 13:34:21 -0400 Received: from mail-pg1-x52e.google.com (mail-pg1-x52e.google.com [IPv6:2607:f8b0:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DDEFE1FEC; Sun, 16 Apr 2023 10:34:04 -0700 (PDT) Received: by mail-pg1-x52e.google.com with SMTP id 41be03b00d2f7-517c0b93cedso1368609a12.3; Sun, 16 Apr 2023 10:34:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681666444; x=1684258444; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=M2z2P2CLLQzPKNwNvzS3QFdbVdZVu7R6LBxzSQ54uz0=; b=fxS2+XSwfgNTBrAVa1jYYnYJ/dMZQP5M+LMfCaCeXmwCsFxpPvWPMS7lNpd3X44Y+T OMyBTnUPHpTYUyTXgAYvEYXmjY1n0hvGQFYz2XGZkbd4Tf9kb/3ZL2BGrqOTZz/tHW3P acnq4gtbrPIBk7RQuLBNsV7x7qJwGRDobHuMEEtqFyWAaBqG+kzRZ5CVp4jOyLTmTJg9 pEKEoTJ8D0dWDBtnMFufpmFo2NKf4I9K/mCiNYTHyVanib2sdacGb0NYNz8Un3ouUTJu 1mCCf421rdYRHX7dtcXqNbHHQCBG5ASwStbQKtZde+3Ommp5Qxzu7ypGP41hRMMh1S4O oksg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681666444; x=1684258444; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=M2z2P2CLLQzPKNwNvzS3QFdbVdZVu7R6LBxzSQ54uz0=; b=K+H611pj7kR4PfdigHBcwF8FoIm6iYua06GvIkgRHszudhp00QopPF9961UrkCqGAl O0Tn3A1wM4ZHh7oFOBtEdLckIXpZkSiWwA6/4NAufQDZUybd9QSr4pMyCHy8iDy/Nlsy 2mr9RCPxGA8SIeySDnkPMHTCy6dcfX3w2pcgScTtgYTlDdUxrzRR5e9CselOvMPTRU1S LYjaGH7VucQ7eeA0zEW5ct3dJrNqIZhdMYP8pxqxsNLu/uCer/Y7ZGELW/j/abqsRLzS QJDckdsW8O2NlxA0zeI7J5vFdwFwDpXqwFJrTFzeHKGvCQ7615Z4JkNhUjbl/QzxWNnh 78HA== X-Gm-Message-State: AAQBX9cMZR99hCKv6pJLgSv/V22lEulA4/ExVOmgS6kiP9ybK0xzDE/D TL77hvTIusT3d6E2FTO2GfJ/AWtnzm+pj52HTNk= X-Google-Smtp-Source: AKy350Z891lGlXuRXrya9/rGVhBzw6K5Cb7Hu8iImxlusJpbOArJD7y/FuvawnII1D3wzHf4wZ9kyA== X-Received: by 2002:a05:6a00:15d1:b0:63b:59ad:dbd5 with SMTP id o17-20020a056a0015d100b0063b59addbd5mr15109875pfu.34.1681666444122; Sun, 16 Apr 2023 10:34:04 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.245.200]) by smtp.gmail.com with ESMTPSA id j22-20020a62b616000000b0062d90f36d16sm6110973pff.88.2023.04.16.10.33.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Apr 2023 10:34:03 -0700 (PDT) From: David Yang To: linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org, David Yang , Michael Turquette , Stephen Boyd , Philipp Zabel , linux-kernel@vger.kernel.org Subject: [PATCH v2 2/4] clk: Add simple clock controller Date: Mon, 17 Apr 2023 01:32:59 +0800 Message-Id: <20230416173302.1185683-3-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230416173302.1185683-1-mmyangfl@gmail.com> References: <20230416173302.1185683-1-mmyangfl@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org These clocks were provided in `include/linux/clk-provider.h`, but lacks DT bindings. Add a clock controller to avoid operation conflict on same register. Signed-off-by: David Yang --- drivers/clk/Makefile | 1 + drivers/clk/clk-of.c | 292 +++++++++++++++++++++++++++++++++++++++++++ drivers/clk/clk-of.h | 26 ++++ 3 files changed, 319 insertions(+) create mode 100644 drivers/clk/clk-of.c create mode 100644 drivers/clk/clk-of.h diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index e3ca0d058a25..6cf0a888b673 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_COMMON_CLK) += clk-fractional-divider.o obj-$(CONFIG_COMMON_CLK) += clk-gpio.o ifeq ($(CONFIG_OF), y) obj-$(CONFIG_COMMON_CLK) += clk-conf.o +obj-$(CONFIG_COMMON_CLK) += clk-of.o endif # hardware specific clock types diff --git a/drivers/clk/clk-of.c b/drivers/clk/clk-of.c new file mode 100644 index 000000000000..3518ae848ed0 --- /dev/null +++ b/drivers/clk/clk-of.c @@ -0,0 +1,292 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2023 David Yang + * + * Simple straight-forward register clocks bindings + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk-of.h" + +struct of_clk_ctrl_priv { + spinlock_t lock; + + struct reset_controller_dev rcdev; + void __iomem *base; + bool rst_set_to_disable; +}; + +static const struct of_clk_flag of_clk_common_flags[] = { + { "set-rate-gate", CLK_SET_RATE_GATE }, + { "set-parent-gate", CLK_SET_PARENT_GATE }, + { "set-rate-parent", CLK_SET_RATE_PARENT }, + { "ignore-unused", CLK_IGNORE_UNUSED }, + { "get-rate-nocache", CLK_GET_RATE_NOCACHE }, + { "set-rate-no-reparent", CLK_SET_RATE_NO_REPARENT }, + { "get-accuracy-nocache", CLK_GET_ACCURACY_NOCACHE }, + { "recalc-new-rates", CLK_RECALC_NEW_RATES }, + { "set-rate-ungate", CLK_SET_RATE_UNGATE }, + { "critical", CLK_IS_CRITICAL }, + { "ops-parent-enable", CLK_OPS_PARENT_ENABLE }, + { "duty-cycle-parent", CLK_DUTY_CYCLE_PARENT }, + { } +}; + +void __iomem *of_clk_get_reg(struct device_node *np) +{ + u32 offset; + void __iomem *reg; + + if (of_property_read_u32(np, "offset", &offset)) + return NULL; + + reg = of_iomap(np->parent, 0); + if (!reg) + return NULL; + + return reg + offset; +} +EXPORT_SYMBOL_GPL(of_clk_get_reg); + +const char *of_clk_get_name(struct device_node *np) +{ + const char *name; + + if (!of_property_read_string(np, "clock-output-name", &name)) + return name; + + return of_node_full_name(np); +} +EXPORT_SYMBOL_GPL(of_clk_get_name); + +unsigned long +of_clk_get_flags(struct device_node *np, const struct of_clk_flag *defs) +{ + unsigned long flags = 0; + + if (!defs) + defs = of_clk_common_flags; + + for (int i = 0; defs[i].prop; i++) + if (of_property_read_bool(np, defs[i].prop)) + flags |= defs[i].flag; + + return flags; +} +EXPORT_SYMBOL_GPL(of_clk_get_flags); + +int of_clk_remove(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + + of_clk_del_provider(np); + clk_hw_unregister(np->data); + + return 0; +} +EXPORT_SYMBOL_GPL(of_clk_remove); + +int of_clk_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = pdev->dev.of_node; + int (*setup)(struct device_node *np) = of_device_get_match_data(dev); + + return setup(np); +} +EXPORT_SYMBOL_GPL(of_clk_probe); + +/** of_rst_ctrl **/ + +#if IS_ENABLED(CONFIG_RESET_CONTROLLER) +static int +of_rst_ctrl_assert(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct of_clk_ctrl_priv *priv = container_of(rcdev, struct of_clk_ctrl_priv, rcdev); + unsigned long flags; + u32 offset = id >> 16; + u8 index = id & 0x1f; + u32 val; + + if (WARN_ON(!priv->base)) + return 0; + + spin_lock_irqsave(&priv->lock, flags); + + val = readl(priv->base + offset); + if (priv->rst_set_to_disable) + val &= ~BIT(index); + else + val |= BIT(index); + writel(val, priv->base + offset); + + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int +of_rst_ctrl_deassert(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct of_clk_ctrl_priv *priv = container_of(rcdev, struct of_clk_ctrl_priv, rcdev); + unsigned long flags; + u32 offset = id >> 16; + u8 index = id & 0x1f; + u32 val; + + if (WARN_ON(!priv->base)) + return 0; + + spin_lock_irqsave(&priv->lock, flags); + + val = readl(priv->base + offset); + if (priv->rst_set_to_disable) + val |= BIT(index); + else + val &= ~BIT(index); + writel(val, priv->base + offset); + + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static const struct reset_control_ops of_rst_ctrl_ops = { + .assert = of_rst_ctrl_assert, + .deassert = of_rst_ctrl_deassert, +}; + +static int of_rst_ctrl_of_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + return (reset_spec->args[0] << 16) | (reset_spec->args[1] & 0x1f); +} + +static void of_rst_ctrl_unsetup(struct device_node *np) +{ + struct of_clk_ctrl_priv *priv = np->data; + + reset_controller_unregister(&priv->rcdev); +} + +static int of_rst_ctrl_setup(struct device_node *np, struct of_clk_ctrl_priv *priv) +{ + priv->base = of_iomap(np, 0); + priv->rst_set_to_disable = of_property_read_bool(np, "set-to-disable"); + + /* register no matter whether reg exists, to detect dts bug */ + priv->rcdev.ops = &of_rst_ctrl_ops; + priv->rcdev.of_node = np; + priv->rcdev.of_reset_n_cells = 2; + priv->rcdev.of_xlate = of_rst_ctrl_of_xlate; + return reset_controller_register(&priv->rcdev); +} +#else +static void of_rst_ctrl_unsetup(struct device_node *np) +{ +} + +static int of_rst_ctrl_setup(struct device_node *np, struct of_clk_ctrl_priv *priv) +{ + return 0; +} +#endif + +/** of_crg_ctrl **/ + +static void of_crg_ctrl_unsetup(struct device_node *np, bool crg) +{ + if (crg) + of_rst_ctrl_unsetup(np); + + kfree(np->data); + np->data = NULL; +} + +static int of_crg_ctrl_setup(struct device_node *np, bool crg) +{ + struct of_clk_ctrl_priv *priv; + int ret; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + np->data = priv; + + spin_lock_init(&priv->lock); + + if (crg) { + ret = of_rst_ctrl_setup(np, priv); + if (ret) + goto err; + } + + return 0; + +err: + kfree(np->data); + np->data = NULL; + return ret; +} + +/** driver **/ + +static void __init of_clk_ctrl_init(struct device_node *np) +{ + of_crg_ctrl_setup(np, false); +} +CLK_OF_DECLARE(of_clk_ctrl, "simple-clock-controller", of_clk_ctrl_init); + +static void __init of_crg_ctrl_init(struct device_node *np) +{ + of_crg_ctrl_setup(np, true); +} +CLK_OF_DECLARE(of_crg_ctrl, "simple-clock-reset-controller", of_crg_ctrl_init); + +static int of_crg_ctrl_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = pdev->dev.of_node; + bool crg = (bool) of_device_get_match_data(dev); + + of_crg_ctrl_unsetup(np, crg); + + return 0; +} + +/* This function is not executed when of_clk_ctrl_init succeeded. */ +static int of_crg_ctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = pdev->dev.of_node; + bool crg = (bool) of_device_get_match_data(dev); + + return of_crg_ctrl_setup(np, crg); +} + +static const struct of_device_id of_crg_ctrl_ids[] = { + { .compatible = "simple-clock-controller", .data = (void *) false }, + { .compatible = "simple-clock-reset-controller", .data = (void *) true }, + { } +}; + +static struct platform_driver of_crg_ctrl_driver = { + .driver = { + .name = "clk_of", + .of_match_table = of_crg_ctrl_ids, + }, + .probe = of_crg_ctrl_probe, + .remove = of_crg_ctrl_remove, +}; +builtin_platform_driver(of_crg_ctrl_driver); diff --git a/drivers/clk/clk-of.h b/drivers/clk/clk-of.h new file mode 100644 index 000000000000..ddb1e57ec2f1 --- /dev/null +++ b/drivers/clk/clk-of.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */ +/* + * Copyright (c) 2023 David Yang + */ + +#include + +struct device_node; +struct platform_device; + +struct of_clk_ctrl { + spinlock_t lock; +}; + +struct of_clk_flag { + const char *prop; + unsigned long flag; +}; + +void __iomem *of_clk_get_reg(struct device_node *np); +const char *of_clk_get_name(struct device_node *np); +unsigned long +of_clk_get_flags(struct device_node *np, const struct of_clk_flag *defs); + +int of_clk_remove(struct platform_device *pdev); +int of_clk_probe(struct platform_device *pdev); From patchwork Sun Apr 16 17:33:01 2023 Content-Type: text/plain; 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Signed-off-by: David Yang --- .../devicetree/bindings/clock/gate-clock.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/gate-clock.yaml diff --git a/Documentation/devicetree/bindings/clock/gate-clock.yaml b/Documentation/devicetree/bindings/clock/gate-clock.yaml new file mode 100644 index 000000000000..3c993cb7e9bb --- /dev/null +++ b/Documentation/devicetree/bindings/clock/gate-clock.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/gate-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Clock which can gate its output + +maintainers: + - David Yang + +description: | + Clock which can gate its output. + + The registers map is retrieved from the parental dt-node. So the clock node + should be represented as a sub-node of a "clock-controller" node. + + See also: linux/clk-provider.h + +properties: + compatible: + const: gate-clock + + '#clock-cells': + const: 0 + + clocks: + maxItems: 1 + description: Parent clock. + + offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Offset in the register map for the control register (in bytes). + + bits: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Bit index which controls the output. + + clock-output-names: + maxItems: 1 + +required: + - compatible + - '#clock-cells' + - offset + - bits + +additionalProperties: false + +examples: + - | + gate-clock@cc.3 { + compatible = "gate-clock"; + #clock-cells = <0>; + offset = <0xcc>; + bits = <3>; + clock-output-names = "my-clk"; + }; From patchwork Sun Apr 16 17:33:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Yang X-Patchwork-Id: 673662 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C664BC77B61 for ; Sun, 16 Apr 2023 17:35:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229794AbjDPRfB (ORCPT ); Sun, 16 Apr 2023 13:35:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229776AbjDPRe7 (ORCPT ); Sun, 16 Apr 2023 13:34:59 -0400 Received: from mail-pf1-x42d.google.com (mail-pf1-x42d.google.com [IPv6:2607:f8b0:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED24826B2; Sun, 16 Apr 2023 10:34:38 -0700 (PDT) Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-63b70ca0a84so747718b3a.2; Sun, 16 Apr 2023 10:34:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681666478; x=1684258478; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bxfOnlh1gWPz4ECc5+gyXwuy61sNCNvLdcJJf29rWhA=; b=hPd8h+vf5YhJGTgRERaLgALldhgleev+V0wqIC4AzrE8ng92mX9Nhi98I3AzaYNiz6 jR8I62aILyO6oIAaxofOc0JbJC2WqXRXuQPD3Q1cgGY1I9JCxBz+RYK7bn3862a1nINC kTkqgnIyN9jv1xzBR+mKuzmB3YT70V7nytrgRUd8CpI8wHusTu31FZbUDiT1y+dZNVPO y8UgYR2t8D5vXE+5FlzZmBe8N4bxLmVdSTk3uO3cK8V++7Wi6zVdvgeBVV/LONAAUTPK FQhrl7OXgNSq9au67KH6e4xeyV7S6GJLp2NswMtfSd8wlYPT31S9UsjU+95OpixHFK88 vOEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681666478; x=1684258478; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bxfOnlh1gWPz4ECc5+gyXwuy61sNCNvLdcJJf29rWhA=; b=f1dAfj8392xlmavW3p0FM6iGJw/a5HMnVhucWPHKjaE7q89TfgUsMqKnVZ+WL2eu9t Q6ftQjuZXguVrfP+9Fj/v8DY/SurKTfW8mNGhl5NyCpxTDsd4vzV4BXd+xz6t3DBbyTz 7bEt7uNPTs69WZQqq4ShUcSab4a71aa2BfZNKLXVkCjctc3BS3zUJynM3CKEI6jjLsDt wiUPHnn/W5yC6EIytVdGluSxY4B+nBDs/X5xkUX7Zvygta8bWLYrTAClgTzsYX6J33a/ e8TkwyEZxnV5a/5r8nw7+VYZFXmXvXzv1APzoj6dXZOlDjanZgN/f2LCEq/7FypD9pBZ 9Rnw== X-Gm-Message-State: AAQBX9d/H2YcmQybfG2Y+ep1lAZpqDionyx/rgoe14Hb8Hz3yycoy9xx dU7HfVh6rt7YKkvMyIOzZxScsVJn/1aO9j+pH/M= X-Google-Smtp-Source: AKy350YMmfJDtdMdCjBQlAMr3FKj0gbXI5/S7pqfHG2aKD6WhYFY+hKx1QoKx7o6B6c9hSxvbJuUzQ== X-Received: by 2002:a05:6a00:890:b0:63a:fae3:9890 with SMTP id q16-20020a056a00089000b0063afae39890mr17928494pfj.24.1681666477842; Sun, 16 Apr 2023 10:34:37 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.245.200]) by smtp.gmail.com with ESMTPSA id j22-20020a62b616000000b0062d90f36d16sm6110973pff.88.2023.04.16.10.34.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Apr 2023 10:34:37 -0700 (PDT) From: David Yang To: linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org, David Yang , Michael Turquette , Stephen Boyd , Philipp Zabel , linux-kernel@vger.kernel.org Subject: [PATCH v2 4/4] clk: gate: Add DT binding Date: Mon, 17 Apr 2023 01:33:02 +0800 Message-Id: <20230416173302.1185683-5-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230416173302.1185683-1-mmyangfl@gmail.com> References: <20230416173302.1185683-1-mmyangfl@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT binding for gate clock as "gate-clock". Signed-off-by: David Yang --- drivers/clk/clk-gate.c | 81 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index 64283807600b..a70df4a2a9a7 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -12,8 +12,11 @@ #include #include #include +#include #include +#include "clk-of.h" + /** * DOC: basic gatable clock which can gate and ungate it's ouput * @@ -257,3 +260,81 @@ struct clk_hw *__devm_clk_hw_register_gate(struct device *dev, return hw; } EXPORT_SYMBOL_GPL(__devm_clk_hw_register_gate); + +#if IS_ENABLED(CONFIG_OF) +static const struct of_clk_flag of_clk_gate_flags[] = { + { "set-to-disable", CLK_GATE_SET_TO_DISABLE }, + { "hiword-mask", CLK_GATE_HIWORD_MASK }, + { "big-endian", CLK_GATE_BIG_ENDIAN }, + { } +}; + +static int of_clk_gate_setup(struct device_node *np) +{ + struct of_clk_ctrl *ctrl = np->parent->data; + const char *name; + void __iomem *reg; + u32 bit_idx; + + const char *property; + struct clk_hw *hw; + int ret; + + reg = of_clk_get_reg(np); + if (!reg) + return -ENOMEM; + name = of_clk_get_name(np); + if (!name) + return -EINVAL; + + property = "bits"; + if (of_property_read_u32(np, property, &bit_idx)) + goto err_property; + + hw = __clk_hw_register_gate(NULL, np, name, + of_clk_get_parent_name(np, 0), + NULL, NULL, of_clk_get_flags(np, NULL), + reg, bit_idx, + of_clk_get_flags(np, of_clk_gate_flags), + &ctrl->lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); + if (ret) + goto err_register; + + np->data = hw; + return 0; + +err_register: + clk_hw_unregister(hw); + return ret; + +err_property: + pr_err("%s: clock %s missing required property \"%s\"\n", + __func__, name, property); + return -EINVAL; +} + +static void __init of_clk_gate_init(struct device_node *np) +{ + of_clk_gate_setup(np); +} +CLK_OF_DECLARE(of_clk_gate, "gate-clock", of_clk_gate_init); + +static const struct of_device_id of_clk_gate_ids[] = { + { .compatible = "gate-clock", .data = of_clk_gate_setup }, + { } +}; + +static struct platform_driver of_clk_gate_driver = { + .driver = { + .name = "clk_gate", + .of_match_table = of_clk_gate_ids, + }, + .probe = of_clk_probe, + .remove = of_clk_remove, +}; +builtin_platform_driver(of_clk_gate_driver); +#endif