From patchwork Tue Apr 18 15:28:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hawkins, Nick" X-Patchwork-Id: 674653 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4AEEC7EE24 for ; Tue, 18 Apr 2023 15:32:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232347AbjDRPcP (ORCPT ); Tue, 18 Apr 2023 11:32:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47982 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232305AbjDRPcL (ORCPT ); Tue, 18 Apr 2023 11:32:11 -0400 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 532B212CB4; Tue, 18 Apr 2023 08:32:08 -0700 (PDT) Received: from pps.filterd (m0134422.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 33I7g3O4027489; Tue, 18 Apr 2023 15:31:36 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : subject : date : message-id : in-reply-to : references; s=pps0720; bh=Tt4JzqIKEid4oeg7pCnXRGju7fBjcdE/E0n7Dx1eby8=; b=AyUo4KuzQy9QPt0mDcea465Y84vT2aqnvfMF+3uN0V9LWsKMBCfCE/pkeITzbmO67SXn t5Phb2KILxlbk8hu0fJ9Z5dE621MD6bx++DEHuKEIQImWc9zj5sm5OP6wxu0b1D93vmJ NePxI2LYOtf0Xnu1pmRrJ2I0Y+Lv2Pr9GM2GuteQ2lF49ZdrwAGB42J0MOjy4gaeebwB PGNV8cZz5gcdHoNYU858QQ4o4v1+jopgNkvg3ZHQyOWThxdpcG94KFS/br14tL8y0kVh z8yzezVZK16dUPcxo5yPqrM5gNZw9xaoUD39jjxj/lBqMTxd+zvzZr/AvhIA1KyxMxKN iw== Received: from p1lg14881.it.hpe.com (p1lg14881.it.hpe.com [16.230.97.202]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3q1mhrmxcx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 18 Apr 2023 15:31:36 +0000 Received: from p1lg14886.dc01.its.hpecorp.net (unknown [10.119.18.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by p1lg14881.it.hpe.com (Postfix) with ESMTPS id CFA32804788; Tue, 18 Apr 2023 15:31:35 +0000 (UTC) Received: from hpe.com (unknown [16.231.227.36]) by p1lg14886.dc01.its.hpecorp.net (Postfix) with ESMTP id 2AE9681532D; Tue, 18 Apr 2023 15:31:35 +0000 (UTC) From: nick.hawkins@hpe.com To: verdun@hpe.com, nick.hawkins@hpe.com, linus.walleij@linaro.org, brgl@bgdev.pl, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, jdelvare@suse.com, linux@roeck-us.net, linux@armlinux.org.uk, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v1 1/9] gpio: gxp: Add HPE GXP GPIO Date: Tue, 18 Apr 2023 10:28:16 -0500 Message-Id: <20230418152824.110823-2-nick.hawkins@hpe.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230418152824.110823-1-nick.hawkins@hpe.com> References: <20230418152824.110823-1-nick.hawkins@hpe.com> X-Proofpoint-ORIG-GUID: 7agTXQ4YaY-0JUjdZOtoPjxiE3naG5NX X-Proofpoint-GUID: 7agTXQ4YaY-0JUjdZOtoPjxiE3naG5NX X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-18_11,2023-04-18_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=999 spamscore=0 clxscore=1015 impostorscore=0 suspectscore=0 bulkscore=0 malwarescore=0 adultscore=0 phishscore=0 lowpriorityscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304180132 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Nick Hawkins The GXP SoC supports GPIO on multiple interfaces: Host, CPLD and Soc pins. The interface from CPLD and Host are interruptable from vic0 and vic1. This driver allows support for both of these interfaces through the use of different compatible bindings. Signed-off-by: Nick Hawkins --- drivers/gpio/Kconfig | 9 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-gxp.c | 1056 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 1066 insertions(+) create mode 100644 drivers/gpio/gpio-gxp.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 13be729710f2..47435307698c 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -1235,6 +1235,15 @@ config HTC_EGPIO several HTC phones. It provides basic support for input pins, output pins, and IRQs. +config GPIO_GXP + tristate "GXP GPIO support" + depends on ARCH_HPE_GXP + select GPIOLIB_IRQCHIP + help + Say Y here to support GXP GPIO controllers. It provides + support for the multiple GPIO interfaces available to be + available to the Host. + config GPIO_JANZ_TTL tristate "Janz VMOD-TTL Digital IO Module" depends on MFD_JANZ_CMODIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index c048ba003367..a7ce0ab097aa 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -63,6 +63,7 @@ obj-$(CONFIG_GPIO_FTGPIO010) += gpio-ftgpio010.o obj-$(CONFIG_GPIO_GE_FPGA) += gpio-ge.o obj-$(CONFIG_GPIO_GPIO_MM) += gpio-gpio-mm.o obj-$(CONFIG_GPIO_GRGPIO) += gpio-grgpio.o +obj-$(CONFIG_GPIO_GXP) += gpio-gxp.o obj-$(CONFIG_GPIO_GW_PLD) += gpio-gw-pld.o obj-$(CONFIG_GPIO_HISI) += gpio-hisi.o obj-$(CONFIG_GPIO_HLWD) += gpio-hlwd.o diff --git a/drivers/gpio/gpio-gxp.c b/drivers/gpio/gpio-gxp.c new file mode 100644 index 000000000000..86f69174434d --- /dev/null +++ b/drivers/gpio/gpio-gxp.c @@ -0,0 +1,1056 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (C) 2023 Hewlett-Packard Enterprise Development Company, L.P. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define GPIDATL 0x40 +#define GPIDATH 0x60 +#define GPODATL 0xb0 +#define GPODATH 0xb4 +#define GPODAT2L 0xf8 +#define GPODAT2H 0xfc +#define GPOOWNL 0x110 +#define GPOOWNH 0x114 +#define GPOOWN2L 0x118 +#define GPOOWN2H 0x11c + +#define GPIO_DIR_OUT 0 +#define GPIO_DIR_IN 1 + +#define PGOOD_MASK 1 + +#define PLREG_INT_GRP_STAT_MASK 0x8 +#define PLREG_INT_HI_PRI_EN 0xC +#define PLREG_INT_GRP5_BASE 0x31 +#define PLREG_INT_GRP6_BASE 0x35 +#define PLREG_INT_GRP5_FLAG 0x30 +#define PLREG_INT_GRP6_FLAG 0x34 +#define PLREG_INT_GRP5_PIN_BASE 59 +#define PLREG_INT_GRP6_PIN_BASE 90 + +enum pl_gpio_pn { + IOP_LED1 = 0, + IOP_LED2, + IOP_LED3, + IOP_LED4, + IOP_LED5, + IOP_LED6, + IOP_LED7, + IOP_LED8, + FAN1_INST = 8, + FAN2_INST, + FAN3_INST, + FAN4_INST, + FAN5_INST, + FAN6_INST, + FAN7_INST, + FAN8_INST, + FAN1_FAIL, + FAN2_FAIL, + FAN3_FAIL, + FAN4_FAIL, + FAN5_FAIL, + FAN6_FAIL, + FAN7_FAIL, + FAN8_FAIL, + LED_IDENTIFY = 56, + LED_HEALTH_RED, + LED_HEALTH_AMBER, + PWR_BTN_INT = 59, + UID_PRESS_INT, + SLP_INT, + ACM_FORCE_OFF = 70, + ACM_REMOVED, + ACM_REQ_N, + PSU1_INST, + PSU2_INST, + PSU3_INST, + PSU4_INST, + PSU5_INST, + PSU6_INST, + PSU7_INST, + PSU8_INST, + PSU1_AC, + PSU2_AC, + PSU3_AC, + PSU4_AC, + PSU5_AC, + PSU6_AC, + PSU7_AC, + PSU8_AC, + PSU1_DC, + PSU2_DC, + PSU3_DC, + PSU4_DC, + PSU5_DC, + PSU6_DC, + PSU7_DC, + PSU8_DC +}; + +enum plreg_gpio_pn { + RESET = 192, + NMI_OUT = 193, + VPBTN = 210, + PGOOD, + PERST, + POST_COMPLETE, +}; + +struct gxp_gpio_drvdata { + struct regmap *csm_map; + void __iomem *fn2_vbtn; + struct regmap *fn2_stat; + struct regmap *vuhc0_map; + void __iomem *vbtn; + struct regmap *pl_led; + struct regmap *pl_health; + struct regmap *pl_int; + struct gpio_chip chip; + int irq; +}; + +extern u8 get_psu_inst(void); +extern u8 get_psu_ac(void); +extern u8 get_psu_dc(void); +extern u8 get_fans_installed(void); +extern u8 get_fans_failed(void); + +static int gxp_gpio_csm_get(struct gpio_chip *chip, unsigned int offset) +{ + struct gxp_gpio_drvdata *drvdata = dev_get_drvdata(chip->parent); + int ret = 0; + + switch (offset) { + case 0 ... 31: + regmap_read(drvdata->csm_map, GPIDATL, &ret); + ret = (ret & BIT(offset)) ? 1 : 0; + break; + case 32 ... 63: + regmap_read(drvdata->csm_map, GPIDATH, &ret); + ret = (ret & BIT(offset - 32)) ? 1 : 0; + break; + case 64 ... 95: + regmap_read(drvdata->csm_map, GPODATL, &ret); + ret = (ret & BIT(offset - 64)) ? 1 : 0; + break; + case 96 ... 127: + regmap_read(drvdata->csm_map, GPODATH, &ret); + ret = (ret & BIT(offset - 96)) ? 1 : 0; + break; + case 128 ... 159: + regmap_read(drvdata->csm_map, GPODAT2L, &ret); + ret = (ret & BIT(offset - 128)) ? 1 : 0; + break; + case 160 ... 191: + regmap_read(drvdata->csm_map, GPODAT2H, &ret); + ret = (ret & BIT(offset - 160)) ? 1 : 0; + break; + case 192: + /* SW_RESET */ + regmap_read(drvdata->csm_map, 0x5C, &ret); + ret = (ret & BIT(15)) ? 1 : 0; + break; + default: + break; + } + + return ret; +} + +static void gxp_gpio_csm_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + struct gxp_gpio_drvdata *drvdata = dev_get_drvdata(chip->parent); + u32 tmp; + + switch (offset) { + case 64 ... 95: + /* Keep ownership setting */ + regmap_read(drvdata->csm_map, GPOOWNL, &tmp); + tmp = (tmp & BIT(offset - 64)) ? 1 : 0; + + regmap_update_bits(drvdata->csm_map, GPOOWNL, + BIT(offset - 64), BIT(offset - 64)); + regmap_update_bits(drvdata->csm_map, GPODATL, + BIT(offset - 64), value ? BIT(offset - 64) : 0); + + /* Restore ownership setting */ + regmap_update_bits(drvdata->csm_map, GPOOWNL, + BIT(offset - 64), tmp ? BIT(offset - 64) : 0); + break; + case 96 ... 127: + /* Keep ownership setting */ + regmap_read(drvdata->csm_map, GPOOWNH, &tmp); + tmp = (tmp & BIT(offset - 96)) ? 1 : 0; + + regmap_update_bits(drvdata->csm_map, GPOOWNH, + BIT(offset - 96), BIT(offset - 96)); + regmap_update_bits(drvdata->csm_map, GPODATH, + BIT(offset - 96), value ? BIT(offset - 96) : 0); + + /* Restore ownership setting */ + regmap_update_bits(drvdata->csm_map, GPOOWNH, + BIT(offset - 96), tmp ? BIT(offset - 96) : 0); + break; + case 128 ... 159: + /* Keep ownership setting */ + regmap_read(drvdata->csm_map, GPOOWN2L, &tmp); + tmp = (tmp & BIT(offset - 128)) ? 1 : 0; + + regmap_update_bits(drvdata->csm_map, GPOOWN2L, + BIT(offset - 128), BIT(offset - 128)); + regmap_update_bits(drvdata->csm_map, GPODAT2L, + BIT(offset - 128), value ? BIT(offset - 128) : 0); + + /* Restore ownership setting */ + regmap_update_bits(drvdata->csm_map, GPOOWN2L, + BIT(offset - 128), tmp ? BIT(offset - 128) : 0); + break; + case 160 ... 191: + /* Keep ownership setting */ + regmap_read(drvdata->csm_map, GPOOWN2H, &tmp); + tmp = (tmp & BIT(offset - 160)) ? 1 : 0; + + regmap_update_bits(drvdata->csm_map, GPOOWN2H, + BIT(offset - 160), BIT(offset - 160)); + regmap_update_bits(drvdata->csm_map, GPODAT2H, + BIT(offset - 160), value ? BIT(offset - 160) : 0); + + /* Restore ownership setting */ + regmap_update_bits(drvdata->csm_map, GPOOWN2H, + BIT(offset - 160), tmp ? BIT(offset - 160) : 0); + break; + case 192: + if (value) { + regmap_update_bits(drvdata->csm_map, 0x5C, + BIT(0), BIT(0)); + regmap_update_bits(drvdata->csm_map, 0x5C, + BIT(15), BIT(15)); + } else { + regmap_update_bits(drvdata->csm_map, 0x5C, + BIT(15), 0); + } + break; + default: + break; + } +} + +static int gxp_gpio_csm_get_direction(struct gpio_chip *chip, + unsigned int offset) +{ + int ret = 0; + + switch (offset) { + case 0 ... 63: + ret = GPIO_DIR_IN; + break; + case 64 ... 191: + ret = GPIO_DIR_OUT; + break; + case 192 ... 193: + ret = GPIO_DIR_OUT; + break; + case 194: + ret = GPIO_DIR_IN; + break; + default: + break; + } + + return ret; +} + +static int gxp_gpio_csm_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + int ret = -EOPNOTSUPP; + + switch (offset) { + case 0 ... 63: + ret = 0; + break; + case 194: + ret = 0; + break; + default: + break; + } + + return ret; +} + +static int gxp_gpio_csm_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + int ret = -EOPNOTSUPP; + + switch (offset) { + case 64 ... 191: + case 192 ... 193: + gxp_gpio_csm_set(chip, offset, value); + ret = 0; + break; + default: + break; + } + + return ret; +} + +static int gxp_gpio_vuhc_get(struct gpio_chip *chip, unsigned int offset) +{ + struct gxp_gpio_drvdata *drvdata = dev_get_drvdata(chip->parent); + unsigned int val; + int ret = 0; + + if (offset < 8) { + regmap_read(drvdata->vuhc0_map, 0x64 + 4 * offset, &val); + ret = (val & BIT(13)) ? 1 : 0; + } + + return ret; +} + +static void gxp_gpio_vuhc_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + switch (offset) { + default: + break; + } +} + +static int gxp_gpio_vuhc_get_direction(struct gpio_chip *chip, + unsigned int offset) +{ + int ret = 0; + + switch (offset) { + case 0: + case 1: + case 2: + ret = GPIO_DIR_IN; + break; + default: + break; + } + + return ret; +} + +static int gxp_gpio_vuhc_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + int ret = -EOPNOTSUPP; + + switch (offset) { + case 0: + case 1: + case 2: + ret = 0; + break; + default: + break; + } + + return ret; +} + +static int gxp_gpio_vuhc_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + int ret = -EOPNOTSUPP; + + switch (offset) { + default: + break; + } + + return ret; +} + +static int gxp_gpio_fn2_get(struct gpio_chip *chip, unsigned int offset) +{ + struct gxp_gpio_drvdata *drvdata = dev_get_drvdata(chip->parent); + unsigned int val; + int ret = 0; + + switch (offset) { + case PGOOD: + regmap_read(drvdata->fn2_stat, 0, &val); + ret = (val & BIT(24)) ? 1 : 0; + + break; + case PERST: + regmap_read(drvdata->fn2_stat, 0, &val); + ret = (val & BIT(25)) ? 1 : 0; + + break; + default: + break; + } + + return ret; +} + +static void gxp_gpio_fn2_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + struct gxp_gpio_drvdata *drvdata = dev_get_drvdata(chip->parent); + + switch (offset) { + case VPBTN: + writeb(4, drvdata->vbtn); + writeb(1, drvdata->fn2_vbtn); + break; + default: + break; + } +} + +static int gxp_gpio_fn2_get_direction(struct gpio_chip *chip, + unsigned int offset) +{ + int ret = GPIO_DIR_IN; + + switch (offset) { + case VPBTN: + ret = GPIO_DIR_OUT; + break; + default: + break; + } + + return ret; +} + +static int gxp_gpio_fn2_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + int ret = -EOPNOTSUPP; + + switch (offset) { + case PGOOD: + case PERST: + case POST_COMPLETE: + ret = 0; + break; + default: + break; + } + + return ret; +} + +static int gxp_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + int ret = 0; + + if (offset < 200) + ret = gxp_gpio_csm_get(chip, offset); + else if (offset >= 250 && offset < 300) + ret = gxp_gpio_vuhc_get(chip, offset - 250); + else if (offset >= 300) + ret = gxp_gpio_fn2_get(chip, offset); + + return ret; +} + +static void gxp_gpio_set(struct gpio_chip *chip, + unsigned int offset, int value) +{ + if (offset < 200) + gxp_gpio_csm_set(chip, offset, value); + else if (offset >= 250 && offset < 300) + gxp_gpio_vuhc_set(chip, offset - 250, value); + else if (offset >= 300) + gxp_gpio_fn2_set(chip, offset, value); +} + +static int gxp_gpio_get_direction(struct gpio_chip *chip, + unsigned int offset) +{ + int ret = 0; + + if (offset < 200) + ret = gxp_gpio_csm_get_direction(chip, offset); + else if (offset >= 250 && offset < 300) + ret = gxp_gpio_vuhc_get_direction(chip, offset - 250); + else if (offset >= 300) + ret = gxp_gpio_fn2_get_direction(chip, offset); + + return ret; +} + +static int gxp_gpio_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + int ret = 0; + + if (offset < 200) + ret = gxp_gpio_csm_direction_input(chip, offset); + else if (offset >= 250 && offset < 300) + ret = gxp_gpio_vuhc_direction_input(chip, offset - 250); + else if (offset >= 300) + ret = gxp_gpio_fn2_direction_input(chip, offset); + + return ret; +} + +static int gxp_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + int ret = 0; + + if (offset < 200) + ret = gxp_gpio_csm_direction_output(chip, offset, value); + else if (offset >= 250 && offset < 300) + ret = gxp_gpio_vuhc_direction_output(chip, offset - 250, value); + return ret; +} + +static struct regmap *gxp_gpio_init_regmap(struct platform_device *pdev, + char *reg_name, u8 bits) +{ + struct regmap_config regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + }; + void __iomem *base; + + if (bits == 8) { + regmap_config.reg_bits = 8; + regmap_config.reg_stride = 1; + regmap_config.val_bits = 8; + regmap_config.max_register = 0xff; + } + + base = devm_platform_ioremap_resource_byname(pdev, reg_name); + if (IS_ERR(base)) + return ERR_CAST(base); + + regmap_config.name = reg_name; + + return devm_regmap_init_mmio(&pdev->dev, base, ®map_config); +} + +static void gxp_gpio_fn2_irq_ack(struct irq_data *d) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(d); + struct gxp_gpio_drvdata *drvdata = dev_get_drvdata(chip->parent); + unsigned int val; + + /* Read latched interrupt */ + regmap_read(drvdata->fn2_stat, 0, &val); + /* Clear latched interrupt */ + regmap_update_bits(drvdata->fn2_stat, 0, + 0xFFFF, 0xFFFF); +} + +#define FN2_SEVMASK 4 +static void gxp_gpio_fn2_irq_set_mask(struct irq_data *d, bool set) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(d); + struct gxp_gpio_drvdata *drvdata = dev_get_drvdata(chip->parent); + + regmap_update_bits(drvdata->fn2_stat, FN2_SEVMASK, + BIT(0), set ? BIT(0) : 0); +} + +static void gxp_gpio_fn2_irq_mask(struct irq_data *d) +{ + gxp_gpio_fn2_irq_set_mask(d, false); +} + +static void gxp_gpio_fn2_irq_unmask(struct irq_data *d) +{ + gxp_gpio_fn2_irq_set_mask(d, true); +} + +static int gxp_gpio_fn2_set_type(struct irq_data *d, unsigned int type) +{ + if (type & IRQ_TYPE_LEVEL_MASK) + irq_set_handler_locked(d, handle_level_irq); + else + irq_set_handler_locked(d, handle_edge_irq); + + return 0; +} + +static irqreturn_t gxp_gpio_fn2_irq_handle(int irq, void *_drvdata) +{ + struct gxp_gpio_drvdata *drvdata = (struct gxp_gpio_drvdata *)_drvdata; + unsigned int val, girq; + + regmap_read(drvdata->fn2_stat, 0, &val); + + if (val & PGOOD_MASK) { + girq = irq_find_mapping(drvdata->chip.irq.domain, PGOOD); + generic_handle_irq(girq); + } + + return IRQ_HANDLED; +} + +static int gxp_gpio_pl_get(struct gpio_chip *chip, unsigned int offset) +{ + struct gxp_gpio_drvdata *drvdata = dev_get_drvdata(chip->parent); + unsigned int val; + int ret = 0; + + switch (offset) { + case IOP_LED1 ... IOP_LED8: + regmap_read(drvdata->pl_led, 0x00, &val); + ret = (val & BIT(offset)) ? 1 : 0; + break; + case FAN1_INST ...FAN8_INST: + ret = (get_fans_installed() & BIT((offset - FAN1_INST))) ? 1 : 0; + break; + case FAN1_FAIL ... FAN8_FAIL: + ret = (get_fans_failed() & BIT((offset - FAN1_FAIL))) ? 1 : 0; + break; + case PWR_BTN_INT ... SLP_INT: + regmap_read(drvdata->pl_int, PLREG_INT_GRP5_FLAG, &val); + /* Active low */ + ret = (val & BIT((offset - PWR_BTN_INT) + 16)) ? 0 : 1; + break; + case PSU1_INST ... PSU8_INST: + ret = (get_psu_inst() & BIT((offset - PSU1_INST))) ? 1 : 0; + break; + case PSU1_AC ... PSU8_AC: + ret = (get_psu_ac() & BIT((offset - PSU1_AC))) ? 1 : 0; + break; + case PSU1_DC ... PSU8_DC: + ret = (get_psu_dc() & BIT((offset - PSU1_DC))) ? 1 : 0; + break; + default: + break; + } + + return ret; +} + +static void gxp_gpio_pl_set(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct gxp_gpio_drvdata *drvdata = dev_get_drvdata(chip->parent); + + switch (offset) { + case IOP_LED1 ... IOP_LED8: + regmap_update_bits(drvdata->pl_led, 0x00, BIT(offset), + value == 0 ? 0 : BIT(offset)); + break; + case LED_IDENTIFY: + regmap_update_bits(drvdata->pl_led, 0x01, BIT(7) | BIT(6), + value == 0 ? BIT(7) : BIT(7) | BIT(6)); + break; + case LED_HEALTH_RED: + regmap_update_bits(drvdata->pl_health, 0x0, BIT(7), + value == 0 ? 0 : BIT(7)); + break; + case LED_HEALTH_AMBER: + regmap_update_bits(drvdata->pl_health, 0x0, BIT(6), + value == 0 ? 0 : BIT(6)); + break; + default: + break; + } +} + +static int gxp_gpio_pl_get_direction(struct gpio_chip *chip, unsigned int offset) +{ + int ret = GPIO_DIR_IN; + + switch (offset) { + case IOP_LED1 ... IOP_LED8: + case LED_IDENTIFY ... LED_HEALTH_AMBER: + case ACM_FORCE_OFF: + case ACM_REQ_N: + ret = GPIO_DIR_OUT; + break; + default: + break; + } + + return ret; +} + +static int gxp_gpio_pl_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + int ret = -EOPNOTSUPP; + + switch (offset) { + case 8 ... 55: + ret = 0; + break; + case 59 ... 65: + ret = 0; + break; + default: + break; + } + + return ret; +} + +static int gxp_gpio_pl_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + int ret = -EOPNOTSUPP; + + switch (offset) { + case IOP_LED1 ... IOP_LED8: + case LED_IDENTIFY ... LED_HEALTH_AMBER: + case ACM_FORCE_OFF: + case ACM_REQ_N: + gxp_gpio_pl_set(chip, offset, value); + ret = 0; + break; + default: + break; + } + + return ret; +} + +static void gxp_gpio_pl_irq_ack(struct irq_data *d) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(d); + struct gxp_gpio_drvdata *drvdata = dev_get_drvdata(chip->parent); + unsigned int val; + + /* Read latched interrupt for group 5 */ + regmap_read(drvdata->pl_int, PLREG_INT_GRP5_FLAG, &val); + /* Clear latched interrupt */ + regmap_update_bits(drvdata->pl_int, PLREG_INT_GRP5_FLAG, + 0xFF, 0xFF); + + /* Read latched interrupt for group 6 */ + regmap_read(drvdata->pl_int, PLREG_INT_GRP6_FLAG, &val); + /* Clear latched interrupt */ + regmap_update_bits(drvdata->pl_int, PLREG_INT_GRP6_FLAG, + 0xFF, 0xFF); +} + +static void gxp_gpio_pl_irq_set_mask(struct irq_data *d, bool set) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(d); + struct gxp_gpio_drvdata *drvdata = dev_get_drvdata(chip->parent); + + regmap_update_bits(drvdata->pl_int, PLREG_INT_GRP5_BASE, + BIT(0) | BIT(2), set ? 0 : BIT(0) | BIT(2)); + + regmap_update_bits(drvdata->pl_int, PLREG_INT_GRP6_BASE, + BIT(2), set ? 0 : BIT(2)); +} + +static void gxp_gpio_pl_irq_mask(struct irq_data *d) +{ + gxp_gpio_pl_irq_set_mask(d, false); +} + +static void gxp_gpio_pl_irq_unmask(struct irq_data *d) +{ + gxp_gpio_pl_irq_set_mask(d, true); +} + +static int gxp_gpio_irq_init_hw(struct gpio_chip *chip) +{ + struct gxp_gpio_drvdata *drvdata = dev_get_drvdata(chip->parent); + + regmap_update_bits(drvdata->pl_int, PLREG_INT_GRP5_BASE, + BIT(0) | BIT(2), 0); + + regmap_update_bits(drvdata->pl_int, PLREG_INT_GRP6_BASE, + BIT(2), 0); + + return 0; +} + +static int gxp_gpio_pl_set_type(struct irq_data *d, unsigned int type) +{ + if (type & IRQ_TYPE_LEVEL_MASK) + irq_set_handler_locked(d, handle_level_irq); + else + irq_set_handler_locked(d, handle_edge_irq); + + return 0; +} + +static irqreturn_t gxp_gpio_pl_irq_handle(int irq, void *_drvdata) +{ + struct gxp_gpio_drvdata *drvdata = (struct gxp_gpio_drvdata *)_drvdata; + unsigned int val, girq, i; + + /* Check group 5 interrupts */ + + regmap_read(drvdata->pl_int, PLREG_INT_GRP5_FLAG, &val); + + if (val) { + for_each_set_bit(i, (unsigned long *)&val, 3) { + girq = irq_find_mapping(drvdata->chip.irq.domain, + i + PLREG_INT_GRP5_PIN_BASE); + generic_handle_irq(girq); + } + + /* Clear latched interrupt */ + regmap_update_bits(drvdata->pl_int, PLREG_INT_GRP5_FLAG, + 0xFF, 0xFF); + regmap_update_bits(drvdata->pl_int, PLREG_INT_GRP5_BASE, + BIT(0) | BIT(2), 0); + } + + /* Check group 6 interrupts */ + + regmap_read(drvdata->pl_int, PLREG_INT_GRP6_FLAG, &val); + + if (val) { + for_each_set_bit(i, (unsigned long *)&val, 3) { + girq = irq_find_mapping(drvdata->chip.irq.domain, + i + PLREG_INT_GRP6_PIN_BASE); + generic_handle_irq(girq); + } + + /* Clear latched interrupt */ + regmap_update_bits(drvdata->pl_int, PLREG_INT_GRP6_FLAG, + 0xFF, 0xFF); + regmap_update_bits(drvdata->pl_int, PLREG_INT_GRP6_BASE, + BIT(2), 0); + } + + return IRQ_HANDLED; +} + +static struct irq_chip gxp_gpio_irqchip = { + .name = "gxp_fn2", + .irq_ack = gxp_gpio_fn2_irq_ack, + .irq_mask = gxp_gpio_fn2_irq_mask, + .irq_unmask = gxp_gpio_fn2_irq_unmask, + .irq_set_type = gxp_gpio_fn2_set_type, +}; + +static struct gpio_chip common_chip = { + .label = "gxp_gpio", + .owner = THIS_MODULE, + .get = gxp_gpio_get, + .set = gxp_gpio_set, + .get_direction = gxp_gpio_get_direction, + .direction_input = gxp_gpio_direction_input, + .direction_output = gxp_gpio_direction_output, + .base = 0, +}; + +static struct gpio_chip plreg_chip = { + .label = "gxp_gpio_plreg", + .owner = THIS_MODULE, + .get = gxp_gpio_pl_get, + .set = gxp_gpio_pl_set, + .get_direction = gxp_gpio_pl_get_direction, + .direction_input = gxp_gpio_pl_direction_input, + .direction_output = gxp_gpio_pl_direction_output, + .base = -1, +}; + +static struct irq_chip gxp_plreg_irqchip = { + .name = "gxp_plreg", + .irq_ack = gxp_gpio_pl_irq_ack, + .irq_mask = gxp_gpio_pl_irq_mask, + .irq_unmask = gxp_gpio_pl_irq_unmask, + .irq_set_type = gxp_gpio_pl_set_type, +}; + +static int gxp_gpio_init(struct platform_device *pdev) +{ + struct gxp_gpio_drvdata *drvdata = dev_get_drvdata(&pdev->dev); + struct gpio_irq_chip *girq; + int ret; + + drvdata->csm_map = gxp_gpio_init_regmap(pdev, "csm", 32); + if (IS_ERR(drvdata->csm_map)) + return dev_err_probe(&pdev->dev, PTR_ERR(drvdata->csm_map), + "failed to map csm_handle\n"); + + drvdata->fn2_vbtn = devm_platform_ioremap_resource_byname(pdev, "fn2-vbtn"); + if (IS_ERR(drvdata->fn2_vbtn)) + return dev_err_probe(&pdev->dev, PTR_ERR(drvdata->fn2_vbtn), + "failed to map fn2_vbtn\n"); + + drvdata->fn2_stat = gxp_gpio_init_regmap(pdev, "fn2-stat", 32); + if (IS_ERR(drvdata->fn2_stat)) + return dev_err_probe(&pdev->dev, PTR_ERR(drvdata->fn2_stat), + "failed to map fn2_stat\n"); + + drvdata->vuhc0_map = gxp_gpio_init_regmap(pdev, "vuhc", 32); + if (IS_ERR(drvdata->vuhc0_map)) + return dev_err_probe(&pdev->dev, PTR_ERR(drvdata->vuhc0_map), + "failed to map vuhc0_map\n"); + + drvdata->vbtn = devm_platform_ioremap_resource_byname(pdev, "vbtn"); + if (IS_ERR(drvdata->vbtn)) + return dev_err_probe(&pdev->dev, PTR_ERR(drvdata->vbtn), + "failed to map vbtn\n"); + girq = &drvdata->chip.irq; + girq->chip = &gxp_gpio_irqchip; + girq->parent_handler = NULL; + girq->num_parents = 0; + girq->parents = NULL; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_edge_irq; + + ret = platform_get_irq(pdev, 0); + if (ret < 0) { + dev_err(&pdev->dev, "Get irq from platform fail - %d\n", ret); + return ret; + } + drvdata->irq = ret; + + ret = devm_request_irq(&pdev->dev, drvdata->irq, gxp_gpio_fn2_irq_handle, + IRQF_SHARED, "gxp-fn2", drvdata); + if (ret < 0) { + dev_err(&pdev->dev, "IRQ handler failed - %d\n", ret); + return ret; + } + drvdata->chip = common_chip; + drvdata->chip.ngpio = 300; + + drvdata->chip.parent = &pdev->dev; + ret = devm_gpiochip_add_data(&pdev->dev, &drvdata->chip, NULL); + if (ret < 0) + dev_err(&pdev->dev, + "Could not register gpiochip for fn2, %d\n", ret); + dev_info(&pdev->dev, "HPE GXP FN2 driver loaded.\n"); + + return 0; +} + +static int gxp_gpio_pl_init(struct platform_device *pdev) +{ + struct gxp_gpio_drvdata *drvdata = dev_get_drvdata(&pdev->dev); + struct gpio_irq_chip *girq; + int ret; + unsigned int val; + + drvdata->pl_led = gxp_gpio_init_regmap(pdev, "pl-led", 8); + if (IS_ERR(drvdata->pl_led)) + return dev_err_probe(&pdev->dev, PTR_ERR(drvdata->pl_int), + "failed to map pl_led\n"); + + drvdata->pl_health = gxp_gpio_init_regmap(pdev, "pl-health", 8); + if (IS_ERR(drvdata->pl_health)) + return dev_err_probe(&pdev->dev, PTR_ERR(drvdata->pl_int), + "failed to map pl_health\n"); + + drvdata->pl_int = gxp_gpio_init_regmap(pdev, "pl-int", 8); + if (IS_ERR(drvdata->pl_int)) + return dev_err_probe(&pdev->dev, PTR_ERR(drvdata->pl_int), + "failed to map pl_int\n"); + + drvdata->chip = plreg_chip; + drvdata->chip.ngpio = 100; + drvdata->chip.parent = &pdev->dev; + + girq = &drvdata->chip.irq; + girq->chip = &gxp_plreg_irqchip; + girq->parent_handler = NULL; + girq->num_parents = 0; + girq->parents = NULL; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_edge_irq; + + girq->init_hw = gxp_gpio_irq_init_hw; + + ret = devm_gpiochip_add_data(&pdev->dev, &drvdata->chip, drvdata); + if (ret < 0) + dev_err(&pdev->dev, "Could not register gpiochip for plreg, %d\n", + ret); + + regmap_update_bits(drvdata->pl_int, PLREG_INT_HI_PRI_EN, + BIT(4) | BIT(5), BIT(4) | BIT(5)); + regmap_update_bits(drvdata->pl_int, PLREG_INT_GRP_STAT_MASK, + BIT(4) | BIT(5), 0x00); + regmap_read(drvdata->pl_int, PLREG_INT_HI_PRI_EN, &val); + regmap_read(drvdata->pl_int, PLREG_INT_GRP_STAT_MASK, &val); + + ret = platform_get_irq(pdev, 0); + if (ret < 0) { + dev_err(&pdev->dev, "Get irq from platform fail - %d\n", ret); + return ret; + } + + drvdata->irq = ret; + + ret = devm_request_irq(&pdev->dev, drvdata->irq, gxp_gpio_pl_irq_handle, + IRQF_SHARED, "gxp-pl", drvdata); + if (ret < 0) { + dev_err(&pdev->dev, "IRQ handler failed - %d\n", ret); + return ret; + } + + return 0; +} + +static const struct of_device_id gxp_gpio_of_match[] = { + { .compatible = "hpe,gxp-gpio"}, + { .compatible = "hpe,gxp-gpio-pl"}, + {} +}; +MODULE_DEVICE_TABLE(of, gxp_gpio_of_match); + +static int gxp_gpio_probe(struct platform_device *pdev) +{ + int ret; + struct gxp_gpio_drvdata *drvdata; + struct device *dev = &pdev->dev; + struct device *parent; + const struct of_device_id *match = of_match_device(gxp_gpio_of_match, dev); + + if (!match) { + dev_err(dev, "device is not compatible"); + return -EINVAL; + } + + parent = dev->parent; + if (!parent) { + dev_err(dev, "no parent\n"); + return -ENODEV; + } + + drvdata = devm_kzalloc(&pdev->dev, sizeof(struct gxp_gpio_drvdata), + GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + platform_set_drvdata(pdev, drvdata); + + if (strcmp(match->compatible, "hpe,gxp-gpio-pl") == 0) + ret = gxp_gpio_pl_init(pdev); + else + ret = gxp_gpio_init(pdev); + + return ret; +} + +static struct platform_driver gxp_gpio_driver = { + .driver = { + .name = "gxp-gpio", + .of_match_table = gxp_gpio_of_match, + }, + .probe = gxp_gpio_probe, +}; +module_platform_driver(gxp_gpio_driver); + +MODULE_AUTHOR("Nick Hawkins "); +MODULE_DESCRIPTION("GPIO interface for GXP"); +MODULE_LICENSE("GPL"); From patchwork Tue Apr 18 15:28:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hawkins, Nick" X-Patchwork-Id: 675319 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9322C77B7D for ; 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Tue, 18 Apr 2023 15:31:37 +0000 Received: from p1lg14886.dc01.its.hpecorp.net (unknown [10.119.18.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by p1lg14880.it.hpe.com (Postfix) with ESMTPS id 7B6DC800217; Tue, 18 Apr 2023 15:31:36 +0000 (UTC) Received: from hpe.com (unknown [16.231.227.36]) by p1lg14886.dc01.its.hpecorp.net (Postfix) with ESMTP id CAE0B816D3A; Tue, 18 Apr 2023 15:31:35 +0000 (UTC) From: nick.hawkins@hpe.com To: verdun@hpe.com, nick.hawkins@hpe.com, linus.walleij@linaro.org, brgl@bgdev.pl, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, jdelvare@suse.com, linux@roeck-us.net, linux@armlinux.org.uk, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v1 2/9] hwmon: (gxp_fan_ctrl) Give GPIO access to fan data Date: Tue, 18 Apr 2023 10:28:17 -0500 Message-Id: <20230418152824.110823-3-nick.hawkins@hpe.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230418152824.110823-1-nick.hawkins@hpe.com> References: <20230418152824.110823-1-nick.hawkins@hpe.com> X-Proofpoint-GUID: IymkpW-Evmgrn-rdu4CClDYAe9CzoyTs X-Proofpoint-ORIG-GUID: IymkpW-Evmgrn-rdu4CClDYAe9CzoyTs X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-18_11,2023-04-18_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 impostorscore=0 mlxscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=999 phishscore=0 priorityscore=1501 clxscore=1015 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304180132 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Nick Hawkins The fan driver has access to the IO that reports fan presence. Add the ability for other drivers such as GPIO to call in to get fan information. Also remove the system power check as the GPIO driver needs it to report power state. Signed-off-by: Nick Hawkins --- drivers/hwmon/gxp-fan-ctrl.c | 58 +++++++++++++++--------------------- 1 file changed, 24 insertions(+), 34 deletions(-) diff --git a/drivers/hwmon/gxp-fan-ctrl.c b/drivers/hwmon/gxp-fan-ctrl.c index 0014b8b0fd41..a8fcea98cc55 100644 --- a/drivers/hwmon/gxp-fan-ctrl.c +++ b/drivers/hwmon/gxp-fan-ctrl.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (C) 2022 Hewlett-Packard Enterprise Development Company, L.P. */ +/* Copyright (C) 2023 Hewlett-Packard Enterprise Development Company, L.P. */ #include #include @@ -11,15 +11,14 @@ #define OFS_FAN_INST 0 /* Is 0 because plreg base will be set at INST */ #define OFS_FAN_FAIL 2 /* Is 2 bytes after base */ -#define OFS_SEVSTAT 0 /* Is 0 because fn2 base will be set at SEVSTAT */ -#define POWER_BIT 24 struct gxp_fan_ctrl_drvdata { void __iomem *base; void __iomem *plreg; - void __iomem *fn2; }; +struct gxp_fan_ctrl_drvdata *drvdata; + static bool fan_installed(struct device *dev, int fan) { struct gxp_fan_ctrl_drvdata *drvdata = dev_get_drvdata(dev); @@ -30,6 +29,16 @@ static bool fan_installed(struct device *dev, int fan) return !!(val & BIT(fan)); } +u8 get_fans_installed(void) +{ + static u8 val; + + val = readb(drvdata->plreg + OFS_FAN_INST); + + return val; +} +EXPORT_SYMBOL(get_fans_installed); + static long fan_failed(struct device *dev, int fan) { struct gxp_fan_ctrl_drvdata *drvdata = dev_get_drvdata(dev); @@ -40,19 +49,19 @@ static long fan_failed(struct device *dev, int fan) return !!(val & BIT(fan)); } -static long fan_enabled(struct device *dev, int fan) +u8 get_fans_failed(void) { - struct gxp_fan_ctrl_drvdata *drvdata = dev_get_drvdata(dev); - u32 val; + static u8 val; - /* - * Check the power status as if the platform is off the value - * reported for the PWM will be incorrect. Report fan as - * disabled. - */ - val = readl(drvdata->fn2 + OFS_SEVSTAT); + val = readb(drvdata->plreg + OFS_FAN_FAIL); + + return val; +} +EXPORT_SYMBOL(get_fans_failed); - return !!((val & BIT(POWER_BIT)) && fan_installed(dev, fan)); +static long fan_enabled(struct device *dev, int fan) +{ + return !!(fan_installed(dev, fan)); } static int gxp_pwm_write(struct device *dev, u32 attr, int channel, long val) @@ -98,20 +107,8 @@ static int gxp_fan_read(struct device *dev, u32 attr, int channel, long *val) static int gxp_pwm_read(struct device *dev, u32 attr, int channel, long *val) { struct gxp_fan_ctrl_drvdata *drvdata = dev_get_drvdata(dev); - u32 reg; - - /* - * Check the power status of the platform. If the platform is off - * the value reported for the PWM will be incorrect. In this case - * report a PWM of zero. - */ - reg = readl(drvdata->fn2 + OFS_SEVSTAT); - - if (reg & BIT(POWER_BIT)) - *val = fan_installed(dev, channel) ? readb(drvdata->base + channel) : 0; - else - *val = 0; + *val = fan_installed(dev, channel) ? readb(drvdata->base + channel) : 0; return 0; } @@ -198,7 +195,6 @@ static const struct hwmon_chip_info gxp_fan_ctrl_chip_info = { static int gxp_fan_ctrl_probe(struct platform_device *pdev) { - struct gxp_fan_ctrl_drvdata *drvdata; struct device *dev = &pdev->dev; struct device *hwmon_dev; @@ -218,12 +214,6 @@ static int gxp_fan_ctrl_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(drvdata->plreg), "failed to map plreg\n"); - drvdata->fn2 = devm_platform_ioremap_resource_byname(pdev, - "fn2"); - if (IS_ERR(drvdata->fn2)) - return dev_err_probe(dev, PTR_ERR(drvdata->fn2), - "failed to map fn2\n"); - hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev, "hpe_gxp_fan_ctrl", drvdata, From patchwork Tue Apr 18 15:28:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hawkins, Nick" X-Patchwork-Id: 675320 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C40CBC7EE22 for ; Tue, 18 Apr 2023 15:32:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232315AbjDRPcM (ORCPT ); Tue, 18 Apr 2023 11:32:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232304AbjDRPcK (ORCPT ); Tue, 18 Apr 2023 11:32:10 -0400 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8444E10D8; Tue, 18 Apr 2023 08:32:07 -0700 (PDT) Received: from pps.filterd (m0148663.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 33IEutOL000767; Tue, 18 Apr 2023 15:31:38 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : subject : date : message-id : in-reply-to : references; s=pps0720; bh=Gkats5dbf8WnZT7mgL+e/Kl1YGcTI9hrVc/iSuuyick=; b=VdC1e+3co4/H4atM6L5OK8B5z/ab0tCVn2gpy/jHNe/7BsHRIPBCZSxrbeFrIYoQVf+Y 1Q5ZVRp1LfWDm9NXI+pTBa+l6PCsK5iqBzA0vvjDHmLcjWySmPqQuUaZ/XV9E2V9W04X FKHQXJAKFn+P7TVYcy88C7MhMoodUr+G5cRJAqeq4qr5xu161Argsv2wc/GU1P3ikgK4 fxijPccXLiStcsBEh853kLlL6f/Pr6DS6kcA93Jluw92jPMOfR903mDQFWfClkwGw/G7 Gzv2e/oacO7F5ov32eYztKnEAMCHzhP/qQ2TMiYf/uZJCVt6cgaRCJ4r2+K0tQMWsnrU fQ== Received: from p1lg14881.it.hpe.com (p1lg14881.it.hpe.com [16.230.97.202]) by mx0a-002e3701.pphosted.com (PPS) with ESMTPS id 3q1wdw0b8x-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 18 Apr 2023 15:31:37 +0000 Received: from p1lg14886.dc01.its.hpecorp.net (unknown [10.119.18.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by p1lg14881.it.hpe.com (Postfix) with ESMTPS id 2FD4E806B40; Tue, 18 Apr 2023 15:31:37 +0000 (UTC) Received: from hpe.com (unknown [16.231.227.36]) by p1lg14886.dc01.its.hpecorp.net (Postfix) with ESMTP id 7671781532D; Tue, 18 Apr 2023 15:31:36 +0000 (UTC) From: nick.hawkins@hpe.com To: verdun@hpe.com, nick.hawkins@hpe.com, linus.walleij@linaro.org, brgl@bgdev.pl, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, jdelvare@suse.com, linux@roeck-us.net, linux@armlinux.org.uk, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v1 3/9] hwmon: (gxp-psu) Add driver to read HPE PSUs Date: Tue, 18 Apr 2023 10:28:18 -0500 Message-Id: <20230418152824.110823-4-nick.hawkins@hpe.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230418152824.110823-1-nick.hawkins@hpe.com> References: <20230418152824.110823-1-nick.hawkins@hpe.com> X-Proofpoint-ORIG-GUID: Fn671cNE7gO5dLU5ieyZxcCyaATF0vl- X-Proofpoint-GUID: Fn671cNE7gO5dLU5ieyZxcCyaATF0vl- X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-18_11,2023-04-18_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 suspectscore=0 mlxlogscore=999 phishscore=0 bulkscore=0 malwarescore=0 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304180132 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Nick Hawkins The GXP SoC can support up to 8 power supplies that it can communicate with via i2c. The GXP PSU driver will provide a method for the GPIO driver with info it reads to be available to the host. Signed-off-by: Nick Hawkins --- drivers/hwmon/Kconfig | 10 + drivers/hwmon/Makefile | 1 + drivers/hwmon/gxp-psu.c | 773 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 784 insertions(+) create mode 100644 drivers/hwmon/gxp-psu.c diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index 5b3b76477b0e..3b56690ea089 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -723,6 +723,16 @@ config SENSORS_GXP_FAN_CTRL The GXP controls fan function via the CPLD through the use of PWM registers. This driver reports status and pwm setting of the fans. +config SENSORS_GXP_PSU + tristate "HPE GXP PSU driver" + depends on ARCH_HPE_GXP || COMPILE_TEST + depends on I2C + help + If you say yes you will get support for GXP psu driver support. The GXP + gets PSU presence and state information from the CPLD. The GXP gets PSU + data via i2c. It provides a method for other drivers to call into get + PSU presence information. + config SENSORS_HIH6130 tristate "Honeywell Humidicon HIH-6130 humidity/temperature sensor" depends on I2C diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index 88712b5031c8..6c84cd52d0d3 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -84,6 +84,7 @@ obj-$(CONFIG_SENSORS_GL520SM) += gl520sm.o obj-$(CONFIG_SENSORS_GSC) += gsc-hwmon.o obj-$(CONFIG_SENSORS_GPIO_FAN) += gpio-fan.o obj-$(CONFIG_SENSORS_GXP_FAN_CTRL) += gxp-fan-ctrl.o +obj-$(CONFIG_SENSORS_GXP_PSU) += gxp-psu.o obj-$(CONFIG_SENSORS_HIH6130) += hih6130.o obj-$(CONFIG_SENSORS_ULTRA45) += ultra45_env.o obj-$(CONFIG_SENSORS_I5500) += i5500_temp.o diff --git a/drivers/hwmon/gxp-psu.c b/drivers/hwmon/gxp-psu.c new file mode 100644 index 000000000000..e4217200c34b --- /dev/null +++ b/drivers/hwmon/gxp-psu.c @@ -0,0 +1,773 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (C) 2023 Hewlett-Packard Enterpise Development Company, L.P. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define READ_REG_CMD 0x00 +#define READ_FRU_CMD 0x22 +#define REG_IN_VOL 0x10 +#define REG_IN_CUR 0x11 +#define REG_IN_PWR 0x12 +#define REG_OUT_VOL 0x20 +#define REG_OUT_CUR 0x21 +#define REG_OUT_PWR 0x22 +#define REG_FAN_SPEED 0x40 +#define REG_INLET_TEMP 0x42 +#define MAX_PSU 0x08 +#define INPUT_CHAN 0 + +#define L_IN_POWER "pin1" +#define L_OUT_POWER "pout1" +#define L_IN_IN "vin" +#define L_OUT_IN "vout1" +#define L_FAN "fan1" +#define L_IN_CURR "iin" +#define L_OUT_CURR "iout1" +#define L_TEMP "temp1" + +static void __iomem *pl_psu; + +struct gxp_psu_drvdata { + struct i2c_client *client; + u16 input_power; + u16 input_voltage; + u16 input_current; + u16 output_power; + u16 output_voltage; + u16 output_current; + s16 inlet_temp; + u16 fan_speed; + u8 id; + struct dentry *debugfs; + u8 spare_part[10]; + u8 product_name[26]; + u8 serial_number[14]; + u8 product_manufacturer[3]; + bool present; /* psu can be physically removed */ + struct mutex update_lock; + struct device *hwmon_dev; +}; + +static u8 psucount; +struct gxp_psu_drvdata *psus[MAX_PSU] = { NULL }; + +u8 get_psu_inst(void) +{ + if (!pl_psu) + return 0; + + return readb(pl_psu); +} +EXPORT_SYMBOL(get_psu_inst); + +u8 get_psu_ac(void) +{ + if (!pl_psu) + return 0; + + return readb(pl_psu + 0x02); +} +EXPORT_SYMBOL(get_psu_ac); + +u8 get_psu_dc(void) +{ + if (!pl_psu) + return 0; + + return readb(pl_psu + 0x03); +} +EXPORT_SYMBOL(get_psu_dc); + +void update_presence(u8 id) +{ + unsigned int i; + unsigned long temp = (unsigned long)readb(pl_psu); + + for_each_set_bit(i, &temp, 8) { + if (i == id) + psus[id]->present = true; + } + + temp = ~temp; + for_each_set_bit(i, &temp, 8) { + if (i == id) + psus[id]->present = false; + } +} + +static unsigned char cal_checksum(unsigned char *buf, unsigned long size) +{ + unsigned char sum = 0; + + while (size > 0) { + sum += (*(buf++)); + size--; + } + return ((~sum) + 1); +} + +static unsigned char valid_checksum(unsigned char *buf, unsigned long size) +{ + unsigned char sum = 0; + + while (size > 0) { + sum += (*(buf++)); + size--; + } + return sum; +} + +static int psu_read_fru(struct gxp_psu_drvdata *drvdata, + u8 offset, u8 length, u8 *value) +{ + struct i2c_client *client = drvdata->client; + unsigned char buf_tx[4] = {(client->addr << 1), READ_FRU_CMD, offset, length}; + unsigned char tx[4] = {0}; + unsigned char chksum = cal_checksum(buf_tx, 4); + int ret = 0; + struct i2c_msg msgs[2] = {0}; + + update_presence(drvdata->id); + + value[0] = '\0'; + + if (!drvdata->present) + return -EOPNOTSUPP; + + tx[0] = READ_FRU_CMD; + tx[1] = offset; + tx[2] = length; + tx[3] = chksum; + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].buf = tx; + msgs[0].len = 4; + msgs[1].addr = client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].buf = value; + msgs[1].len = length; + + mutex_lock(&drvdata->update_lock); + ret = i2c_transfer(client->adapter, msgs, 2); + mutex_unlock(&drvdata->update_lock); + if (ret < 0) { + dev_err(&client->dev, + "gxppsu_i2c_tx_fail addr:0x%x offest:0x%x length:0x%x chk:0x%x ret:0x%x\n", + client->addr, offset, length, chksum, ret); + return ret; + } + + return ret; +} + +static int psu_read_reg_word(struct gxp_psu_drvdata *drvdata, + u8 reg, u16 *value) +{ + struct i2c_client *client = drvdata->client; + unsigned char buf_tx[3] = {(client->addr << 1), READ_REG_CMD, reg}; + unsigned char buf_rx[3] = {0}; + unsigned char tx[3] = {0}; + unsigned char rx[3] = {0}; + unsigned char chksum = cal_checksum(buf_tx, 3); + struct i2c_msg msgs[2] = {0}; + int ret = 0; + + tx[0] = 0; + tx[1] = reg; + tx[2] = chksum; + + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].buf = tx; + msgs[0].len = 3; + msgs[1].addr = client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].buf = rx; + msgs[1].len = 3; + mutex_lock(&drvdata->update_lock); + ret = i2c_transfer(client->adapter, msgs, 2); + mutex_unlock(&drvdata->update_lock); + if (ret < 0) { + dev_err(&client->dev, + "gxppsu_i2c_tx_fail addr:0x%x reg:0x%x chk:0x%x ret:0x%x\n", + client->addr, reg, chksum, ret); + return ret; + } + + buf_rx[0] = rx[0]; + buf_rx[1] = rx[1]; + buf_rx[2] = rx[2]; + if (valid_checksum(buf_rx, 3) != 0) { + dev_err(&client->dev, + "gxppsu_checksum_fail addr:0x%x reg:0x%x, data:%x %x %x\n", + client->addr, reg, rx[0], rx[1], rx[2]); + return -EAGAIN; + } + + *value = rx[0] + (rx[1] << 8); + + return ret; +} + +static int gxppsu_update_client(struct device *dev, u8 reg) +{ + struct gxp_psu_drvdata *drvdata = dev_get_drvdata(dev); + int ret = 0; + + update_presence(drvdata->id); + + if (!drvdata->present) + return -EOPNOTSUPP; + + switch (reg) { + case REG_IN_PWR: + ret = psu_read_reg_word(drvdata, REG_IN_PWR, + &drvdata->input_power); + break; + case REG_IN_VOL: + ret = psu_read_reg_word(drvdata, REG_IN_VOL, + &drvdata->input_voltage); + break; + case REG_IN_CUR: + ret = psu_read_reg_word(drvdata, REG_IN_CUR, + &drvdata->input_current); + break; + case REG_OUT_PWR: + ret = psu_read_reg_word(drvdata, REG_OUT_PWR, + &drvdata->output_power); + break; + case REG_OUT_VOL: + ret = psu_read_reg_word(drvdata, REG_OUT_VOL, + &drvdata->output_voltage); + break; + case REG_OUT_CUR: + ret = psu_read_reg_word(drvdata, REG_OUT_CUR, + &drvdata->output_current); + break; + case REG_INLET_TEMP: + ret = psu_read_reg_word(drvdata, REG_INLET_TEMP, + &drvdata->inlet_temp); + break; + case REG_FAN_SPEED: + ret = psu_read_reg_word(drvdata, REG_FAN_SPEED, + &drvdata->fan_speed); + break; + default: + dev_err(&drvdata->client->dev, "gxppsu_error_reg 0x%x\n", reg); + return -EOPNOTSUPP; + } + + return ret; +} + +static int gxp_psu_get_power_input(struct device *dev, u32 attr, int channel, + long *val) +{ + struct gxp_psu_drvdata *drvdata = dev_get_drvdata(dev); + int ret = 0; + u8 reg; + + if (channel == INPUT_CHAN) + reg = REG_IN_PWR; + else + reg = REG_OUT_PWR; + + ret = gxppsu_update_client(dev, reg); + if (ret < 0) + return ret; + + if (channel == INPUT_CHAN) + *val = drvdata->input_power; + else + *val = drvdata->output_power; + + return 0; +} + +static int gxp_psu_get_in_input(struct device *dev, u32 attr, int channel, + long *val) +{ + struct gxp_psu_drvdata *drvdata = dev_get_drvdata(dev); + int ret = 0; + u8 reg; + + if (channel == INPUT_CHAN) + reg = REG_IN_VOL; + else + reg = REG_OUT_VOL; + + ret = gxppsu_update_client(dev, reg); + if (ret < 0) + return ret; + + if (channel == INPUT_CHAN) + *val = drvdata->input_voltage; + else + *val = drvdata->output_voltage; + + return 0; +} + +static int gxp_psu_get_curr_input(struct device *dev, u32 attr, int channel, + long *val) +{ + struct gxp_psu_drvdata *drvdata = dev_get_drvdata(dev); + int ret = 0; + u8 reg; + + if (channel == INPUT_CHAN) + reg = REG_IN_CUR; + else + reg = REG_OUT_CUR; + + ret = gxppsu_update_client(dev, reg); + + if (ret < 0) + return ret; + + if (channel == INPUT_CHAN) + *val = drvdata->input_current; + else + *val = drvdata->output_current; + + return 0; +} + +static int gxp_psu_get_temp_input(struct device *dev, u32 attr, int channel, + long *val) +{ + struct gxp_psu_drvdata *drvdata = dev_get_drvdata(dev); + int ret = 0; + u8 reg = REG_INLET_TEMP; + + ret = gxppsu_update_client(dev, reg); + if (ret < 0) + return ret; + + *val = drvdata->inlet_temp; + + return 0; +}; + +static int gxp_psu_get_fan_input(struct device *dev, u32 attr, int channel, + long *val) +{ + struct gxp_psu_drvdata *drvdata = dev_get_drvdata(dev); + int ret = 0; + u8 reg = REG_FAN_SPEED; + + ret = gxppsu_update_client(dev, reg); + if (ret < 0) + return ret; + + *val = drvdata->fan_speed; + + return 0; +} + +void swapbytes(void *input, size_t len) +{ + unsigned int i; + unsigned char *in = (unsigned char *)input, tmp; + + for (i = 0; i < len / 2; i++) { + tmp = *(in + i); + *(in + i) = *(in + len - i - 1); + *(in + len - i - 1) = tmp; + } +} + +static const struct hwmon_channel_info *gxp_psu_info[] = { + HWMON_CHANNEL_INFO(power, + HWMON_P_INPUT | HWMON_P_LABEL, + HWMON_P_INPUT | HWMON_P_LABEL), + HWMON_CHANNEL_INFO(in, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL), + HWMON_CHANNEL_INFO(fan, + HWMON_F_INPUT | HWMON_F_LABEL), + HWMON_CHANNEL_INFO(curr, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL), + HWMON_CHANNEL_INFO(temp, + HWMON_T_INPUT | HWMON_T_LABEL), + NULL +}; + +static umode_t gxp_psu_is_visible(const void *_data, enum hwmon_sensor_types type, + u32 attr, int channel) +{ + umode_t mode = 0; + + switch (type) { + case hwmon_power: + switch (attr) { + case hwmon_power_input: + case hwmon_power_label: + mode = 0444; + break; + default: + break; + } + break; + case hwmon_in: + switch (attr) { + case hwmon_in_input: + case hwmon_in_label: + mode = 0444; + break; + default: + break; + } + break; + case hwmon_fan: + switch (attr) { + case hwmon_fan_input: + case hwmon_fan_label: + mode = 0444; + break; + default: + break; + } + break; + case hwmon_curr: + switch (attr) { + case hwmon_curr_input: + case hwmon_curr_label: + mode = 0444; + break; + default: + break; + } + break; + case hwmon_temp: + switch (attr) { + case hwmon_temp_input: + case hwmon_temp_label: + mode = 0444; + break; + default: + break; + } + break; + default: + break; + } + + return mode; +} + +static int gxp_psu_read(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long *val) +{ + switch (type) { + case hwmon_power: + switch (attr) { + case hwmon_power_input: + return gxp_psu_get_power_input(dev, attr, channel, + val); + default: + break; + } + break; + case hwmon_in: + switch (attr) { + case hwmon_in_input: + return gxp_psu_get_in_input(dev, attr, channel, + val); + default: + break; + } + break; + case hwmon_fan: + switch (attr) { + case hwmon_fan_input: + return gxp_psu_get_fan_input(dev, attr, channel, + val); + default: + break; + } + break; + case hwmon_curr: + switch (attr) { + case hwmon_curr_input: + return gxp_psu_get_curr_input(dev, attr, channel, + val); + default: + break; + } + break; + case hwmon_temp: + switch (attr) { + case hwmon_temp_input: + return gxp_psu_get_temp_input(dev, attr, channel, + val); + default: + break; + } + break; + default: + break; + } + return -EOPNOTSUPP; +} + +static int gxp_psu_read_string(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, const char **str) +{ + switch (type) { + case hwmon_power: + switch (attr) { + case hwmon_power_label: + *str = channel ? L_OUT_POWER : L_IN_POWER; + return 0; + default: + break; + } + case hwmon_in: + switch (attr) { + case hwmon_in_label: + *str = channel ? L_OUT_IN : L_IN_IN; + return 0; + default: + break; + } + case hwmon_fan: + switch (attr) { + case hwmon_fan_label: + *str = L_FAN; + return 0; + default: + break; + } + case hwmon_curr: + switch (attr) { + case hwmon_curr_label: + *str = channel ? L_OUT_CURR : L_IN_CURR; + return 0; + default: + break; + } + case hwmon_temp: + switch (attr) { + case hwmon_temp_label: + *str = L_TEMP; + return 0; + default: + break; + } + default: + break; + } + return -EOPNOTSUPP; +} + +static const struct hwmon_ops gxp_psu_ops = { + .is_visible = gxp_psu_is_visible, + .read = gxp_psu_read, + .read_string = gxp_psu_read_string, +}; + +static const struct hwmon_chip_info gxp_psu_chip_info = { + .ops = &gxp_psu_ops, + .info = gxp_psu_info, +}; + +#ifdef CONFIG_DEBUG_FS + +static int serial_number_show(struct seq_file *seqf, void *unused) +{ + struct gxp_psu_drvdata *drvdata = seqf->private; + int ret = 0; + + ret = psu_read_fru(drvdata, 91, 14, &drvdata->serial_number[0]); + if (ret < 0) { + dev_err(&drvdata->client->dev, "Unknown product serial number %d", ret); + seq_puts(seqf, "unknown\n"); + return 0; + } + + seq_printf(seqf, "%s\n", drvdata->serial_number); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(serial_number); + +static int manufacturer_show(struct seq_file *seqf, void *unused) +{ + struct gxp_psu_drvdata *drvdata = seqf->private; + int ret = 0; + + ret = psu_read_fru(drvdata, 197, 3, &drvdata->product_manufacturer[0]); + if (ret < 0) { + dev_err(&drvdata->client->dev, "Unknown product manufacturer %d", ret); + seq_puts(seqf, "unknown\n"); + return 0; + } + + swapbytes(&drvdata->product_manufacturer[0], 3); + seq_printf(seqf, "%s\n", drvdata->product_manufacturer); + return 0; +} +DEFINE_SHOW_ATTRIBUTE(manufacturer); + +static int product_name_show(struct seq_file *seqf, void *unused) +{ + struct gxp_psu_drvdata *drvdata = seqf->private; + int ret = 0; + + ret = psu_read_fru(drvdata, 50, 26, &drvdata->product_name[0]); + if (ret < 0) { + dev_err(&drvdata->client->dev, "Unknown product name %d", ret); + seq_puts(seqf, "unknown\n"); + return 0; + } + + seq_printf(seqf, "%s\n", drvdata->product_name); + return 0; +} +DEFINE_SHOW_ATTRIBUTE(product_name); + +static int spare_show(struct seq_file *seqf, void *unused) +{ + struct gxp_psu_drvdata *drvdata = seqf->private; + int ret = 0; + + ret = psu_read_fru(drvdata, 18, 10, &drvdata->spare_part[0]); + if (ret < 0) { + dev_err(&drvdata->client->dev, "Unknown product spare %d", ret); + seq_puts(seqf, "unknown\n"); + return 0; + } + + seq_printf(seqf, "%s\n", drvdata->spare_part); + return 0; +} +DEFINE_SHOW_ATTRIBUTE(spare); + +static int present_show(struct seq_file *seqf, void *unused) +{ + struct gxp_psu_drvdata *drvdata = seqf->private; + + update_presence(drvdata->id); + + if (drvdata->present) + seq_puts(seqf, "yes\n"); + else + seq_puts(seqf, "no\n"); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(present); + +static void gxp_psu_debugfs_init(struct gxp_psu_drvdata *drvdata) +{ + char name[32]; + + scnprintf(name, sizeof(name), "%s_%s-%d", dev_name(drvdata->hwmon_dev), + drvdata->client->name, drvdata->client->addr); + + drvdata->debugfs = debugfs_create_dir(name, NULL); + + debugfs_create_file("serial_number", 0444, drvdata->debugfs, drvdata, &serial_number_fops); + + debugfs_create_file("manufacturer", 0444, drvdata->debugfs, drvdata, &manufacturer_fops); + + debugfs_create_file("product_name", 0444, drvdata->debugfs, drvdata, &product_name_fops); + + debugfs_create_file("spare", 0444, drvdata->debugfs, drvdata, &spare_fops); + + debugfs_create_file("present", 0444, drvdata->debugfs, drvdata, &present_fops); + + if (!debugfs_initialized()) + dev_err(&drvdata->client->dev, "Debug FS not Init"); +} + +#else + +static void gxp_psu_debugfs_init(struct gxp_psu_drvdata *drvdata) +{ +} + +#endif + +static int gxp_psu_probe(struct i2c_client *client) +{ + struct gxp_psu_drvdata *drvdata; + struct device *hwmon_dev; + struct device_node *np; + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL)) + return -EIO; + + drvdata = devm_kzalloc(&client->dev, sizeof(struct gxp_psu_drvdata), + GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + if (!pl_psu) { + np = of_parse_phandle(client->dev.of_node, "hpe,sysreg", 0); + if (!np) + return -ENODEV; + + pl_psu = of_iomap(np, 0); + if (IS_ERR(pl_psu)) + return dev_err_probe(&client->dev, IS_ERR(pl_psu), + "failed to map pl_psu"); + } + + drvdata->client = client; + i2c_set_clientdata(client, drvdata); + + mutex_init(&drvdata->update_lock); + drvdata->hwmon_dev = NULL; + hwmon_dev = devm_hwmon_device_register_with_info(&client->dev, + "hpe_gxp_psu", + drvdata, + &gxp_psu_chip_info, + NULL); + if (IS_ERR(hwmon_dev)) + return PTR_ERR(hwmon_dev); + + drvdata->hwmon_dev = hwmon_dev; + + drvdata->id = psucount; + + psus[psucount] = drvdata; + + update_presence(drvdata->id); + + psucount++; + + gxp_psu_debugfs_init(drvdata); + + return 0; +} + +static const struct of_device_id gxp_psu_of_match[] = { + { .compatible = "hpe,gxp-psu" }, + {}, +}; +MODULE_DEVICE_TABLE(of, gxp_psu_of_match); + +static struct i2c_driver gxp_psu_driver = { + .class = I2C_CLASS_HWMON, + .driver = { + .name = "gxp-psu", + .of_match_table = gxp_psu_of_match, + }, + .probe_new = gxp_psu_probe, +}; +module_i2c_driver(gxp_psu_driver); + +MODULE_AUTHOR("Nick Hawkins "); +MODULE_DESCRIPTION("HPE GXP PSU driver"); +MODULE_LICENSE("GPL"); From patchwork Tue Apr 18 15:28:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hawkins, Nick" X-Patchwork-Id: 674652 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E201C77B7E for ; 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Tue, 18 Apr 2023 15:31:38 +0000 Received: from p1lg14886.dc01.its.hpecorp.net (unknown [10.119.18.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by p1lg14878.it.hpe.com (Postfix) with ESMTPS id E06E6132CB; Tue, 18 Apr 2023 15:31:37 +0000 (UTC) Received: from hpe.com (unknown [16.231.227.36]) by p1lg14886.dc01.its.hpecorp.net (Postfix) with ESMTP id 2640C8175C0; Tue, 18 Apr 2023 15:31:37 +0000 (UTC) From: nick.hawkins@hpe.com To: verdun@hpe.com, nick.hawkins@hpe.com, linus.walleij@linaro.org, brgl@bgdev.pl, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, jdelvare@suse.com, linux@roeck-us.net, linux@armlinux.org.uk, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v1 4/9] dt-bindings: hwmon: Modify hpe,gxp-fan-ctrl Date: Tue, 18 Apr 2023 10:28:19 -0500 Message-Id: <20230418152824.110823-5-nick.hawkins@hpe.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230418152824.110823-1-nick.hawkins@hpe.com> References: <20230418152824.110823-1-nick.hawkins@hpe.com> X-Proofpoint-GUID: jwIB54FRM9lWowhdNps47Qo1GzTVKuRO X-Proofpoint-ORIG-GUID: jwIB54FRM9lWowhdNps47Qo1GzTVKuRO X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-18_11,2023-04-18_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 spamscore=0 mlxlogscore=999 priorityscore=1501 adultscore=0 suspectscore=0 malwarescore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304180132 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Nick Hawkins Remove the fn2 register reference as GPIO will be using it. Signed-off-by: Nick Hawkins --- .../devicetree/bindings/hwmon/hpe,gxp-fan-ctrl.yaml | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/hwmon/hpe,gxp-fan-ctrl.yaml b/Documentation/devicetree/bindings/hwmon/hpe,gxp-fan-ctrl.yaml index 4a52aac6be72..ee70f06787f6 100644 --- a/Documentation/devicetree/bindings/hwmon/hpe,gxp-fan-ctrl.yaml +++ b/Documentation/devicetree/bindings/hwmon/hpe,gxp-fan-ctrl.yaml @@ -21,13 +21,11 @@ properties: items: - description: Fan controller PWM - description: Programmable logic - - description: Function 2 reg-names: items: - const: base - const: pl - - const: fn2 required: - compatible @@ -40,6 +38,6 @@ examples: - | fan-controller@1000c00 { compatible = "hpe,gxp-fan-ctrl"; - reg = <0x1000c00 0x200>, <0xd1000000 0xff>, <0x80200000 0x100000>; - reg-names = "base", "pl", "fn2"; + reg = <0x1000c00 0x200>, <0xd1000000 0xff>; + reg-names = "base", "pl"; }; From patchwork Tue Apr 18 15:28:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hawkins, Nick" X-Patchwork-Id: 675321 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34570C77B75 for ; Tue, 18 Apr 2023 15:32:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232292AbjDRPcJ (ORCPT ); Tue, 18 Apr 2023 11:32:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231727AbjDRPcJ (ORCPT ); Tue, 18 Apr 2023 11:32:09 -0400 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AB17B125AD; Tue, 18 Apr 2023 08:32:06 -0700 (PDT) Received: from pps.filterd (m0150242.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 33I7rAQr028406; Tue, 18 Apr 2023 15:31:39 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : subject : date : message-id : in-reply-to : references : mime-version; s=pps0720; bh=BLhWr7KA05LWTtyvACxcjFLqx/2vJ08FWT4M67w7BaQ=; b=VSMs/Kb6RtsDSJfpluG2R5QhgjO3aonnYWhkBvQgH2VT4qOhRVcxkppVjnfz0sXNpXVs jNdyQnDIcpe6GciiTNpsC/p/kJffO2fV5v5oDg7oV6ueJsQWgL3Pod+74vhXzlKYLZC4 rV2qBCpHxZF+ZsKrFghfvmIT4MHjRRapI3+8k0DIEdgoRaVkf4VRx7UYBtsd3jSMGxOs sZTQVZHiQhzw2nZ457K15IRJ2WxKCgDHEXGdwyyOuUvqs99SEDMrzI+a4o2V4gRFVNy5 h5x3JZPCb6eDPES9oRJCCL+3zP8Jj0bMPqrge7awdAUqypPbQChKCfA68148HLZKoEDx SQ== Received: from p1lg14881.it.hpe.com (p1lg14881.it.hpe.com [16.230.97.202]) by mx0a-002e3701.pphosted.com (PPS) with ESMTPS id 3q1ca1045s-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 18 Apr 2023 15:31:39 +0000 Received: from p1lg14886.dc01.its.hpecorp.net (unknown [10.119.18.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by p1lg14881.it.hpe.com (Postfix) with ESMTPS id 80D9F805E92; Tue, 18 Apr 2023 15:31:38 +0000 (UTC) Received: from hpe.com (unknown [16.231.227.36]) by p1lg14886.dc01.its.hpecorp.net (Postfix) with ESMTP id D6D7481733A; Tue, 18 Apr 2023 15:31:37 +0000 (UTC) From: nick.hawkins@hpe.com To: verdun@hpe.com, nick.hawkins@hpe.com, linus.walleij@linaro.org, brgl@bgdev.pl, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, jdelvare@suse.com, linux@roeck-us.net, linux@armlinux.org.uk, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v1 5/9] dt-bindings: gpio: Add HPE GXP GPIO Date: Tue, 18 Apr 2023 10:28:20 -0500 Message-Id: <20230418152824.110823-6-nick.hawkins@hpe.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230418152824.110823-1-nick.hawkins@hpe.com> References: <20230418152824.110823-1-nick.hawkins@hpe.com> X-Proofpoint-GUID: gwlaID5TfhXmNWG6DHkXrFURaNaViBqw X-Proofpoint-ORIG-GUID: gwlaID5TfhXmNWG6DHkXrFURaNaViBqw X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-18_11,2023-04-18_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 impostorscore=0 mlxscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=999 phishscore=0 priorityscore=1501 clxscore=1015 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304180132 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Nick Hawkins Provide access to the registers and interrupts for GPIO. The GPIO will have two driver instances: One for host, the other for CPLD. Signed-off-by: Nick Hawkins --- .../bindings/gpio/hpe,gxp-gpio.yaml | 137 ++++++++++++++++++ 1 file changed, 137 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/hpe,gxp-gpio.yaml diff --git a/Documentation/devicetree/bindings/gpio/hpe,gxp-gpio.yaml b/Documentation/devicetree/bindings/gpio/hpe,gxp-gpio.yaml new file mode 100644 index 000000000000..1cf4cff26d5f --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/hpe,gxp-gpio.yaml @@ -0,0 +1,137 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/hpe,gxp-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HPE GXP gpio controllers + +maintainers: + - Nick Hawkins + +description: + Interruptable GPIO drivers for the HPE GXP that covers multiple interfaces. + +properties: + compatible: + oneOf: + - items: + - enum: + - hpe,gxp-gpio + - hpe,gxp-gpio-pl + + reg: + minItems: 3 + maxItems: 6 + + reg-names: + minItems: 3 + maxItems: 6 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-line-names: + minItems: 1 + maxItems: 300 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - gpio-controller + - "#gpio-cells" + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + enum: + - hpe,gxp-gpio + then: + properties: + reg: + items: + - description: CSM + - description: fn2 virtual button + - description: fn2 system status + - description: vuhc status + - description: external virtual button + reg-names: + items: + - const: csm + - const: fn2-vbtn + - const: fn2-stat + - const: vuhc + - const: vbtn + - if: + properties: + compatible: + contains: + enum: + - hpe,gxp-gpio-pl + then: + properties: + reg: + items: + - description: Programmable logic led + - description: Programmable logic health led + - description: Programmable logic interrupt interface + reg-names: + items: + - const: pl-led + - const: pl-health + - const: pl-int + +examples: + - | + gpio@0 { + compatible = "hpe,gxp-gpio"; + reg = <0x0 0x400>, <0x200046 0x1>, <0x200070 0x08>, <0x400064 0x80>, <0x5100030f 0x1>; + reg-names = "csm", "fn2-vbtn", "fn2-stat", "vuhc", "vbtn"; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&vic0>; + interrupts = <10>; + gpio-line-names = + "IOP_LED1", "IOP_LED2", "IOP_LED3", "IOP_LED4", "IOP_LED5", "IOP_LED6", "IOP_LED7", "IOP_LED8", + "FAN1_INST", "FAN2_INST", "FAN3_INST", "FAN4_INST", "FAN5_INST", "FAN6_INST", "FAN7_INST", + "FAN8_INST", "FAN1_FAIL", "FAN2_FAIL", "FAN3_FAIL", "FAN4_FAIL", "FAN5_FAIL", "FAN6_FAIL", + "FAN7_FAIL", "FAN8_FAIL", "FAN1_ID", "FAN2_ID", "FAN3_ID", "FAN4_ID", "FAN5_ID", "FAN6_ID", + "FAN7_ID", "FAN8_ID", "IDENTIFY", "HEALTH_RED", "HEALTH_AMBER", "POWER_BUTTON", "UID_PRESS", + "SLP", "NMI_BUTTON", "RESET_BUTTON", "SIO_S5", "SO_ON_CONTROL", "PSU1_INST", "PSU2_INST", + "PSU3_INST", "PSU4_INST", "PSU5_INST", "PSU6_INST", "PSU7_INST", "PSU8_INST", "PSU1_AC", + "PSU2_AC", "PSU3_AC", "PSU4_AC", "PSU5_AC", "PSU6_AC", "PSU7_AC", "PSU8_AC", "PSU1_DC", + "PSU2_DC", "PSU3_DC", "PSU4_DC", "PSU5_DC", "PSU6_DC", "PSU7_DC", "PSU8_DC", "", "", "", "", + "", "", "", "", "", "", "", "", "", ""; + }; + + - | + gpio@51000304 { + compatible = "hpe,gxp-gpio-pl"; + reg = <0x51000304 0x2>, <0x5100030d 0x01>, <0x51000380 0x7f>; + reg-names = "pl-led", "pl-health", "pl-int"; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&vic0>; + interrupts = <24>; + gpio-line-names = + "IOP_LED1", "IOP_LED2", "IOP_LED3", "IOP_LED4", "IOP_LED5", "IOP_LED6", "IOP_LED7", "IOP_LED8", + "FAN1_INST", "FAN2_INST", "FAN3_INST", "FAN4_INST", "FAN5_INST", "FAN6_INST", "FAN7_INST", + "FAN8_INST", "FAN1_FAIL", "FAN2_FAIL", "FAN3_FAIL", "FAN4_FAIL", "FAN5_FAIL", "FAN6_FAIL", + "FAN7_FAIL", "FAN8_FAIL", "FAN1_ID", "FAN2_ID", "FAN3_ID", "FAN4_ID", "FAN5_ID", "FAN6_ID", + "FAN7_ID", "FAN8_ID", "IDENTIFY", "HEALTH_RED", "HEALTH_AMBER", "POWER_BUTTON", "UID_PRESS", + "SLP", "NMI_BUTTON", "RESET_BUTTON", "SIO_S5", "SO_ON_CONTROL", "PSU1_INST", "PSU2_INST", + "PSU3_INST", "PSU4_INST", "PSU5_INST", "PSU6_INST", "PSU7_INST", "PSU8_INST", "PSU1_AC", + "PSU2_AC", "PSU3_AC", "PSU4_AC", "PSU5_AC", "PSU6_AC", "PSU7_AC", "PSU8_AC", "PSU1_DC", + "PSU2_DC", "PSU3_DC", "PSU4_DC", "PSU5_DC", "PSU6_DC", "PSU7_DC", "PSU8_DC", "", "", "", "", + "", "", "", "", "", "", "", "", "", ""; + }; From patchwork Tue Apr 18 15:28:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hawkins, Nick" X-Patchwork-Id: 675317 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D381AC7EE29 for ; Tue, 18 Apr 2023 15:32:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232444AbjDRPcl (ORCPT ); Tue, 18 Apr 2023 11:32:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232360AbjDRPc3 (ORCPT ); Tue, 18 Apr 2023 11:32:29 -0400 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24B021447E; Tue, 18 Apr 2023 08:32:17 -0700 (PDT) Received: from pps.filterd (m0134420.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 33IBVxHj019523; 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Tue, 18 Apr 2023 15:31:39 +0000 (UTC) Received: from hpe.com (unknown [16.231.227.36]) by p1lg14886.dc01.its.hpecorp.net (Postfix) with ESMTP id 86E9B81733B; Tue, 18 Apr 2023 15:31:38 +0000 (UTC) From: nick.hawkins@hpe.com To: verdun@hpe.com, nick.hawkins@hpe.com, linus.walleij@linaro.org, brgl@bgdev.pl, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, jdelvare@suse.com, linux@roeck-us.net, linux@armlinux.org.uk, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v1 6/9] dt-bindings: hwmon: Add HPE GXP PSU Support Date: Tue, 18 Apr 2023 10:28:21 -0500 Message-Id: <20230418152824.110823-7-nick.hawkins@hpe.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230418152824.110823-1-nick.hawkins@hpe.com> References: <20230418152824.110823-1-nick.hawkins@hpe.com> X-Proofpoint-GUID: llG_UHI9fBhjAXZ7JLrgV-1tJt87eTRh X-Proofpoint-ORIG-GUID: llG_UHI9fBhjAXZ7JLrgV-1tJt87eTRh X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-18_11,2023-04-18_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 spamscore=0 mlxlogscore=999 priorityscore=1501 adultscore=0 suspectscore=0 malwarescore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304180132 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Nick Hawkins Provide i2c register information and CPLD register information to the driver. Signed-off-by: Nick Hawkins --- .../bindings/hwmon/hpe,gxp-psu.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwmon/hpe,gxp-psu.yaml diff --git a/Documentation/devicetree/bindings/hwmon/hpe,gxp-psu.yaml b/Documentation/devicetree/bindings/hwmon/hpe,gxp-psu.yaml new file mode 100644 index 000000000000..60ca0f6ace46 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/hpe,gxp-psu.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/hpe,gxp-psu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HPE GXP psu controller + +maintainers: + - Nicholas Hawkins + +properties: + compatible: + const: hpe,gxp-psu + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + + hpe,sysreg: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the global status registers shared between each psu + controller instance. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + psu@48 { + compatible = "hpe,gxp-psu"; + reg = <0x48>; + hpe,sysreg = <&sysreg_system_controller2>; + }; + }; From patchwork Tue Apr 18 15:28:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hawkins, Nick" X-Patchwork-Id: 674650 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73E7BC77B7F for ; Tue, 18 Apr 2023 15:32:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232333AbjDRPcl (ORCPT ); Tue, 18 Apr 2023 11:32:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232369AbjDRPca (ORCPT ); Tue, 18 Apr 2023 11:32:30 -0400 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2B58713879; 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Tue, 18 Apr 2023 15:31:39 +0000 (UTC) Received: from hpe.com (unknown [16.231.227.36]) by p1lg14886.dc01.its.hpecorp.net (Postfix) with ESMTP id 2F53E81733A; Tue, 18 Apr 2023 15:31:39 +0000 (UTC) From: nick.hawkins@hpe.com To: verdun@hpe.com, nick.hawkins@hpe.com, linus.walleij@linaro.org, brgl@bgdev.pl, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, jdelvare@suse.com, linux@roeck-us.net, linux@armlinux.org.uk, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v1 7/9] ARM: dts: gxp: add psu, i2c, gpio Date: Tue, 18 Apr 2023 10:28:22 -0500 Message-Id: <20230418152824.110823-8-nick.hawkins@hpe.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230418152824.110823-1-nick.hawkins@hpe.com> References: <20230418152824.110823-1-nick.hawkins@hpe.com> X-Proofpoint-GUID: jzlnY3bNHyLJihobDT4oF8pW9MGrW95V X-Proofpoint-ORIG-GUID: jzlnY3bNHyLJihobDT4oF8pW9MGrW95V X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-18_11,2023-04-18_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 impostorscore=0 mlxscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=963 phishscore=0 priorityscore=1501 clxscore=1015 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304180132 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Nick Hawkins Add support for the GXP I2C, PSU, and GPIO drivers. As well as adjust register ranges to be correct. Signed-off-by: Nick Hawkins --- arch/arm/boot/dts/hpe-bmc-dl360gen10.dts | 161 ++++++++++++++++++ arch/arm/boot/dts/hpe-gxp.dtsi | 197 ++++++++++++++++++++--- 2 files changed, 338 insertions(+), 20 deletions(-) diff --git a/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts b/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts index 3a7382ce40ef..487b6485a832 100644 --- a/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts +++ b/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts @@ -23,4 +23,165 @@ device_type = "memory"; reg = <0x40000000 0x20000000>; }; + + i2cmux@4 { + compatible = "i2c-mux-reg"; + i2c-parent = <&i2c4>; + reg = <0xd1000374 0x1>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + i2cmux@6 { + compatible = "i2c-mux-reg"; + i2c-parent = <&i2c6>; + reg = <0xd1000376 0x1>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + eeprom@50 { + compatible = "atmel,24c02"; + pagesize = <8>; + reg = <0x50>; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; + psu@58 { + compatible = "hpe,gxp-psu"; + reg = <0x58>; + hpe,sysreg = <&sysreg_system_controller2>; + }; + + psu@59 { + compatible = "hpe,gxp-psu"; + reg = <0x59>; + hpe,sysreg = <&sysreg_system_controller2>; + }; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&gpio { + gpio-line-names = + "", "", "", "", "", "", "", "", "", "", /*0 - 9*/ + "", "", "", "", "", "", "", "", "", "", /*10 - 19*/ + "", "", "", "", "", "", "", "", "", "", /*20 - 29*/ + "", "", "", "", "", "", "", "", "", "", /*30 - 39*/ + "", "", "", "", "", "", "", "", "", "", /*40 - 49*/ + "", "", "", "", "", "", "", "", "", "", /*50 - 59*/ + "", "", "", "", "", "", "", "", "", "", /*60 - 69*/ + "", "", "", "", "", "", "", "", "", "", /*70 - 79*/ + "", "", "", "", "", "", "", "", "", "", /*80 - 89*/ + "", "", "", "", "", "", "", "", "", "", /*90 - 99*/ + "", "", "", "", "", "", "", "", "", "", /*100 - 109*/ + "", "", "", "", "", "", "", "", "", "", /*110 - 119*/ + "", "", "", "", "", "", "", "", "", "", /*120 - 129*/ + "", "", "", "", "", "", "", "", "", "", /*130 - 139*/ + "", "", "", "", "", "", "", "", "", "", /*140 - 149*/ + "", "", "", "", "", "", "", "", "", "", /*150 - 159*/ + "", "", "", "", "", "", "", "", "", "", /*160 - 169*/ + "", "", "", "", "", "", "", "", "", "", /*170 - 179*/ + "", "", "", "", "", "", "", "", "", "", /*180 - 189*/ + "", "", "RESET_OUT", "NMI_OUT", "", "", "", "", "", "", /*190 - 199*//*GPIO*/ + "", "", "", "", "", "", "", "", "", "", /*Vuhc 200-209*/ + "POWER_OUT", "PS_PWROK", "PCIERST", "POST_COMPLETE", "", "", "", "", "", ""; /*210 - 219*/ +}; + +&gpio1 { + gpio-line-names = + "IOP_LED1", "IOP_LED2", "IOP_LED3", "IOP_LED4", "IOP_LED5", "IOP_LED6", "IOP_LED7", + "IOP_LED8", "FAN1_INST", "FAN2_INST", "FAN3_INST", "FAN4_INST", "FAN5_INST", "FAN6_INST", + "FAN7_INST", "FAN8_INST", "FAN1_FAIL", "FAN2_FAIL", "FAN3_FAIL", "FAN4_FAIL", "FAN5_FAIL", + "FAN6_FAIL", "FAN7_FAIL", "FAN8_FAIL", "FAN1_ID", "FAN2_ID", "FAN3_ID", "FAN4_ID", + "FAN5_ID", "FAN6_ID", "FAN7_ID", "FAN8_ID", "IDENTIFY", "HEALTH_RED", "HEALTH_AMBER", + "POWER_BUTTON", "UID_PRESS", "SLP", "NMI_BUTTON", "RESET_BUTTON", "SIO_S5", + "SO_ON_CONTROL", "PSU1_INST", "PSU2_INST", "PSU3_INST", "PSU4_INST", "PSU5_INST", + "PSU6_INST", "PSU7_INST", "PSU8_INST", "PSU1_AC", "PSU2_AC", "PSU3_AC", "PSU4_AC", + "PSU5_AC", "PSU6_AC", "PSU7_AC", "PSU8_AC", "PSU1_DC", "PSU2_DC", "PSU3_DC", "PSU4_DC", + "PSU5_DC", "PSU6_DC", "PSU7_DC", "PSU8_DC", "", "", "", "", + "", "", "", "", "", "", "", "", "", ""; }; diff --git a/arch/arm/boot/dts/hpe-gxp.dtsi b/arch/arm/boot/dts/hpe-gxp.dtsi index cf735b3c4f35..8a8faf7fbd60 100644 --- a/arch/arm/boot/dts/hpe-gxp.dtsi +++ b/arch/arm/boot/dts/hpe-gxp.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree file for HPE GXP + * Device Tree for HPE GXP */ /dts-v1/; @@ -52,76 +52,233 @@ cache-level = <2>; }; - ahb@c0000000 { + ahb@80000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0xc0000000 0x30000000>; - dma-ranges; + ranges = <0x0 0x80000000 0x20000000>, + <0x40000000 0xc0000000 0x3fff0000>; - vic0: interrupt-controller@eff0000 { + vic0: interrupt-controller@4eff0000 { compatible = "arm,pl192-vic"; - reg = <0xeff0000 0x1000>; + reg = <0x4eff0000 0x1000>; interrupt-controller; #interrupt-cells = <1>; }; - vic1: interrupt-controller@80f00000 { + vic1: interrupt-controller@f00000 { compatible = "arm,pl192-vic"; - reg = <0x80f00000 0x1000>; + reg = <0xf00000 0x1000>; interrupt-controller; #interrupt-cells = <1>; }; - uarta: serial@e0 { + uarta: serial@400000e0 { compatible = "ns16550a"; - reg = <0xe0 0x8>; + reg = <0x400000e0 0x8>; interrupts = <17>; interrupt-parent = <&vic0>; clock-frequency = <1846153>; reg-shift = <0>; }; - uartb: serial@e8 { + uartb: serial@400000e8 { compatible = "ns16550a"; - reg = <0xe8 0x8>; + reg = <0x400000e8 0x8>; interrupts = <18>; interrupt-parent = <&vic0>; clock-frequency = <1846153>; reg-shift = <0>; }; - uartc: serial@f0 { + uartc: serial@400000f0 { compatible = "ns16550a"; - reg = <0xf0 0x8>; + reg = <0x400000f0 0x8>; interrupts = <19>; interrupt-parent = <&vic0>; clock-frequency = <1846153>; reg-shift = <0>; }; - usb0: usb@efe0000 { + usb0: usb@4efe0000 { compatible = "hpe,gxp-ehci", "generic-ehci"; - reg = <0xefe0000 0x100>; + reg = <0x4efe0000 0x100>; interrupts = <7>; interrupt-parent = <&vic0>; }; - st: timer@80 { + st: timer@40000080 { compatible = "hpe,gxp-timer"; - reg = <0x80 0x16>; + reg = <0x40000080 0x16>; interrupts = <0>; interrupt-parent = <&vic0>; clocks = <&iopclk>; clock-names = "iop"; }; - usb1: usb@efe0100 { + usb1: usb@4efe0100 { compatible = "hpe,gxp-ohci", "generic-ohci"; - reg = <0xefe0100 0x110>; + reg = <0x4efe0100 0x110>; interrupts = <6>; interrupt-parent = <&vic0>; }; + + sysreg_system_controller: syscon@400000f8 { + compatible = "hpe,gxp-sysreg", "syscon"; + reg = <0x400000f8 0x8>; + }; + + sysreg_system_controller2: syscon@51000319 { + compatible = "hpe,gxp-sysreg", "syscon"; + reg = <0x51000319 0x4>; + }; + + i2c0: i2c@40002000 { + compatible = "hpe,gxp-i2c"; + reg = <0x40002000 0x70>; + interrupts = <9>; + interrupt-parent = <&vic0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + hpe,sysreg = <&sysreg_system_controller>; + clock-frequency = <100000>; + }; + + i2c1: i2c@40002100 { + compatible = "hpe,gxp-i2c"; + reg = <0x40002100 0x70>; + interrupts = <9>; + interrupt-parent = <&vic0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + hpe,sysreg = <&sysreg_system_controller>; + clock-frequency = <100000>; + }; + + i2c2: i2c@40002200 { + compatible = "hpe,gxp-i2c"; + reg = <0x40002200 0x70>; + interrupts = <9>; + interrupt-parent = <&vic0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + hpe,sysreg = <&sysreg_system_controller>; + clock-frequency = <100000>; + }; + + i2c3: i2c@40002300 { + compatible = "hpe,gxp-i2c"; + reg = <0x40002300 0x70>; + interrupts = <9>; + interrupt-parent = <&vic0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + hpe,sysreg = <&sysreg_system_controller>; + clock-frequency = <100000>; + }; + + i2c4: i2c@40002400 { + compatible = "hpe,gxp-i2c"; + reg = <0x40002400 0x70>; + interrupts = <9>; + interrupt-parent = <&vic0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + hpe,sysreg = <&sysreg_system_controller>; + clock-frequency = <100000>; + }; + + i2c5: i2c@40002500 { + compatible = "hpe,gxp-i2c"; + reg = <0x40002500 0x70>; + interrupts = <9>; + interrupt-parent = <&vic0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + hpe,sysreg = <&sysreg_system_controller>; + clock-frequency = <100000>; + }; + + i2c6: i2c@40002600 { + compatible = "hpe,gxp-i2c"; + reg = <0x40002600 0x70>; + interrupts = <9>; + interrupt-parent = <&vic0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + hpe,sysreg = <&sysreg_system_controller>; + clock-frequency = <100000>; + }; + + i2c7: i2c@40002700 { + compatible = "hpe,gxp-i2c"; + reg = <0x40002700 0x70>; + interrupts = <9>; + interrupt-parent = <&vic0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + hpe,sysreg = <&sysreg_system_controller>; + clock-frequency = <100000>; + }; + + i2c8: i2c@40002800 { + compatible = "hpe,gxp-i2c"; + reg = <0x40002800 0x70>; + interrupts = <9>; + interrupt-parent = <&vic0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + hpe,sysreg = <&sysreg_system_controller>; + clock-frequency = <100000>; + }; + + i2c9: i2c@40002900 { + compatible = "hpe,gxp-i2c"; + reg = <0x40002900 0x70>; + interrupts = <9>; + interrupt-parent = <&vic0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + hpe,sysreg = <&sysreg_system_controller>; + clock-frequency = <100000>; + }; + + fan-controller@40000c10 { /* 0xc0000c10 */ + compatible = "hpe,gxp-fan-ctrl"; + reg = <0x40000c10 0x8>, <0x51000327 0x06>; + reg-names = "base", "pl"; + }; + + gpio: gpio@0 { + compatible = "hpe,gxp-gpio"; + reg = <0x0 0x400>, <0x200046 0x1>, <0x200070 0x08>, + <0x400064 0x80>, <0x5100030f 0x1>; + reg-names = "csm", "fn2-vbtn", "fn2-stat", "vuhc", "vbtn"; + gpio-controller; + #gpio-cells = <2>; + interrupts = <0>; + interrupt-parent = <&vic1>; + }; + + gpio1: gpio@51000304 { + compatible = "hpe,gxp-gpio-pl"; + reg = <0x51000304 0x2>, <0x5100030d 0x01>, <0x51000380 0x7f>; + reg-names = "pl-led", "pl-health", "pl-int"; + gpio-controller; + #gpio-cells = <2>; + interrupts = <26>; + interrupt-parent = <&vic0>; + }; }; }; }; From patchwork Tue Apr 18 15:28:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hawkins, Nick" X-Patchwork-Id: 675318 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A448AC77B78 for ; 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Tue, 18 Apr 2023 15:31:41 +0000 Received: from p1lg14886.dc01.its.hpecorp.net (unknown [10.119.18.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by p1lg14881.it.hpe.com (Postfix) with ESMTPS id 8E6EB806B78; Tue, 18 Apr 2023 15:31:40 +0000 (UTC) Received: from hpe.com (unknown [16.231.227.36]) by p1lg14886.dc01.its.hpecorp.net (Postfix) with ESMTP id D60EE81732F; Tue, 18 Apr 2023 15:31:39 +0000 (UTC) From: nick.hawkins@hpe.com To: verdun@hpe.com, nick.hawkins@hpe.com, linus.walleij@linaro.org, brgl@bgdev.pl, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, jdelvare@suse.com, linux@roeck-us.net, linux@armlinux.org.uk, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v1 8/9] ARM: multi_v7_defconfig: Add PSU, GPIO, and I2C Date: Tue, 18 Apr 2023 10:28:23 -0500 Message-Id: <20230418152824.110823-9-nick.hawkins@hpe.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230418152824.110823-1-nick.hawkins@hpe.com> References: <20230418152824.110823-1-nick.hawkins@hpe.com> X-Proofpoint-ORIG-GUID: apShHr2eoYeqIH1XWn91XRpVUs_5Pinm X-Proofpoint-GUID: apShHr2eoYeqIH1XWn91XRpVUs_5Pinm X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-18_11,2023-04-18_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 suspectscore=0 mlxlogscore=830 phishscore=0 bulkscore=0 malwarescore=0 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304180132 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Nick Hawkins Add the CONFIG_I2C_GXP, CONFIG_GPIO_GXP, and CONFIG_SENSORS_GXP_PSU symbols. Make CONFIG_SENSORS_GXP_FAN_CTRL=y Signed-off-by: Nick Hawkins --- arch/arm/configs/multi_v7_defconfig | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 084cc612ea23..fcfbcd233fb8 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -405,6 +405,7 @@ CONFIG_I2C_DAVINCI=y CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_I2C_DIGICOLOR=m CONFIG_I2C_EMEV2=m +CONFIG_I2C_GXP=m CONFIG_I2C_IMX=y CONFIG_I2C_MESON=y CONFIG_I2C_MV64XXX=y @@ -478,6 +479,7 @@ CONFIG_GPIO_ASPEED_SGPIO=y CONFIG_GPIO_DAVINCI=y CONFIG_GPIO_DWAPB=y CONFIG_GPIO_EM=y +CONFIG_GPIO_GXP=y CONFIG_GPIO_MPC8XXX=y CONFIG_GPIO_MXC=y CONFIG_GPIO_RCAR=y @@ -527,7 +529,8 @@ CONFIG_SENSORS_NTC_THERMISTOR=m CONFIG_SENSORS_PWM_FAN=m CONFIG_SENSORS_RASPBERRYPI_HWMON=m CONFIG_SENSORS_INA2XX=m -CONFIG_SENSORS_GXP_FAN_CTRL=m +CONFIG_SENSORS_GXP_FAN_CTRL=y +CONFIG_SENSORS_GXP_PSU=y CONFIG_CPU_THERMAL=y CONFIG_DEVFREQ_THERMAL=y CONFIG_IMX_THERMAL=y From patchwork Tue Apr 18 15:28:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hawkins, Nick" X-Patchwork-Id: 674654 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CB18C77B7F for ; Tue, 18 Apr 2023 15:32:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232332AbjDRPcM (ORCPT ); Tue, 18 Apr 2023 11:32:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47964 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232313AbjDRPcK (ORCPT ); Tue, 18 Apr 2023 11:32:10 -0400 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE2C3125B1; Tue, 18 Apr 2023 08:32:08 -0700 (PDT) Received: from pps.filterd (m0134420.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 33IBHK90013970; Tue, 18 Apr 2023 15:31:42 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : subject : date : message-id : in-reply-to : references; s=pps0720; bh=dAIIzQaU+Kiqn9GnVIQkPXlXHdyWvMYyRuSKEZVxqpw=; b=eV8QatR6OZ46jcsfGDjYtnEm3WWs6/ECPhsgN9abctszN66wrieQLuMwybL+uqlUhguS sgZaT1R6YFi0+pb1kEYFt4TNZWSgh0fVHQxNK8tBUviIBksoX9caiS4xgyAsi6WOD12W nztcq9y8egggARHhODm9vj/CWxHMUNtZNw5imSiiEhE837mQXiy0r5Rdv/PyFRPne4Js JE1oBGUCz/ATP8qmEuv//LMevgTB9FHjgZ8UIWbOdWc04o6JxWw138m6MuDIZZukJdVI OJ8MIlMRiXFREPeGimH3gFmDCgdSbuXl7SDRwBu3kz9BSnW3ywAa02XtR7vt0hklzVxr zQ== Received: from p1lg14879.it.hpe.com (p1lg14879.it.hpe.com [16.230.97.200]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3q1t6pj428-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 18 Apr 2023 15:31:42 +0000 Received: from p1lg14886.dc01.its.hpecorp.net (unknown [10.119.18.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by p1lg14879.it.hpe.com (Postfix) with ESMTPS id 8726913059; Tue, 18 Apr 2023 15:31:41 +0000 (UTC) Received: from hpe.com (unknown [16.231.227.36]) by p1lg14886.dc01.its.hpecorp.net (Postfix) with ESMTP id 8AD4B81532D; Tue, 18 Apr 2023 15:31:40 +0000 (UTC) From: nick.hawkins@hpe.com To: verdun@hpe.com, nick.hawkins@hpe.com, linus.walleij@linaro.org, brgl@bgdev.pl, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, jdelvare@suse.com, linux@roeck-us.net, linux@armlinux.org.uk, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v1 9/9] MAINTAINERS: hpe: Add GPIO, PSU Date: Tue, 18 Apr 2023 10:28:24 -0500 Message-Id: <20230418152824.110823-10-nick.hawkins@hpe.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230418152824.110823-1-nick.hawkins@hpe.com> References: <20230418152824.110823-1-nick.hawkins@hpe.com> X-Proofpoint-GUID: D-5jxxe18OTKk68YzM-A06-LVUnk68gS X-Proofpoint-ORIG-GUID: D-5jxxe18OTKk68YzM-A06-LVUnk68gS X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-18_11,2023-04-18_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 spamscore=0 mlxlogscore=999 priorityscore=1501 adultscore=0 suspectscore=0 malwarescore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304180132 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Nick Hawkins List the files added for GPIO and PSU support. Signed-off-by: Nick Hawkins --- MAINTAINERS | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a3b14ec33830..6df959ebf523 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2239,7 +2239,9 @@ M: Nick Hawkins S: Maintained F: Documentation/hwmon/gxp-fan-ctrl.rst F: Documentation/devicetree/bindings/arm/hpe,gxp.yaml +F: Documentation/devicetree/bindings/gpio/hpe,gxp-gpio.yaml F: Documentation/devicetree/bindings/hwmon/hpe,gxp-fan-ctrl.yaml +F: Documentation/devicetree/bindings/hwmon/hpe,gxp-psu.yaml F: Documentation/devicetree/bindings/i2c/hpe,gxp-i2c.yaml F: Documentation/devicetree/bindings/spi/hpe,gxp-spifi.yaml F: Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml @@ -2247,7 +2249,9 @@ F: arch/arm/boot/dts/hpe-bmc* F: arch/arm/boot/dts/hpe-gxp* F: arch/arm/mach-hpe/ F: drivers/clocksource/timer-gxp.c +F: drivers/gpio/gpio-gxp.c F: drivers/hwmon/gxp-fan-ctrl.c +F: drivers/hwmon/gxp-psu.c F: drivers/i2c/busses/i2c-gxp.c F: drivers/spi/spi-gxp.c F: drivers/watchdog/gxp-wdt.c