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[83.9.29.144]) by smtp.gmail.com with ESMTPSA id q17-20020a19a411000000b004d86808fd33sm2365895lfc.15.2023.04.18.05.10.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 05:10:59 -0700 (PDT) From: Konrad Dybcio Date: Tue, 18 Apr 2023 14:10:56 +0200 Subject: [PATCH v2 1/5] dt-bindings: display/msm: Add reg bus interconnect MIME-Version: 1.0 Message-Id: <20230417-topic-dpu_regbus-v2-1-91a66d04898e@linaro.org> References: <20230417-topic-dpu_regbus-v2-0-91a66d04898e@linaro.org> In-Reply-To: <20230417-topic-dpu_regbus-v2-0-91a66d04898e@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681819856; l=1310; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=9eGzIhdzE/kh12Ssb8zLi8BB+5t4kj0lnuayorvjl54=; b=6fysWEnV+Y3QmSTMiVPNmoQ9u0QIAaEjvJEkX1mj0vdB2azvjMKBFTXFeb43KILmDBjB8FFs4iVp BB/S89PrA4Ytu9jBc2Dfi9OeeG/7wbARaGTUTtuRCJrQlU8X+ytt X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's another path that needs to be handled to ensure MDSS functions properly, namely the "reg bus", a.k.a the CPU-MDSS interconnect. Gating that path may have a variety of effects.. from none to otherwise inexplicable DSI timeouts.. Describe it in bindings to allow for use in device trees. Signed-off-by: Konrad Dybcio --- Documentation/devicetree/bindings/display/msm/mdss-common.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml index ccd7d6417523..30a8aed4289a 100644 --- a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml +++ b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml @@ -66,12 +66,14 @@ properties: items: - description: Interconnect path from mdp0 (or a single mdp) port to the data bus - description: Interconnect path from mdp1 port to the data bus + - description: Interconnect path from CPU to the reg bus interconnect-names: minItems: 1 items: - const: mdp0-mem - const: mdp1-mem + - const: cpu-cfg resets: items: From patchwork Tue Apr 18 12:10:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 674683 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7DD3BC77B78 for ; Tue, 18 Apr 2023 12:12:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230384AbjDRMMT (ORCPT ); Tue, 18 Apr 2023 08:12:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46778 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231651AbjDRMLh (ORCPT ); Tue, 18 Apr 2023 08:11:37 -0400 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E194E2D58 for ; Tue, 18 Apr 2023 05:11:02 -0700 (PDT) Received: by mail-lj1-x229.google.com with SMTP id 38308e7fff4ca-2a7ac89b82dso20513451fa.1 for ; Tue, 18 Apr 2023 05:11:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681819861; x=1684411861; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=TusSYFhXpBTw3hD+Ig+2V6T5nJHWfXxfYQbiZRqJGNM=; b=qMjBZA6z4JwNv9nrY6ZukrVlV+5UNrtliICVTRHPh2CGw8TS41gty9nTL35MX8JJYC BV/AGuAdODhe4i8kD0urhXqyIxDomSAZfMUwiJaDRULOVXEtLJ3C83xJWgzTyAb8ItSi VaidmBVR8YcdgSk+NgWd+3aCzzIz2J4Mu8u0fN4KOTDxoIBQ6G6WGy0X7jXB/nQ4NUbR 2yThvJC/cZpurp7BZqr8f99Mclucd1PkJu1RE+8Te0Zm9yAZ0c/hH0U/HvwEllyF+8cg M6AalA1t0wbUQwceXnEmIvRoGohFNuPFXkQchMgdco4WH4PARnSVKsLMs3h9f7DWJPLm HETQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681819861; x=1684411861; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TusSYFhXpBTw3hD+Ig+2V6T5nJHWfXxfYQbiZRqJGNM=; b=dQZrbQQtr5xodzq1awm+oYqpLSczOQIsQ6yCisT9s9AYS0jHjfE72rFJ5HzCx67SVR QolaRXxfKB53Up1zO51Li34ZNOpMMac+9q7TuesDoxBtyH5ho2wskkLoXk///lDsyklx nk2R6LvecAuYfJbQduse/Ge5FQ4PV11m6SvnFSD9FlGbmhmTZ2yHT3ceaVcszaNVTAPp 7xp3FfHBbUPf3G3lN78meittlrFqs6/D+pRVnzaNoPFZKcF1Ccpnh43DjO25FDOTCKLf JnnmBFDDDeJOglFQsXJl8b9vP+QOR0mfuDtqBnQ9kHDEt6re3leJ1eXx/2+Intw7Saah MUVQ== X-Gm-Message-State: AAQBX9fKSThBzMTa+mol6gFiVQpaThzhWySd6/gD/SZVhd4yhCEfVCg9 +TkAWoGYUBRa1k3qHFpeRxkerg== X-Google-Smtp-Source: AKy350YFUr7D3ZA8FFCg0jBRLCUecF1TE4KPX3EM0XpcwN/O7LigF3RcuDV8Htc9b1S2Ec40qe9zRA== X-Received: by 2002:ac2:4556:0:b0:4ea:f636:6d02 with SMTP id j22-20020ac24556000000b004eaf6366d02mr2287331lfm.18.1681819860976; Tue, 18 Apr 2023 05:11:00 -0700 (PDT) Received: from [192.168.1.101] (abyj144.neoplus.adsl.tpnet.pl. [83.9.29.144]) by smtp.gmail.com with ESMTPSA id q17-20020a19a411000000b004d86808fd33sm2365895lfc.15.2023.04.18.05.10.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 05:11:00 -0700 (PDT) From: Konrad Dybcio Date: Tue, 18 Apr 2023 14:10:57 +0200 Subject: [PATCH v2 2/5] drm/msm/dpu1: Rename path references to mdp_path MIME-Version: 1.0 Message-Id: <20230417-topic-dpu_regbus-v2-2-91a66d04898e@linaro.org> References: <20230417-topic-dpu_regbus-v2-0-91a66d04898e@linaro.org> In-Reply-To: <20230417-topic-dpu_regbus-v2-0-91a66d04898e@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681819856; l=3187; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=RHVX4b0dy7ygKXk/64XZDOzn26jUEVt2/m6N5KVO6Vs=; b=r2TFBVO5Hj5SdRdHTZ0YLUP9sN8AtEd+o8gl6ja50IX5vktPr9lMiBBhBuvVF1QlIRM+I182r2iE 3e7I94N5DkppyOmS4WSIUeWXQZcRNBW8stdmAZtfC7dB3OlvbPvx X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The DPU1 driver needs to handle all MDPn<->DDR paths, as well as CPU<->SLAVE_DISPLAY_CFG. The former ones share how their values are calculated, but the latter one has static predefines spanning all SoCs. In preparation for supporting the CPU<->SLAVE_DISPLAY_CFG path, rename the path-related struct members to include "mdp_". Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 10 +++++----- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 12 ++++++------ drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 4 ++-- 3 files changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c index 1d9d83d7b99e..349c6cb3301d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c @@ -230,18 +230,18 @@ static int _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms, DRM_DEBUG_ATOMIC("crtc=%d bw=%llu paths:%d\n", tmp_crtc->base.id, - dpu_cstate->new_perf.bw_ctl, kms->num_paths); + dpu_cstate->new_perf.bw_ctl, kms->num_mdp_paths); } } - if (!kms->num_paths) + if (!kms->num_mdp_paths) return 0; avg_bw = perf.bw_ctl; - do_div(avg_bw, (kms->num_paths * 1000)); /*Bps_to_icc*/ + do_div(avg_bw, (kms->num_mdp_paths * 1000)); /*Bps_to_icc*/ - for (i = 0; i < kms->num_paths; i++) - icc_set_bw(kms->path[i], avg_bw, perf.max_per_pipe_ib); + for (i = 0; i < kms->num_mdp_paths; i++) + icc_set_bw(kms->mdp_path[i], avg_bw, perf.max_per_pipe_ib); return ret; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 0e7a68714e9e..dd6c1c40ab9e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -397,12 +397,12 @@ static int dpu_kms_parse_data_bus_icc_path(struct dpu_kms *dpu_kms) if (IS_ERR_OR_NULL(path0)) return PTR_ERR_OR_ZERO(path0); - dpu_kms->path[0] = path0; - dpu_kms->num_paths = 1; + dpu_kms->mdp_path[0] = path0; + dpu_kms->num_mdp_paths = 1; if (!IS_ERR_OR_NULL(path1)) { - dpu_kms->path[1] = path1; - dpu_kms->num_paths++; + dpu_kms->mdp_path[1] = path1; + dpu_kms->num_mdp_paths++; } return 0; } @@ -1238,8 +1238,8 @@ static int __maybe_unused dpu_runtime_suspend(struct device *dev) dev_pm_opp_set_rate(dev, 0); clk_bulk_disable_unprepare(dpu_kms->num_clocks, dpu_kms->clocks); - for (i = 0; i < dpu_kms->num_paths; i++) - icc_set_bw(dpu_kms->path[i], 0, 0); + for (i = 0; i < dpu_kms->num_mdp_paths; i++) + icc_set_bw(dpu_kms->mdp_path[i], 0, 0); return 0; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index aca39a4689f4..d5d9bec90705 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -109,8 +109,8 @@ struct dpu_kms { * when disabled. */ atomic_t bandwidth_ref; - struct icc_path *path[2]; - u32 num_paths; + struct icc_path *mdp_path[2]; + u32 num_mdp_paths; }; struct vsync_info { From patchwork Tue Apr 18 12:10:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 675345 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 372FDC77B76 for ; Tue, 18 Apr 2023 12:12:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230173AbjDRMMS (ORCPT ); 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[83.9.29.144]) by smtp.gmail.com with ESMTPSA id q17-20020a19a411000000b004d86808fd33sm2365895lfc.15.2023.04.18.05.11.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 05:11:02 -0700 (PDT) From: Konrad Dybcio Date: Tue, 18 Apr 2023 14:10:58 +0200 Subject: [PATCH v2 3/5] drm/msm/mdss: Rename path references to mdp_path MIME-Version: 1.0 Message-Id: <20230417-topic-dpu_regbus-v2-3-91a66d04898e@linaro.org> References: <20230417-topic-dpu_regbus-v2-0-91a66d04898e@linaro.org> In-Reply-To: <20230417-topic-dpu_regbus-v2-0-91a66d04898e@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681819856; l=2175; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=mFT0UyX9LhxCNCpprLZW/XLO+LLNqKMZSGZE8MZeFUU=; b=GK2A60TzVMQEAOzKUYKUR6rw8jItcwySKTJju9xkPZNGM9M1lTpTARcjPYfRz6gWTY1sXayeI4j8 7oyqnIXZBh56Seh+aoobZZkMDYr+Pqf4TEujHIxmbrCBrmvszl0p X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The DPU1 driver needs to handle all MDPn<->DDR paths, as well as CPU<->SLAVE_DISPLAY_CFG. The former ones share how their values are calculated, but the latter one has static predefines spanning all SoCs. In preparation for supporting the CPU<->SLAVE_DISPLAY_CFG path, rename the path-related struct members to include "mdp_". Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/msm_mdss.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index e8c93731aaa1..9e2ce7f22677 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -48,8 +48,8 @@ struct msm_mdss { struct irq_domain *domain; } irq_controller; const struct msm_mdss_data *mdss_data; - struct icc_path *path[2]; - u32 num_paths; + struct icc_path *mdp_path[2]; + u32 num_mdp_paths; }; static int msm_mdss_parse_data_bus_icc_path(struct device *dev, @@ -62,13 +62,13 @@ static int msm_mdss_parse_data_bus_icc_path(struct device *dev, if (IS_ERR_OR_NULL(path0)) return PTR_ERR_OR_ZERO(path0); - msm_mdss->path[0] = path0; - msm_mdss->num_paths = 1; + msm_mdss->mdp_path[0] = path0; + msm_mdss->num_mdp_paths = 1; path1 = of_icc_get(dev, "mdp1-mem"); if (!IS_ERR_OR_NULL(path1)) { - msm_mdss->path[1] = path1; - msm_mdss->num_paths++; + msm_mdss->mdp_path[1] = path1; + msm_mdss->num_mdp_paths++; } return 0; @@ -79,16 +79,16 @@ static void msm_mdss_put_icc_path(void *data) struct msm_mdss *msm_mdss = data; int i; - for (i = 0; i < msm_mdss->num_paths; i++) - icc_put(msm_mdss->path[i]); + for (i = 0; i < msm_mdss->num_mdp_paths; i++) + icc_put(msm_mdss->mdp_path[i]); } static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, unsigned long bw) { int i; - for (i = 0; i < msm_mdss->num_paths; i++) - icc_set_bw(msm_mdss->path[i], 0, Bps_to_icc(bw)); + for (i = 0; i < msm_mdss->num_mdp_paths; i++) + icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(bw)); } static void msm_mdss_irq(struct irq_desc *desc) From patchwork Tue Apr 18 12:10:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 675344 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCEFBC7EE21 for ; Tue, 18 Apr 2023 12:12:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231156AbjDRMMV (ORCPT ); Tue, 18 Apr 2023 08:12:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231679AbjDRMLk (ORCPT ); Tue, 18 Apr 2023 08:11:40 -0400 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2D96F7DA0 for ; Tue, 18 Apr 2023 05:11:05 -0700 (PDT) Received: by mail-lf1-x12e.google.com with SMTP id 2adb3069b0e04-4edcc885d8fso570623e87.1 for ; Tue, 18 Apr 2023 05:11:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681819864; x=1684411864; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=PbVhusCEghNKEPZ8TLDEdqw82MnqWQVPyy1y462DY9k=; b=swJ6/Exu986U2znXzl7Sx2Lj5KHn8dVTqtNXNU+FIA6UM4wu/HEowRKYm/z/prpcId VM4J6JeqKPWlKvFhNaIOa3hMIKyq3Ol2bCH+MuacZfeSMQYCIqw6IrWTcjFA44fKZD9D cDgyxq+DxNgfR7zcwKKzE6VMiW4t6vRJl15M+NeWyeAmZWc+Jd30zpaz4oY2U++ojnTz U79skAUExsLFHiqAKXKQa+kF96i1q5n4yJXyltnxgqkQljs6Ped4PgsaowdunD1QRi++ v82pM6y3+7PaKdK53jsDSGhmXyxvKn/4CQc7HRwfT8xxRvagvG9X6Wi9l2cdpaPbIM9I SRpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681819864; x=1684411864; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PbVhusCEghNKEPZ8TLDEdqw82MnqWQVPyy1y462DY9k=; b=Ba/hrbIiVti6HMG+xzxyATr4+iIi0UsD9VdX5uQvbhiiBdVbsoegwK5cVDGejdEeoo TdQ7oaLzjvmHM3kV6YOyRF9syKQc2bn7yDf0f5PBG7/JIS1/OOcysG+4vzW/MwlCBO6m BTH4XpsUyRbnJcxTEWdW49m5Lc1JQmLmo+xxQZuG7fMhgWFZ0hZ3Ck5ylimHb22/UWnQ iJICrM2Xprp/E3HvQ3aKL/34TXv7tL1WJLQQSxCfcAbuRGz9ESpDWD2C+Qg5JqDyQ8m8 GL+9KqjTmrlWY3MruEnlbJIqIra+aPfX/1jotFJBvfm2MLXuWpjRABYLKaFdrhrSJJCb af8w== X-Gm-Message-State: AAQBX9fKOAum4syKUTI9OHBj9OpldyekDr6ZQygAzIzOry++BAjo7H62 aN7XPeAIDlPiY6cVjnxlEjjldQ== X-Google-Smtp-Source: AKy350bPFfWUOLpWel/8DUUJQFJNYhY785GrX3wMbeGJZeX8OlOeyQdJUrVbfdfWsy1pAnBkEYqUkw== X-Received: by 2002:ac2:511b:0:b0:4eb:13ff:6ca7 with SMTP id q27-20020ac2511b000000b004eb13ff6ca7mr2818344lfb.16.1681819863993; Tue, 18 Apr 2023 05:11:03 -0700 (PDT) Received: from [192.168.1.101] (abyj144.neoplus.adsl.tpnet.pl. [83.9.29.144]) by smtp.gmail.com with ESMTPSA id q17-20020a19a411000000b004d86808fd33sm2365895lfc.15.2023.04.18.05.11.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 05:11:03 -0700 (PDT) From: Konrad Dybcio Date: Tue, 18 Apr 2023 14:10:59 +0200 Subject: [PATCH v2 4/5] drm/msm/mdss: Handle the reg bus ICC path MIME-Version: 1.0 Message-Id: <20230417-topic-dpu_regbus-v2-4-91a66d04898e@linaro.org> References: <20230417-topic-dpu_regbus-v2-0-91a66d04898e@linaro.org> In-Reply-To: <20230417-topic-dpu_regbus-v2-0-91a66d04898e@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681819856; l=3137; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=wX+gJPCe8UmLoFyI2GJLXSE1t0Mv12xmqDSsK2E8jZI=; b=Fl2losD0yxtKUBCjTBabIjaes/wJD0CNKIE43B+HBU9fLD5PGoyshXp3GJ8ZfODxRfctdbQnAGhz EDCNeSo8CFhnc35D2jEK9RnI6hh2Gf2ys+xxVtGeDWOXIMH07UQL X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's another path that needs to be handled to ensure MDSS functions properly, namely the "reg bus", a.k.a the CPU-MDSS interconnect. Gating that path may have a variety of effects.. from none to otherwise inexplicable DSI timeouts.. On the MDSS side, we only have to ensure that it's on at what Qualcomm downstream calls "77 MHz", a.k.a 76.8 Mbps and turn it off at suspend. To achieve that, make msm_mdss_icc_request_bw() accept a boolean to indicate whether we want the busses to be on or off, as this function's only use is to vote for minimum or no bandwidth at all. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/msm_mdss.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 9e2ce7f22677..4d126d20d661 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -50,6 +50,7 @@ struct msm_mdss { const struct msm_mdss_data *mdss_data; struct icc_path *mdp_path[2]; u32 num_mdp_paths; + struct icc_path *reg_bus_path; }; static int msm_mdss_parse_data_bus_icc_path(struct device *dev, @@ -57,6 +58,7 @@ static int msm_mdss_parse_data_bus_icc_path(struct device *dev, { struct icc_path *path0; struct icc_path *path1; + struct icc_path *reg_bus_path; path0 = of_icc_get(dev, "mdp0-mem"); if (IS_ERR_OR_NULL(path0)) @@ -71,6 +73,10 @@ static int msm_mdss_parse_data_bus_icc_path(struct device *dev, msm_mdss->num_mdp_paths++; } + reg_bus_path = of_icc_get(dev, "cpu-cfg"); + if (!IS_ERR_OR_NULL(reg_bus_path)) + msm_mdss->reg_bus_path = reg_bus_path; + return 0; } @@ -83,12 +89,15 @@ static void msm_mdss_put_icc_path(void *data) icc_put(msm_mdss->mdp_path[i]); } -static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, unsigned long bw) +static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, bool enable) { int i; for (i = 0; i < msm_mdss->num_mdp_paths; i++) - icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(bw)); + icc_set_bw(msm_mdss->mdp_path[i], 0, enable ? Bps_to_icc(MIN_IB_BW) : 0); + + if (msm_mdss->reg_bus_path) + icc_set_bw(msm_mdss->reg_bus_path, 0, enable ? 76800 : 0); } static void msm_mdss_irq(struct irq_desc *desc) @@ -241,7 +250,7 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) * the interconnect is enabled (non-zero bandwidth). Let's make sure * that the interconnects are at least at a minimum amount. */ - msm_mdss_icc_request_bw(msm_mdss, MIN_IB_BW); + msm_mdss_icc_request_bw(msm_mdss, true); ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks); if (ret) { @@ -289,7 +298,7 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) static int msm_mdss_disable(struct msm_mdss *msm_mdss) { clk_bulk_disable_unprepare(msm_mdss->num_clocks, msm_mdss->clocks); - msm_mdss_icc_request_bw(msm_mdss, 0); + msm_mdss_icc_request_bw(msm_mdss, false); return 0; } From patchwork Tue Apr 18 12:11:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 674682 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09631C7EE22 for ; Tue, 18 Apr 2023 12:12:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230490AbjDRMMT (ORCPT ); Tue, 18 Apr 2023 08:12:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231681AbjDRMLl (ORCPT ); Tue, 18 Apr 2023 08:11:41 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 42AC58681 for ; Tue, 18 Apr 2023 05:11:07 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id 2adb3069b0e04-4edb9039a4cso2063564e87.3 for ; Tue, 18 Apr 2023 05:11:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681819865; x=1684411865; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=jK7H3+ErS03Ewzys5ptfYi+3TCq3sJWDKGWiaxXPxVc=; b=fuHWc+pU6kSJ5B8ILg4cxboqaKg4YG4zzH+6szvYhrPIEcDw4trMLqi08eXiaM5Gkf 4RQaBvCm/cvtj7QAiqHndJHs1DkkQ9rMq2qm+yoTBS8AJdGFkTyndwfOxGXf//6wdsyO kZW103oYYampkvOOTH33ac6xyyGemNBb2+RhXJe4rgIRdLBjZ83bpwBsIb4ikNmGvK2K 6UnAbgQJdzHYWJC3RS3uFVwzg56p6BGs6cAiR2F6Mf7FFVmvDb1Blg80pTKDGbfnPZnN jvLrrgB9IdOweZLM57gORL1VfoEZoaRNKwQr7J/y/UYvhBtYDCHJ5Qtksulr2LnpxGf+ xaYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681819865; x=1684411865; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jK7H3+ErS03Ewzys5ptfYi+3TCq3sJWDKGWiaxXPxVc=; b=dyc58VdQNO6MQBKasr6M/z2Bl1xu9QhsvR6MDVYKptH/Tf0zSJj0OLpQzkMehgUJQR kTVaCTGnmFjDsIp0czdi2iHRgVWQPVdPw1RNOz7f5FqSG72bR5oBRKY9kSGQwRkwqKnY /cR4tHbKJ/ZzC0Zm3h7GsdY1ybbCrBE3VdT/GMCdKGJQWjVE2Llq7cwfElzHmR/cYlkj 6k8LrJGs8QXOm3bCuPwnxbs63fVRSXZobkIa74hGSUBpNTL5tOF/3+1qbv1rheDeTOZe 9ZQU9Slw5HvmIIvPM7aVzYbbQH/SnkIvmIYaJxyX3QLuzurzPCUhFpnMliWps9qWk27g VfsA== X-Gm-Message-State: AAQBX9e50X57lRbTR3M6q008n8JKOMqndniE+MpneaRFroZaLuA7rlD2 dtSgT3o0rGm+pece0yzri15XAA== X-Google-Smtp-Source: AKy350aWumsOXwDHQ/uYnZksZvKsIYQklkw41JcEKfVA2ot7VlI5J1+K4X9e8gNvBxNHCMWbjY7cmQ== X-Received: by 2002:ac2:43bb:0:b0:4ed:c3a1:752a with SMTP id t27-20020ac243bb000000b004edc3a1752amr1958180lfl.45.1681819865345; Tue, 18 Apr 2023 05:11:05 -0700 (PDT) Received: from [192.168.1.101] (abyj144.neoplus.adsl.tpnet.pl. [83.9.29.144]) by smtp.gmail.com with ESMTPSA id q17-20020a19a411000000b004d86808fd33sm2365895lfc.15.2023.04.18.05.11.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 05:11:05 -0700 (PDT) From: Konrad Dybcio Date: Tue, 18 Apr 2023 14:11:00 +0200 Subject: [PATCH v2 5/5] drm/msm/dpu1: Handle the reg bus ICC path MIME-Version: 1.0 Message-Id: <20230417-topic-dpu_regbus-v2-5-91a66d04898e@linaro.org> References: <20230417-topic-dpu_regbus-v2-0-91a66d04898e@linaro.org> In-Reply-To: <20230417-topic-dpu_regbus-v2-0-91a66d04898e@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681819856; l=3473; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=xOdy2dn+gE2SKrybPYSqoFq4IriT0JQjTQ+e3Ay5cn0=; b=h9ntcpkRQz9/aOBujWPi2GBuMqSjHjzJl4e3f8Ec2wwZlXLEV4LprmN69VRjW49s9bxj9Fi/LWe0 LEWJnLoPDtmj5vBJezWgfnSaCTM6RowO4Lqti71GkxnGl0OFOQI+ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's another path that needs to be handled to ensure MDSS functions properly, namely the "reg bus", a.k.a the CPU-MDSS interconnect. Gating that path may have a variety of effects.. from none to otherwise inexplicable DSI timeouts.. On the DPU side, we need to keep the bus alive. The vendor driver kickstarts it to max (300Mbps) throughput on first commit, but in exchange for some battery life in rare DPU-enabled-panel-disabled usecases, we can request it at DPU init and gate it at suspend. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 22 ++++++++++++++++++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 + 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index dd6c1c40ab9e..5e1ed338114d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -384,15 +384,17 @@ static int dpu_kms_global_obj_init(struct dpu_kms *dpu_kms) return 0; } -static int dpu_kms_parse_data_bus_icc_path(struct dpu_kms *dpu_kms) +static int dpu_kms_parse_icc_paths(struct dpu_kms *dpu_kms) { struct icc_path *path0; struct icc_path *path1; + struct icc_path *reg_bus_path; struct drm_device *dev = dpu_kms->dev; struct device *dpu_dev = dev->dev; path0 = msm_icc_get(dpu_dev, "mdp0-mem"); path1 = msm_icc_get(dpu_dev, "mdp1-mem"); + reg_bus_path = msm_icc_get(dpu_dev, "cpu-cfg"); if (IS_ERR_OR_NULL(path0)) return PTR_ERR_OR_ZERO(path0); @@ -404,6 +406,10 @@ static int dpu_kms_parse_data_bus_icc_path(struct dpu_kms *dpu_kms) dpu_kms->mdp_path[1] = path1; dpu_kms->num_mdp_paths++; } + + if (!IS_ERR_OR_NULL(reg_bus_path)) + dpu_kms->reg_bus_path = reg_bus_path; + return 0; } @@ -1039,7 +1045,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms) DPU_DEBUG("REG_DMA is not defined"); } - dpu_kms_parse_data_bus_icc_path(dpu_kms); + dpu_kms_parse_icc_paths(dpu_kms); rc = pm_runtime_resume_and_get(&dpu_kms->pdev->dev); if (rc < 0) @@ -1241,6 +1247,9 @@ static int __maybe_unused dpu_runtime_suspend(struct device *dev) for (i = 0; i < dpu_kms->num_mdp_paths; i++) icc_set_bw(dpu_kms->mdp_path[i], 0, 0); + if (dpu_kms->reg_bus_path) + icc_set_bw(dpu_kms->reg_bus_path, 0, 0); + return 0; } @@ -1261,6 +1270,15 @@ static int __maybe_unused dpu_runtime_resume(struct device *dev) return rc; } + /* + * The vendor driver supports setting 76.8 / 150 / 300 MBps on this + * path, but it seems to go for the highest level when display output + * is enabled and zero otherwise. For simplicity, we can assume that + * DPU being enabled and running implies that. + */ + if (dpu_kms->reg_bus_path) + icc_set_bw(dpu_kms->reg_bus_path, 0, MBps_to_icc(300)); + dpu_vbif_init_memtypes(dpu_kms); drm_for_each_encoder(encoder, ddev) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index d5d9bec90705..c332381d58c4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -111,6 +111,7 @@ struct dpu_kms { atomic_t bandwidth_ref; struct icc_path *mdp_path[2]; u32 num_mdp_paths; + struct icc_path *reg_bus_path; }; struct vsync_info {