From patchwork Fri May 31 03:00:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 165480 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp141907ili; Thu, 30 May 2019 20:01:12 -0700 (PDT) X-Google-Smtp-Source: APXvYqyMO/FeFQjiGAsngCaiGay6Vtw/7O1XhCIvP6LexEc7jyOJ1JJabrgh9/ghFoJrcQ3dg2B6 X-Received: by 2002:a63:700b:: with SMTP id l11mr6402795pgc.449.1559271671878; Thu, 30 May 2019 20:01:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559271671; cv=none; d=google.com; s=arc-20160816; b=oSZ7it5fY8qoh7Z7q4HVo6wy/dgQEVgS9eNq/xynnd6CMZAApu+O4VWTzyf9O4aWF3 wqUcZIinC7YVLZ0fLwgF3U3wX8fFzUJevKhHo6VMXqIEv6KtJ/vN/YHkBP/cdaIqhIXR rMUvrwX/HTfYQrHdwwOcE/JAc/6QgQHj+AaOlETQc64HU7/m72xt7DxxZtPIRSh1HCgh z+T4RlpPe3blY73PCLsaaLcNe0v2zuXwASO07+SM+4MIF7WyLu8x6HT1yBJIf06FE9Wi MDSlKYL9Ysh/gY5DydPE6xWCRuW5mMiLg8x9vUnhOrbDw9rP4BA+ry3865XBUAmN9LGM 6bPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=JAKPz5HiR/M9MZ5W/93Y/2txxEly1u4ytdsXz4IxAZM=; b=eL8+aylet8vkHRxoCpZtQMdRB6/YJs4WzHhdABWpfb3miGKOzDPW4J96HQ8oLCVjix nRRBZ+p6gWhbQKyf37Tk2ioSMQlKkeh2L659/VZaJhgEdhc7Z3MFVmfyJMqO8TcRUzJP IDQ3ZT48PHDfV1PnghVpTX673jkoOJBpWu6Kemn2q0938vzOdPFTiVKGnQiG0G80ECeM Q2Stfv6QD45xLOLTdE4bYpz8BRfebwDmHWfDXdSZkTR+8pdJi8+uZOY+SSjDdal2BvVV CTsl8mjWsn7ywZRTyvNuDrN9Da6fpxdLAAXB++3VZ4GRHlHcqoBmUbnkcu0xbxt0tmZD xgUg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PtlXPcbo; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id m8sm6991549pff.137.2019.05.30.20.01.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 30 May 2019 20:01:01 -0700 (PDT) From: Bjorn Andersson To: Andy Gross Cc: David Brown , Rob Herring , Mark Rutland , Doug Anderson , Arun Kumar Neelakantam , Vinod Koul , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 1/4] dt-bindings: soc: qcom: Add AOSS QMP binding Date: Thu, 30 May 2019 20:00:54 -0700 Message-Id: <20190531030057.18328-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190531030057.18328-1-bjorn.andersson@linaro.org> References: <20190531030057.18328-1-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add binding for the QMP based side-channel communication mechanism to the AOSS, which is used to control resources not exposed through the RPMh interface. Reviewed-by: Rob Herring Reviewed-by: Vinod Koul Signed-off-by: Bjorn Andersson --- Changes since v7: - Fix spelling of "Messaging" .../bindings/soc/qcom/qcom,aoss-qmp.txt | 81 +++++++++++++++++++ include/dt-bindings/power/qcom-aoss-qmp.h | 14 ++++ 2 files changed, 95 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt create mode 100644 include/dt-bindings/power/qcom-aoss-qmp.h -- 2.18.0 diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt new file mode 100644 index 000000000000..954ffee0a9c4 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt @@ -0,0 +1,81 @@ +Qualcomm Always-On Subsystem side channel binding + +This binding describes the hardware component responsible for side channel +requests to the always-on subsystem (AOSS), used for certain power management +requests that is not handled by the standard RPMh interface. Each client in the +SoC has it's own block of message RAM and IRQ for communication with the AOSS. +The protocol used to communicate in the message RAM is known as Qualcomm +Messaging Protocol (QMP) + +The AOSS side channel exposes control over a set of resources, used to control +a set of debug related clocks and to affect the low power state of resources +related to the secondary subsystems. These resources are exposed as a set of +power-domains. + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,sdm845-aoss-qmp" + +- reg: + Usage: required + Value type: + Definition: the base address and size of the message RAM for this + client's communication with the AOSS + +- interrupts: + Usage: required + Value type: + Definition: should specify the AOSS message IRQ for this client + +- mboxes: + Usage: required + Value type: + Definition: reference to the mailbox representing the outgoing doorbell + in APCS for this client, as described in mailbox/mailbox.txt + +- #clock-cells: + Usage: optional + Value type: + Definition: must be 0 + The single clock represents the QDSS clock. + +- #power-domain-cells: + Usage: optional + Value type: + Definition: must be 1 + The provided power-domains are: + CDSP state (0), LPASS state (1), modem state (2), SLPI + state (3), SPSS state (4) and Venus state (5). + += SUBNODES +The AOSS side channel also provides the controls for three cooling devices, +these are expressed as subnodes of the QMP node. The name of the node is used +to identify the resource and must therefor be "cx", "mx" or "ebi". + +- #cooling-cells: + Usage: optional + Value type: + Definition: must be 2 + += EXAMPLE + +The following example represents the AOSS side-channel message RAM and the +mechanism exposing the power-domains, as found in SDM845. + + aoss_qmp: qmp@c300000 { + compatible = "qcom,sdm845-aoss-qmp"; + reg = <0x0c300000 0x100000>; + interrupts = ; + mboxes = <&apss_shared 0>; + + #power-domain-cells = <1>; + + cx_cdev: cx { + #cooling-cells = <2>; + }; + + mx_cdev: mx { + #cooling-cells = <2>; + }; + }; diff --git a/include/dt-bindings/power/qcom-aoss-qmp.h b/include/dt-bindings/power/qcom-aoss-qmp.h new file mode 100644 index 000000000000..ec336d31dee4 --- /dev/null +++ b/include/dt-bindings/power/qcom-aoss-qmp.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018, Linaro Ltd. */ + +#ifndef __DT_BINDINGS_POWER_QCOM_AOSS_QMP_H +#define __DT_BINDINGS_POWER_QCOM_AOSS_QMP_H + +#define AOSS_QMP_LS_CDSP 0 +#define AOSS_QMP_LS_LPASS 1 +#define AOSS_QMP_LS_MODEM 2 +#define AOSS_QMP_LS_SLPI 3 +#define AOSS_QMP_LS_SPSS 4 +#define AOSS_QMP_LS_VENUS 5 + +#endif From patchwork Fri May 31 03:00:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 165483 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp141983ili; Thu, 30 May 2019 20:01:17 -0700 (PDT) X-Google-Smtp-Source: APXvYqwB/TOBagEEtOQOBEVKWhz0cKFDCgQP+37FEtHp8woJjFF0ijbc1UgzDD8K687A49RriluW X-Received: by 2002:a17:90a:a00a:: with SMTP id q10mr6478573pjp.102.1559271677417; Thu, 30 May 2019 20:01:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559271677; cv=none; d=google.com; s=arc-20160816; b=H8IpIYudZA2kEzVFRiLXkc7x4Ym50cx9Ff6P8YvNbrFnuJBbfDnpRKn4YkJcXWRw01 wtOaiw3nKw7+3ANbvHIMLeCNkW4mddvdm8KnWjjcFbaRS8jfUONv/0n+ETSYNEYi6NfX qFDJZJksQZxq+cFzj0YOfn7Pu/D3SrwLFlTdQQrQO/yGmsqy5NmhWR3RrWgEVvTDP97+ N6fPGXkaHDxM8fVxRC0NXcA/y6M8Zyl9XmdbciF14WqBer4fZEr7sf3AIeN/LTcBctiS FshldRkh76iPCHDEDmNwECrjvnld+PeB8P/bUr/CF183Bc7FqeIcFYgM9barA62ckEfS z20g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=mNdvV3voe7Bq5kBZY+4RBehFVoyd/KAztdQ7qfKu7zs=; b=ba9sA363GvR9bskuJfHzqiXzSmWGzrQZ+01Ya0rzbKamJg/WyXj2oAG10XVKcURr1S NRevSMi1AQ1GIXkncdaRpMYVHIekVW3fZnqjPFczWWbommdzWjLjZ5c1Orb89YtFKF+l /g25gFWGZ2BdEMUyBtC5GfaS4bWtJgzi5c+If6za6tHnbV5Ptl6fr4nUgncy7YbCl8lw ZdAIhDIhQodRYwmCeB1WHF/U9bbGOIykGJjtfHfyDNxORoxX4lSX4KTqLeESTmW7QiE6 KMdCRPZEImeR9OAXVbuxQPw2RbokfgA7C6OKiCYls82PPV80HmMGX4QsC9uW1LFg495e qE0w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AbYekzDm; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id m8sm6991549pff.137.2019.05.30.20.01.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 30 May 2019 20:01:03 -0700 (PDT) From: Bjorn Andersson To: Andy Gross Cc: David Brown , Rob Herring , Mark Rutland , Doug Anderson , Arun Kumar Neelakantam , Vinod Koul , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 2/4] soc: qcom: Add AOSS QMP driver Date: Thu, 30 May 2019 20:00:55 -0700 Message-Id: <20190531030057.18328-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190531030057.18328-1-bjorn.andersson@linaro.org> References: <20190531030057.18328-1-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Always On Subsystem (AOSS) Qualcomm Messaging Protocol (QMP) driver is used to communicate with the AOSS for certain side-channel requests, that are not available through the RPMh interface. The communication is a very simple synchronous mechanism of messages being written in message RAM and a doorbell in the AOSS is rung. As the AOSS has processed the message length is cleared and an interrupt is fired by the AOSS as acknowledgment. The driver exposes the QDSS clock as a clock and the low-power state associated with the remoteprocs in the system as a set of power-domains. Tested-by: Sai Prakash Ranjan Signed-off-by: Bjorn Andersson --- Changes since v7: - Fixed handling of of_clk_add_hw_provider() errors - Reduced QMP_MSG_LEN to 64 - constify constant strings - GENMASK() bitmasks - Fix return value of qmp_open() drivers/soc/qcom/Kconfig | 12 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/qcom_aoss.c | 479 +++++++++++++++++++++++++++++++++++ 3 files changed, 492 insertions(+) create mode 100644 drivers/soc/qcom/qcom_aoss.c -- 2.18.0 diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 1ee298f6bf17..7aa0d1f17e65 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -3,6 +3,18 @@ # menu "Qualcomm SoC drivers" +config QCOM_AOSS_QMP + tristate "Qualcomm AOSS Driver" + depends on ARCH_QCOM || COMPILE_TEST + depends on MAILBOX + depends on COMMON_CLK + select PM_GENERIC_DOMAINS + help + This driver provides the means of communicating with and controlling + the low-power state for resources related to the remoteproc + subsystems as well as controlling the debug clocks exposed by the Always On + Subsystem (AOSS) using Qualcomm Messaging Protocol (QMP). + config QCOM_COMMAND_DB bool "Qualcomm Command DB" depends on ARCH_QCOM || COMPILE_TEST diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index ffe519b0cb66..eeb088beb15f 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 CFLAGS_rpmh-rsc.o := -I$(src) +obj-$(CONFIG_QCOM_AOSS_QMP) += qcom_aoss.o obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o obj-$(CONFIG_QCOM_COMMAND_DB) += cmd-db.o obj-$(CONFIG_QCOM_GLINK_SSR) += glink_ssr.o diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c new file mode 100644 index 000000000000..369d4cab96b0 --- /dev/null +++ b/drivers/soc/qcom/qcom_aoss.c @@ -0,0 +1,479 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019, Linaro Ltd + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#define QMP_DESC_MAGIC 0x0 +#define QMP_DESC_VERSION 0x4 +#define QMP_DESC_FEATURES 0x8 + +/* AOP-side offsets */ +#define QMP_DESC_UCORE_LINK_STATE 0xc +#define QMP_DESC_UCORE_LINK_STATE_ACK 0x10 +#define QMP_DESC_UCORE_CH_STATE 0x14 +#define QMP_DESC_UCORE_CH_STATE_ACK 0x18 +#define QMP_DESC_UCORE_MBOX_SIZE 0x1c +#define QMP_DESC_UCORE_MBOX_OFFSET 0x20 + +/* Linux-side offsets */ +#define QMP_DESC_MCORE_LINK_STATE 0x24 +#define QMP_DESC_MCORE_LINK_STATE_ACK 0x28 +#define QMP_DESC_MCORE_CH_STATE 0x2c +#define QMP_DESC_MCORE_CH_STATE_ACK 0x30 +#define QMP_DESC_MCORE_MBOX_SIZE 0x34 +#define QMP_DESC_MCORE_MBOX_OFFSET 0x38 + +#define QMP_STATE_UP GENMASK(15, 0) +#define QMP_STATE_DOWN GENMASK(31, 16) + +#define QMP_MAGIC 0x4d41494c /* mail */ +#define QMP_VERSION 1 + +/* 64 bytes is enough to store the requests and provides padding to 4 bytes */ +#define QMP_MSG_LEN 64 + +/** + * struct qmp - driver state for QMP implementation + * @msgram: iomem referencing the message RAM used for communication + * @dev: reference to QMP device + * @mbox_client: mailbox client used to ring the doorbell on transmit + * @mbox_chan: mailbox channel used to ring the doorbell on transmit + * @offset: offset within @msgram where messages should be written + * @size: maximum size of the messages to be transmitted + * @event: wait_queue for synchronization with the IRQ + * @tx_lock: provides synchronization between multiple callers of qmp_send() + * @qdss_clk: QDSS clock hw struct + * @pd_data: genpd data + */ +struct qmp { + void __iomem *msgram; + struct device *dev; + + struct mbox_client mbox_client; + struct mbox_chan *mbox_chan; + + size_t offset; + size_t size; + + wait_queue_head_t event; + + struct mutex tx_lock; + + struct clk_hw qdss_clk; + struct genpd_onecell_data pd_data; +}; + +struct qmp_pd { + struct qmp *qmp; + struct generic_pm_domain pd; +}; + +#define to_qmp_pd_resource(res) container_of(res, struct qmp_pd, pd) + +static void qmp_kick(struct qmp *qmp) +{ + mbox_send_message(qmp->mbox_chan, NULL); + mbox_client_txdone(qmp->mbox_chan, 0); +} + +static bool qmp_magic_valid(struct qmp *qmp) +{ + return readl(qmp->msgram + QMP_DESC_MAGIC) == QMP_MAGIC; +} + +static bool qmp_link_acked(struct qmp *qmp) +{ + return readl(qmp->msgram + QMP_DESC_MCORE_LINK_STATE_ACK) == QMP_STATE_UP; +} + +static bool qmp_mcore_channel_acked(struct qmp *qmp) +{ + return readl(qmp->msgram + QMP_DESC_MCORE_CH_STATE_ACK) == QMP_STATE_UP; +} + +static bool qmp_ucore_channel_up(struct qmp *qmp) +{ + return readl(qmp->msgram + QMP_DESC_UCORE_CH_STATE) == QMP_STATE_UP; +} + +static int qmp_open(struct qmp *qmp) +{ + int ret; + u32 val; + + if (!qmp_magic_valid(qmp)) { + dev_err(qmp->dev, "QMP magic doesn't match\n"); + return -EINVAL; + } + + val = readl(qmp->msgram + QMP_DESC_VERSION); + if (val != QMP_VERSION) { + dev_err(qmp->dev, "unsupported QMP version %d\n", val); + return -EINVAL; + } + + qmp->offset = readl(qmp->msgram + QMP_DESC_MCORE_MBOX_OFFSET); + qmp->size = readl(qmp->msgram + QMP_DESC_MCORE_MBOX_SIZE); + if (!qmp->size) { + dev_err(qmp->dev, "invalid mailbox size\n"); + return -EINVAL; + } + + /* Ack remote core's link state */ + val = readl(qmp->msgram + QMP_DESC_UCORE_LINK_STATE); + writel(val, qmp->msgram + QMP_DESC_UCORE_LINK_STATE_ACK); + + /* Set local core's link state to up */ + writel(QMP_STATE_UP, qmp->msgram + QMP_DESC_MCORE_LINK_STATE); + + qmp_kick(qmp); + + ret = wait_event_timeout(qmp->event, qmp_link_acked(qmp), HZ); + if (!ret) { + dev_err(qmp->dev, "ucore didn't ack link\n"); + goto timeout_close_link; + } + + writel(QMP_STATE_UP, qmp->msgram + QMP_DESC_MCORE_CH_STATE); + + qmp_kick(qmp); + + ret = wait_event_timeout(qmp->event, qmp_ucore_channel_up(qmp), HZ); + if (!ret) { + dev_err(qmp->dev, "ucore didn't open channel\n"); + goto timeout_close_channel; + } + + /* Ack remote core's channel state */ + writel(QMP_STATE_UP, qmp->msgram + QMP_DESC_UCORE_CH_STATE_ACK); + + qmp_kick(qmp); + + ret = wait_event_timeout(qmp->event, qmp_mcore_channel_acked(qmp), HZ); + if (!ret) { + dev_err(qmp->dev, "ucore didn't ack channel\n"); + goto timeout_close_channel; + } + + return 0; + +timeout_close_channel: + writel(QMP_STATE_DOWN, qmp->msgram + QMP_DESC_MCORE_CH_STATE); + +timeout_close_link: + writel(QMP_STATE_DOWN, qmp->msgram + QMP_DESC_MCORE_LINK_STATE); + qmp_kick(qmp); + + return -ETIMEDOUT; +} + +static void qmp_close(struct qmp *qmp) +{ + writel(QMP_STATE_DOWN, qmp->msgram + QMP_DESC_MCORE_CH_STATE); + writel(QMP_STATE_DOWN, qmp->msgram + QMP_DESC_MCORE_LINK_STATE); + qmp_kick(qmp); +} + +static irqreturn_t qmp_intr(int irq, void *data) +{ + struct qmp *qmp = data; + + wake_up_interruptible_all(&qmp->event); + + return IRQ_HANDLED; +} + +static bool qmp_message_empty(struct qmp *qmp) +{ + return readl(qmp->msgram + qmp->offset) == 0; +} + +/** + * qmp_send() - send a message to the AOSS + * @qmp: qmp context + * @data: message to be sent + * @len: length of the message + * + * Transmit @data to AOSS and wait for the AOSS to acknowledge the message. + * @len must be a multiple of 4 and not longer than the mailbox size. Access is + * synchronized by this implementation. + * + * Return: 0 on success, negative errno on failure + */ +static int qmp_send(struct qmp *qmp, const void *data, size_t len) +{ + int ret; + + if (WARN_ON(len + sizeof(u32) > qmp->size)) + return -EINVAL; + + if (WARN_ON(len % sizeof(u32))) + return -EINVAL; + + mutex_lock(&qmp->tx_lock); + + /* The message RAM only implements 32-bit accesses */ + __iowrite32_copy(qmp->msgram + qmp->offset + sizeof(u32), + data, len / sizeof(u32)); + writel(len, qmp->msgram + qmp->offset); + qmp_kick(qmp); + + ret = wait_event_interruptible_timeout(qmp->event, + qmp_message_empty(qmp), HZ); + if (!ret) { + dev_err(qmp->dev, "ucore did not ack channel\n"); + ret = -ETIMEDOUT; + + /* Clear message from buffer */ + writel(0, qmp->msgram + qmp->offset); + } else { + ret = 0; + } + + mutex_unlock(&qmp->tx_lock); + + return ret; +} + +static int qmp_qdss_clk_prepare(struct clk_hw *hw) +{ + static const char buf[QMP_MSG_LEN] = "{class: clock, res: qdss, val: 1}"; + struct qmp *qmp = container_of(hw, struct qmp, qdss_clk); + + return qmp_send(qmp, buf, sizeof(buf)); +} + +static void qmp_qdss_clk_unprepare(struct clk_hw *hw) +{ + static const char buf[QMP_MSG_LEN] = "{class: clock, res: qdss, val: 0}"; + struct qmp *qmp = container_of(hw, struct qmp, qdss_clk); + + qmp_send(qmp, buf, sizeof(buf)); +} + +static const struct clk_ops qmp_qdss_clk_ops = { + .prepare = qmp_qdss_clk_prepare, + .unprepare = qmp_qdss_clk_unprepare, +}; + +static int qmp_qdss_clk_add(struct qmp *qmp) +{ + struct clk_init_data qdss_init = { + .ops = &qmp_qdss_clk_ops, + .name = "qdss", + }; + int ret; + + qmp->qdss_clk.init = &qdss_init; + ret = clk_hw_register(qmp->dev, &qmp->qdss_clk); + if (ret < 0) { + dev_err(qmp->dev, "failed to register qdss clock\n"); + return ret; + } + + ret = of_clk_add_hw_provider(qmp->dev->of_node, of_clk_hw_simple_get, + &qmp->qdss_clk); + if (ret < 0) { + dev_err(qmp->dev, "unable to register of clk hw provider\n"); + clk_hw_unregister(&qmp->qdss_clk); + } + + return ret; +} + +static void qmp_qdss_clk_remove(struct qmp *qmp) +{ + of_clk_del_provider(qmp->dev->of_node); + clk_hw_unregister(&qmp->qdss_clk); +} + +static int qmp_pd_power_toggle(struct qmp_pd *res, bool enable) +{ + char buf[QMP_MSG_LEN] = {}; + + snprintf(buf, sizeof(buf), + "{class: image, res: load_state, name: %s, val: %s}", + res->pd.name, enable ? "on" : "off"); + return qmp_send(res->qmp, buf, sizeof(buf)); +} + +static int qmp_pd_power_on(struct generic_pm_domain *domain) +{ + return qmp_pd_power_toggle(to_qmp_pd_resource(domain), true); +} + +static int qmp_pd_power_off(struct generic_pm_domain *domain) +{ + return qmp_pd_power_toggle(to_qmp_pd_resource(domain), false); +} + +static const char * const sdm845_resources[] = { + [AOSS_QMP_LS_CDSP] = "cdsp", + [AOSS_QMP_LS_LPASS] = "adsp", + [AOSS_QMP_LS_MODEM] = "modem", + [AOSS_QMP_LS_SLPI] = "slpi", + [AOSS_QMP_LS_SPSS] = "spss", + [AOSS_QMP_LS_VENUS] = "venus", +}; + +static int qmp_pd_add(struct qmp *qmp) +{ + struct genpd_onecell_data *data = &qmp->pd_data; + struct device *dev = qmp->dev; + struct qmp_pd *res; + size_t num = ARRAY_SIZE(sdm845_resources); + int ret; + int i; + + res = devm_kcalloc(dev, num, sizeof(*res), GFP_KERNEL); + if (!res) + return -ENOMEM; + + data->domains = devm_kcalloc(dev, num, sizeof(*data->domains), + GFP_KERNEL); + if (!data->domains) + return -ENOMEM; + + for (i = 0; i < num; i++) { + res[i].qmp = qmp; + res[i].pd.name = sdm845_resources[i]; + res[i].pd.power_on = qmp_pd_power_on; + res[i].pd.power_off = qmp_pd_power_off; + + ret = pm_genpd_init(&res[i].pd, NULL, true); + if (ret < 0) { + dev_err(dev, "failed to init genpd\n"); + goto unroll_genpds; + } + + data->domains[i] = &res[i].pd; + } + + data->num_domains = i; + + ret = of_genpd_add_provider_onecell(dev->of_node, data); + if (ret < 0) + goto unroll_genpds; + + return 0; + +unroll_genpds: + for (i--; i >= 0; i--) + pm_genpd_remove(data->domains[i]); + + return ret; +} + +static void qmp_pd_remove(struct qmp *qmp) +{ + struct genpd_onecell_data *data = &qmp->pd_data; + struct device *dev = qmp->dev; + int i; + + of_genpd_del_provider(dev->of_node); + + for (i = 0; i < data->num_domains; i++) + pm_genpd_remove(data->domains[i]); +} + +static int qmp_probe(struct platform_device *pdev) +{ + struct resource *res; + struct qmp *qmp; + int irq; + int ret; + + qmp = devm_kzalloc(&pdev->dev, sizeof(*qmp), GFP_KERNEL); + if (!qmp) + return -ENOMEM; + + qmp->dev = &pdev->dev; + init_waitqueue_head(&qmp->event); + mutex_init(&qmp->tx_lock); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + qmp->msgram = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(qmp->msgram)) + return PTR_ERR(qmp->msgram); + + qmp->mbox_client.dev = &pdev->dev; + qmp->mbox_client.knows_txdone = true; + qmp->mbox_chan = mbox_request_channel(&qmp->mbox_client, 0); + if (IS_ERR(qmp->mbox_chan)) { + dev_err(&pdev->dev, "failed to acquire ipc mailbox\n"); + return PTR_ERR(qmp->mbox_chan); + } + + irq = platform_get_irq(pdev, 0); + ret = devm_request_irq(&pdev->dev, irq, qmp_intr, IRQF_ONESHOT, + "aoss-qmp", qmp); + if (ret < 0) { + dev_err(&pdev->dev, "failed to request interrupt\n"); + goto err_free_mbox; + } + + ret = qmp_open(qmp); + if (ret < 0) + goto err_free_mbox; + + ret = qmp_qdss_clk_add(qmp); + if (ret) + goto err_close_qmp; + + ret = qmp_pd_add(qmp); + if (ret) + goto err_remove_qdss_clk; + + platform_set_drvdata(pdev, qmp); + + return 0; + +err_remove_qdss_clk: + qmp_qdss_clk_remove(qmp); +err_close_qmp: + qmp_close(qmp); +err_free_mbox: + mbox_free_channel(qmp->mbox_chan); + + return ret; +} + +static int qmp_remove(struct platform_device *pdev) +{ + struct qmp *qmp = platform_get_drvdata(pdev); + + qmp_qdss_clk_remove(qmp); + qmp_pd_remove(qmp); + + qmp_close(qmp); + mbox_free_channel(qmp->mbox_chan); + + return 0; +} + +static const struct of_device_id qmp_dt_match[] = { + { .compatible = "qcom,sdm845-aoss-qmp", }, + {} +}; +MODULE_DEVICE_TABLE(of, qmp_dt_match); + +static struct platform_driver qmp_driver = { + .driver = { + .name = "qcom_aoss_qmp", + .of_match_table = qmp_dt_match, + }, + .probe = qmp_probe, + .remove = qmp_remove, +}; +module_platform_driver(qmp_driver); + +MODULE_DESCRIPTION("Qualcomm AOSS QMP driver"); +MODULE_LICENSE("GPL v2"); From patchwork Fri May 31 03:00:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 165481 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp141926ili; 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id m8sm6991549pff.137.2019.05.30.20.01.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 30 May 2019 20:01:04 -0700 (PDT) From: Bjorn Andersson To: Andy Gross Cc: David Brown , Rob Herring , Mark Rutland , Doug Anderson , Arun Kumar Neelakantam , Vinod Koul , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 3/4] arm64: dts: qcom: Add AOSS QMP node Date: Thu, 30 May 2019 20:00:56 -0700 Message-Id: <20190531030057.18328-4-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190531030057.18328-1-bjorn.andersson@linaro.org> References: <20190531030057.18328-1-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The AOSS QMP provides a number of power domains, used for QDSS and PIL, add the node for this. Tested-by: Sibi Sankar Reviewed-by: Sibi Sankar Reviewed-by: Vinod Koul Signed-off-by: Bjorn Andersson --- Changes since v7: - None arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.18.0 diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index fcb93300ca62..b25c251b6503 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2142,6 +2142,16 @@ #reset-cells = <1>; }; + aoss_qmp: qmp@c300000 { + compatible = "qcom,sdm845-aoss-qmp"; + reg = <0 0x0c300000 0 0x100000>; + interrupts = ; + mboxes = <&apss_shared 0>; + + #clock-cells = <0>; + #power-domain-cells = <1>; + }; + spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0 0x0c440000 0 0x1100>, From patchwork Fri May 31 03:00:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 165482 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp141933ili; Thu, 30 May 2019 20:01:13 -0700 (PDT) X-Google-Smtp-Source: APXvYqw3OcAEMZGJm+pZ4Lv2X+Ktpy976U0b/KhXlHv6+WfivoDyICl0dteCrzGfTxSNK05e8H+e X-Received: by 2002:a17:90a:8409:: with SMTP id j9mr6908288pjn.2.1559271673577; Thu, 30 May 2019 20:01:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559271673; cv=none; d=google.com; s=arc-20160816; b=tuMfA/VyswQfp7/Pr9Uint8vEdUxgZN9IdboBfYZW7lB8ZbLH1YqDgM2hj4fPBVSFs vagGktphzzSrico5mHddovkX4urkO6KAbDk/eAwuWiDZZHmBLL2PbBPRzflsGdRFm6fC r+WPeJY1MWtqOMxNtCaG1cdUjvMcZFEshMmAsyYaiLoKLJzwtlfzrmh6T4SgiaVy2n+f 0f0jZOsDu3Na+6Q697HOf+3SVG9P4rIUiCGFXHADE3FxmDSqfFfY3B8T2wJMZHBhXi3z MkG0/XWmuzhVIyGSQdK6tFChbSPE/LBL+MVw1tY6UQfErOzq0J4suCOK9Yqd8Bgl2x/s /K1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=9oOs0PxskGic5/b7RTQxcSk0/t3lEcqZGj07P5otHq8=; b=MU0mMwlxhoUj7bB/Lur2C67sOARBmbNu15I6/0ddYHRH9hkwjG0xSyZGNVtMtysfYV INzWJlepjqIhi0ZxRQCoSoO+7ErydppPAwVnNJ0DdQE6mKYqqgXmAAzj9AN7rMzfVUpa RiB9aHaxcKr9DonnzsXG5l1eBE32n8cBRXHtb1gYFa9PQIXT54BzrRsJKM1EidjS+mQ2 H0FgNQObxjbT3OBFsTxfZT/U2yN//itJrxENx8wQ2NOEBP40ejMESVMC7UUCsy1ZoIjr l48FvEKJs6kQ2xLdtMwt1GRYQcPuBd6fTAanpL1KLQcjN+9n99MqLpEEUzwsdN/mbVlB bUCg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qsAugKex; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id m8sm6991549pff.137.2019.05.30.20.01.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 30 May 2019 20:01:05 -0700 (PDT) From: Bjorn Andersson To: Andy Gross Cc: David Brown , Rob Herring , Mark Rutland , Doug Anderson , Arun Kumar Neelakantam , Vinod Koul , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 4/4] arm64: dts: qcom: sdm845: Add Q6V5 MSS node Date: Thu, 30 May 2019 20:00:57 -0700 Message-Id: <20190531030057.18328-5-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190531030057.18328-1-bjorn.andersson@linaro.org> References: <20190531030057.18328-1-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sibi Sankar This patch adds Q6V5 MSS remoteproc node for SDM845 SoCs. Reviewed-by: Douglas Anderson Reviewed-by: Vinod Koul Signed-off-by: Sibi Sankar Signed-off-by: Bjorn Andersson --- Changes since v7: - None arch/arm64/boot/dts/qcom/sdm845.dtsi | 58 ++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) -- 2.18.0 diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index b25c251b6503..978ceaec78cb 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1671,6 +1671,64 @@ }; }; + mss_pil: remoteproc@4080000 { + compatible = "qcom,sdm845-mss-pil"; + reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; + reg-names = "qdsp6", "rmb"; + + interrupts-extended = + <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack", + "shutdown-ack"; + + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>, + <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_MSS_SNOC_AXI_CLK>, + <&gcc GCC_MSS_MFAB_AXIS_CLK>, + <&gcc GCC_PRNG_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "bus", "mem", "gpll0_mss", + "snoc_axi", "mnoc_axi", "prng", "xo"; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + resets = <&aoss_reset AOSS_CC_MSS_RESTART>, + <&pdc_reset PDC_MODEM_SYNC_RESET>; + reset-names = "mss_restart", "pdc_reset"; + + qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; + + power-domains = <&aoss_qmp 2>, + <&rpmhpd SDM845_CX>, + <&rpmhpd SDM845_MX>, + <&rpmhpd SDM845_MSS>; + power-domain-names = "load_state", "cx", "mx", "mss"; + + mba { + memory-region = <&mba_region>; + }; + + mpss { + memory-region = <&mpss_region>; + }; + + glink-edge { + interrupts = ; + label = "modem"; + qcom,remote-pid = <1>; + mboxes = <&apss_shared 12>; + }; + }; + gpucc: clock-controller@5090000 { compatible = "qcom,sdm845-gpucc"; reg = <0 0x05090000 0 0x9000>;