From patchwork Wed Apr 19 14:41:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud Vrac X-Patchwork-Id: 675103 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94431C6FD18 for ; Wed, 19 Apr 2023 14:42:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233424AbjDSOmF (ORCPT ); Wed, 19 Apr 2023 10:42:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43020 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233331AbjDSOmD (ORCPT ); Wed, 19 Apr 2023 10:42:03 -0400 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E64A744A7 for ; Wed, 19 Apr 2023 07:41:58 -0700 (PDT) Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-3f178da21b5so11849835e9.3 for ; Wed, 19 Apr 2023 07:41:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebox-fr.20221208.gappssmtp.com; s=20221208; t=1681915317; x=1684507317; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=QOtCCZEZcabVSo6ibhq9qM6H/gWQgiZ4yShGSbi2dIs=; b=v73jw3xqTQUVgXczV6VibuF8JzrL/ShtyFABv3vUyAsKXR6lZdiQZIIbGMj/at/OEP x4xU7JXIVke63B3ABGTzR88C8KQpod/Vy/NaBJAclm36oD/wlZU1cKjcliDclaFbcyyx rUgh/oDxSKnA6LKj+kCiKHiszLMXshysRzYgO7zUCTlNae5lL+EoWfPOsfvh3X+S/iJp t3gRoKVaic1EQGuC1uMFLANOPfJSz93tUHWO3Vfx9YBY3RGqPNG1hf1HRuWdxiBErnBx Mh4bHZWqfnk7is2rQuReq+WWLJvb4f1l2J+fw47Xs4MOk+2X4PUWrjobxCkahDE9c8nU MLjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681915317; x=1684507317; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QOtCCZEZcabVSo6ibhq9qM6H/gWQgiZ4yShGSbi2dIs=; b=BWMyp3tYqWICvInc1ZpFEycul2yZbcTPHFynKMon+Q7sgkSuAN0LmiChZlX35+ZO6j KE9pZMPCoYWJ1msuuNN6Fv4jN6sGK6ORstDvxf46rWf80QJRHpAnLu1/7zNAr2WPebSj nAMwKwscUBeHP11vSXp/yVdKnWgyQWhSTNd9uPfM4c+oO8I1bUGoWFyzmL5ulTpqPVYW ae3IhMt+pegPZgrT8zplTRx8FEONxYr4SbWfYm6DQZ4Pn222k9GTBa1tsmZ2nlXemUfz z93NbEOEOijX7MdarKytJqOUxvXEQ9fa9BANKExgxhbFzotPAZNdFqJWZmI+VFQUOtiI H4ig== X-Gm-Message-State: AAQBX9dyXw5sR6Wg8sEIV2/VHUe/vbC3Yyd76Ql0EE3qiSuMT6ARt/EV DFsDAI5z/AeN03vVriy9jRst/SS2oZ6NOX4ORg== X-Google-Smtp-Source: AKy350Z4jFNf20Hlc2GWv28CTXaygiHWdHklMvv/5X5zjnBS4ogAsyzgZ1W89NxiPUYqbOGQz9cXEg== X-Received: by 2002:adf:f010:0:b0:2fa:6929:eb81 with SMTP id j16-20020adff010000000b002fa6929eb81mr4309583wro.31.1681915317445; Wed, 19 Apr 2023 07:41:57 -0700 (PDT) Received: from [127.0.1.1] (freebox.vlq16.iliad.fr. [213.36.7.13]) by smtp.gmail.com with ESMTPSA id m22-20020a7bcb96000000b003f17131952fsm2388519wmi.29.2023.04.19.07.41.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 07:41:57 -0700 (PDT) From: Arnaud Vrac Date: Wed, 19 Apr 2023 16:41:09 +0200 Subject: [PATCH 02/11] drm/msm/dpu: use the actual lm maximum width instead of a hardcoded value MIME-Version: 1.0 Message-Id: <20230419-dpu-tweaks-v1-2-d1bac46db075@freebox.fr> References: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> In-Reply-To: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Arnaud Vrac X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1453; i=avrac@freebox.fr; h=from:subject:message-id; bh=F1W/wchYMCu2VjLqHH6U+LrWUMc7lJp207y9YaxngyM=; b=owEBbQKS/ZANAwAIAXED/9m7NDSrAcsmYgBkP/2YRHSjxXabDh0Gu+NKzHbr/LV2esVhNCjWe gUDIZ3V20WJAjMEAAEIAB0WIQSUwb/ndwkXHdZ/QQZxA//ZuzQ0qwUCZD/9mAAKCRBxA//ZuzQ0 q9tYD/9LxTx1cpzUZKY3M7CrNX2Jf6IGVMYxyJqcOvjHmPaMEElWxCjSZ2oY2ZbE+F1S6z5JPsq P9UgmupIvqwIEvcsVnhcvW1wXyfcPH8xyZ8kRhW4LQIfS3VW/ySRdNndBtPtjVVRFJzvOiZHDVd MWcdkols1Sb8bAPlDeuXffjYMWYkzgqcDzJk7Iq5FerkvkQt91s18X7Mht3pKgvlak4SdMYXKpc kE5ULRYhNvt8XbKAUPTDDLMZo4XrsGo+fua4M8AXfPp0du/QMqlP7SxL6NadQfsINl5RuQUlmyq 0lf64+UUU2Als0GNKEvEAmy4sv8iQBv0rru0jzDW5jlw/aarbONgpxYDcIcQHoesDAOTa4WA6dO OiDqWXskg/QCG7LYfo9JSg0S9ohG6dC+sE+bypkM+TqNLcobWOVObLs6dYOhMBGhxD0SW0HCLC5 hIjiQVeoupzgYXhjJeLJjEZtiwsTx0OPxXL67WzZ4Tfs7UzTOi0XVVqa4kl3K8xXp3Ybj3xCPPf Q+ToaLhrxKsyuA8VeXC2yCWM7d5o5tfG6oohLDoqeXB2Jd5nj8Oo8jWeoUDUfG+bGliN+CXIkF1 XM2LKRVo2Hl1KwyNWNHGUsnlUE7mPmB2QoZREpw7VhwsTDdvAWMpV3ZKTJkXkuH6Ir/ouEFm/oE 3txKrd1uS68t15g== X-Developer-Key: i=avrac@freebox.fr; a=openpgp; fpr=6225092072BB58E3CEEC091E75392A176D952DB4 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This avoids using two LMs instead of one when the display width is lower than the maximum supported value. For example on MSM8996/MSM8998, the actual maxwidth is 2560, so we would use two LMs for 1280x720 or 1920x1080 resolutions, while one is enough. Signed-off-by: Arnaud Vrac --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 1dc5dbe585723..dd2914726c4f6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -53,8 +53,6 @@ #define IDLE_SHORT_TIMEOUT 1 -#define MAX_HDISPLAY_SPLIT 1080 - /* timeout in frames waiting for frame done */ #define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5 @@ -568,10 +566,12 @@ static struct msm_display_topology dpu_encoder_get_topology( */ if (intf_count == 2) topology.num_lm = 2; - else if (!dpu_kms->catalog->caps->has_3d_merge) - topology.num_lm = 1; + else if (dpu_kms->catalog->caps->has_3d_merge && + dpu_kms->catalog->mixer_count > 0 && + mode->hdisplay > dpu_kms->catalog->mixer[0].sblk->maxwidth) + topology.num_lm = 2; else - topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; + topology.num_lm = 1; if (crtc_state->ctm) topology.num_dspp = topology.num_lm; From patchwork Wed Apr 19 14:41:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud Vrac X-Patchwork-Id: 675102 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D650BC6FD18 for ; Wed, 19 Apr 2023 14:42:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233465AbjDSOmO (ORCPT ); Wed, 19 Apr 2023 10:42:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43050 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233378AbjDSOmE (ORCPT ); Wed, 19 Apr 2023 10:42:04 -0400 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C714046A1 for ; Wed, 19 Apr 2023 07:41:59 -0700 (PDT) Received: by mail-wm1-x32d.google.com with SMTP id d8-20020a05600c3ac800b003ee6e324b19so1556595wms.1 for ; Wed, 19 Apr 2023 07:41:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebox-fr.20221208.gappssmtp.com; s=20221208; t=1681915318; x=1684507318; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=gvyREH2toDbRX8jPDQqcQOz9n9jRJ61Ib08FCCvn3Ik=; b=fiEmjRI5sy66IY14yPYdCnD3Wng5CaWmy8/JWcrmhUpLJm++qPxhqYFuZBBwad2Bk1 fRC3PzylukzxUDXSaONiWypd1Qdz05sGYKefLuw6OlnX0ItB1uSbRHZ8BB9JEI+2f4tG ODTG+NUZEU6Bz49uGDl1rbfofa0a2OQPMnNxd0z56unCc1W9/2JHjUzvzMqYysrAmn2e LM8DuZQPfdNstgogGHSUQYrwhPTNUpWSVbCBuwrTjhnRPl/iUG/dltawjO0l42MNo37i irA1ZHZz+utK25dZM6ERc+rbyPl/k+FsCapqQdUoNmpPXQDwJMZc43wHrPLb2/Bemt4m 1iTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681915318; x=1684507318; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gvyREH2toDbRX8jPDQqcQOz9n9jRJ61Ib08FCCvn3Ik=; b=lr3T89843hqeWdns0v8i//N+duKS30aTv1TiLQiK0avxz5TZf1pFO0b+6z12e3NfJ3 acdDHE9ZzAJa+YoLamte9UyiEdx3q7X+XwsUtDZCSPEc9lIWSOWuqAsBmzxnC8VJ5Km7 8o+iI7oTF+h+es5SPOq6DQwy++cu4cAAKZqlKqNodUCsKmWdr5c7To6n2PJXmQvxGhQK 5n0pECpVKK2K46YnysnRFm9wWeeFiO7yoOJiFTJsAbWlGGettubKXmJ+Ui3ENWr1SD4P C08YUZY1xPx2+RqW82FxFrftDRCANE0UDaBK9Y8n51cEBj4mdytGiV3r0F+jrpRmIdQF b11w== X-Gm-Message-State: AAQBX9d2U3UGYU7QyQ3t5fOFOwAn6jv93ZmZ93/fePK4WnN5PN6K82gu gVCO9ncKkHtlwoOkocN8Wy3n X-Google-Smtp-Source: AKy350Y41eDbjV44lpKj/xlTrUrnQ2HFRVzK6oIGLJjemuk1KHFBsUN/7nExtMcIBIBSxZ+5N0s1qw== X-Received: by 2002:a1c:740d:0:b0:3f0:3d47:2cc5 with SMTP id p13-20020a1c740d000000b003f03d472cc5mr17091590wmc.10.1681915318268; Wed, 19 Apr 2023 07:41:58 -0700 (PDT) Received: from [127.0.1.1] (freebox.vlq16.iliad.fr. [213.36.7.13]) by smtp.gmail.com with ESMTPSA id m22-20020a7bcb96000000b003f17131952fsm2388519wmi.29.2023.04.19.07.41.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 07:41:58 -0700 (PDT) From: Arnaud Vrac Date: Wed, 19 Apr 2023 16:41:11 +0200 Subject: [PATCH 04/11] drm/msm/dpu: allow using lm mixer base stage MIME-Version: 1.0 Message-Id: <20230419-dpu-tweaks-v1-4-d1bac46db075@freebox.fr> References: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> In-Reply-To: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Arnaud Vrac X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1074; i=avrac@freebox.fr; h=from:subject:message-id; bh=NbkvlB+Rp9R8nBIqIbNdud3AhKbbO3pB8C+IbGJ1/iw=; b=owEBbQKS/ZANAwAIAXED/9m7NDSrAcsmYgBkP/2cS8NGHA5wCfb2NpdA7+TL/3Juvg4voqljd dCN9998hUiJAjMEAAEIAB0WIQSUwb/ndwkXHdZ/QQZxA//ZuzQ0qwUCZD/9nAAKCRBxA//ZuzQ0 qzq2EAC8YPFyE4WUiu8BKSb1ZitW40OEsReZvh9sxbDZTP3qWZ+pC1T6aDRLrWtGd01II9zSvnZ 1e1WtK52yoxgFMMIs9m76wrqd+HyouhNxyA49sA+TJ54CNigIw70r1AjmJlKxS5t4D7JONHX8EN 8WcDnTOyTyjhOSuR7GMbNNQvMSoyIbLnBwDQi2JgPFIH74gUttelxpiXYp/o3BlfmCvu+jFUJ0m 6DvZ646BwFhHgi+WdDeR0xa1UHABA2DR5YfRKQEfsd37Utg/ljJuurZ+676ax7Q/f+x5nhrv6tQ 3MFCvmBJ0WPec4eyrvX/O5sqBeYoGrluaPJwBbwwerXAypw1clzFh5o90KY3sr1APTgKO8fNdWa dWf31VLcAWvEOm552brE5gYPZ3nmq151VbNilEz0wGK9BrzP6aiA3PvLX4iJpj9MxEwGlB13zuL efJ1ZwqB7FcJZB73j5f4OpckUi5z6ytaxwbNhEs/Ls8H59xlpsey2J2pvhfQIayi+nKxgF2mZLX nknVZm6xJQd8qjCKv31ErlindIv/OJMLYWB8CGTjLDSredGRtnPUyTHFPl192rjH4UydVVLvf3N BB9TxwJFD+a2TxomXyKgp7DOHsOjeQeReXiNxSuqzfxaFm2ti/HxPir504dyFomWRoUK2BxkKLW pB4JplwICLGWejQ== X-Developer-Key: i=avrac@freebox.fr; a=openpgp; fpr=6225092072BB58E3CEEC091E75392A176D952DB4 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The dpu backend already handles applying alpha to the base stage, so we can use it to render the bottom plane in all cases. This allows mixing one additional plane with the hardware mixer. Signed-off-by: Arnaud Vrac --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 14b5cfe306113..148921ed62f85 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -881,7 +881,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; r_pipe->sspp = NULL; - pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos; + pstate->stage = DPU_STAGE_BASE + pstate->base.normalized_zpos; if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) { DPU_ERROR("> %d plane stages assigned\n", pdpu->catalog->caps->max_mixer_blendstages - DPU_STAGE_0); From patchwork Wed Apr 19 14:41:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud Vrac X-Patchwork-Id: 675101 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41C73C77B7C for ; Wed, 19 Apr 2023 14:42:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233317AbjDSOmS (ORCPT ); Wed, 19 Apr 2023 10:42:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43072 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233406AbjDSOmE (ORCPT ); Wed, 19 Apr 2023 10:42:04 -0400 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B64A54C20 for ; Wed, 19 Apr 2023 07:42:00 -0700 (PDT) Received: by mail-wm1-x32a.google.com with SMTP id v3so4205020wml.0 for ; Wed, 19 Apr 2023 07:42:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebox-fr.20221208.gappssmtp.com; s=20221208; t=1681915319; x=1684507319; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=hkfWN99F4hBvx1XEfrJngIeLn15ofD5JlY1D197wDT8=; b=3Cxnjb3YswWA056HbGtIB6yadcSK4Yw3KDO0AMN47lIDDhRRgAWvheSzQq8kp0BwkS 2Nyc/uYul5Iv+c4Vbn9nFXOMVfRBohbbkWocAG3ZKtrNETAr4kStKiew2dhHkoeXzs6n bzcnOQt5hzd8m4iwwFPB4/orgBLtAHK+7O5n7QbqgrwmHWC3l7rkPq1mY9mwqiS6HBxG e2fgrzmdzmEffoQJIBtRek/UGiI0KqVKa87HhQJNF7bqzvlUg1jg1fGwcmwQYAzmUiGE KIIJDqCPxUwSRyC0bwipOmSllHVYHwHwVEGrxinDD/uJVSl5iD1zA/Xz68bpvzAxAfbq S+YA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681915319; x=1684507319; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hkfWN99F4hBvx1XEfrJngIeLn15ofD5JlY1D197wDT8=; b=kjkZSwfzgvS3ZZmPz6FXr0d92QojpSwDbIBTJQuFocMhytKLH17cVdLr9NgUzrQplq YY15k5jMhdAxu5zO4AK32nAUCiv/SNQKcQquPKgVHzDUXkORXCrscmpUsyAOEtvrPt0d 0IbPetz9ZutxJFZePetb1Dxb/mbjgBbprkm4xewWrAH5UpTYMRYazEIU0xOevlQnWJrS BLmIza7K6uRqMVW6XcTh35BWuEGmrswS5wlp6AKBUf8C32cAlE4TTRGRCrOQ6CfbDW4j I4sU+MoY8i/jUPqnrjpYJT1zllch7hd21SDxgHXkKKdR0NUlcEZHMZKGN27lOPznMN6A sSgg== X-Gm-Message-State: AAQBX9e9UPuxGfR2Tvz1dMQzmv8r0pRYdRUXK7IIFPbiNMaBlSDFeKNr /FKq32uXq8wqfgN94sXpg2jS X-Google-Smtp-Source: AKy350Z4XvreRKuse360cUN0YJiTS3FQn+PMeJOel2baif9x0ixM+kMjMz4P1+eNretMarvSA/00hQ== X-Received: by 2002:a7b:ce89:0:b0:3f0:68ce:5465 with SMTP id q9-20020a7bce89000000b003f068ce5465mr17171216wmj.7.1681915319103; Wed, 19 Apr 2023 07:41:59 -0700 (PDT) Received: from [127.0.1.1] (freebox.vlq16.iliad.fr. [213.36.7.13]) by smtp.gmail.com with ESMTPSA id m22-20020a7bcb96000000b003f17131952fsm2388519wmi.29.2023.04.19.07.41.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 07:41:58 -0700 (PDT) From: Arnaud Vrac Date: Wed, 19 Apr 2023 16:41:13 +0200 Subject: [PATCH 06/11] drm/msm/dpu: support cursor sspp hw blocks MIME-Version: 1.0 Message-Id: <20230419-dpu-tweaks-v1-6-d1bac46db075@freebox.fr> References: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> In-Reply-To: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Arnaud Vrac X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4055; i=avrac@freebox.fr; h=from:subject:message-id; bh=JIN3wOAwRVDkVnPtsZfcQyHShaT43mZJjQaS4MuN1UU=; b=owEBbQKS/ZANAwAIAXED/9m7NDSrAcsmYgBkP/2izIHn4G021J6ANBFbFX+WtbijpqW9KvBFY pB2QJc9EzyJAjMEAAEIAB0WIQSUwb/ndwkXHdZ/QQZxA//ZuzQ0qwUCZD/9ogAKCRBxA//ZuzQ0 qx3jD/wP2/AD6Il7RXMRRrIsrRVYu3W++Ep5Yc+PFxyTi5+BnuCvuv8VakNG1e9ubJ6WWyT6d3b xnctAKrsGKFOMyC/7mGJ9+5CwR0EJ9Hn1DZVfZ3S0RZng8TxD5CUAHlSJifKfvZEh8PHlNoABuP 9LX2eXedY1HDcoYeLFKer1BD19/6V03G0E+HwgKWlUtHuI3sZlyWdB5lMBFdM6MbfApECvNXWBl vfYNv7JxAlf9KVBpc66UfCKuBwjakG19dvxDeodFnGVCHINs5yIW1+W/jUz85vadPUempbJWlwk bZHLkqbdtptrzTVYcGRJ8H+JRv4wCi4maG3l4Y407VPtYkTJJJyLhhZ6Ktgz1m5WHfOUI+wB1VT 0+EX9Jm+qyFY3MxTDmd2GJi8rElsK87p+D+/jLszbWnJrA64jmazciEODemu0wVL+MPqX9bNbPs wn0XE7GOtU7oFE8pvtZFoR3iPkfiYSj6tRy57NAMeD7xDbGZ46nOOdNhiml0pHqtpB8MeNyf3iz B+Hor7gxz7abwgQfN+S6FoKrBLWdnwzoa7TQU33PxQhc6A1tQwf5cm+z3cxLKR+MiKjhlDRcftN PHyhv3TtV9vcPpnXk1LHLSXHHlrWG4ySJTmft2kGccJXG3UlJfkV7DBhVnjkv8WWcZYTBJLuBgE x9mqsOvYDGc2YTQ== X-Developer-Key: i=avrac@freebox.fr; a=openpgp; fpr=6225092072BB58E3CEEC091E75392A176D952DB4 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Cursor SSPP must be assigned to the last mixer stage, so we assign an immutable zpos property with a value higher than primary/overlay planes, to ensure it will always be on top. Signed-off-by: Arnaud Vrac --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 19 ++++++++++++++----- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 26 +++++++++++++++++++++++--- 2 files changed, 37 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 0e7a68714e9e1..6cce0f6cfcb01 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -738,13 +738,22 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) for (i = 0; i < catalog->sspp_count; i++) { enum drm_plane_type type; - if ((catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)) - && cursor_planes_idx < max_crtc_count) - type = DRM_PLANE_TYPE_CURSOR; - else if (primary_planes_idx < max_crtc_count) + if (catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)) { + if (cursor_planes_idx < max_crtc_count) { + type = DRM_PLANE_TYPE_CURSOR; + } else if (catalog->sspp[i].type == SSPP_TYPE_CURSOR) { + /* Cursor SSPP can only be used in the last + * mixer stage, so it doesn't make sense to + * assign two of those to the same CRTC */ + continue; + } else { + type = DRM_PLANE_TYPE_OVERLAY; + } + } else if (primary_planes_idx < max_crtc_count) { type = DRM_PLANE_TYPE_PRIMARY; - else + } else { type = DRM_PLANE_TYPE_OVERLAY; + } DPU_DEBUG("Create plane type %d with features %lx (cur %lx)\n", type, catalog->sspp[i].features, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 128ecdc145260..5a7bb8543866c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -881,7 +881,14 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; r_pipe->sspp = NULL; - pstate->stage = DPU_STAGE_BASE + pstate->base.normalized_zpos; + if (pipe_hw_caps->type == SSPP_TYPE_CURSOR) { + /* enforce cursor sspp to use the last mixer stage */ + pstate->stage = DPU_STAGE_BASE + + pdpu->catalog->caps->max_mixer_blendstages; + } else { + pstate->stage = DPU_STAGE_BASE + pstate->base.normalized_zpos; + } + if (pstate->stage > DPU_STAGE_BASE + pdpu->catalog->caps->max_mixer_blendstages) { DPU_ERROR("> %d plane mixer stages assigned\n", pdpu->catalog->caps->max_mixer_blendstages); @@ -1463,6 +1470,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, struct msm_drm_private *priv = dev->dev_private; struct dpu_kms *kms = to_dpu_kms(priv->kms); struct dpu_hw_sspp *pipe_hw; + const uint64_t *format_modifiers; uint32_t num_formats; uint32_t supported_rotations; int ret = -EINVAL; @@ -1489,15 +1497,27 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, format_list = pipe_hw->cap->sblk->format_list; num_formats = pipe_hw->cap->sblk->num_formats; + if (pipe_hw->cap->type == SSPP_TYPE_CURSOR) + format_modifiers = NULL; + else + format_modifiers = supported_format_modifiers; + ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs, format_list, num_formats, - supported_format_modifiers, type, NULL); + format_modifiers, type, NULL); if (ret) goto clean_plane; pdpu->catalog = kms->catalog; - ret = drm_plane_create_zpos_property(plane, 0, 0, DPU_ZPOS_MAX); + if (pipe_hw->cap->type == SSPP_TYPE_CURSOR) { + /* cursor SSPP can only be used in the last mixer stage, + * enforce it by maxing out the cursor plane zpos */ + ret = drm_plane_create_zpos_immutable_property(plane, DPU_ZPOS_MAX); + } else { + ret = drm_plane_create_zpos_property(plane, 0, 0, DPU_ZPOS_MAX - 1); + } + if (ret) DPU_ERROR("failed to install zpos property, rc = %d\n", ret); From patchwork Wed Apr 19 14:41:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud Vrac X-Patchwork-Id: 675100 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37F73C77B7C for ; Wed, 19 Apr 2023 14:42:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233410AbjDSOma (ORCPT ); Wed, 19 Apr 2023 10:42:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43088 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233423AbjDSOmF (ORCPT ); Wed, 19 Apr 2023 10:42:05 -0400 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1788C527A for ; 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[213.36.7.13]) by smtp.gmail.com with ESMTPSA id m22-20020a7bcb96000000b003f17131952fsm2388519wmi.29.2023.04.19.07.41.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 07:41:59 -0700 (PDT) From: Arnaud Vrac Date: Wed, 19 Apr 2023 16:41:14 +0200 Subject: [PATCH 07/11] drm/msm/dpu: add sspp cursor blocks to msm8998 hw catalog MIME-Version: 1.0 Message-Id: <20230419-dpu-tweaks-v1-7-d1bac46db075@freebox.fr> References: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> In-Reply-To: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Arnaud Vrac X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3909; i=avrac@freebox.fr; h=from:subject:message-id; bh=ipqD9/zdMktG6jZ1bu4phPRN971JkBvc1JQ2BoirwDo=; b=owEBbQKS/ZANAwAIAXED/9m7NDSrAcsmYgBkP/2l9vG3IDNbhr+jhjy4oTIFGSW36RdaDadrV 86j61QWHFOJAjMEAAEIAB0WIQSUwb/ndwkXHdZ/QQZxA//ZuzQ0qwUCZD/9pQAKCRBxA//ZuzQ0 q8FhEACdwf8oEgYArrqf178JDo2Lso4yghQW7d+5aHzqw5icxRDKOQ+2nbEnyR6Y8hk2r0t+Y2F GhWBQpncaZL1tqDzAGnG2O8hxNG+J34LZlqaXdD51p+Ksmmd+Vyvji9TrYhsNdPLjRhLAjUV2gd NfHlUU06QerURwjrCJjiIVOlUzoUyWIMFQIakQtxpYB0LnBPS+WDASAYzT511FThnuf57ayLh9G Vs05zPmzHllDQ7TJpbF/UvoN/8yQh2k/1m+gs5EtDcia0HdcsZoZtLX9JtwA/Piw2hjOZ9eVDvA flcGI3183GRrfyeVKC+7AW9B8ttL6d7ou1c1wZPK4ZauMgvMUlW1PTRESP7UFLbPv0mWIIywgDu DwCd6WW+GsGUpOhCD3HGPRyIYjHTF53x2c6YQa09a/E/kW5CjpKaTjpNnENWTGEac2d0MoGJROT qOXZH75BWv2mNjQYAdoKNlt6vSlZy5+FKSZdfYrNKd5ZxS0rEnZLJCsjXAAJPGO+I/RhlpJ4X2o CK4ZEmPkOp2w8UKmBXGgo+/4UMQkQRfwYqfWvui3dVDFiobcS2PmTikKGXLz863AWN+bMNgRULl i1CsHl8O8INZjKgnDMQjKdAeWZcD8ihSTYqSxiaotCnkgUH5OLA9kHPD/pKRit4yWDNselmFtGk 5n4VAVHk4hbV6Ww== X-Developer-Key: i=avrac@freebox.fr; a=openpgp; fpr=6225092072BB58E3CEEC091E75392A176D952DB4 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Now that cursor sspp blocks can be used for cursor planes, enable them on msm8998. The dma sspp blocks that were assigned to cursor planes can now be used for overlay planes instead. Signed-off-by: Arnaud Vrac --- .../drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 8 +++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 34 ++++++++++++++++++++++ 2 files changed, 40 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index b07e8a9941f79..7de393b0f91d7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -90,10 +90,14 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = { sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1ac, DMA_MSM8998_MASK, sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1ac, DMA_CURSOR_MSM8998_MASK, + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1ac, DMA_MSM8998_MASK, sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1ac, DMA_CURSOR_MSM8998_MASK, + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1ac, DMA_MSM8998_MASK, sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), + SSPP_BLK("sspp_12", SSPP_CURSOR0, 0x34000, 0x1ac, DMA_CURSOR_MSM8998_MASK, + msm8998_cursor_sblk_0, 2, SSPP_TYPE_CURSOR, DPU_CLK_CTRL_CURSOR0), + SSPP_BLK("sspp_13", SSPP_CURSOR1, 0x36000, 0x1ac, DMA_CURSOR_MSM8998_MASK, + msm8998_cursor_sblk_1, 10, SSPP_TYPE_CURSOR, DPU_CLK_CTRL_CURSOR1), }; static const struct dpu_lm_cfg msm8998_lm[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 8d5d782a43398..f34fa704936bc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -242,6 +242,22 @@ static const uint32_t wb2_formats[] = { DRM_FORMAT_XBGR4444, }; +static const uint32_t cursor_formats[] = { + DRM_FORMAT_ARGB8888, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_RGBA8888, + DRM_FORMAT_BGRA8888, + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB1555, + DRM_FORMAT_ABGR1555, + DRM_FORMAT_RGBA5551, + DRM_FORMAT_BGRA5551, + DRM_FORMAT_ARGB4444, + DRM_FORMAT_ABGR4444, + DRM_FORMAT_RGBA4444, + DRM_FORMAT_BGRA4444, +}; + /************************************************************* * SSPP sub blocks config *************************************************************/ @@ -300,6 +316,19 @@ static const uint32_t wb2_formats[] = { .virt_num_formats = ARRAY_SIZE(plane_formats), \ } +#define _CURSOR_SBLK(num) \ + { \ + .maxdwnscale = SSPP_UNITY_SCALE, \ + .maxupscale = SSPP_UNITY_SCALE, \ + .smart_dma_priority = 0, \ + .src_blk = {.name = STRCAT("sspp_src_", num), \ + .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \ + .format_list = cursor_formats, \ + .num_formats = ARRAY_SIZE(cursor_formats), \ + .virt_format_list = cursor_formats, \ + .virt_num_formats = ARRAY_SIZE(cursor_formats), \ + } + static const struct dpu_sspp_sub_blks msm8998_vig_sblk_0 = _VIG_SBLK("0", 0, DPU_SSPP_SCALER_QSEED3); static const struct dpu_sspp_sub_blks msm8998_vig_sblk_1 = @@ -309,6 +338,11 @@ static const struct dpu_sspp_sub_blks msm8998_vig_sblk_2 = static const struct dpu_sspp_sub_blks msm8998_vig_sblk_3 = _VIG_SBLK("3", 0, DPU_SSPP_SCALER_QSEED3); +static const struct dpu_sspp_sub_blks msm8998_cursor_sblk_0 = + _CURSOR_SBLK("12"); +static const struct dpu_sspp_sub_blks msm8998_cursor_sblk_1 = + _CURSOR_SBLK("13"); + static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = { .rot_maxheight = 1088, .rot_num_formats = ARRAY_SIZE(rotation_v2_formats), From patchwork Wed Apr 19 14:41:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud Vrac X-Patchwork-Id: 675099 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 165CFC77B73 for ; Wed, 19 Apr 2023 14:42:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233570AbjDSOmf (ORCPT ); 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[213.36.7.13]) by smtp.gmail.com with ESMTPSA id m22-20020a7bcb96000000b003f17131952fsm2388519wmi.29.2023.04.19.07.42.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 07:42:00 -0700 (PDT) From: Arnaud Vrac Date: Wed, 19 Apr 2023 16:41:18 +0200 Subject: [PATCH 11/11] drm/msm/dpu: do not use mixer that supports dspp when not required MIME-Version: 1.0 Message-Id: <20230419-dpu-tweaks-v1-11-d1bac46db075@freebox.fr> References: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> In-Reply-To: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Arnaud Vrac X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=774; i=avrac@freebox.fr; h=from:subject:message-id; bh=eCHzSh6ygzKMrynLk5I85+wK8ZD9bT9L4MBgozHvN38=; b=owEBbQKS/ZANAwAIAXED/9m7NDSrAcsmYgBkP/2wtV1Bh/RNv/ZG/8M0oZScFy8jinYXpQd0Z l2D8Gf954aJAjMEAAEIAB0WIQSUwb/ndwkXHdZ/QQZxA//ZuzQ0qwUCZD/9sAAKCRBxA//ZuzQ0 q1UJD/46OiGy56oZou1FdqKU/7l7QduKNHg/kGvjVQ6ejPCZbi3rN1/KsuGcpsfBDYnC9kEplxb uvdYGoJX7RbyRfP0M3er/R6d7fMOk7+uwCXDmsyGn5VfJ7qpkCgEutRG5O4KWV1oeiMna21h5F+ DxVJuA2pBpUFw7JjL6fGQh1Sng8FWO8Uzcf391FHb3cK0xFZv0KXlAZAx4c6OpodRauIXYXkNd1 Jcu5WViknxy5Ftn5+rJxEstwF7C63jyhlPLrZhjTyKqiCWVfyFXjEWAjGFdr/TkXh5WAEjbhSSt mU7nNxVjPtdxR6ie2B698VBZj3If5GylQw0/7BVI1Lq5qUA8eqzENzlcX+r6s3G0Lliqr3Zzl6F Sb1WxTjhcgQTYWU2Lotuy1lRuydJoEpSDSBpTnF4/agODy2JryUMyueEMDsy45r/1JSHkLKGNWY Pxle7Moqu1T+SjaNR7FQcs0TaLpSNvLGdjSregG/hZjCAWYtx8IIfLuuMKYRUTNLJ8X7jpS3E4t if08fYjYLSdG8uEyrg8/r7C4/A8NbcuuGuppH+nYYs/fnrfZguQQ/b9w9ZqLB08fs+zi0Ofy6Q7 BWH5IzsYUYPdCf1/YN9bRJVoomXeRs5JSezRgMaF+ItDKS+kvI7o55nypbz0Ktlkt/IdxqkEhso yRJYDH3EDrznDuw== X-Developer-Key: i=avrac@freebox.fr; a=openpgp; fpr=6225092072BB58E3CEEC091E75392A176D952DB4 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This avoids using lm blocks that support DSPP when not needed, to keep those resources available. Signed-off-by: Arnaud Vrac --- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index f4dda88a73f7d..4b393d46c743f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -362,7 +362,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(struct dpu_rm *rm, *pp_idx = idx; if (!reqs->topology.num_dspp) - return true; + return !lm_cfg->dspp; idx = lm_cfg->dspp - DSPP_0; if (idx < 0 || idx >= ARRAY_SIZE(rm->dspp_blks)) {