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[83.9.29.144]) by smtp.gmail.com with ESMTPSA id w8-20020ac25d48000000b004eedb66983csm324256lfd.273.2023.04.20.15.31.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 15:31:22 -0700 (PDT) From: Konrad Dybcio Date: Fri, 21 Apr 2023 00:31:10 +0200 Subject: [PATCH v2 01/13] dt-bindings: display/msm: dsi-controller-main: Add SM6350 MIME-Version: 1.0 Message-Id: <20230411-topic-straitlagoon_mdss-v2-1-5def73f50980@linaro.org> References: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio , Rob Herring X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1682029879; l=1129; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=1EZeD/7Id9o6cBL4ylQ4GNUTK1f0wLzgpRCWpr/xxlY=; b=wcPs44uEQqo7xru1sJ+NnetyZuOSV0ot3K+yGfD6q7BPkHkYw3QFtH5LXw7Tm1g/nLRcx7x2ZTpV PmFalNyZAsKNw3ajQaTN5bG899GZ4jB9ffY6uOvQVN4xLUyZfp7t X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the DSI host found on SM6350. Acked-by: Rob Herring Signed-off-by: Konrad Dybcio --- Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index e6c1ebfe8a32..6f367a1fabf8 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -26,6 +26,7 @@ properties: - qcom,sdm660-dsi-ctrl - qcom,sdm845-dsi-ctrl - qcom,sm6115-dsi-ctrl + - qcom,sm6350-dsi-ctrl - qcom,sm8150-dsi-ctrl - qcom,sm8250-dsi-ctrl - qcom,sm8350-dsi-ctrl @@ -285,6 +286,7 @@ allOf: contains: enum: - qcom,msm8998-dsi-ctrl + - qcom,sm6350-dsi-ctrl then: properties: clocks: From patchwork Thu Apr 20 22:31:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 675694 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DDBD9C7618E for ; Thu, 20 Apr 2023 22:31:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232935AbjDTWbj (ORCPT ); Thu, 20 Apr 2023 18:31:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49728 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232790AbjDTWbb (ORCPT ); Thu, 20 Apr 2023 18:31:31 -0400 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 39E27423C for ; Thu, 20 Apr 2023 15:31:28 -0700 (PDT) Received: by mail-lf1-x12e.google.com with SMTP id 2adb3069b0e04-4ec81773d50so950538e87.2 for ; Thu, 20 Apr 2023 15:31:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682029886; x=1684621886; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=VJj4iUa0gP8dE+G0RSh+D7ANM6WUiBcMefoNYHpmjLo=; b=iLhtUyLEI5h9707Bz0eSJLkguwBa6XOJGzh37I0z2vb9Ca/QoEpeiMWcjQJqrI9Vkt QnD8TaJtg9wiBBv5Srk1pmhII07sprdy7KxQI1qs4W4zdqJ/6ZouOobyFrI2nQS04vNA tRbJv412j/22VhX2xsSLTn/9fdFvmpnt26wBHM2IS7/DqMvksvO2WZWJvV3/ckVNX4GO LkHNGyI0KN70paicigpYlelseajoNfziasQnGi1kOOSO4MWXJQu1sOMblsnIn7r6CaS7 +EbUAuC1hKqrbSc75Rj2Fk5oOiEE3VyxvvWpoKJHM4dBoULM/p80aYwzah/Bc9+0eZNl +9Gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682029886; x=1684621886; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VJj4iUa0gP8dE+G0RSh+D7ANM6WUiBcMefoNYHpmjLo=; b=N3+QsFQfRqV54y9S3kYRcQU5y1FZ1xBsHP9AlUX1j4G4DxDCVF9mY4x80Zfh+d6NCm 3gFycvvd+HBSdqeGUiMJxCdDroB73pUyEYnHY14K/8HZAs2y1Lr8ddfn3KTaNfYRx5Yi qc/KRQNen1QNVwdUcGQPVGoObT06IOkL4v8JBnd8k7OIpBZ6o79BltE3WzlBLdfD5h7P t0Line0Wd8ARGuhH40z2XIcuaYbCPcoVQy+DQykhrBeFG8sizajkHMhs5nDGx1RA7kZt VE7/zY+WX3JjG1J82+Fj5CCuRGmtMmFtPCX+Obx8XV/g/IKqRU4NEyfc5OXqOipiqxQr QEMA== X-Gm-Message-State: AAQBX9eQ8ZDzgp4mZmdHlDRlVvinRGQEKGqNx2zjGcMDro2T8qD8yYcz uljv90dip4NpSarleagL9DJUKA== X-Google-Smtp-Source: AKy350ZaZKdhevb+I6R02zGNmsqx/pDBw3ojmDsIhknsvSc29GRoNLxYD149FtIJnIMVKdZ7Ve5p7A== X-Received: by 2002:ac2:44db:0:b0:4db:3847:12f0 with SMTP id d27-20020ac244db000000b004db384712f0mr740802lfm.50.1682029886498; Thu, 20 Apr 2023 15:31:26 -0700 (PDT) Received: from [192.168.1.101] (abyj144.neoplus.adsl.tpnet.pl. [83.9.29.144]) by smtp.gmail.com with ESMTPSA id w8-20020ac25d48000000b004eedb66983csm324256lfd.273.2023.04.20.15.31.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 15:31:26 -0700 (PDT) From: Konrad Dybcio Date: Fri, 21 Apr 2023 00:31:12 +0200 Subject: [PATCH v2 03/13] dt-bindings: display/msm: Add SM6350 DPU MIME-Version: 1.0 Message-Id: <20230411-topic-straitlagoon_mdss-v2-3-5def73f50980@linaro.org> References: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1682029879; l=3116; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Jn7UUu6GoDaa1TPUPCp5gGqhPJdOjKwB/r9DEtFoZ/8=; b=hT4Kv6Rl8AlI+YMEYKy2x199yWG2QcMaUez6pKcGxf95PxJ9gt3z6p728s1HkV514Q/8P2XvMAM1 /Y9sppidCF+LVbqRnM8i2sidRJyhpuat81PIaTk/VypHfDVN6QLI X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the SM6350 DPU. Signed-off-by: Konrad Dybcio --- .../bindings/display/msm/qcom,sm6350-dpu.yaml | 94 ++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml new file mode 100644 index 000000000000..979fcf81afc9 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm6350-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DPU dt properties for SM6350 target + +maintainers: + - Konrad Dybcio + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + items: + - const: qcom,sm6350-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display axi clock + - description: Display ahb clock + - description: Display rot clock + - description: Display lut clock + - description: Display core clock + - description: Display vsync clock + + clock-names: + items: + - const: bus + - const: iface + - const: rot + - const: lut + - const: core + - const: vsync + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + display-controller@ae01000 { + compatible = "qcom,sm6350-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", "iface", "rot", "lut", "core", + "vsync"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + power-domains = <&rpmhpd SM6350_CX>; + operating-points-v2 = <&mdp_opp_table>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; +... 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[83.9.29.144]) by smtp.gmail.com with ESMTPSA id w8-20020ac25d48000000b004eedb66983csm324256lfd.273.2023.04.20.15.31.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 15:31:29 -0700 (PDT) From: Konrad Dybcio Date: Fri, 21 Apr 2023 00:31:14 +0200 Subject: [PATCH v2 05/13] dt-bindings: display/msm: Add SM6375 DPU MIME-Version: 1.0 Message-Id: <20230411-topic-straitlagoon_mdss-v2-5-5def73f50980@linaro.org> References: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1682029879; l=3492; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=vZzhA97oxdwZ/IPQF/OKwzeLk8iG5rTuB8ZFpx6DRZ0=; b=LHP9urgYRNjLl/5VSCLQUISqeihQSxNIUZy+XvNKkOEL9JqpSWQ2vdVfistdyy8B/5eY1mn0oqT/ KKMShazuBkrzUMnshYU5IHSJ7DAkhujaMV7IaAqS4nX6dB6v7NvC X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document SM6375 DPU. Signed-off-by: Konrad Dybcio --- .../bindings/display/msm/qcom,sm6375-dpu.yaml | 106 +++++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-dpu.yaml new file mode 100644 index 000000000000..76dc5a7efebf --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-dpu.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm6375-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DPU dt properties for SM6375 target + +maintainers: + - Konrad Dybcio + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + items: + - const: qcom,sm6375-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display iface clock + - description: Display bus clock + - description: Display core clock + - description: Display lut clock + - description: Display rot clock + - description: Display vsync clock + - description: Display throttle clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + - const: lut + - const: rot + - const: vsync + - const: throttle + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + display-controller@ae01000 { + compatible = "qcom,sm6375-dpu"; + reg = <0x05e01000 0x8e030>, + <0x05eb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&gcc GCC_DISP_THROTTLE_CORE_CLK>; + clock-names = "iface", + "bus", + "core", + "lut", + "rot", + "vsync", + "throttle"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd SM6375_VDDCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; +... 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[83.9.29.144]) by smtp.gmail.com with ESMTPSA id w8-20020ac25d48000000b004eedb66983csm324256lfd.273.2023.04.20.15.31.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 15:31:34 -0700 (PDT) From: Konrad Dybcio Date: Fri, 21 Apr 2023 00:31:17 +0200 Subject: [PATCH v2 08/13] drm/msm: mdss: Add SM6350 support MIME-Version: 1.0 Message-Id: <20230411-topic-straitlagoon_mdss-v2-8-5def73f50980@linaro.org> References: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1682029879; l=1325; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=YJnhuotbycPo0Lxuk2IRtdOzqse8Z1bIU0CErB+UTrw=; b=d5k6WYZUd1XbcPs5nVQlXqkJtEycVrXqJI6R1+zGm9QHV1JuWYVoLyI0UBWtYcyZeJB+Ge8Enm6E pWe8cxtkBAoI/eYMad7nfABBlIGkHpu+c6+M/fst+9zWU45spktu X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for MDSS on SM6350. Signed-off-by: Konrad Dybcio Reviewed-by: Marijn Suijten --- drivers/gpu/drm/msm/msm_mdss.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index e8c93731aaa1..4e3a5f0c303c 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -538,6 +538,14 @@ static const struct msm_mdss_data sdm845_data = { .highest_bank_bit = 2, }; +static const struct msm_mdss_data sm6350_data = { + .ubwc_version = UBWC_2_0, + .ubwc_dec_version = UBWC_2_0, + .ubwc_swizzle = 6, + .ubwc_static = 0x1e, + .highest_bank_bit = 1, +}; + static const struct msm_mdss_data sm8150_data = { .ubwc_version = UBWC_3_0, .ubwc_dec_version = UBWC_3_0, @@ -571,6 +579,7 @@ static const struct of_device_id mdss_dt_match[] = { { .compatible = "qcom,sc8180x-mdss", .data = &sc8180x_data }, { .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data }, { .compatible = "qcom,sm6115-mdss", .data = &sm6115_data }, + { .compatible = "qcom,sm6350-mdss", .data = &sm6350_data }, { .compatible = "qcom,sm8150-mdss", .data = &sm8150_data }, { .compatible = "qcom,sm8250-mdss", .data = &sm8250_data }, { .compatible = "qcom,sm8350-mdss", .data = &sm8250_data }, From patchwork Thu Apr 20 22:31:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 675691 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 519C0C77B7C for ; Thu, 20 Apr 2023 22:32:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233224AbjDTWcU (ORCPT ); Thu, 20 Apr 2023 18:32:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233120AbjDTWbx (ORCPT ); Thu, 20 Apr 2023 18:31:53 -0400 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 39D856A5A for ; Thu, 20 Apr 2023 15:31:39 -0700 (PDT) Received: by mail-lf1-x129.google.com with SMTP id 2adb3069b0e04-4edb9039a4cso932670e87.3 for ; Thu, 20 Apr 2023 15:31:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682029897; x=1684621897; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=4dxb6oAKpk/izyLUqwvlAuj2ZVQP3uibHpiE+szXdbE=; b=DAuz47bFZN+8HBZqxZK1xj7vzFzuO5b/1oE9TuSvW0GiNsasQcVrsGm053yAVeTTWk 2eN2fLzuJUom7JY4uk8VzYM5t+Vt90VQSFHOImPOPGH5d2aBs/ma1TV1EsB3hmrVNL+5 ahOSabOREEjvp8WdlOY370jq6G9AHZlEybYDvCFtf26OGrWAc4KINxo2JanYmCFSYtmr GGVWfZgHiEssIb4MPY2W0LHkXupzdMfsfKizgaqOfgkRTwfrvTUANnon/p66kUXi0BvB j0vf5jiHsd9MNstYqNSnQNL+6BUzYIX00gEgCymaDJQz6ouRQh062a72SrYm+Wof0Itf 24YA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682029897; x=1684621897; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4dxb6oAKpk/izyLUqwvlAuj2ZVQP3uibHpiE+szXdbE=; b=hMjuLm/qkvZj6t6DN9gjLM+1CNBNhfRQtZrzJGh6so9aDoY9ztR7XBy97rCX/+B9CB Chyj2fHZ9i/b916CU7iFRtX7xIadkvzMrrRKiaEfyrMhvdoQyUTFx+6G9q4AKQWWVmya +uek3U19wkFEuWlo1ktZ+tz2rcKouldmN43kqMvhdvFWVat30lwtZ40+SAzDqKhBUqOi e5wrC788b5Ks8A2urUo6IFg51tvcmenVJcYrqr8E0obhIFgX4xU3cCsNpTgmKiSz8Aij vTyv2JqEAGcRKLP36NqqQXfK6V4j+SCzGg25HIKFvHtuASlwgpoDYM24pKj5pKVUw4CS xoEQ== X-Gm-Message-State: AAQBX9dOs/bvFs3JA/Sj5JqDQACXCi+0mOyR513xi+WwPadQQgY0nvmb 7QS57PWgsOPafYz1o5tzsY/arg== X-Google-Smtp-Source: AKy350Z1Bt4w+Q8dsaEpaq74hi/eXznKY4JqZVcjq9ZvaaLcRchaTXMaiCYfstpq5UqMMZYjcpMfkw== X-Received: by 2002:ac2:55ba:0:b0:4db:2ab7:43e6 with SMTP id y26-20020ac255ba000000b004db2ab743e6mr789579lfg.44.1682029896888; Thu, 20 Apr 2023 15:31:36 -0700 (PDT) Received: from [192.168.1.101] (abyj144.neoplus.adsl.tpnet.pl. [83.9.29.144]) by smtp.gmail.com with ESMTPSA id w8-20020ac25d48000000b004eedb66983csm324256lfd.273.2023.04.20.15.31.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 15:31:36 -0700 (PDT) From: Konrad Dybcio Date: Fri, 21 Apr 2023 00:31:18 +0200 Subject: [PATCH v2 09/13] drm/msm/dpu: Add SM6375 support MIME-Version: 1.0 Message-Id: <20230411-topic-straitlagoon_mdss-v2-9-5def73f50980@linaro.org> References: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1682029879; l=8991; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=OM9y6PPtTxs3PCRleFOoCKfkmbVbBCFmJ4Gx6zoTa1k=; b=AD47pEiIgc6SBG55l/F4tvWLbCWuIV84cWo3vheN3jMPT4OBsk1AjKv3SdyxLhIAvDun6mV0m5F1 VHKQaDx4Ddis/q/gmMx5BLUc5iO0DsOdbO7OuckIaqya8surkD6Y X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add basic SM6375 support to the DPU1 driver to enable display output. Signed-off-by: Konrad Dybcio --- .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 5 - .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 152 +++++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 14 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 5 files changed, 168 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index 687a508cbaa6..d46b43964be6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -126,11 +126,6 @@ static const struct dpu_vbif_cfg sm6350_vbif[] = { }, }; -static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = { - {.fl = 0, .lut = 0x0011223344556677 }, - {.fl = 0, .lut = 0x0011223445566777 }, -}; - static const struct dpu_perf_cfg sm6350_perf_data = { .max_bw_low = 4200000, .max_bw_high = 5100000, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h new file mode 100644 index 000000000000..19ca0051e072 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DPU_6_9_SM6375_H +#define _DPU_6_9_SM6375_H + +static const struct dpu_caps sm6375_dpu_caps = { + .max_mixer_width = 2048, + .max_mixer_blendstages = 0x4, + .qseed_type = DPU_SSPP_SCALER_QSEED4, + .has_dim_layer = true, + .has_idle_pc = true, + .max_linewidth = 2160, + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_ubwc_cfg sm6375_ubwc_cfg = { + .ubwc_version = DPU_HW_UBWC_VER_20, + .ubwc_swizzle = 6, + .highest_bank_bit = 1, +}; + +static const struct dpu_mdp_cfg sm6375_mdp[] = { + { + .name = "top_0", .id = MDP_TOP, + .base = 0x0, .len = 0x494, + .features = 0, + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + }, +}; + +static const struct dpu_ctl_cfg sm6375_ctl[] = { + { + .name = "ctl_0", .id = CTL_0, + .base = 0x1000, .len = 0x1dc, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, +}; + +static const struct dpu_sspp_cfg sm6375_sspp[] = { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK, + sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), +}; + +static const struct dpu_lm_cfg sm6375_lm[] = { + LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK, + &sm6375_lm_sblk, PINGPONG_0, 0, DSPP_0), +}; + +static const struct dpu_dspp_cfg sm6375_dspp[] = { + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), +}; + +static const struct dpu_pingpong_cfg sm6375_pp[] = { + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + -1), +}; + +static const struct dpu_intf_cfg sm6375_intf[] = { + INTF_BLK("intf_0", INTF_0, 0x00000, 0x2c0, INTF_NONE, 0, 0, 0, 0, 0), + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7280_MASK, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), +}; + +static const struct dpu_vbif_cfg sm6375_vbif[] = { + { + .name = "vbif_0", .id = VBIF_RT, + .base = 0, .len = 0x2008, + .features = BIT(DPU_VBIF_QOS_REMAP), + .xin_halt_timeout = 0x4000, + .qos_rp_remap_size = 0x40, + .qos_rt_tbl = { + .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl), + .priority_lvl = sdm845_rt_pri_lvl, + }, + .qos_nrt_tbl = { + .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl), + .priority_lvl = sdm845_nrt_pri_lvl, + }, + .memtype_count = 14, + .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, + }, +}; + +static const struct dpu_perf_cfg sm6375_perf_data = { + .max_bw_low = 5200000, + .max_bw_high = 6200000, + .min_core_ib = 2500000, + .min_llcc_ib = 0, /* No LLCC on this SoC */ + .min_dram_ib = 1600000, + .min_prefill_lines = 24, + /* TODO: confirm danger_lut_tbl */ + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff}, + .qos_lut_tbl = { + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile), + .entries = sm6350_qos_linear_macrotile + }, + {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile), + .entries = sm6350_qos_linear_macrotile + }, + {.nentry = ARRAY_SIZE(sc7180_qos_nrt), + .entries = sc7180_qos_nrt + }, + }, + .cdp_cfg = { + {.rd_enable = 1, .wr_enable = 1}, + {.rd_enable = 1, .wr_enable = 0} + }, + .clk_inefficiency_factor = 105, + .bw_inefficiency_factor = 120, +}; + +const struct dpu_mdss_cfg dpu_sm6375_cfg = { + .caps = &sm6375_dpu_caps, + .ubwc = &sm6375_ubwc_cfg, + .mdp_count = ARRAY_SIZE(sm6375_mdp), + .mdp = sm6375_mdp, + .ctl_count = ARRAY_SIZE(sm6375_ctl), + .ctl = sm6375_ctl, + .sspp_count = ARRAY_SIZE(sm6375_sspp), + .sspp = sm6375_sspp, + .mixer_count = ARRAY_SIZE(sm6375_lm), + .mixer = sm6375_lm, + .dspp_count = ARRAY_SIZE(sm6375_dspp), + .dspp = sm6375_dspp, + .pingpong_count = ARRAY_SIZE(sm6375_pp), + .pingpong = sm6375_pp, + .intf_count = ARRAY_SIZE(sm6375_intf), + .intf = sm6375_intf, + .vbif_count = ARRAY_SIZE(sm6375_vbif), + .vbif = sm6375_vbif, + .perf = &sm6375_perf_data, + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_INTR) | \ + BIT(MDP_INTF1_INTR) +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 52750b592b36..29516273dd6b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -440,6 +440,14 @@ static const struct dpu_lm_sub_blks sc7180_lm_sblk = { }, }; +static const struct dpu_lm_sub_blks sm6375_lm_sblk = { + .maxwidth = 2048, + .maxblendstages = 4, /* excluding base layer */ + .blendstage_base = { /* offsets relative to mixer base */ + 0x20, 0x38, 0x50, 0x68 + }, +}; + /* QCM2290 */ static const struct dpu_lm_sub_blks qcm2290_lm_sblk = { @@ -751,6 +759,11 @@ static const struct dpu_qos_lut_entry sc7180_qos_linear[] = { {.fl = 0, .lut = 0x0011222222335777}, }; +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = { + {.fl = 0, .lut = 0x0011223344556677 }, + {.fl = 0, .lut = 0x0011223445566777 }, +}; + static const struct dpu_qos_lut_entry sm8150_qos_linear[] = { {.fl = 0, .lut = 0x0011222222223357 }, }; @@ -808,6 +821,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = { #include "catalog/dpu_6_3_sm6115.h" #include "catalog/dpu_6_4_sm6350.h" #include "catalog/dpu_6_5_qcm2290.h" +#include "catalog/dpu_6_9_sm6375.h" #include "catalog/dpu_7_0_sm8350.h" #include "catalog/dpu_7_2_sc7280.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index f9611bd75e02..b4f193037869 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -884,6 +884,7 @@ extern const struct dpu_mdss_cfg dpu_sc7180_cfg; extern const struct dpu_mdss_cfg dpu_sm6115_cfg; extern const struct dpu_mdss_cfg dpu_sm6350_cfg; extern const struct dpu_mdss_cfg dpu_qcm2290_cfg; +extern const struct dpu_mdss_cfg dpu_sm6375_cfg; extern const struct dpu_mdss_cfg dpu_sm8350_cfg; extern const struct dpu_mdss_cfg dpu_sc7280_cfg; extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 46be7ad8d615..980c3c8f8269 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1287,6 +1287,7 @@ static const struct of_device_id dpu_dt_match[] = { { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, }, { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, }, { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, }, + { .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, }, { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, }, { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, }, { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, }, From patchwork Thu Apr 20 22:31:20 2023 Content-Type: text/plain; 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[83.9.29.144]) by smtp.gmail.com with ESMTPSA id w8-20020ac25d48000000b004eedb66983csm324256lfd.273.2023.04.20.15.31.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 15:31:39 -0700 (PDT) From: Konrad Dybcio Date: Fri, 21 Apr 2023 00:31:20 +0200 Subject: [PATCH v2 11/13] iommu/arm-smmu-qcom: Add SM6375 DPU compatible MIME-Version: 1.0 Message-Id: <20230411-topic-straitlagoon_mdss-v2-11-5def73f50980@linaro.org> References: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1682029879; l=785; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=/9HUTFzDlWhvA+x0Ieoh1uk/GJ56evseSi3zEZVI4y0=; b=ROJxpQig3kurlmL1S3QtRtECNCPVtfMcinbv+K27HQnjedkIX8uJX5aG6iQpvL9I7p/oUOGv9hbW FCr4DwNFAO+ezsbjZfziED0S7dhYav6nqfEfdzaeIBUDDYNQX+Nk X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the SM6375 DPU compatible to clients compatible list, as it also needs the workarounds. Signed-off-by: Konrad Dybcio --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index ae09c627bc84..995ab5172883 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -255,6 +255,7 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { { .compatible = "qcom,sm8250-mdss" }, { .compatible = "qcom,sdm845-mdss" }, { .compatible = "qcom,sdm845-mss-pil" }, + { .compatible = "qcom,sm6375-mdss" }, { } }; From patchwork Thu Apr 20 22:31:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 675689 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1D88C77B7E for ; Thu, 20 Apr 2023 22:32:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233283AbjDTWcg (ORCPT ); Thu, 20 Apr 2023 18:32:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51124 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233199AbjDTWcN (ORCPT ); Thu, 20 Apr 2023 18:32:13 -0400 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C367F72AB for ; Thu, 20 Apr 2023 15:31:45 -0700 (PDT) Received: by mail-lf1-x12b.google.com with SMTP id 2adb3069b0e04-4eca19c3430so961734e87.1 for ; Thu, 20 Apr 2023 15:31:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682029903; x=1684621903; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=J8QyMbXoOHe4maJ/141Gl2opRXdF3vmPM4GP90Suqw8=; b=I0RuJim/ZifvTMm7CVHkzXSjJOF2vA532KiwtNLFVTQXWBbhF+e+ARmTjaDBf18orf qiKADkH5X0erT010RrJfLz4JiZfUTBQc7LnyAcaj+kXCPtP8M26HKUaUBYcmqV3JSio1 S0JmaO1Ubte8l9JRUmFkjhmj+gL5Fn27RRXMiCrkZacFiX+oNJ02ZpYQOPXkrT3fXswV upgGN5hgqC37TjWrUtT2TsWS1Di/+9IZzoWAl+LZj3XIq+61sTWVq8yl+sNFV5pUb4uM o7ddN/EfAW+F3mxpGcj2YWLcuCrMLKrcdKbyxgLN8tur0LLLWV/O9et6c8Hbry4HJtC3 v9ZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682029903; x=1684621903; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J8QyMbXoOHe4maJ/141Gl2opRXdF3vmPM4GP90Suqw8=; b=Ii0dOgmHRwwJ/PzGTAvQJx/OYRiMZ2ug69xccCRbSoMB4TxkufKHRvEn0Nmw6ZYts9 LFTSppqL641mR13DB1ogm38NzMznynT4OPOcF6RAZZgRUbp99Qa+F+iE9kQ72bEEwfvw o9SfGrkVxLr7eyAReM4Nx5uw0zf5vS6Xl1aU71finL9RrM5mdf9Y54GKhT+XlFLVNKQ4 gAGju/ENcWMQ+P8Vudw619QEDAqzrgoGNUc4Pwju9Ekp4E2a4JHW1IiGAqGBv/Oh5YtE oDPu/8ZI5v1wIfSu/Hz5rqTBDQ65hJeWVVWjnkbugoUMeWDW5XclHCF7nanfo1vM61HJ dj3g== X-Gm-Message-State: AAQBX9cHdOI8pzWJWvLX8JF+dkjZcyMhJNs5j45TzlBICa0C9wL1VtwY QNrvVIo4KkFm9JbBYRwdAAAC4A== X-Google-Smtp-Source: AKy350a1EqNhSqyvroEQFXEC3oNWZWKJ59j7Y7boNYcM6me6/l6zelpIdJE5bpeODyX5Mgx2NKVt3A== X-Received: by 2002:a05:6512:388e:b0:4eb:104b:bf61 with SMTP id n14-20020a056512388e00b004eb104bbf61mr801740lft.58.1682029903471; Thu, 20 Apr 2023 15:31:43 -0700 (PDT) Received: from [192.168.1.101] (abyj144.neoplus.adsl.tpnet.pl. [83.9.29.144]) by smtp.gmail.com with ESMTPSA id w8-20020ac25d48000000b004eedb66983csm324256lfd.273.2023.04.20.15.31.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 15:31:43 -0700 (PDT) From: Konrad Dybcio Date: Fri, 21 Apr 2023 00:31:22 +0200 Subject: [PATCH v2 13/13] iommu/arm-smmu-qcom: Sort the compatible list alphabetically MIME-Version: 1.0 Message-Id: <20230411-topic-straitlagoon_mdss-v2-13-5def73f50980@linaro.org> References: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1682029879; l=1047; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=4qlkXIpajO/screcnHozmWYEhsqRxqVWMGV9cb8adn0=; b=ku9MGWJ3g/n4SA+sMB5iIoSn/fJTWnS8wuxtVJXhCx8ML1znDgY0ILA0SMGsj+MXNuuj71iXZ8bD ZTVT1H7eBDFOQ12L6qLMqL1bRuGLZ14HOqrXVKTsCzbIlw32UOfb X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org It got broken at some point, fix it up. Signed-off-by: Konrad Dybcio --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 2daaa600ac75..e64c737724c4 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -251,12 +251,12 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { { .compatible = "qcom,sc7280-mss-pil" }, { .compatible = "qcom,sc8180x-mdss" }, { .compatible = "qcom,sc8280xp-mdss" }, - { .compatible = "qcom,sm8150-mdss" }, - { .compatible = "qcom,sm8250-mdss" }, { .compatible = "qcom,sdm845-mdss" }, { .compatible = "qcom,sdm845-mss-pil" }, { .compatible = "qcom,sm6350-mdss" }, { .compatible = "qcom,sm6375-mdss" }, + { .compatible = "qcom,sm8150-mdss" }, + { .compatible = "qcom,sm8250-mdss" }, { } };