From patchwork Sat Apr 22 07:37:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hao Zhang X-Patchwork-Id: 676225 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90040C7EE23 for ; Sat, 22 Apr 2023 07:38:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229635AbjDVHiU (ORCPT ); Sat, 22 Apr 2023 03:38:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229588AbjDVHiO (ORCPT ); Sat, 22 Apr 2023 03:38:14 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F71D1BC5; Sat, 22 Apr 2023 00:38:06 -0700 (PDT) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 33M7Wnnj032162; Sat, 22 Apr 2023 07:37:47 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=cCCZYAS2/s8RWHNCco2a0RAur54j7AIPIzJr3VO0/vY=; b=jpty315bCqWcFyo/DoIXxM4MDwzxWHStLLAmzx4feSIu41XTpUx8xwvZTjTLXChZeTYs Bpgm4x966aEuuQkkqN6yaHw9rBmeePrx0AQBf8wbMhXhL5oJ/QCBX3w4gWelEJ7TFjM9 As46stYG8YPrnsTuGwXmfGIaMT5hekHnvoqy1LKldWwZRtihLbfCgdcgQ2knLVnYgHyO lhU66OVP98jegT26JE1X6uKDfsnMgv4YMHG2GnFosOWq1cEMCn4SKfM5EGhazFSJMwnX Uq2cpOAqV34jnQgsI6DvA9i5lkHCANdTFxaXr0zv+ucW7vC7KnzDd3+nKe8LHYErDckg Gw== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3q48e1r5mk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 22 Apr 2023 07:37:46 +0000 Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 33M7bjV6007658 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 22 Apr 2023 07:37:45 GMT Received: from hazha-gv.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Sat, 22 Apr 2023 00:37:39 -0700 From: Hao Zhang To: Suzuki K Poulose , Mike Leach , Leo Yan , Alexander Shishkin , Mathieu Poirier , Konrad Dybcio , "Rob Herring" , Krzysztof Kozlowski , Andy Gross , "Paul Walmsley" , Palmer Dabbelt , Albert Ou , Jonathan Corbet CC: Hao Zhang , Greg Kroah-Hartman , , , , , Tingwei Zhang , Jinlong Mao , Yuanfang Zhang , Tao Zhang , Trilok Soni , , Bjorn Andersson , Subject: [PATCH v3 1/3] Coresight: Add coresight dummy driver Date: Sat, 22 Apr 2023 15:37:12 +0800 Message-ID: <20230422073714.38844-2-quic_hazha@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230422073714.38844-1-quic_hazha@quicinc.com> References: <20230422073714.38844-1-quic_hazha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: X86axpGb_sjpFv6MYDYGnvkI6Cnp1Fq_ X-Proofpoint-ORIG-GUID: X86axpGb_sjpFv6MYDYGnvkI6Cnp1Fq_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-21_08,2023-04-21_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 adultscore=0 bulkscore=0 mlxlogscore=999 priorityscore=1501 mlxscore=0 spamscore=0 impostorscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304220064 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some Coresight devices that kernel don't have permission to access or configure. So there need driver to register dummy devices as Coresight devices. It may also be used to define components that may not have any programming interfaces (e.g, static links), so that paths can be established in the driver. Provide Coresight API for dummy device operations, such as enabling and disabling dummy devices. Build the Coresight path for dummy sink or dummy source for debugging. Signed-off-by: Hao Zhang --- drivers/hwtracing/coresight/Kconfig | 11 ++ drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-dummy.c | 179 ++++++++++++++++++ include/linux/coresight.h | 1 + 4 files changed, 192 insertions(+) create mode 100644 drivers/hwtracing/coresight/coresight-dummy.c diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index 2b5bbfffbc4f..06f0a7594169 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -236,4 +236,15 @@ config CORESIGHT_TPDA To compile this driver as a module, choose M here: the module will be called coresight-tpda. + +config CORESIGHT_DUMMY + tristate "Dummy driver support" + help + Enables support for dummy driver. Dummy driver can be used for + CoreSight sources/sinks that are owned and configured by some + other subsystem and use Linux drivers to configure rest of trace + path. + + To compile this driver as a module, choose M here: the module will be + called coresight-dummy. endif diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index 33bcc3f7b8ae..995d3b2c76df 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -30,3 +30,4 @@ obj-$(CONFIG_CORESIGHT_TPDA) += coresight-tpda.o coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \ coresight-cti-sysfs.o obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o +obj-$(CONFIG_CORESIGHT_DUMMY) += coresight-dummy.o diff --git a/drivers/hwtracing/coresight/coresight-dummy.c b/drivers/hwtracing/coresight/coresight-dummy.c new file mode 100644 index 000000000000..1fb8b3d1c170 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-dummy.c @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include "coresight-priv.h" +#include "coresight-trace-id.h" + +struct dummy_drvdata { + struct device *dev; + struct coresight_device *csdev; + int traceid; +}; + +DEFINE_CORESIGHT_DEVLIST(source_devs, "dummy_source"); +DEFINE_CORESIGHT_DEVLIST(sink_devs, "dummy_sink"); + +static int dummy_source_enable(struct coresight_device *csdev, + struct perf_event *event, u32 mode) +{ + struct dummy_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + dev_dbg(drvdata->dev, "Dummy source enabled\n"); + + return 0; +} + +static void dummy_source_disable(struct coresight_device *csdev, + struct perf_event *event) +{ + struct dummy_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + dev_dbg(drvdata->dev, "Dummy source disabled\n"); +} + +static int dummy_sink_enable(struct coresight_device *csdev, u32 mode, + void *data) +{ + struct dummy_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + dev_dbg(drvdata->dev, "Dummy sink enabled\n"); + + return 0; +} + +static int dummy_sink_disable(struct coresight_device *csdev) +{ + struct dummy_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + dev_dbg(drvdata->dev, "Dummy sink disabled\n"); + + return 0; +} + +static const struct coresight_ops_source dummy_source_ops = { + .enable = dummy_source_enable, + .disable = dummy_source_disable, +}; + +static const struct coresight_ops dummy_source_cs_ops = { + .source_ops = &dummy_source_ops, +}; + +static const struct coresight_ops_sink dummy_sink_ops = { + .enable = dummy_sink_enable, + .disable = dummy_sink_disable, +}; + +static const struct coresight_ops dummy_sink_cs_ops = { + .sink_ops = &dummy_sink_ops, +}; + +static int dummy_probe(struct platform_device *pdev) +{ + int trace_id; + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + struct coresight_platform_data *pdata; + struct dummy_drvdata *drvdata; + struct coresight_desc desc = { 0 }; + + if (of_device_is_compatible(node, "arm,coresight-dummy-source")) { + trace_id = coresight_trace_id_get_system_id(); + if (trace_id < 0) + return trace_id; + + desc.name = coresight_alloc_device_name(&source_devs, dev); + if (!desc.name) + return -ENOMEM; + + desc.type = CORESIGHT_DEV_TYPE_SOURCE; + desc.subtype.source_subtype = + CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS; + desc.ops = &dummy_source_cs_ops; + } else if (of_device_is_compatible(node, "arm,coresight-dummy-sink")) { + desc.name = coresight_alloc_device_name(&sink_devs, dev); + if (!desc.name) + return -ENOMEM; + + desc.type = CORESIGHT_DEV_TYPE_SINK; + desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_DUMMY; + desc.ops = &dummy_sink_cs_ops; + } else { + dev_err(dev, "Device type not set\n"); + return -EINVAL; + } + + pdata = coresight_get_platform_data(dev); + if (IS_ERR(pdata)) + return PTR_ERR(pdata); + pdev->dev.platform_data = pdata; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->dev = &pdev->dev; + platform_set_drvdata(pdev, drvdata); + + desc.pdata = pdev->dev.platform_data; + desc.dev = &pdev->dev; + drvdata->csdev = coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); + + drvdata->traceid = (u8)trace_id; + + pm_runtime_enable(dev); + dev_dbg(dev, "Dummy device initialized\n"); + + return 0; +} + +static int dummy_remove(struct platform_device *pdev) +{ + struct dummy_drvdata *drvdata = platform_get_drvdata(pdev); + struct device *dev = &pdev->dev; + + pm_runtime_disable(dev); + coresight_unregister(drvdata->csdev); + return 0; +} + +static const struct of_device_id dummy_match[] = { + {.compatible = "arm,coresight-dummy-source"}, + {.compatible = "arm,coresight-dummy-sink"}, + {}, +}; + +static struct platform_driver dummy_driver = { + .probe = dummy_probe, + .remove = dummy_remove, + .driver = { + .name = "coresight-dummy", + .of_match_table = dummy_match, + }, +}; + +static int __init dummy_init(void) +{ + return platform_driver_register(&dummy_driver); +} +module_init(dummy_init); + +static void __exit dummy_exit(void) +{ + platform_driver_unregister(&dummy_driver); +} +module_exit(dummy_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("CoreSight dummy driver"); diff --git a/include/linux/coresight.h b/include/linux/coresight.h index f19a47b9bb5a..6db4b49751cf 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -45,6 +45,7 @@ enum coresight_dev_type { }; enum coresight_dev_subtype_sink { + CORESIGHT_DEV_SUBTYPE_SINK_DUMMY, CORESIGHT_DEV_SUBTYPE_SINK_PORT, CORESIGHT_DEV_SUBTYPE_SINK_BUFFER, CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM, From patchwork Sat Apr 22 07:37:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hao Zhang X-Patchwork-Id: 676226 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0362C6FD18 for ; Sat, 22 Apr 2023 07:38:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229556AbjDVHiO (ORCPT ); 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Sat, 22 Apr 2023 07:37:53 +0000 Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 33M7bq5Z003864 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 22 Apr 2023 07:37:52 GMT Received: from hazha-gv.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Sat, 22 Apr 2023 00:37:46 -0700 From: Hao Zhang To: Suzuki K Poulose , Mike Leach , Leo Yan , Alexander Shishkin , Mathieu Poirier , Konrad Dybcio , "Rob Herring" , Krzysztof Kozlowski , Andy Gross , "Paul Walmsley" , Palmer Dabbelt , Albert Ou , Jonathan Corbet CC: Hao Zhang , Greg Kroah-Hartman , , , , , Tingwei Zhang , Jinlong Mao , Yuanfang Zhang , Tao Zhang , Trilok Soni , , Bjorn Andersson , Subject: [PATCH v3 2/3] dt-bindings: arm: Add Coresight Dummy Trace Date: Sat, 22 Apr 2023 15:37:13 +0800 Message-ID: <20230422073714.38844-3-quic_hazha@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230422073714.38844-1-quic_hazha@quicinc.com> References: <20230422073714.38844-1-quic_hazha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: JnabgeTynP75g-Kpp9ZRPX63LJhsIZDk X-Proofpoint-ORIG-GUID: JnabgeTynP75g-Kpp9ZRPX63LJhsIZDk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-21_08,2023-04-21_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 adultscore=0 bulkscore=0 mlxlogscore=912 priorityscore=1501 mlxscore=0 spamscore=0 impostorscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304220064 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add new coresight-dummy.yaml file describing the bindings required to define coresight dummy trace in the device trees. Signed-off-by: Hao Zhang --- .../bindings/arm/arm,coresight-dummy.yaml | 101 ++++++++++++++++++ 1 file changed, 101 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-dummy.yaml diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dummy.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dummy.yaml new file mode 100644 index 000000000000..48d864aefaaa --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dummy.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-dummy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Coresight Dummy component + +description: | + Coresight Dummy Trace Module is for the specific devices that kernel + don't have permission to access or configure, e.g., CoreSight TPDMs + on Qualcomm platforms. So there need driver to register dummy devices + as Coresight devices. It may also be used to define components that + may not have any programming interfaces (e.g, static links), so that + paths can be established in the driver. Provide Coresight API for + dummy device operations, such as enabling and disabling dummy devices. + Build the Coresight path for dummy sink or dummy source for debugging. + + The primary use case of the coresight dummy is to build path in kernel + side for dummy sink and dummy source. + +maintainers: + - Mao Jinlong + - Tao Zhang + - Hao Zhang + +properties: + compatible: + oneOf: + - enum: + - arm,coresight-dummy-sink + - arm,coresight-dummy-source + + out-ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port: + description: Output connection from the source to Coresight + Trace bus. + $ref: /schemas/graph.yaml#/properties/port + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port: + description: Input connection from the Coresight Trace bus to + dummy sink, such as Embedded USB debugger(EUD). + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + +if: + # If the compatible contains the below value + properties: + compatible: + contains: + const: arm,coresight-dummy-sink + +then: + required: + - in-ports + +else: + required: + - out-ports + +additionalProperties: false + +examples: + # Minimum dummy sink definition. Dummy sink connect to coresight replicator. + - | + sink { + compatible = "arm,coresight-dummy-sink"; + + in-ports { + port { + eud_in_replicator_swao: endpoint { + remote-endpoint = <&replicator_swao_out_eud>; + }; + }; + }; + }; + + # Minimum dummy source definition. Dummy source connect to coresight funnel. + - | + source { + compatible = "arm,coresight-dummy-source"; + + out-ports { + port { + dummy_riscv_out_funnel_swao: endpoint { + remote-endpoint = <&funnel_swao_in_dummy_riscv>; + }; + }; + }; + }; + +... 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Signed-off-by: Hao Zhang --- .../trace/coresight/coresight-dummy.rst | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 Documentation/trace/coresight/coresight-dummy.rst diff --git a/Documentation/trace/coresight/coresight-dummy.rst b/Documentation/trace/coresight/coresight-dummy.rst new file mode 100644 index 000000000000..d0f73253f694 --- /dev/null +++ b/Documentation/trace/coresight/coresight-dummy.rst @@ -0,0 +1,34 @@ +.. SPDX-License-Identifier: GPL-2.0 + +============================= +Coresight Dummy Trace Module +============================= + + :Author: Hao Zhang + :Date: April 2023 + +Introduction +--------------------------- + +Coresight Dummy Trace Module is for the specific devices that kernel +don't have permission to access or configure, e.g., CoreSight TPDMs +on Qualcomm platforms. So there need driver to register dummy devices +as Coresight devices. It may also be used to define components that +may not have any programming interfaces (e.g, static links), so that +paths can be established in the driver. Provide Coresight API for +dummy device operations, such as enabling and disabling dummy devices. +Build the Coresight path for dummy sink or dummy source for debugging. + +Config details +--------------------------- + +There are two types of nodes, dummy sink and dummy source. The nodes +should be observed at the below coresight path:: + + ``/sys/bus/coresight/devices``. + +e.g.:: + + / $ ls -l /sys/bus/coresight/devices | grep dummy + dummy0 -> ../../../devices/platform/soc@0/soc@0:dummy_source/dummy0 + dummy1 -> ../../../devices/platform/soc@0/soc@0:dummy_sink/dummy1