From patchwork Wed Apr 26 06:35:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samin Guo X-Patchwork-Id: 677235 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07193C7EE23 for ; Wed, 26 Apr 2023 06:35:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239614AbjDZGfz (ORCPT ); Wed, 26 Apr 2023 02:35:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52426 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239611AbjDZGfx (ORCPT ); Wed, 26 Apr 2023 02:35:53 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9AB0B211D; Tue, 25 Apr 2023 23:35:52 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id AA2B37FD6; Wed, 26 Apr 2023 14:35:44 +0800 (CST) Received: from EXMBX162.cuchost.com (172.16.6.72) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 26 Apr 2023 14:35:44 +0800 Received: from starfive-sdk.starfivetech.com (171.223.208.138) by EXMBX162.cuchost.com (172.16.6.72) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 26 Apr 2023 14:35:43 +0800 From: Samin Guo To: , , , Peter Geis , Frank CC: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Andrew Lunn , "Heiner Kallweit" , Russell King , "Samin Guo" , Yanhong Wang Subject: [PATCH v1 2/2] net: phy: motorcomm: Add pad drive strength cfg support Date: Wed, 26 Apr 2023 14:35:41 +0800 Message-ID: <20230426063541.15378-3-samin.guo@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230426063541.15378-1-samin.guo@starfivetech.com> References: <20230426063541.15378-1-samin.guo@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX162.cuchost.com (172.16.6.72) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The motorcomm phy (YT8531) supports the ability to adjust the drive strength of the rx_clk/rx_data, and the default strength may not be suitable for all boards. So add configurable options to better match the boards.(e.g. StarFive VisionFive 2) Signed-off-by: Samin Guo --- drivers/net/phy/motorcomm.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c index 2fa5a90e073b..08f28ed83e60 100644 --- a/drivers/net/phy/motorcomm.c +++ b/drivers/net/phy/motorcomm.c @@ -236,6 +236,11 @@ */ #define YTPHY_WCR_TYPE_PULSE BIT(0) +#define YTPHY_PAD_DRIVE_STRENGTH_REG 0xA010 +#define YTPHY_RGMII_RXC_DS GENMASK(15, 13) +#define YTPHY_RGMII_RXD_DS GENMASK(5, 4) /* Bit 1 and 0 of rgmii_rxd_ds */ +#define YTPHY_RGMII_RXD_DS2 BIT(12) /* Bit 2 of rgmii_rxd_ds */ + #define YTPHY_SYNCE_CFG_REG 0xA012 #define YT8521_SCR_SYNCE_ENABLE BIT(5) /* 1b0 output 25m clock @@ -1495,6 +1500,7 @@ static int yt8531_config_init(struct phy_device *phydev) { struct device_node *node = phydev->mdio.dev.of_node; int ret; + u32 val; ret = ytphy_rgmii_clk_delay_config_with_lock(phydev); if (ret < 0) @@ -1518,6 +1524,32 @@ static int yt8531_config_init(struct phy_device *phydev) return ret; } + if (!of_property_read_u32(node, "rx-clk-driver-strength", &val)) { + ret = ytphy_modify_ext_with_lock(phydev, + YTPHY_PAD_DRIVE_STRENGTH_REG, + YTPHY_RGMII_RXC_DS, + FIELD_PREP(YTPHY_RGMII_RXC_DS, val)); + if (ret < 0) + return ret; + } + + if (!of_property_read_u32(node, "rx-data-driver-strength", &val)) { + if (val > FIELD_MAX(YTPHY_RGMII_RXD_DS)) { + val &= FIELD_MAX(YTPHY_RGMII_RXD_DS); + val = FIELD_PREP(YTPHY_RGMII_RXD_DS, val); + val |= YTPHY_RGMII_RXD_DS2; + } else { + val = FIELD_PREP(YTPHY_RGMII_RXD_DS, val); + } + + ret = ytphy_modify_ext_with_lock(phydev, + YTPHY_PAD_DRIVE_STRENGTH_REG, + YTPHY_RGMII_RXD_DS | YTPHY_RGMII_RXD_DS2, + val); + if (ret < 0) + return ret; + } + return 0; }