From patchwork Thu May 4 20:06:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 679190 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C48BC77B7C for ; Thu, 4 May 2023 20:23:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232634AbjEDUXU (ORCPT ); Thu, 4 May 2023 16:23:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33968 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232128AbjEDUXA (ORCPT ); Thu, 4 May 2023 16:23:00 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D339460DD; Thu, 4 May 2023 13:08:56 -0700 (PDT) Received: from localhost (unknown [188.27.34.213]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id 1ACB166056FE; Thu, 4 May 2023 21:06:59 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1683230819; bh=FAY1EPbzVsY+T4aD7Y+s8uKBaKAiDAFUSJuuliQH5Ko=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=K0g/PopkGy/ytdJlNuQK+/YBNqdYPmR0qFKbxcczNPnJu7F4Vz3YUtRGMnoPOd4/Q SVkO3mP1g04isjX3tDLN6ehlb/E2SzBQbQzMERbqfQvvGgDgYCCbyi17a5PmMOADGN PNpx4mMQqRidja+tIKODSw4CWllXJxxLF9aKOnJLzZF2kPAIzUyhGGTUnzyd0vfyvf 2dmgYqlDsef5SutVFB7yStze4ghkDiOPhrH8ZBznAsvRrqhZ7saT6gCI+Tv2TPUFt7 V56dfFuB9q+Kg5afDmszFAtxsgLZCcuPT6qk7mSm1kPrW6X1mD9x8SviEkvDQbUP3B eRH83iAyVHEgg== From: Cristian Ciocaltea To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Philipp Zabel , Sebastian Reichel , Shreeya Patel , Kever Yang , Finley Xiao , Vincent Legoll Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 1/8] dt-bindings: nvmem: Convert rockchip-otp.txt to dt-schema Date: Thu, 4 May 2023 23:06:41 +0300 Message-Id: <20230504200648.1119866-2-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230504200648.1119866-1-cristian.ciocaltea@collabora.com> References: <20230504200648.1119866-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Rockchip OTP memory bindings to dt-schema. Signed-off-by: Cristian Ciocaltea Reviewed-by: Heiko Stuebner --- .../bindings/nvmem/rockchip,otp.yaml | 82 +++++++++++++++++++ .../bindings/nvmem/rockchip-otp.txt | 25 ------ 2 files changed, 82 insertions(+), 25 deletions(-) create mode 100644 Documentation/devicetree/bindings/nvmem/rockchip,otp.yaml delete mode 100644 Documentation/devicetree/bindings/nvmem/rockchip-otp.txt diff --git a/Documentation/devicetree/bindings/nvmem/rockchip,otp.yaml b/Documentation/devicetree/bindings/nvmem/rockchip,otp.yaml new file mode 100644 index 000000000000..4cd425ae2823 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/rockchip,otp.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/rockchip,otp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip internal OTP (One Time Programmable) memory + +maintainers: + - Heiko Stuebner + +allOf: + - $ref: nvmem.yaml# + +properties: + compatible: + enum: + - rockchip,px30-otp + - rockchip,rk3308-otp + + reg: + maxItems: 1 + + clocks: + maxItems: 3 + + clock-names: + items: + - const: otp + - const: apb_pclk + - const: phy + + resets: + maxItems: 1 + + reset-names: + items: + - const: phy + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + +unevaluatedProperties: false + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + otp: efuse@ff290000 { + compatible = "rockchip,px30-otp"; + reg = <0x0 0xff290000 0x0 0x4000>; + clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, + <&cru PCLK_OTP_PHY>; + clock-names = "otp", "apb_pclk", "phy"; + resets = <&cru SRST_OTP_PHY>; + reset-names = "phy"; + #address-cells = <1>; + #size-cells = <1>; + + cpu_id: id@7 { + reg = <0x07 0x10>; + }; + + cpu_leakage: cpu-leakage@17 { + reg = <0x17 0x1>; + }; + + performance: performance@1e { + reg = <0x1e 0x1>; + bits = <4 3>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/nvmem/rockchip-otp.txt b/Documentation/devicetree/bindings/nvmem/rockchip-otp.txt deleted file mode 100644 index 40f649f7c2e5..000000000000 --- a/Documentation/devicetree/bindings/nvmem/rockchip-otp.txt +++ /dev/null @@ -1,25 +0,0 @@ -Rockchip internal OTP (One Time Programmable) memory device tree bindings - -Required properties: -- compatible: Should be one of the following. - - "rockchip,px30-otp" - for PX30 SoCs. - - "rockchip,rk3308-otp" - for RK3308 SoCs. -- reg: Should contain the registers location and size -- clocks: Must contain an entry for each entry in clock-names. -- clock-names: Should be "otp", "apb_pclk" and "phy". -- resets: Must contain an entry for each entry in reset-names. - See ../../reset/reset.txt for details. -- reset-names: Should be "phy". - -See nvmem.txt for more information. - -Example: - otp: otp@ff290000 { - compatible = "rockchip,px30-otp"; - reg = <0x0 0xff290000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, - <&cru PCLK_OTP_PHY>; - clock-names = "otp", "apb_pclk", "phy"; - }; From patchwork Thu May 4 20:06:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 679188 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5161BC77B78 for ; Thu, 4 May 2023 20:39:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230122AbjEDUjT (ORCPT ); Thu, 4 May 2023 16:39:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53668 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230474AbjEDUjA (ORCPT ); Thu, 4 May 2023 16:39:00 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DAD8222F6D; Thu, 4 May 2023 13:33:24 -0700 (PDT) Received: from localhost (unknown [188.27.34.213]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id 7D64D6605706; Thu, 4 May 2023 21:07:04 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1683230824; bh=bsTYiFtKphZh0XX4Lj4uy3XKBQ72cqtuCs3n4S2XrLE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VarQny02pcjwxuZN35D8+n09G0gD2N5TIHVicIy4RHQSzpJCKfAsbDN+rtRc/FsIV xenUc25X8oZkTYOtWiVXBR+fjWFq9fITiqyT9faQaaK2+H8A7FzYIMo4oVLBgZwDGb VciirdQjZrvHCCXXgc/+oDZr22hzWQkzQej0rVc+8a/2E0Ny6b1ThKHpVACO8GFG0+ 7AenE7Qh4saScriLumELH5pO8oHsAYiH7Vq60QtKrhhElyB90PuXwQHVlN2nGgUNUJ q0YRvdMo0p6spbsL//13GqjIR8CtxigPxtXKNue3+8qMjlNED5RZWhjvKXKworGtAo 1anN3d8ADkpKQ== From: Cristian Ciocaltea To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Philipp Zabel , Sebastian Reichel , Shreeya Patel , Kever Yang , Finley Xiao , Vincent Legoll Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 3/8] nvmem: rockchip-otp: Add clks and reg_read to rockchip_data Date: Thu, 4 May 2023 23:06:43 +0300 Message-Id: <20230504200648.1119866-4-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230504200648.1119866-1-cristian.ciocaltea@collabora.com> References: <20230504200648.1119866-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In preparation to support new Rockchip OTP memory devices with different clock configurations and register layout, extend rockchip_data struct with the related members: clks, num_clks, reg_read. Additionally, to avoid managing redundant driver data, drop num_clks member from rockchip_otp struct and update all references to point to the equivalent member in rockchip_data. Signed-off-by: Cristian Ciocaltea Tested-by: Vincent Legoll Reviewed-by: Heiko Stuebner --- drivers/nvmem/rockchip-otp.c | 79 ++++++++++++++++++++++-------------- 1 file changed, 49 insertions(+), 30 deletions(-) diff --git a/drivers/nvmem/rockchip-otp.c b/drivers/nvmem/rockchip-otp.c index 9f53bcce2f87..b5a84b379da4 100644 --- a/drivers/nvmem/rockchip-otp.c +++ b/drivers/nvmem/rockchip-otp.c @@ -54,21 +54,19 @@ #define OTPC_TIMEOUT 10000 +struct rockchip_data { + int size; + const char * const *clks; + int num_clks; + nvmem_reg_read_t reg_read; +}; + struct rockchip_otp { struct device *dev; void __iomem *base; - struct clk_bulk_data *clks; - int num_clks; + struct clk_bulk_data *clks; struct reset_control *rst; -}; - -/* list of required clocks */ -static const char * const rockchip_otp_clocks[] = { - "otp", "apb_pclk", "phy", -}; - -struct rockchip_data { - int size; + const struct rockchip_data *data; }; static int rockchip_otp_reset(struct rockchip_otp *otp) @@ -132,29 +130,23 @@ static int rockchip_otp_ecc_enable(struct rockchip_otp *otp, bool enable) return ret; } -static int rockchip_otp_read(void *context, unsigned int offset, - void *val, size_t bytes) +static int px30_otp_read(void *context, unsigned int offset, + void *val, size_t bytes) { struct rockchip_otp *otp = context; u8 *buf = val; - int ret = 0; - - ret = clk_bulk_prepare_enable(otp->num_clks, otp->clks); - if (ret < 0) { - dev_err(otp->dev, "failed to prepare/enable clks\n"); - return ret; - } + int ret; ret = rockchip_otp_reset(otp); if (ret) { dev_err(otp->dev, "failed to reset otp phy\n"); - goto disable_clks; + return ret; } ret = rockchip_otp_ecc_enable(otp, false); if (ret < 0) { dev_err(otp->dev, "rockchip_otp_ecc_enable err\n"); - goto disable_clks; + return ret; } writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL); @@ -174,8 +166,28 @@ static int rockchip_otp_read(void *context, unsigned int offset, read_end: writel(0x0 | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL); -disable_clks: - clk_bulk_disable_unprepare(otp->num_clks, otp->clks); + + return ret; +} + +static int rockchip_otp_read(void *context, unsigned int offset, + void *val, size_t bytes) +{ + struct rockchip_otp *otp = context; + int ret; + + if (!otp->data || !otp->data->reg_read) + return -EINVAL; + + ret = clk_bulk_prepare_enable(otp->data->num_clks, otp->clks); + if (ret < 0) { + dev_err(otp->dev, "failed to prepare/enable clks\n"); + return ret; + } + + ret = otp->data->reg_read(context, offset, val, bytes); + + clk_bulk_disable_unprepare(otp->data->num_clks, otp->clks); return ret; } @@ -189,8 +201,15 @@ static struct nvmem_config otp_config = { .reg_read = rockchip_otp_read, }; +static const char * const px30_otp_clocks[] = { + "otp", "apb_pclk", "phy", +}; + static const struct rockchip_data px30_data = { .size = 0x40, + .clks = px30_otp_clocks, + .num_clks = ARRAY_SIZE(px30_otp_clocks), + .reg_read = px30_otp_read, }; static const struct of_device_id rockchip_otp_match[] = { @@ -225,21 +244,21 @@ static int rockchip_otp_probe(struct platform_device *pdev) if (!otp) return -ENOMEM; + otp->data = data; otp->dev = dev; otp->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(otp->base)) return PTR_ERR(otp->base); - otp->num_clks = ARRAY_SIZE(rockchip_otp_clocks); - otp->clks = devm_kcalloc(dev, otp->num_clks, - sizeof(*otp->clks), GFP_KERNEL); + otp->clks = devm_kcalloc(dev, data->num_clks, sizeof(*otp->clks), + GFP_KERNEL); if (!otp->clks) return -ENOMEM; - for (i = 0; i < otp->num_clks; ++i) - otp->clks[i].id = rockchip_otp_clocks[i]; + for (i = 0; i < data->num_clks; ++i) + otp->clks[i].id = data->clks[i]; - ret = devm_clk_bulk_get(dev, otp->num_clks, otp->clks); + ret = devm_clk_bulk_get(dev, data->num_clks, otp->clks); if (ret) return ret; From patchwork Thu May 4 20:06:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 679186 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 367ABC77B7C for ; Thu, 4 May 2023 20:40:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229506AbjEDUkN (ORCPT ); Thu, 4 May 2023 16:40:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53950 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231598AbjEDUjz (ORCPT ); Thu, 4 May 2023 16:39:55 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CCE9D1A1CD; Thu, 4 May 2023 13:34:44 -0700 (PDT) Received: from localhost (unknown [188.27.34.213]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id 3779B6605701; Thu, 4 May 2023 21:07:08 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1683230828; bh=tj5wNFVQXlsB8/T7XkM5lV9GRsAs+861QXowj8ll4qg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=D5fUQzDh9jZEt4W5d0V5VZwBtc1VqHnMitIS+KkO9iiZxxrcKpyyR/dEow0nnuQmj ISR0vIw7Lpk+hC0hNaUF+F+TfDHc3foG3jBzfdDdd1i8Fn2yGfKkJ0PhdBdKT+qvkw Oufm+hnUZBbqTuWAuNosAZpMfaTQwjeH/ROcbcTKNyIPueZdoiPIBJjxPK4qo+t+bA c6BOWprlQYeRoy9piCHGnilDSN56RoG4Gd3v4DrFxfSq7E8ZU8SoBwipsE4VPgh+HS 8hHd8rnHCLq9tA6IglAWi95kjzn/Xk5aEidcK1G95V/m1PYysQzNn5F2ovUp++aemm Wm0SJVgQ/8BZg== From: Cristian Ciocaltea To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Philipp Zabel , Sebastian Reichel , Shreeya Patel , Kever Yang , Finley Xiao , Vincent Legoll Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 4/8] nvmem: rockchip-otp: Generalize rockchip_otp_wait_status() Date: Thu, 4 May 2023 23:06:44 +0300 Message-Id: <20230504200648.1119866-5-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230504200648.1119866-1-cristian.ciocaltea@collabora.com> References: <20230504200648.1119866-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In preparation to support additional Rockchip OTP memory devices with different register layout, generalize rockchip_otp_wait_status() to accept a new parameter for specifying the offset of the status register. Signed-off-by: Cristian Ciocaltea Tested-by: Vincent Legoll Reviewed-by: Heiko Stuebner --- drivers/nvmem/rockchip-otp.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/nvmem/rockchip-otp.c b/drivers/nvmem/rockchip-otp.c index b5a84b379da4..b62e001f9116 100644 --- a/drivers/nvmem/rockchip-otp.c +++ b/drivers/nvmem/rockchip-otp.c @@ -90,18 +90,19 @@ static int rockchip_otp_reset(struct rockchip_otp *otp) return 0; } -static int rockchip_otp_wait_status(struct rockchip_otp *otp, u32 flag) +static int rockchip_otp_wait_status(struct rockchip_otp *otp, + unsigned int reg, u32 flag) { u32 status = 0; int ret; - ret = readl_poll_timeout_atomic(otp->base + OTPC_INT_STATUS, status, + ret = readl_poll_timeout_atomic(otp->base + reg, status, (status & flag), 1, OTPC_TIMEOUT); if (ret) return ret; /* clean int status */ - writel(flag, otp->base + OTPC_INT_STATUS); + writel(flag, otp->base + reg); return 0; } @@ -123,7 +124,7 @@ static int rockchip_otp_ecc_enable(struct rockchip_otp *otp, bool enable) writel(SBPI_ENABLE_MASK | SBPI_ENABLE, otp->base + OTPC_SBPI_CTRL); - ret = rockchip_otp_wait_status(otp, OTPC_SBPI_DONE); + ret = rockchip_otp_wait_status(otp, OTPC_INT_STATUS, OTPC_SBPI_DONE); if (ret < 0) dev_err(otp->dev, "timeout during ecc_enable\n"); @@ -156,7 +157,7 @@ static int px30_otp_read(void *context, unsigned int offset, otp->base + OTPC_USER_ADDR); writel(OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK, otp->base + OTPC_USER_ENABLE); - ret = rockchip_otp_wait_status(otp, OTPC_USER_DONE); + ret = rockchip_otp_wait_status(otp, OTPC_INT_STATUS, OTPC_USER_DONE); if (ret < 0) { dev_err(otp->dev, "timeout during read setup\n"); goto read_end; From patchwork Thu May 4 20:06:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 679185 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E666BC77B78 for ; Thu, 4 May 2023 20:40:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230001AbjEDUkP (ORCPT ); Thu, 4 May 2023 16:40:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53612 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231624AbjEDUjz (ORCPT ); Thu, 4 May 2023 16:39:55 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5D9D65FD7; Thu, 4 May 2023 13:34:45 -0700 (PDT) Received: from localhost (unknown [188.27.34.213]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id 276456605702; Thu, 4 May 2023 21:07:11 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1683230831; bh=QY6rnLRfHC9dXg+8BbD6mqIP1zCqEQmwLS6ENTx+qfY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RvDTFACjzeBm2rFU3uAOCw0rcmWMiAd63/IZOt7IK0hz6Le+EGcutL7FByoUkeHs0 6CWhe6rEu6J7uOFsM1i8tw1CtSr/Y9suiwYkbSU/aufYh9mgIU0ShLaG6y/mwY0sTp Kk6Cddb4XkKWjnb7VCFU5HSAkZMlntS4niDuVptBabPCm1df1uswkR2zP7mywvidV6 a9TAl6Dx/jbxn4tlbRqJiZI8i1i1tFdTWfwnbGcoMFyCicJ8Dv1UjIfz+cTi+ti/b0 1DAuwK9hU2VN4rIgVmHhtL+IsAJXMTc7or2W3l3/KMVkkYN5lUUn4qHCtfZJYqkKnp jhl/+eKKSEqYQ== From: Cristian Ciocaltea To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Philipp Zabel , Sebastian Reichel , Shreeya Patel , Kever Yang , Finley Xiao , Vincent Legoll Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 5/8] nvmem: rockchip-otp: Use devm_reset_control_array_get_exclusive() Date: Thu, 4 May 2023 23:06:45 +0300 Message-Id: <20230504200648.1119866-6-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230504200648.1119866-1-cristian.ciocaltea@collabora.com> References: <20230504200648.1119866-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In preparation to support new Rockchip OTP memory devices having specific reset configurations, switch devm_reset_control_get() to devm_reset_control_array_get_exclusive(). Signed-off-by: Cristian Ciocaltea Tested-by: Vincent Legoll Reviewed-by: Heiko Stuebner --- drivers/nvmem/rockchip-otp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/nvmem/rockchip-otp.c b/drivers/nvmem/rockchip-otp.c index b62e001f9116..439aea1f8874 100644 --- a/drivers/nvmem/rockchip-otp.c +++ b/drivers/nvmem/rockchip-otp.c @@ -263,7 +263,7 @@ static int rockchip_otp_probe(struct platform_device *pdev) if (ret) return ret; - otp->rst = devm_reset_control_get(dev, "phy"); + otp->rst = devm_reset_control_array_get_exclusive(dev); if (IS_ERR(otp->rst)) return PTR_ERR(otp->rst); From patchwork Thu May 4 20:06:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 679187 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A30AC77B7C for ; Thu, 4 May 2023 20:39:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230390AbjEDUjX (ORCPT ); Thu, 4 May 2023 16:39:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230387AbjEDUjH (ORCPT ); Thu, 4 May 2023 16:39:07 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D5CED19D4C; Thu, 4 May 2023 13:33:34 -0700 (PDT) Received: from localhost (unknown [188.27.34.213]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id 60EA866056FF; Thu, 4 May 2023 21:07:14 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1683230834; bh=liP+soMrPQDOXxG2SMtxGxRaMcIPp5ZaL+QpnsunI+8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Mog/gRj1ztd5K51jKBGYdqmuisZiPHDnvVb5L5W0/NkdTgORXgtK2QJ29Rov0kYQP 7dcSIu/NYIixTxqqAaljb1XMfnBGfY5giCriXv+sKPrVy0FfRtSlABBG9X8tysw5yZ 8wzCHbvT9l84lc5cq96B4ax0XwxlClSGkBhmbky+fYLVTcNVvMdxwI0s2Xv/pc3TfL K0I8AhLvAzIKIHdacgqJY3n5wbpa0QukcYmipZbefRAy66o8fCaunv8MVGT4zXdwdQ bXTmiTONhmJe8jZE2dK4Bfn8YxjtEh3erIyoZewTqSWDafVguO4i2M0/4iPuM4Uybf 57OYJEmZ9UVkg== From: Cristian Ciocaltea To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Philipp Zabel , Sebastian Reichel , Shreeya Patel , Kever Yang , Finley Xiao , Vincent Legoll Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 6/8] nvmem: rockchip-otp: Improve probe error handling Date: Thu, 4 May 2023 23:06:46 +0300 Message-Id: <20230504200648.1119866-7-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230504200648.1119866-1-cristian.ciocaltea@collabora.com> References: <20230504200648.1119866-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enhance error handling in the probe function by making use of dev_err_probe(), which ensures the error code is always printed, in addition to the specified error message. Signed-off-by: Cristian Ciocaltea Tested-by: Vincent Legoll Reviewed-by: Heiko Stuebner --- drivers/nvmem/rockchip-otp.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/drivers/nvmem/rockchip-otp.c b/drivers/nvmem/rockchip-otp.c index 439aea1f8874..84bf956cc4e1 100644 --- a/drivers/nvmem/rockchip-otp.c +++ b/drivers/nvmem/rockchip-otp.c @@ -235,10 +235,8 @@ static int rockchip_otp_probe(struct platform_device *pdev) int ret, i; data = of_device_get_match_data(dev); - if (!data) { - dev_err(dev, "failed to get match data\n"); - return -EINVAL; - } + if (!data) + return dev_err_probe(dev, -EINVAL, "failed to get match data\n"); otp = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_otp), GFP_KERNEL); @@ -249,7 +247,8 @@ static int rockchip_otp_probe(struct platform_device *pdev) otp->dev = dev; otp->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(otp->base)) - return PTR_ERR(otp->base); + return dev_err_probe(dev, PTR_ERR(otp->base), + "failed to ioremap resource\n"); otp->clks = devm_kcalloc(dev, data->num_clks, sizeof(*otp->clks), GFP_KERNEL); @@ -261,18 +260,22 @@ static int rockchip_otp_probe(struct platform_device *pdev) ret = devm_clk_bulk_get(dev, data->num_clks, otp->clks); if (ret) - return ret; + return dev_err_probe(dev, ret, "failed to get clocks\n"); otp->rst = devm_reset_control_array_get_exclusive(dev); if (IS_ERR(otp->rst)) - return PTR_ERR(otp->rst); + return dev_err_probe(dev, PTR_ERR(otp->rst), + "failed to get resets\n"); otp_config.size = data->size; otp_config.priv = otp; otp_config.dev = dev; - nvmem = devm_nvmem_register(dev, &otp_config); - return PTR_ERR_OR_ZERO(nvmem); + nvmem = devm_nvmem_register(dev, &otp_config); + if (IS_ERR(nvmem)) + return dev_err_probe(dev, PTR_ERR(nvmem), + "failed to register nvmem device\n"); + return 0; } static struct platform_driver rockchip_otp_driver = {