From patchwork Mon May 8 18:16:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 679984 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A7A1C7EE22 for ; Mon, 8 May 2023 18:17:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230187AbjEHSRF (ORCPT ); Mon, 8 May 2023 14:17:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57306 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232779AbjEHSRE (ORCPT ); Mon, 8 May 2023 14:17:04 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B4175FE8 for ; Mon, 8 May 2023 11:17:03 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id AA98A62F0F for ; Mon, 8 May 2023 18:17:02 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7550CC4339C; Mon, 8 May 2023 18:16:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1683569822; bh=pEkQiWBINoXiTLpYTJ+D1743e4SOfUpdwjwXGQmi2Nk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LpCAVUaxcJjhoad5gbeqsUQCfaua+zg6IbA5rkPbTdwywu2JKINyDuAdkH7BIzECp FGXurYzC2J/OgJgceOMyePFn0+i9ll10Xs7l1qSVdNvvZmGQFn5BlxkCIGLPSCU7Zx 78U2CcMMAvcG+15+JBjCBSaHVNmjA/4WRs7O0R7+7JCOnbBBn/KbvcH0TYsXod7j71 hJ82onfdcnNyPY9edo8xz8xHVmu1Mt1BZLTmb8YdVvVRKz9ntuemhnyiTB9LFKPwhL EJ7W6SOmU2xtJe/ihfsP/hpaThNWYHyze+7zwmOAwvF44liqTxobAPUbWEHYwRZaO5 6VNDvFIWa1yPA== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Heiko Stuebner , Andrew Jones , Sunil V L , Yangyu Chen , devicetree@vger.kernel.org Subject: [RFC 2/6] dt-bindings: riscv: add riscv, isa-extension-* property and incompatible example Date: Mon, 8 May 2023 19:16:22 +0100 Message-Id: <20230508-sneeze-cesarean-d1aff8be9cc8@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230508-hypnotic-phobia-99598439d828@spud> References: <20230508-hypnotic-phobia-99598439d828@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3388; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=mr+KTOsZI6CeMW3M1d3JDMm2IRvhFpi9WHx/17JxyMg=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCmRNqUqQpc3/nj4h//xeaPUtb86SlI0GVYZLykrf5tq+ 1RzZ5FJRykLgxgHg6yYIkvi7b4WqfV/XHY497yFmcPKBDKEgYtTACbyTIPhn7rL/Jb6hHuPuW2L P6o2LojcddjYO/DrjX82F5QKUw7fvsvwT2F1xbvzjdWcjxW2+t92Welp6KV85kzi7oD8O1f7eI/ 5cgEA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley This dt-binding is illustrative *only*, it doesn't yet do what I want it to do in terms of enforcement etc. I am yet to figure out exactly how to wrangle the binding such that the individual properties have more generous versions than the generic pattern property. This binding *will* generate errors, and needs rework before it can seriously be considered. Nevertheless, it should demonstrate how I intend such a property be used. Not-signed-off-by: Conor Dooley --- .../devicetree/bindings/riscv/cpus.yaml | 61 ++++++++++++++++++- 1 file changed, 60 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 405915b04d69..cccb3b2ae23d 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -100,6 +100,15 @@ properties: lowercase. $ref: "/schemas/types.yaml#/definitions/string" pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ + deprecated: true + + riscv,isa-base: + description: + Identifies the base ISA supported by a hart. + $ref: "/schemas/types.yaml#/definitions/string" + enum: + - rv32i + - rv64i # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false @@ -136,8 +145,32 @@ properties: DMIPS/MHz, relative to highest capacity-dmips-mhz in the system. + riscv,isa-extension-v: + description: RISC-V Vector extension + $ref: "/schemas/types.yaml#/definitions/string" + oneOf: + - const: v1.0.0 + description: the original incarnation + - const: v1.0.1 + description: backwards compat was broken here + +patternProperties: + "^riscv,isa-extension-*": + description: + Catch-all property for ISA extensions that do not need any special + handling, and of which all known versions are compatible with their + original revision. + $ref: "/schemas/types.yaml#/definitions/string" + enum: + - v1.0.0 + +oneOf: + - required: + - riscv,isa-base + - required: + - riscv,isa + required: - - riscv,isa - interrupt-controller additionalProperties: true @@ -208,4 +241,30 @@ examples: }; }; }; + + - | + // Example 3: Extension specification + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + reg = <0>; + compatible = "riscv"; + riscv,isa-base = "rv64i"; + riscv,isa-extension-i = "v1.0.0"; + riscv,isa-extension-m = "v1.0.0"; + riscv,isa-extension-a = "v1.0.0"; + riscv,isa-extension-f = "v1.0.0"; + riscv,isa-extension-d = "v1.0.0"; + riscv,isa-extension-c = "v2.0.0"; + riscv,isa-extension-v = "v1.0.1"; + mmu-type = "riscv,sv48"; + interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + }; ... From patchwork Mon May 8 18:16:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 679983 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0BB75C7EE22 for ; Mon, 8 May 2023 18:17:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232820AbjEHSRN (ORCPT ); Mon, 8 May 2023 14:17:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232779AbjEHSRL (ORCPT ); Mon, 8 May 2023 14:17:11 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 570295BBE for ; Mon, 8 May 2023 11:17:09 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C1B0F61E7B for ; Mon, 8 May 2023 18:17:08 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 92CB0C4339E; Mon, 8 May 2023 18:17:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1683569828; bh=gDn1qNH4xsBYthgkWZ/em1+NKvHh2zOBpGtKE3Kkd9E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fy0R37YJZ+qpMbPvgvndws5ZRECKzZAA0rPv9fBFCZ5RDt6lPp3ZQS9YpHUdlEjs3 EpOsR/MTJRTk3VlrX97HGv9a7dZaitvOksgQ6zNz71wxhTl4tvdMvdZ32hl+/G8+jS HK/UpBPYtWdViiU9JEfj2v7o4AKaeH7V8bXSD72G4srhVpLVBx3mIqP6eBfk4Oo5pn zFhl8eYUIOV5673izj4FirYSR/GfTWDoUuwMhBnlnWtPKdqUx7C2mdZgWSq6TJU4uB BZxlXEvsRfG140EKi9KkXdwwpFa8YMevkljNfeHGlioWEfhm01yHF75OOhj7G/xoGV ZclSh88zLAPIw== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Heiko Stuebner , Andrew Jones , Sunil V L , Yangyu Chen , devicetree@vger.kernel.org Subject: [RFC 4/6] RISC-V: add support for riscv,isa-base property Date: Mon, 8 May 2023 19:16:24 +0100 Message-Id: <20230508-village-robotics-54fdbcb96ee5@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230508-hypnotic-phobia-99598439d828@spud> References: <20230508-hypnotic-phobia-99598439d828@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=9974; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=X1JoMdz0XypRBvha+Fq4gfZjd7/ZEaml0zIsOaAfMPE=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCmRNmXXEnd9sfxbW63MLP0ksi1Ifovs3piU92fy/Z6vu tU+cf7FjlIWBjEOBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAExk1TWG/5U/nX4ZKKdNM7rE tHKRs7rYJYlNrRz1kmZOhu6ve+SPljMyvKn+lepQonj+1OM1Vs4T5pR9XOhsr5Y7oSpP4NF1ddE 8dgA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley I'm not entirely sure if this is needed, but I felt we still needed a mechanism for communicating the base ISA. Perhaps the i here should not even be present, but a way to encode the bit-width is missing from my key-value stuff. Very much open to suggestions on this aspect. Signed-off-by: Conor Dooley --- arch/riscv/include/asm/hwcap.h | 8 +-- arch/riscv/kernel/cpu.c | 119 +++++++++------------------------ arch/riscv/kernel/cpufeature.c | 41 ++++++++++++ 3 files changed, 73 insertions(+), 95 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index f963a7a82ce1..cb4b3df0a5d5 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -59,13 +59,6 @@ #include -struct riscv_isa_ext_data { - /* Name of the extension displayed to userspace via /proc/cpuinfo */ - char uprop[RISCV_ISA_EXT_NAME_LEN_MAX]; - /* The logical ISA extension ID */ - unsigned int isa_ext_id; -}; - struct riscv_isa_extension { const u64 key; const char *name; @@ -83,6 +76,7 @@ struct riscv_isa_extension { } extern const struct riscv_isa_extension riscv_isa_extensions[]; +extern const size_t riscv_isa_extensions_count; unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 0d5d580dca61..c29643dca0f7 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -59,8 +59,25 @@ int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *har return -ENODEV; } + if (of_property_read_string(node, "riscv,isa-base", &isa)) + goto old_interface; + + if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32i", 5)) + return -ENODEV; + + if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64i", 5)) + return -ENODEV; + + if (!of_property_present(node, "riscv,isa-extension-m") || + !of_property_present(node, "riscv,isa-extension-a")) + return -ENODEV; + + return 0; + +old_interface: if (of_property_read_string(node, "riscv,isa", &isa)) { - pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart); + pr_warn("CPU with hartid=%lu has no \"riscv,isa-base\" or \"riscv,isa\" property\n", + *hart); return -ENODEV; } @@ -157,106 +174,33 @@ static int __init riscv_cpuinfo_init(void) arch_initcall(riscv_cpuinfo_init); #ifdef CONFIG_PROC_FS - -#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ - { \ - .uprop = #UPROP, \ - .isa_ext_id = EXTID, \ - } - -/* - * The canonical order of ISA extension names in the ISA string is defined in - * chapter 27 of the unprivileged specification. - * - * Ordinarily, for in-kernel data structures, this order is unimportant but - * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo. - * - * The specification uses vague wording, such as should, when it comes to - * ordering, so for our purposes the following rules apply: - * - * 1. All multi-letter extensions must be separated from other extensions by an - * underscore. - * - * 2. Additional standard extensions (starting with 'Z') must be sorted after - * single-letter extensions and before any higher-privileged extensions. - - * 3. The first letter following the 'Z' conventionally indicates the most - * closely related alphabetical extension category, IMAFDQLCBKJTPVH. - * If multiple 'Z' extensions are named, they must be ordered first by - * category, then alphabetically within a category. - * - * 3. Standard supervisor-level extensions (starting with 'S') must be listed - * after standard unprivileged extensions. If multiple supervisor-level - * extensions are listed, they must be ordered alphabetically. - * - * 4. Standard machine-level extensions (starting with 'Zxm') must be listed - * after any lower-privileged, standard extensions. If multiple - * machine-level extensions are listed, they must be ordered - * alphabetically. - * - * 5. Non-standard extensions (starting with 'X') must be listed after all - * standard extensions. If multiple non-standard extensions are listed, they - * must be ordered alphabetically. - * - * An example string following the order is: - * rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux - * - * New entries to this struct should follow the ordering rules described above. - */ -static struct riscv_isa_ext_data isa_ext_arr[] = { - __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), - __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), - __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), - __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), - __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), - __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), - __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), - __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), - __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), - __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), - __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), - __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), -}; - static void print_isa_ext(struct seq_file *f) { - struct riscv_isa_ext_data *edata; int i = 0, arr_sz; - arr_sz = ARRAY_SIZE(isa_ext_arr) - 1; + arr_sz = riscv_isa_extensions_count - 1; /* No extension support available */ if (arr_sz <= 0) return; - for (i = 0; i <= arr_sz; i++) { - edata = &isa_ext_arr[i]; - if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id)) + for (i = 0; i < arr_sz; i++) { + if (!__riscv_isa_extension_available(NULL, riscv_isa_extensions[i].key)) continue; - seq_printf(f, "_%s", edata->uprop); + if (riscv_isa_extensions[i].multi_letter) + seq_printf(f, "_"); + + seq_printf(f, "%s", riscv_isa_extensions[i].name); } } -/* - * These are the only valid base (single letter) ISA extensions as per the spec. - * It also specifies the canonical order in which it appears in the spec. - * Some of the extension may just be a place holder for now (B, K, P, J). - * This should be updated once corresponding extensions are ratified. - */ -static const char base_riscv_exts[13] = "imafdqcbkjpvh"; - -static void print_isa(struct seq_file *f, const char *isa) +static void print_isa(struct seq_file *f) { - int i; + if (IS_ENABLED(CONFIG_64BIT)) + seq_puts(f, "isa\t\t: rv64"); + else + seq_puts(f, "isa\t\t: rv32"); - seq_puts(f, "isa\t\t: "); - /* Print the rv[64/32] part */ - seq_write(f, isa, 4); - for (i = 0; i < sizeof(base_riscv_exts); i++) { - if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a')) - /* Print only enabled the base ISA extensions */ - seq_write(f, &base_riscv_exts[i], 1); - } print_isa_ext(f); seq_puts(f, "\n"); } @@ -312,8 +256,7 @@ static int c_show(struct seq_file *m, void *v) seq_printf(m, "processor\t: %lu\n", cpu_id); seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id)); - if (!of_property_read_string(node, "riscv,isa", &isa)) - print_isa(m, isa); + print_isa(m); print_mmu(m); if (!of_property_read_string(node, "compatible", &compat) && strcmp(compat, "riscv")) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 1ead76adf60f..d415a86a11e7 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -93,6 +93,45 @@ static bool riscv_isa_extension_check(int id) return true; } +/* + * The canonical order of ISA extension names in the ISA string is defined in + * chapter 27 of the unprivileged specification. + * + * Ordinarily, for in-kernel data structures, this order is unimportant but + * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo. + * + * The specification uses vague wording, such as should, when it comes to + * ordering, so for our purposes the following rules apply: + * + * 1. All multi-letter extensions must be separated from other extensions by an + * underscore. + * + * 2. Additional standard extensions (starting with 'Z') must be sorted after + * single-letter extensions and before any higher-privileged extensions. + + * 3. The first letter following the 'Z' conventionally indicates the most + * closely related alphabetical extension category, IMAFDQLCBKJTPVH. + * If multiple 'Z' extensions are named, they must be ordered first by + * category, then alphabetically within a category. + * + * 3. Standard supervisor-level extensions (starting with 'S') must be listed + * after standard unprivileged extensions. If multiple supervisor-level + * extensions are listed, they must be ordered alphabetically. + * + * 4. Standard machine-level extensions (starting with 'Zxm') must be listed + * after any lower-privileged, standard extensions. If multiple + * machine-level extensions are listed, they must be ordered + * alphabetically. + * + * 5. Non-standard extensions (starting with 'X') must be listed after all + * standard extensions. If multiple non-standard extensions are listed, they + * must be ordered alphabetically. + * + * An example string following the order is: + * rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux + * + * New entries to this struct should follow the ordering rules described above. + */ const struct riscv_isa_extension riscv_isa_extensions[] = { RISCV_ISA_EXT_CFG(i, RISCV_ISA_EXT_i, "v1.0.0", false), RISCV_ISA_EXT_CFG(m, RISCV_ISA_EXT_m, "v1.0.0", false), @@ -121,6 +160,8 @@ const struct riscv_isa_extension riscv_isa_extensions[] = { RISCV_ISA_EXT_CFG("", RISCV_ISA_EXT_MAX, "", false), }; +const size_t riscv_isa_extensions_count = ARRAY_SIZE(riscv_isa_extensions); + static void __init riscv_fill_hwcap_isa_string(void) { struct device_node *node; From patchwork Mon May 8 18:16:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 679982 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12931C77B75 for ; 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s=k20201202; t=1683569834; bh=BeSBiMW5kmgs7+Z7icdUc3/2UWyKIKrlY/vXI6gIZDU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=F850zsgIjLZZIVsp/40NUEh0Et3PjVKwqFK17JJEOj4Qv2WUfB1tB58G2VLPTBQmG 8XRfUAi8yafgVdWrpZ1vfyScdT8FxrJOdvC3iwtV1yUA8f0Fgs3Sh1j/iv2AGpGI4d njKbCwX2JHJpJQQPGGD+XLX60EZQdKDiUC2IU4au6A/AIBcr573u3Hti4OBRAJ8+1W SUHRBOJEVon0J31fEDuq7y/ZLzPp539+XRI0PVC2OXYcgCNjQ32XZvIjWYSJB9KhGj 64wLFYsidBsWtjUzxndJ0BcJfZRqfopOiA90Meomd/ICeHOkUK6WFLVpwHN9DUXY1m bt/IdqNFsU9lg== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Heiko Stuebner , Andrew Jones , Sunil V L , Yangyu Chen , devicetree@vger.kernel.org Subject: [RFC 6/6] riscv: dts: microchip: use new riscv,isa-extension-* properties for mpfs Date: Mon, 8 May 2023 19:16:26 +0100 Message-Id: <20230508-elf-dismay-799bb48a635e@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230508-hypnotic-phobia-99598439d828@spud> References: <20230508-hypnotic-phobia-99598439d828@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2933; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=sxz5UhIOaJj8Re9+hSvtSwbaV+pJMl6xzcAp79D9KJ0=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCmRNmWBZjpFz00vJS05+L9L+f2fzB2CqnuOxv4vyjCY1 aDQqX6io5SFQYyDQVZMkSXxdl+L1Po/Ljuce97CzGFlAhnCwMUpABM5JcXIsDaoQu7ndSPHiFVZ b6r+XVDUX7+QO+WEwN/4JVafG774vWT4n/X1LGvk2k8PHu2w26F8MObA3czOT/KLMu2ezbrw/db +2UwA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 42 ++++++++++++++++++++++--- 1 file changed, 37 insertions(+), 5 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 104504352e99..53efb5e03c64 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -21,7 +21,11 @@ cpu0: cpu@0 { i-cache-sets = <128>; i-cache-size = <16384>; reg = <0>; - riscv,isa = "rv64imac"; + riscv,isa-base = "rv64i"; + riscv,isa-extension-i = "v1.0.0"; + riscv,isa-extension-m = "v1.0.0"; + riscv,isa-extension-a = "v1.0.0"; + riscv,isa-extension-c = "v1.0.0"; clocks = <&clkcfg CLK_CPU>; status = "disabled"; @@ -47,7 +51,14 @@ cpu1: cpu@1 { i-tlb-size = <32>; mmu-type = "riscv,sv39"; reg = <1>; - riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extension-i = "v1.0.0"; + riscv,isa-extension-m = "v1.0.0"; + riscv,isa-extension-a = "v1.0.0"; + riscv,isa-extension-f = "v1.0.0"; + riscv,isa-extension-d = "v1.0.0"; + riscv,isa-extension-c = "v1.0.0"; + riscv,isa-extension-zicsr = "v1.0.0"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -75,7 +86,14 @@ cpu2: cpu@2 { i-tlb-size = <32>; mmu-type = "riscv,sv39"; reg = <2>; - riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extension-i = "v1.0.0"; + riscv,isa-extension-m = "v1.0.0"; + riscv,isa-extension-a = "v1.0.0"; + riscv,isa-extension-f = "v1.0.0"; + riscv,isa-extension-d = "v1.0.0"; + riscv,isa-extension-c = "v1.0.0"; + riscv,isa-extension-zicsr = "v1.0.0"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -103,7 +121,14 @@ cpu3: cpu@3 { i-tlb-size = <32>; mmu-type = "riscv,sv39"; reg = <3>; - riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extension-i = "v1.0.0"; + riscv,isa-extension-m = "v1.0.0"; + riscv,isa-extension-a = "v1.0.0"; + riscv,isa-extension-f = "v1.0.0"; + riscv,isa-extension-d = "v1.0.0"; + riscv,isa-extension-c = "v1.0.0"; + riscv,isa-extension-zicsr = "v1.0.0"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -131,7 +156,14 @@ cpu4: cpu@4 { i-tlb-size = <32>; mmu-type = "riscv,sv39"; reg = <4>; - riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extension-i = "v1.0.0"; + riscv,isa-extension-m = "v1.0.0"; + riscv,isa-extension-a = "v1.0.0"; + riscv,isa-extension-f = "v1.0.0"; + riscv,isa-extension-d = "v1.0.0"; + riscv,isa-extension-c = "v1.0.0"; + riscv,isa-extension-zicsr = "v1.0.0"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>;