From patchwork Sat Jun 8 19:53:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 166203 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2157449ili; Sat, 8 Jun 2019 12:53:48 -0700 (PDT) X-Google-Smtp-Source: APXvYqyjKK7graLeClc9be1+WVFKjlavUJyMa0BAQR6eTJPEjzaMwYg566YvVsdeE1Z4pa5l7XBi X-Received: by 2002:a62:2f87:: with SMTP id v129mr66999233pfv.9.1560023628676; Sat, 08 Jun 2019 12:53:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560023628; cv=none; d=google.com; s=arc-20160816; b=eNEbqYuJUtrGm9urVEtbLRICESedg0J/45EygpE4ywqTFrulgjBOfBoceLkIoCAFJP vXaS0VkcfZ+53893Lq4NhFH1d+KNFOa8Kqm10CIVN5o/NUvoZzrCTb4i9DaVnsNhWZmZ yrsQty07CLjaI2zupt68VDxDfTePOf766zS1M4iUV3ggTOG0iu6/oiLcAfV7og8nl0Lb Ccmkd7f2lWXtaTVw0/IGnyKZJdS8o1xbgsL1wR9DsHuVBcRfa8SOxLKC8htj1D0CaZou L4IMCQlWOD85R3/ukKcHA8ZPUdXkUBQXp6xUve2meWbxxVSYjlR4tZ8F94/NawOe66Na qOXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=83a8MoLcEJiG177cdK9PZRkYinryGGyKPXFycKJosaY=; b=wYposlVIEva0TiSiuoTv0sAEeVDVcVgp8CjtBJBzuGWHwqtKkabIFr86ZL8p6UPvWH hjxEp2Ka9iJTiiKbVM2kb/VbfLIZb45x4sBMB5/6Jm9xyqBCbpeArWqhASOI8cnPNhPt JZEMv7g4MOywl6soBttajEOHS4CpgizXOHsHaBxVRz0REehkz+TiD/oZuXZnHGiVDqh+ yBl1rs7crZt7k397By5f14FxprrA+CYqksrmJwBNeubY2pEfhDXIQDZsiFSyAwQUsbHt uF6nIMbQYsFBZA+AD2cTSpno+lSfUm/k6GIeqIXjsX0T8RJAnwxH8E/9/iCNk6EM7E1k VVDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="WaL7D/rJ"; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j1si5428596pld.399.2019.06.08.12.53.48; Sat, 08 Jun 2019 12:53:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="WaL7D/rJ"; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727518AbfFHTxr (ORCPT + 5 others); Sat, 8 Jun 2019 15:53:47 -0400 Received: from mail-pl1-f193.google.com ([209.85.214.193]:35035 "EHLO mail-pl1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727519AbfFHTxq (ORCPT ); Sat, 8 Jun 2019 15:53:46 -0400 Received: by mail-pl1-f193.google.com with SMTP id p1so2098362plo.2 for ; Sat, 08 Jun 2019 12:53:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=83a8MoLcEJiG177cdK9PZRkYinryGGyKPXFycKJosaY=; b=WaL7D/rJC7D65LYWj8NEGexxrwXKI6tDAcL/sPB5lIlAPrDTQq/rJPqVXrqxsuQO/5 s5LYiCX3KAJImUAWhIcUtCQvKmhSvwjvfsYKV7629GpfDEqN+O7gnSyjKWdoEAm3WAoo hSns9rM0WAhBvFiH1yqncIKN+kITrQB9h+g1vrzvS37cz/RZ1eRsgTv+fKqt1rPuz0Jl yMMNINDh8FHhcVGvkcMBO8aXn9Vdv9+QXPkpUwSaYm68BbAVZfpkJr1/Ok9DnQOfYus1 k5IdIjOE86acO7FP3iSBBWsTcFl/0JQaD5GBDET/1PkxBFMMRzSbUSDzslILD3iH7iwD Sp9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=83a8MoLcEJiG177cdK9PZRkYinryGGyKPXFycKJosaY=; b=RHthQGecal7l9r4VFrBDjek/L9fFOOHoZBrBGgKkoy2dYMpAWbQfzgXqEr84EwyrCR k4dX/x3kkUwDXQbbV5HpjKjjwjHUOh9KmA+2tGN6JzpCrolpUTiuoPGYFK7Frcrxo5zI HeMXbHjQopm9bObcHziLVL3jvYO887LPhbsknFpYQYzzGzWcDYBGmm+S0KsSeH5IQkRs GhO52utThT14yp4DxzJKv03ZW67EC4qu9FIWIdAp048+OeS+bdkHXqjzfM5bQKh5Iby9 FGNkHvP1MSVCYZIycfcfDRAIRFgBnJG+qxD/5QvXLzYDP4KR3Os2qYXBy+cNDwYeMpDa 7c2Q== X-Gm-Message-State: APjAAAXw0mdRVGbF5QbaaYHygZ+Tnsz8L5wEXcWhynSGyE4evurc04I/ +Z1upxkGCL632bX6Chmyaf4C X-Received: by 2002:a17:902:bc3:: with SMTP id 61mr4289938plr.324.1560023625983; Sat, 08 Jun 2019 12:53:45 -0700 (PDT) Received: from localhost.localdomain ([2405:204:7185:fba9:ec1e:ad07:23ac:d3ee]) by smtp.gmail.com with ESMTPSA id b35sm6034377pjc.15.2019.06.08.12.53.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 08 Jun 2019 12:53:45 -0700 (PDT) From: Manivannan Sadhasivam To: ulf.hansson@linaro.org, afaerber@suse.de, robh+dt@kernel.org, sboyd@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, thomas.liau@actions-semi.com, linux-actions@lists.infradead.org, linus.walleij@linaro.org, linux-clk@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 1/7] clk: actions: Fix factor clk struct member access Date: Sun, 9 Jun 2019 01:23:11 +0530 Message-Id: <20190608195317.6336-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190608195317.6336-1-manivannan.sadhasivam@linaro.org> References: <20190608195317.6336-1-manivannan.sadhasivam@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Since the helper "owl_factor_helper_round_rate" is shared between factor and composite clocks, using the factor clk specific helper function like "hw_to_owl_factor" to access its members will create issues when called from composite clk specific code. Hence, pass the "factor_hw" struct pointer directly instead of fetching it using factor clk specific helpers. This issue has been observed when a composite clock like "sd0_clk" tried to call "owl_factor_helper_round_rate" resulting in pointer dereferencing error. Fixes: 4bb78fc9744a ("clk: actions: Add factor clock support") Signed-off-by: Manivannan Sadhasivam --- drivers/clk/actions/owl-factor.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/drivers/clk/actions/owl-factor.c b/drivers/clk/actions/owl-factor.c index 317d4a9e112e..f419dfdd334f 100644 --- a/drivers/clk/actions/owl-factor.c +++ b/drivers/clk/actions/owl-factor.c @@ -64,11 +64,10 @@ static unsigned int _get_table_val(const struct clk_factor_table *table, return val; } -static int clk_val_best(struct clk_hw *hw, unsigned long rate, +static int clk_val_best(const struct owl_factor_hw *factor_hw, + struct clk_hw *hw, unsigned long rate, unsigned long *best_parent_rate) { - struct owl_factor *factor = hw_to_owl_factor(hw); - struct owl_factor_hw *factor_hw = &factor->factor_hw; const struct clk_factor_table *clkt = factor_hw->table; unsigned long parent_rate, try_parent_rate, best = 0, cur_rate; unsigned long parent_rate_saved = *best_parent_rate; @@ -126,7 +125,7 @@ long owl_factor_helper_round_rate(struct owl_clk_common *common, const struct clk_factor_table *clkt = factor_hw->table; unsigned int val, mul = 0, div = 1; - val = clk_val_best(&common->hw, rate, parent_rate); + val = clk_val_best(factor_hw, &common->hw, rate, parent_rate); _get_table_div_mul(clkt, val, &mul, &div); return *parent_rate * mul / div; From patchwork Sat Jun 8 19:53:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 166205 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2157559ili; Sat, 8 Jun 2019 12:54:01 -0700 (PDT) X-Google-Smtp-Source: APXvYqy1viXEe0xq8vKHr5xqtlXktxHaTj4g1zADV280ZmOxVyTMG93Txs8KuwUeV84+4Lzk/xFJ X-Received: by 2002:a17:90a:aa85:: with SMTP id l5mr12094302pjq.69.1560023641328; Sat, 08 Jun 2019 12:54:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560023641; cv=none; d=google.com; s=arc-20160816; b=nFy6AJSnHTtMy6CsM/n+FNTFaRK8ywV5X5ANRxwSllpSKmFFeqaMSWmvQuU/K5X7XH s2+vAf7UWFpc8/t2TAedIso1cMOY7aMPSFmOr7Uud41Ak+uz39FNWsInz4yFyXapmmwn dB40YthXR7obPy+HA5hhEoE6RXo5mXVnNIRKk53o3tNJP92ApNx2i+2jVgbopjdQBaFC DIV7DVVcQiUC3b1VyrEsRPqWGjn81Csh2jwcZ4qmi+LH+1+tP48iDyidLoNKC5SR6cx3 fQWVAfnIlaoQd/6iHuUizusivxe6w4TtziLUonv8sgA2zYi5Amdfpl9MBjzwfdekDmTz q+SA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=GdUGLfzA/moIy9fqv00a3/N33TZrVkt63TobdJZyyCw=; b=MNgIW58StKW4lcBvgwFwjYZYhSyObRompUIdnWbYJL6wI1e7cnuXOXQY++UioJreRl MJxtKs5lAhIrTlAUh+h0NhTZgspwbN95OuAxZ9j5b8Q/tHpR/LGbCZbnfnVZf8d1IXw4 vzJ/RKtuoAxns+n2yuPa9YdPSjRZ4WbrT+X2lJsFcc/seEf2DXg1QXmI070blgWlxStN CI8MzMke2A1MLsRLmBiGJi6zd6Wd76hkyowmZJxPP6O/haQ+bQC5Nr9yjNACVEFnLh+8 vT5GBIdsJM6qc81DwDfWDieCE3iPKexY7w0qIHKJ5dFbbtNjh4jucC1uSsvTZNbOZcLF tMAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZNKNnaGM; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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There are 4 MMC controllers in this SoC which can be used for accessing SD/MMC/SDIO cards. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/actions/s900.dtsi | 45 +++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/actions/s900.dtsi b/arch/arm64/boot/dts/actions/s900.dtsi index df3a68a3ac97..eb35cf78ab73 100644 --- a/arch/arm64/boot/dts/actions/s900.dtsi +++ b/arch/arm64/boot/dts/actions/s900.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include @@ -284,5 +285,49 @@ dma-requests = <46>; clocks = <&cmu CLK_DMAC>; }; + + mmc0: mmc@e0330000 { + compatible = "actions,owl-mmc"; + reg = <0x0 0xe0330000 0x0 0x4000>; + interrupts = ; + clocks = <&cmu CLK_SD0>; + resets = <&cmu RESET_SD0>; + dmas = <&dma 2>; + dma-names = "mmc"; + status = "disabled"; + }; + + mmc1: mmc@e0334000 { + compatible = "actions,owl-mmc"; + reg = <0x0 0xe0334000 0x0 0x4000>; + interrupts = ; + clocks = <&cmu CLK_SD1>; + resets = <&cmu RESET_SD1>; + dmas = <&dma 3>; + dma-names = "mmc"; + status = "disabled"; + }; + + mmc2: mmc@e0338000 { + compatible = "actions,owl-mmc"; + reg = <0x0 0xe0338000 0x0 0x4000>; + interrupts = ; + clocks = <&cmu CLK_SD2>; + resets = <&cmu RESET_SD2>; + dmas = <&dma 4>; + dma-names = "mmc"; + status = "disabled"; + }; + + mmc3: mmc@e033c000 { + compatible = "actions,owl-mmc"; + reg = <0x0 0xe033c000 0x0 0x4000>; + interrupts = ; + clocks = <&cmu CLK_SD3>; + resets = <&cmu RESET_SD3>; + dmas = <&dma 46>; + dma-names = "mmc"; + status = "disabled"; + }; }; }; From patchwork Sat Jun 8 19:53:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 166207 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2157782ili; Sat, 8 Jun 2019 12:54:23 -0700 (PDT) X-Google-Smtp-Source: APXvYqzk8F/03utTnacgSMAJuOC99UoKSE8W+eBMxnhoE7HnFqjE71X0kadECM7JQ8ocIHh+p0oM X-Received: by 2002:a17:902:ba88:: with SMTP id k8mr55160844pls.196.1560023663083; Sat, 08 Jun 2019 12:54:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560023663; cv=none; d=google.com; s=arc-20160816; b=PI4TwRHSumrvKVMFBeQnCEDPv/Jgm7GNEzw0xwrPDy6PLxu/FMZbSPZtcdwa+tHmHF otG+TRN2Hz7dzS67Lb9hAb2ZcD/D1PIDso1mr/IiB/ygN7GtUULJRLw7VG7AhTsqJY/U QxytqUAve1pXRwoBofh+TAoKulSqkqeDM7IOi+pJUw1t7Ph8+dmRLETmJaHs4E1cfH3b UFrcDNzPRSXfPJB/LnDnZyXyao9RNYjCYWjJCIaYbZb/WvK5l0vsTxlgDggTO7GzJvCA ysh2dUIoF+OwRcEwc5hKPaxzLXx1TuPanM+J94nrSFwQ+zYmX5d7l5Vr9FAewrntV4sN g4Tw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=DRy0GAwEQ4jLbVlk0524dcA7YE+/rzQQboxvf6syCC0=; b=0KfMvSdgsON8Lq+fKo6nbINDPtPBNJT0LnN90bihiwFP1QRrVWb5Rz0hToVE3QST7v NLBOmis4/zW/5RLwz906RqmJZ2QwdAMrikkidVihbb5ybatUMz++wT9AtOYzvV+yUXMu C2eEyT9HiERFN1q2YdYw0i0izeqjI1oOeJHW3htgzXMjW/ZuqhrPGUB3O/jEEjOaQXzs xqsnWn/wMlO3Dg/Xp7ZeqOVjHZAlsl+2KntkzARTxmbTo/wavtXcTUz1sxw5RhzWr9KF wWGqAQEjvoQdfe0Ogt05DqNtAq0r9sIdUO/HRG+7hOj3CRtHWj2CW5krad0X39KRA5nZ aL7A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mLnIQ29x; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y66si5403653pfy.197.2019.06.08.12.54.22; Sat, 08 Jun 2019 12:54:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mLnIQ29x; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727682AbfFHTyW (ORCPT + 5 others); Sat, 8 Jun 2019 15:54:22 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:36668 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727678AbfFHTyW (ORCPT ); Sat, 8 Jun 2019 15:54:22 -0400 Received: by mail-pg1-f194.google.com with SMTP id a3so2908769pgb.3 for ; Sat, 08 Jun 2019 12:54:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=DRy0GAwEQ4jLbVlk0524dcA7YE+/rzQQboxvf6syCC0=; b=mLnIQ29x8de/+e39B7FHAaUQnwf1h0KnABFF7u0jMPHhYLO9R/hzrENNjbgUQPHVdt 96QDLoqULQyVk8XpBxBCBJyuULBA3K7wgoHivsIXfqqhboDF2uubmfT1c+9AogUG6cT7 /oY2qHC+4ArYsT7aaSJkfObWRsW28quZtfh57V1le/z+79tE7GfUFmRcPy71GIfVKneY Dyv5TkSa8V/hcJGBc4hioiYycVfI4Li61ayOPo+KHPi4Sk1M/fBIy+bUZOtXA8aCpiNQ 3iqvxeLeqHHWU3nu8wMWnzyvI/V9cvVdw6UkQ4PnFqUYULYYPMrkoOscwYPQhN8p4SjS j0nQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DRy0GAwEQ4jLbVlk0524dcA7YE+/rzQQboxvf6syCC0=; b=N7ygyGETXpYtYr8sPFzoZtmCBSGHXcYkH7vH21QwKI5pqBAHc0Ivwkbo8x3u6j+ypX za0YGSWyNeD1PubuxoCEQfUdw1SM3U4xXRz3xnvQ/USyT8jYlRo5Z7mlQEckT/KD2XcH qvblggpRXz497fuzefsxK0a3eW7OYaioMjBRdNWrKQlPWfxEjOVtiV/ug8vYg84IQqvx ON7KmAO62Me7f/d7+pKw7KQ+M5wA1hB1H46xHydb0eOeKPRc3dSGEXF/mQW5eHVPV2i6 CyxEC0TiiiRptc4UYQE4g2gEFS78YFBt67RF0V8I6WkTZui14bxNJv/1H0pNnFXzvZix KMmg== X-Gm-Message-State: APjAAAVsIoaxITSZt6giHMeG+P37qR07T44d9WAmuVaatquegvg/5JoG ZV5wOlnPbMG6r5UIZ9PrFji3 X-Received: by 2002:a62:6143:: with SMTP id v64mr29132985pfb.42.1560023660920; Sat, 08 Jun 2019 12:54:20 -0700 (PDT) Received: from localhost.localdomain ([2405:204:7185:fba9:ec1e:ad07:23ac:d3ee]) by smtp.gmail.com with ESMTPSA id b35sm6034377pjc.15.2019.06.08.12.54.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 08 Jun 2019 12:54:20 -0700 (PDT) From: Manivannan Sadhasivam To: ulf.hansson@linaro.org, afaerber@suse.de, robh+dt@kernel.org, sboyd@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, thomas.liau@actions-semi.com, linux-actions@lists.infradead.org, linus.walleij@linaro.org, linux-clk@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 5/7] mmc: Add Actions Semi Owl SoCs SD/MMC driver Date: Sun, 9 Jun 2019 01:23:15 +0530 Message-Id: <20190608195317.6336-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190608195317.6336-1-manivannan.sadhasivam@linaro.org> References: <20190608195317.6336-1-manivannan.sadhasivam@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add SD/MMC driver for Actions Semi Owl SoCs. This driver currently supports standard, high speed, SDR12, SDR25 and SDR50. DDR50 mode is supported but it is untested. There is no SDIO support for now. Signed-off-by: Manivannan Sadhasivam --- drivers/mmc/host/Kconfig | 8 + drivers/mmc/host/Makefile | 1 + drivers/mmc/host/owl-mmc.c | 705 +++++++++++++++++++++++++++++++++++++ 3 files changed, 714 insertions(+) create mode 100644 drivers/mmc/host/owl-mmc.c -- 2.17.1 diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 931770f17087..7ae65eff26a4 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -1006,3 +1006,11 @@ config MMC_SDHCI_AM654 If you have a controller with this interface, say Y or M here. If unsure, say N. + +config MMC_OWL + tristate "Actions Semi Owl SD/MMC Host Controller support" + depends on HAS_DMA + depends on ARCH_ACTIONS || COMPILE_TEST + help + This selects support for the SD/MMC Host Controller on + Actions Semi Owl SoCs. diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 73578718f119..41a0b1728389 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -73,6 +73,7 @@ obj-$(CONFIG_MMC_SUNXI) += sunxi-mmc.o obj-$(CONFIG_MMC_USDHI6ROL0) += usdhi6rol0.o obj-$(CONFIG_MMC_TOSHIBA_PCI) += toshsd.o obj-$(CONFIG_MMC_BCM2835) += bcm2835.o +obj-$(CONFIG_MMC_OWL) += owl-mmc.o obj-$(CONFIG_MMC_REALTEK_PCI) += rtsx_pci_sdmmc.o obj-$(CONFIG_MMC_REALTEK_USB) += rtsx_usb_sdmmc.o diff --git a/drivers/mmc/host/owl-mmc.c b/drivers/mmc/host/owl-mmc.c new file mode 100644 index 000000000000..8158ebedb2a4 --- /dev/null +++ b/drivers/mmc/host/owl-mmc.c @@ -0,0 +1,705 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Actions Semi Owl SoCs SD/MMC driver + * + * Copyright (c) 2014 Actions Semi Inc. + * Copyright (c) 2019 Manivannan Sadhasivam + * + * TODO: SDIO support + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * SDC registers + */ +#define OWL_REG_SD_EN 0x0000 +#define OWL_REG_SD_CTL 0x0004 +#define OWL_REG_SD_STATE 0x0008 +#define OWL_REG_SD_CMD 0x000c +#define OWL_REG_SD_ARG 0x0010 +#define OWL_REG_SD_RSPBUF0 0x0014 +#define OWL_REG_SD_RSPBUF1 0x0018 +#define OWL_REG_SD_RSPBUF2 0x001c +#define OWL_REG_SD_RSPBUF3 0x0020 +#define OWL_REG_SD_RSPBUF4 0x0024 +#define OWL_REG_SD_DAT 0x0028 +#define OWL_REG_SD_BLK_SIZE 0x002c +#define OWL_REG_SD_BLK_NUM 0x0030 +#define OWL_REG_SD_BUF_SIZE 0x0034 + +/* SD_EN Bits */ +#define OWL_SD_EN_RANE BIT(31) +#define OWL_SD_EN_RAN_SEED(x) (((x) & 0x3f) << 24) +#define OWL_SD_EN_S18EN BIT(12) +#define OWL_SD_EN_RESE BIT(10) +#define OWL_SD_EN_DAT1_S BIT(9) +#define OWL_SD_EN_CLK_S BIT(8) +#define OWL_SD_ENABLE BIT(7) +#define OWL_SD_EN_BSEL BIT(6) +#define OWL_SD_EN_SDIOEN BIT(3) +#define OWL_SD_EN_DDREN BIT(2) +#define OWL_SD_EN_DATAWID(x) (((x) & 0x3) << 0) + +/* SD_CTL Bits */ +#define OWL_SD_CTL_TOUTEN BIT(31) +#define OWL_SD_CTL_TOUTCNT(x) (((x) & 0x7f) << 24) +#define OWL_SD_CTL_DELAY_MSK GENMASK(23, 16) +#define OWL_SD_CTL_RDELAY(x) (((x) & 0xf) << 20) +#define OWL_SD_CTL_WDELAY(x) (((x) & 0xf) << 16) +#define OWL_SD_CTL_CMDLEN BIT(13) +#define OWL_SD_CTL_SCC BIT(12) +#define OWL_SD_CTL_TCN(x) (((x) & 0xf) << 8) +#define OWL_SD_CTL_TS BIT(7) +#define OWL_SD_CTL_LBE BIT(6) +#define OWL_SD_CTL_C7EN BIT(5) +#define OWL_SD_CTL_TM(x) (((x) & 0xf) << 0) + +#define OWL_SD_DELAY_LOW_CLK 0x0f +#define OWL_SD_DELAY_MID_CLK 0x0a +#define OWL_SD_DELAY_HIGH_CLK 0x09 +#define OWL_SD_RDELAY_DDR50 0x0a +#define OWL_SD_WDELAY_DDR50 0x08 + +/* SD_STATE Bits */ +#define OWL_SD_STATE_DAT1BS BIT(18) +#define OWL_SD_STATE_SDIOB_P BIT(17) +#define OWL_SD_STATE_SDIOB_EN BIT(16) +#define OWL_SD_STATE_TOUTE BIT(15) +#define OWL_SD_STATE_BAEP BIT(14) +#define OWL_SD_STATE_MEMRDY BIT(12) +#define OWL_SD_STATE_CMDS BIT(11) +#define OWL_SD_STATE_DAT1AS BIT(10) +#define OWL_SD_STATE_SDIOA_P BIT(9) +#define OWL_SD_STATE_SDIOA_EN BIT(8) +#define OWL_SD_STATE_DAT0S BIT(7) +#define OWL_SD_STATE_TEIE BIT(6) +#define OWL_SD_STATE_TEI BIT(5) +#define OWL_SD_STATE_CLNR BIT(4) +#define OWL_SD_STATE_CLC BIT(3) +#define OWL_SD_STATE_WC16ER BIT(2) +#define OWL_SD_STATE_RC16ER BIT(1) +#define OWL_SD_STATE_CRC7ER BIT(0) + +struct owl_mmc_host { + struct device *dev; + struct reset_control *reset; + void __iomem *base; + struct clk *clk; + struct completion sdc_complete; + spinlock_t lock; + int irq; + u32 clock; + bool ddr_50; + + enum dma_data_direction dma_dir; + struct dma_chan *dma; + struct dma_async_tx_descriptor *desc; + struct dma_slave_config dma_cfg; + struct completion dma_complete; + + struct mmc_host *mmc; + struct mmc_request *mrq; + struct mmc_command *cmd; + struct mmc_data *data; +}; + +static inline void mmc_writel(struct owl_mmc_host *owl_host, u32 reg, u32 data) +{ + writel(data, owl_host->base + reg); +} + +static inline u32 mmc_readl(struct owl_mmc_host *owl_host, u32 reg) +{ + return readl(owl_host->base + reg); +} + +static void mmc_update_reg(void __iomem *reg, unsigned int val, bool state) +{ + unsigned int regval; + + regval = readl(reg); + + if (state) + regval |= val; + else + regval &= ~val; + + writel(regval, reg); +} + +static irqreturn_t owl_irq_handler(int irq, void *devid) +{ + struct owl_mmc_host *owl_host = devid; + unsigned long flags; + u32 state; + + spin_lock_irqsave(&owl_host->lock, flags); + + state = mmc_readl(owl_host, OWL_REG_SD_STATE); + if (state & OWL_SD_STATE_TEI) { + state = mmc_readl(owl_host, OWL_REG_SD_STATE); + state |= OWL_SD_STATE_TEI; + mmc_writel(owl_host, OWL_REG_SD_STATE, state); + complete(&owl_host->sdc_complete); + } + + spin_unlock_irqrestore(&owl_host->lock, flags); + + return IRQ_HANDLED; +} + +static void owl_mmc_finish_request(struct owl_mmc_host *owl_host) +{ + struct mmc_request *mrq = owl_host->mrq; + struct mmc_data *data = mrq->data; + + /* Should never be NULL */ + WARN_ON(!mrq); + + owl_host->mrq = NULL; + + if (data) + dma_unmap_sg(owl_host->dma->device->dev, data->sg, data->sg_len, + owl_host->dma_dir); + + /* Finally finish request */ + mmc_request_done(owl_host->mmc, mrq); +} + +static void owl_mmc_send_cmd(struct owl_mmc_host *owl_host, + struct mmc_command *cmd, + struct mmc_data *data) +{ + u32 mode, state, resp[2]; + u32 cmd_rsp_mask = 0; + + init_completion(&owl_host->sdc_complete); + + switch (mmc_resp_type(cmd)) { + case MMC_RSP_NONE: + mode = OWL_SD_CTL_TM(0); + break; + + case MMC_RSP_R1: + if (data) { + if (data->flags & MMC_DATA_READ) + mode = OWL_SD_CTL_TM(4); + else + mode = OWL_SD_CTL_TM(5); + } else { + mode = OWL_SD_CTL_TM(1); + } + cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER; + + break; + + case MMC_RSP_R1B: + mode = OWL_SD_CTL_TM(3); + cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER; + break; + + case MMC_RSP_R2: + mode = OWL_SD_CTL_TM(2); + cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER; + break; + + case MMC_RSP_R3: + mode = OWL_SD_CTL_TM(1); + cmd_rsp_mask = OWL_SD_STATE_CLNR; + break; + + default: + dev_warn(owl_host->dev, "Unknown MMC command\n"); + cmd->error = -EINVAL; + return; + } + + /* Keep current WDELAY and RDELAY */ + mode |= (mmc_readl(owl_host, OWL_REG_SD_CTL) & (0xff << 16)); + + /* Start to send corresponding command type */ + mmc_writel(owl_host, OWL_REG_SD_ARG, cmd->arg); + mmc_writel(owl_host, OWL_REG_SD_CMD, cmd->opcode); + + /* Set LBE to send clk at the end of last read block */ + if (data) { + mode |= (OWL_SD_CTL_TS | OWL_SD_CTL_LBE | 0x64000000); + } else { + mode &= ~(OWL_SD_CTL_TOUTEN | OWL_SD_CTL_LBE); + mode |= OWL_SD_CTL_TS; + } + + owl_host->cmd = cmd; + + /* Start transfer */ + mmc_writel(owl_host, OWL_REG_SD_CTL, mode); + + if (data) + return; + + if (!wait_for_completion_timeout(&owl_host->sdc_complete, 30 * HZ)) { + dev_err(owl_host->dev, "CMD interrupt timeout\n"); + cmd->error = -ETIMEDOUT; + return; + } + + state = mmc_readl(owl_host, OWL_REG_SD_STATE); + if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) { + if (cmd_rsp_mask & state) { + if (state & OWL_SD_STATE_CLNR) { + dev_err(owl_host->dev, "Error CMD_NO_RSP\n"); + cmd->error = -EILSEQ; + return; + } + + if (state & OWL_SD_STATE_CRC7ER) { + dev_err(owl_host->dev, "Error CMD_RSP_CRC\n"); + cmd->error = -EILSEQ; + return; + } + } + + if (mmc_resp_type(cmd) & MMC_RSP_136) { + cmd->resp[3] = mmc_readl(owl_host, OWL_REG_SD_RSPBUF0); + cmd->resp[2] = mmc_readl(owl_host, OWL_REG_SD_RSPBUF1); + cmd->resp[1] = mmc_readl(owl_host, OWL_REG_SD_RSPBUF2); + cmd->resp[0] = mmc_readl(owl_host, OWL_REG_SD_RSPBUF3); + } else { + resp[0] = mmc_readl(owl_host, OWL_REG_SD_RSPBUF0); + resp[1] = mmc_readl(owl_host, OWL_REG_SD_RSPBUF1); + cmd->resp[0] = resp[1] << 24 | resp[0] >> 8; + cmd->resp[1] = resp[1] >> 8; + } + } +} + +static void owl_mmc_dma_complete(void *param) +{ + struct owl_mmc_host *owl_host = param; + struct mmc_data *data = owl_host->data; + + if (data) + complete(&owl_host->dma_complete); +} + +static int owl_mmc_prepare_data(struct owl_mmc_host *owl_host, + struct mmc_data *data) +{ + u32 total; + + mmc_update_reg(owl_host->base + OWL_REG_SD_EN, OWL_SD_EN_BSEL, true); + mmc_writel(owl_host, OWL_REG_SD_BLK_NUM, data->blocks); + mmc_writel(owl_host, OWL_REG_SD_BLK_SIZE, data->blksz); + total = data->blksz * data->blocks; + + if (total < 512) + mmc_writel(owl_host, OWL_REG_SD_BUF_SIZE, total); + else + mmc_writel(owl_host, OWL_REG_SD_BUF_SIZE, 512); + + if (data->flags & MMC_DATA_WRITE) { + owl_host->dma_dir = DMA_TO_DEVICE; + owl_host->dma_cfg.direction = DMA_MEM_TO_DEV; + } else { + owl_host->dma_dir = DMA_FROM_DEVICE; + owl_host->dma_cfg.direction = DMA_DEV_TO_MEM; + } + + dma_map_sg(owl_host->dma->device->dev, data->sg, + data->sg_len, owl_host->dma_dir); + + dmaengine_slave_config(owl_host->dma, &owl_host->dma_cfg); + owl_host->desc = dmaengine_prep_slave_sg(owl_host->dma, data->sg, + data->sg_len, + owl_host->dma_cfg.direction, + DMA_PREP_INTERRUPT | + DMA_CTRL_ACK); + if (!owl_host->desc) { + dev_err(owl_host->dev, "Can't prepare slave sg\n"); + return -EBUSY; + } + + owl_host->data = data; + + owl_host->desc->callback = owl_mmc_dma_complete; + owl_host->desc->callback_param = (void *)owl_host; + data->error = 0; + + return 0; +} + +static void owl_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) +{ + struct owl_mmc_host *owl_host = mmc_priv(mmc); + struct mmc_data *data = mrq->data; + int ret; + + owl_host->mrq = mrq; + if (mrq->data) { + ret = owl_mmc_prepare_data(owl_host, data); + if (ret < 0) { + data->error = ret; + goto err_out; + } + + init_completion(&owl_host->dma_complete); + dmaengine_submit(owl_host->desc); + dma_async_issue_pending(owl_host->dma); + } + + owl_mmc_send_cmd(owl_host, mrq->cmd, data); + + if (data) { + if (!wait_for_completion_timeout(&owl_host->sdc_complete, + 10 * HZ)) { + dev_err(owl_host->dev, "CMD interrupt timeout\n"); + mrq->cmd->error = -ETIMEDOUT; + dmaengine_terminate_all(owl_host->dma); + goto err_out; + } + + if (!wait_for_completion_timeout(&owl_host->dma_complete, + 5 * HZ)) { + dev_err(owl_host->dev, "DMA interrupt timeout\n"); + mrq->cmd->error = -ETIMEDOUT; + dmaengine_terminate_all(owl_host->dma); + goto err_out; + } + + if (data->stop) + owl_mmc_send_cmd(owl_host, data->stop, NULL); + + data->bytes_xfered = data->blocks * data->blksz; + } + +err_out: + owl_mmc_finish_request(owl_host); +} + +static int owl_mmc_set_clk_rate(struct owl_mmc_host *owl_host, + unsigned int rate) +{ + unsigned long clk_rate; + int ret; + u32 reg; + + reg = mmc_readl(owl_host, OWL_REG_SD_CTL); + reg &= ~OWL_SD_CTL_DELAY_MSK; + + /* Set RDELAY and WDELAY based on the clock */ + if (rate <= 1000000) { + mmc_writel(owl_host, OWL_REG_SD_CTL, reg | + OWL_SD_CTL_RDELAY(OWL_SD_DELAY_LOW_CLK) | + OWL_SD_CTL_WDELAY(OWL_SD_DELAY_LOW_CLK)); + } else if ((rate > 1000000) && (rate <= 26000000)) { + mmc_writel(owl_host, OWL_REG_SD_CTL, reg | + OWL_SD_CTL_RDELAY(OWL_SD_DELAY_MID_CLK) | + OWL_SD_CTL_WDELAY(OWL_SD_DELAY_MID_CLK)); + } else if ((rate > 26000000) && (rate <= 52000000) && !owl_host->ddr_50) { + mmc_writel(owl_host, OWL_REG_SD_CTL, reg | + OWL_SD_CTL_RDELAY(OWL_SD_DELAY_HIGH_CLK) | + OWL_SD_CTL_WDELAY(OWL_SD_DELAY_HIGH_CLK)); + /* DDR50 mode has special delay chain */ + } else if ((rate > 26000000) && (rate <= 52000000) && owl_host->ddr_50) { + mmc_writel(owl_host, OWL_REG_SD_CTL, reg | + OWL_SD_CTL_RDELAY(OWL_SD_RDELAY_DDR50) | + OWL_SD_CTL_WDELAY(OWL_SD_WDELAY_DDR50)); + } else { + dev_err(owl_host->dev, "SD clock rate not supported\n"); + return -EINVAL; + } + + clk_rate = clk_round_rate(owl_host->clk, rate << 1); + ret = clk_set_rate(owl_host->clk, clk_rate); + + return ret; +} + +static void owl_mmc_set_clk(struct owl_mmc_host *owl_host, struct mmc_ios *ios) +{ + if (!ios->clock) + return; + + owl_host->clock = ios->clock; + owl_mmc_set_clk_rate(owl_host, ios->clock); +} + +static void owl_mmc_set_bus_width(struct owl_mmc_host *owl_host, + struct mmc_ios *ios) +{ + u32 reg; + + reg = mmc_readl(owl_host, OWL_REG_SD_EN); + reg &= ~0x03; + switch (ios->bus_width) { + case MMC_BUS_WIDTH_1: + break; + case MMC_BUS_WIDTH_4: + reg |= OWL_SD_EN_DATAWID(1); + break; + case MMC_BUS_WIDTH_8: + reg |= OWL_SD_EN_DATAWID(2); + break; + } + + mmc_writel(owl_host, OWL_REG_SD_EN, reg); +} + +static void owl_mmc_ctr_reset(struct owl_mmc_host *owl_host) +{ + reset_control_assert(owl_host->reset); + udelay(20); + reset_control_deassert(owl_host->reset); +} + +static void owl_mmc_power_on(struct owl_mmc_host *owl_host) +{ + u32 mode; + + init_completion(&owl_host->sdc_complete); + + /* Enable transfer end IRQ */ + mmc_update_reg(owl_host->base + OWL_REG_SD_STATE, + OWL_SD_STATE_TEIE, true); + + /* Send init clk */ + mode = (mmc_readl(owl_host, OWL_REG_SD_CTL) & (0xff << 16)); + mode |= OWL_SD_CTL_TS | OWL_SD_CTL_TCN(5) | OWL_SD_CTL_TM(8); + mmc_writel(owl_host, OWL_REG_SD_CTL, mode); + + if (!wait_for_completion_timeout(&owl_host->sdc_complete, HZ)) { + dev_err(owl_host->dev, "CMD interrupt timeout\n"); + return; + } +} + +static void owl_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) +{ + struct owl_mmc_host *owl_host = mmc_priv(mmc); + + switch (ios->power_mode) { + case MMC_POWER_UP: + dev_dbg(owl_host->dev, "Powering card up\n"); + + /* Reset the SDC controller to clear all previous states */ + owl_mmc_ctr_reset(owl_host); + clk_prepare_enable(owl_host->clk); + mmc_writel(owl_host, OWL_REG_SD_EN, OWL_SD_ENABLE | + OWL_SD_EN_RESE); + + break; + + case MMC_POWER_ON: + dev_dbg(owl_host->dev, "Powering card on\n"); + owl_mmc_power_on(owl_host); + + break; + + case MMC_POWER_OFF: + dev_dbg(owl_host->dev, "Powering card off\n"); + clk_disable_unprepare(owl_host->clk); + + return; + + default: + dev_dbg(owl_host->dev, "Ignoring unknown card power state\n"); + break; + } + + if (ios->clock != owl_host->clock) + owl_mmc_set_clk(owl_host, ios); + + owl_mmc_set_bus_width(owl_host, ios); + + /* Enable DDR mode if requested */ + if (ios->timing == MMC_TIMING_UHS_DDR50) { + owl_host->ddr_50 = 1; + mmc_update_reg(owl_host->base + OWL_REG_SD_EN, + OWL_SD_EN_DDREN, true); + } else { + owl_host->ddr_50 = 0; + } +} + +static int owl_mmc_start_signal_voltage_switch(struct mmc_host *mmc, + struct mmc_ios *ios) +{ + struct owl_mmc_host *owl_host = mmc_priv(mmc); + + /* It is enough to change the pad ctrl bit for voltage switch */ + switch (ios->signal_voltage) { + case MMC_SIGNAL_VOLTAGE_330: + mmc_update_reg(owl_host->base + OWL_REG_SD_EN, + OWL_SD_EN_S18EN, false); + break; + case MMC_SIGNAL_VOLTAGE_180: + mmc_update_reg(owl_host->base + OWL_REG_SD_EN, + OWL_SD_EN_S18EN, true); + break; + default: + return -ENOTSUPP; + } + + return 0; +} + +static const struct mmc_host_ops owl_mmc_ops = { + .request = owl_mmc_request, + .set_ios = owl_mmc_set_ios, + .get_ro = mmc_gpio_get_ro, + .get_cd = mmc_gpio_get_cd, + .start_signal_voltage_switch = owl_mmc_start_signal_voltage_switch, +}; + +static int owl_mmc_probe(struct platform_device *pdev) +{ + struct owl_mmc_host *owl_host; + struct mmc_host *mmc; + struct resource *res; + int ret; + + mmc = mmc_alloc_host(sizeof(struct owl_mmc_host), &pdev->dev); + if (!mmc) { + dev_err(&pdev->dev, "mmc alloc host failed\n"); + return -ENOMEM; + } + platform_set_drvdata(pdev, mmc); + + owl_host = mmc_priv(mmc); + owl_host->dev = &pdev->dev; + owl_host->mmc = mmc; + spin_lock_init(&owl_host->lock); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + owl_host->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(owl_host->base)) { + dev_err(&pdev->dev, "Failed to remap registers\n"); + ret = PTR_ERR(owl_host->base); + goto err_free_host; + } + + owl_host->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(owl_host->clk)) { + dev_err(&pdev->dev, "No clock defined\n"); + ret = PTR_ERR(owl_host->clk); + goto err_free_host; + } + + owl_host->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL); + if (IS_ERR(owl_host->reset)) { + dev_err(&pdev->dev, "Could not get reset control\n"); + ret = PTR_ERR(owl_host->reset); + goto err_free_host; + } + + mmc->ops = &owl_mmc_ops; + mmc->max_blk_count = 512; + mmc->max_blk_size = 512; + mmc->max_segs = 256; + mmc->max_seg_size = 262144; + mmc->max_req_size = 262144; + /* 100kHz ~ 52MHz */ + mmc->f_min = 100000; + mmc->f_max = 52000000; + mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | + MMC_CAP_4_BIT_DATA; + mmc->caps2 = (MMC_CAP2_BOOTPART_NOACC | MMC_CAP2_NO_SDIO); + mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | + MMC_VDD_165_195; + + ret = mmc_of_parse(mmc); + if (ret) + goto err_free_host; + + pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); + pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; + owl_host->dma = dma_request_slave_channel(&pdev->dev, "mmc"); + if (!owl_host->dma) { + dev_err(owl_host->dev, "Failed to get external DMA channel.\n"); + ret = -ENXIO; + goto err_free_host; + } + + dev_info(&pdev->dev, "Using %s for DMA transfers\n", + dma_chan_name(owl_host->dma)); + + owl_host->dma_cfg.src_addr = res->start + OWL_REG_SD_DAT; + owl_host->dma_cfg.dst_addr = res->start + OWL_REG_SD_DAT; + owl_host->dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + owl_host->dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + owl_host->dma_cfg.device_fc = false; + + owl_host->irq = platform_get_irq(pdev, 0); + if (owl_host->irq < 0) { + ret = -EINVAL; + goto err_free_host; + } + + ret = devm_request_irq(&pdev->dev, owl_host->irq, owl_irq_handler, + 0, dev_name(&pdev->dev), owl_host); + if (ret) { + dev_err(&pdev->dev, "Failed to request irq %d\n", + owl_host->irq); + goto err_free_host; + } + + ret = mmc_add_host(mmc); + if (ret) { + dev_err(&pdev->dev, "Failed to add host\n"); + goto err_free_host; + } + + dev_dbg(&pdev->dev, "Owl MMC Controller Initialized\n"); + + return 0; + +err_free_host: + mmc_free_host(mmc); + + return ret; +} + +static int owl_mmc_remove(struct platform_device *pdev) +{ + struct mmc_host *mmc = platform_get_drvdata(pdev); + struct owl_mmc_host *owl_host = mmc_priv(mmc); + + mmc_remove_host(mmc); + disable_irq(owl_host->irq); + mmc_free_host(mmc); + + return 0; +} + +static const struct of_device_id owl_mmc_of_match[] = { + {.compatible = "actions,owl-mmc",}, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, owl_mmc_of_match); + +static struct platform_driver owl_mmc_driver = { + .driver = { + .name = "owl_mmc", + .of_match_table = of_match_ptr(owl_mmc_of_match), + }, + .probe = owl_mmc_probe, + .remove = owl_mmc_remove, +}; +module_platform_driver(owl_mmc_driver); + +MODULE_DESCRIPTION("Actions Semi Owl SoCs SD/MMC Driver"); +MODULE_AUTHOR("Actions Semi"); +MODULE_AUTHOR("Manivannan Sadhasivam "); +MODULE_LICENSE("GPL"); From patchwork Sat Jun 8 19:53:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 166208 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2157862ili; Sat, 8 Jun 2019 12:54:31 -0700 (PDT) X-Google-Smtp-Source: APXvYqwikAkkvhwWwbjqgzcosFVXLns9lUfmsPGDS2Z4zeJHgvQQnuMt+HhTSFR+bHTrlsCXWi5K X-Received: by 2002:a63:ec42:: with SMTP id r2mr8916089pgj.262.1560023670905; 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Signed-off-by: Manivannan Sadhasivam --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.1 diff --git a/MAINTAINERS b/MAINTAINERS index a6954776a37e..11d6937c4688 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1336,6 +1336,7 @@ F: drivers/clk/actions/ F: drivers/clocksource/timer-owl* F: drivers/dma/owl-dma.c F: drivers/i2c/busses/i2c-owl.c +F: drivers/mmc/host/owl-mmc.c F: drivers/pinctrl/actions/* F: drivers/soc/actions/ F: include/dt-bindings/power/owl-* @@ -1344,6 +1345,7 @@ F: Documentation/devicetree/bindings/arm/actions.txt F: Documentation/devicetree/bindings/clock/actions,owl-cmu.txt F: Documentation/devicetree/bindings/dma/owl-dma.txt F: Documentation/devicetree/bindings/i2c/i2c-owl.txt +F: Documentation/devicetree/bindings/mmc/owl-mmc.txt F: Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt F: Documentation/devicetree/bindings/power/actions,owl-sps.txt F: Documentation/devicetree/bindings/timer/actions,owl-timer.txt