From patchwork Wed May 17 08:00:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Tokarev X-Patchwork-Id: 682903 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp230521wrt; Wed, 17 May 2023 01:09:36 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4sWyEdNl3/qG6CgnV5PW3GtpSEuKfUsj0wGQA44avEnhZfdML2p3IqVJqzmUAN5E3TZdTQ X-Received: by 2002:ad4:5bac:0:b0:619:4232:aa87 with SMTP id 12-20020ad45bac000000b006194232aa87mr54364104qvq.24.1684310976636; Wed, 17 May 2023 01:09:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684310976; cv=none; d=google.com; s=arc-20160816; b=nxnBGJRQqT03ll9PHDWADI637ov1J3Ci6nBi7NbevCYREp0o4wPtUdyyjtuD+CIo9r GrehDSnZMK380c9qRoG4eZH3t9AYXAlFXNw5JW4nmlxGMhpBpGgQlYpmhLrU9RKPs1z5 NwCQYEUvQON6Gd0rDOrZKqresJrz2u78v1a4FwkYx+h8+aYIR7EuiWvegq70lTA187KL 50uyfaOVLeGIT+f/aOWz/8rOIF4m7tRQMkCRtvnPWb28poFQu5SbBQdQD7+FSKcuJbkK AvY7QKIvufWYvE6ZTpyQZuD64kHE0o/UYllNj3UYwDekHjhByDGQiWgJ8akHoHXm99mD 1pSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=qX1w5HKe63hOj739JegGghzCFVOwHSxF3hixEYsrhBA=; b=syKdumnAAyCeqHwMm0sjYcDcNFTuvydvKzOx9reO0vVcxTDyD4hfzZmD1fhZPGC1UN ZKSva7j9LoM+AMwQE1y8d+GUn+Ewy/xWQzS0DYYjZlNzCtj2k0nsHKhuTAyghhJmnfKo xzFG46QktvjS85wgiF5U7xQ40l3U87mNTGaj1VISSs5d3QaBQRkm6Zg8IXt+6RnImKg4 T3Ty2nb8tfsJhqSgVTtGpwcG6gntGZUmhZo4s2fNSwFJN1Vp+MWEwtIMumRmZdWZcPWP +049ovT9UM2EHUMVFn+kczEdLhBBWHNDSwxMGCZ+6SHdi14vjjX2ulJRqMVYD0GbuonV zC4Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j1-20020ae9c201000000b007578e03b68esi959321qkg.698.2023.05.17.01.09.36 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 17 May 2023 01:09:36 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pzC6Y-0002Jf-9x; Wed, 17 May 2023 04:01:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzC6G-00021G-7H; Wed, 17 May 2023 04:01:35 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzC6D-0000Yc-Ow; Wed, 17 May 2023 04:01:31 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id B26F86750; Wed, 17 May 2023 11:00:57 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 30CB85E08; Wed, 17 May 2023 11:00:57 +0300 (MSK) Received: (nullmailer pid 3624099 invoked by uid 1000); Wed, 17 May 2023 08:00:56 -0000 From: Michael Tokarev To: qemu-stable@nongnu.org Cc: qemu-devel@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Thomas Huth , Markus Armbruster , Kevin Wolf Subject: [PATCH v8.0.1 07/36] qemu-options: finesse the recommendations around -blockdev Date: Wed, 17 May 2023 11:00:27 +0300 Message-Id: <20230517080056.3623993-7-mjt@msgid.tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: <<20230517073442.3622973-0-mjt@msgid.tls.msk.ru> References: <20230517073442.3622973-0-mjt@msgid.tls.msk.ru> MIME-Version: 1.0 Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Alex Bennée We are a bit premature in recommending -blockdev/-device as the best way to configure block devices. It seems there are times the more human friendly -drive still makes sense especially when -snapshot is involved. Improve the language to hopefully make things clearer. Suggested-by: Michael Tokarev Signed-off-by: Alex Bennée Reviewed-by: Thomas Huth Cc: Markus Armbruster Cc: Kevin Wolf Message-Id: <20230424092249.58552-7-alex.bennee@linaro.org> (cherry picked from commit c1654c3e37c31fb638597efedcd07d071837b78b) Signed-off-by: Michael Tokarev --- qemu-options.hx | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/qemu-options.hx b/qemu-options.hx index 59bdf67a2c..4b8855a4f7 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -1143,10 +1143,22 @@ have gone through several iterations as the feature set and complexity of the block layer have grown. Many online guides to QEMU often reference older and deprecated options, which can lead to confusion. -The recommended modern way to describe disks is to use a combination of +The most explicit way to describe disks is to use a combination of ``-device`` to specify the hardware device and ``-blockdev`` to describe the backend. The device defines what the guest sees and the -backend describes how QEMU handles the data. +backend describes how QEMU handles the data. It is the only guaranteed +stable interface for describing block devices and as such is +recommended for management tools and scripting. + +The ``-drive`` option combines the device and backend into a single +command line option which is a more human friendly. There is however no +interface stability guarantee although some older board models still +need updating to work with the modern blockdev forms. + +Older options like ``-hda`` are essentially macros which expand into +``-drive`` options for various drive interfaces. The original forms +bake in a lot of assumptions from the days when QEMU was emulating a +legacy PC, they are not recommended for modern configurations. ERST @@ -1639,6 +1651,14 @@ SRST the raw disk image you use is not written back. You can however force the write back by pressing C-a s (see the :ref:`disk images` chapter in the System Emulation Users Guide). + + .. warning:: + snapshot is incompatible with ``-blockdev`` (instead use qemu-img + to manually create snapshot images to attach to your blockdev). + If you have mixed ``-blockdev`` and ``-drive`` declarations you + can use the 'snapshot' property on your drive declarations + instead of this global option. + ERST DEF("fsdev", HAS_ARG, QEMU_OPTION_fsdev, From patchwork Wed May 17 08:00:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Tokarev X-Patchwork-Id: 682908 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp231144wrt; Wed, 17 May 2023 01:11:10 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6rlu9LGdMs2DBSArRmyFJhIkKJ9RKj3bxyyUwjRejuAQYOTpZYihdzDFJtED0bCX8o/YpQ X-Received: by 2002:ac8:5c50:0:b0:3e3:937b:2a64 with SMTP id j16-20020ac85c50000000b003e3937b2a64mr68998119qtj.18.1684311069949; Wed, 17 May 2023 01:11:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684311069; cv=none; d=google.com; s=arc-20160816; b=h5uKxXHc7bTd2IzyOUxz5pgiE8JcJEN8Ug8Na3ao2mrQVkdVyU5+EuNcL/ycTdVxr1 NzriP0XyjmGg2lif+cQSRYUAHK0WC9sbrLxo9cOvenRuNLhzipns3SnP+sNMYH/U5ZdO YSl1gvzNyvQ88kTuRrey3lJNZds+hR3pKOHObMcVhFGMnqDGmy0j3ubej5sHQd+7yf5g mSWE8fhLlZ0iZ7dlOEG48UcqBLpiUYORLTFoYqJuUobF1V9hE6G8+56+pWODrplSPFPE KvQntEdGyjQtBzc1CvXP5LSFoGQXrN1jw0VpEH/dIf+pLQIXzwvXoO5NNGbrDyej6vSO kQPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=8Oov5WFv0306D3of2zoviUvx+YT40NUCLwxPNZZd238=; b=FP7OgWkoq+HN23mSW1EvnaMHWWt352zPCRfrSTKCBMNO0Y/tAe3Kt5C202p9v3OZ2p KMReSXb9qQ+jbqcz0KH14QDyq4QvYYXPdfgXQ4qnhuXYLcv1GoYKdaEndagETsLpWH56 MZFFq0qVH6gXFqP5njreqvTHFyZJXOqz4AjndmO1d1ld+amf+LMncSVJ0Z0dbqLmgXfj AbVgw8igjOpV9fVZq+c7vAKLRXpprnZaOy79/MrIia5NIWmFJr7BZh4WmpIRgY0cn3sc BOoDq2+Tw4usdrTR1tattqKbPDDRAeRjZ+oKYaQgHhXjiiL+4ItSDV5XkWIyZlwzsfkd 34Xg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id l20-20020a05622a051400b003ef49fe5460si12510010qtx.765.2023.05.17.01.11.09 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 17 May 2023 01:11:09 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pzC6X-0002Hc-RH; Wed, 17 May 2023 04:01:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzC5z-0001s3-4n; Wed, 17 May 2023 04:01:21 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzC5s-0000YW-DT; Wed, 17 May 2023 04:01:12 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id D5DD56751; Wed, 17 May 2023 11:00:57 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 5F32B5E09; Wed, 17 May 2023 11:00:57 +0300 (MSK) Received: (nullmailer pid 3624102 invoked by uid 1000); Wed, 17 May 2023 08:00:56 -0000 From: Michael Tokarev To: qemu-stable@nongnu.org Cc: qemu-devel@nongnu.org, Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Alex?= =?utf-8?q?_Benn=C3=A9e?= Subject: [PATCH v8.0.1 08/36] docs/about/deprecated.rst: Add "since 7.1" tag to dtb-kaslr-seed deprecation Date: Wed, 17 May 2023 11:00:28 +0300 Message-Id: <20230517080056.3623993-8-mjt@msgid.tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: <<20230517073442.3622973-0-mjt@msgid.tls.msk.ru> References: <20230517073442.3622973-0-mjt@msgid.tls.msk.ru> MIME-Version: 1.0 Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Peter Maydell In commit 5242876f37ca we deprecated the dtb-kaslr-seed property of the virt board, but forgot the "since n.n" tag in the documentation of this in deprecated.rst. This deprecation note first appeared in the 7.1 release, so retrospectively add the correct "since 7.1" annotation to it. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Message-id: 20230420122256.1023709-1-peter.maydell@linaro.org (cherry picked from commit ac64ebbecf80f6bc764d120f85fe9fa28fbd9e85) Signed-off-by: Michael Tokarev --- docs/about/deprecated.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index 1ca9dc33d6..914938fd76 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -219,8 +219,8 @@ Use the more generic event ``DEVICE_UNPLUG_GUEST_ERROR`` instead. System emulator machines ------------------------ -Arm ``virt`` machine ``dtb-kaslr-seed`` property -'''''''''''''''''''''''''''''''''''''''''''''''' +Arm ``virt`` machine ``dtb-kaslr-seed`` property (since 7.1) +'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' The ``dtb-kaslr-seed`` property on the ``virt`` board has been deprecated; use the new name ``dtb-randomness`` instead. The new name From patchwork Wed May 17 08:00:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Tokarev X-Patchwork-Id: 682898 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp227810wrt; Wed, 17 May 2023 01:02:11 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5E3HD5sWHL0CO4DYgS4k4uTc9TycPvqMvfVhh+VS5AUGIE+kXXQmn1sLRVTHJoiR/FFiju X-Received: by 2002:a05:622a:174a:b0:3f5:34fc:f216 with SMTP id l10-20020a05622a174a00b003f534fcf216mr13510197qtk.54.1684310531630; Wed, 17 May 2023 01:02:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684310531; cv=none; d=google.com; s=arc-20160816; b=wclLDl+BZyBedWwScdv+vCxUl7/KPaqiz3EfB4uxT8t3emiTW+MgAN6NBJ1BaTS6Uc M4yGwGoItDJvrsLNSPF/5NstQOrDOvs4ujLE0RtQMisA8W+jnLNBuwwR57OmewPM9EAL JMeO7KUA26IPODbCzNvs6AumInfB/SHVevlrhee8jhikI93bdUMBSOBKJqzwRrFAToy+ 9KWY6SLhCLUpSP7Fl1brVjd2hFoojRd3iKc02mjwtPY7WFBSkq+BMOvan6I623hyslp8 W4G0MM13B4L4WYiIy4NqfJf3ZIern8P0FtmSRUse6h+5Xxyor7gxDs41cR3f3oTZs5XU Hcvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=Qvem2rHcMg9zrJFA4/Y5bQTC1esOyIAEA7wGjjPNjH8=; b=eaRWU2KgRarmv31iaas2TwjAdpWlTPgo48MmS8iZf5FdQs5iLXj7bNvFlAL72qo7In BwtNBL2aJFak12c0hs1gszCPV03OMui8wbQlF7SC1EUcVxVabSNu3mNv1WN+oYGS9md9 6mw9L0uhfjC88Ht0JeVcXfn8fFxlUe1jhCVpwJcv1toEiZ4hbZqasPJCMPsqNc2cA3D7 bYLKHnxK3YYoy9vZK8YF1wyvDPHc+tddf8rPPvAMwT45ns83W4UYea3Ly5bLElpgLAvY bRZ5AUhPH2L07GVpvBUqAVpeZ8MsHP6q0Wq2HV7WpWTcOwjeDECmz2YTdvdxwo1bYiua dK1w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 8-20020ac85708000000b003eaf7aca02asi12579413qtw.376.2023.05.17.01.02.11 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 17 May 2023 01:02:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pzC69-0001wB-Fx; Wed, 17 May 2023 04:01:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzC61-0001si-2Q; Wed, 17 May 2023 04:01:21 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzC5t-0000Yj-MQ; Wed, 17 May 2023 04:01:15 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 4285B6753; Wed, 17 May 2023 11:00:58 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id BCDD85E0B; Wed, 17 May 2023 11:00:57 +0300 (MSK) Received: (nullmailer pid 3624108 invoked by uid 1000); Wed, 17 May 2023 08:00:56 -0000 From: Michael Tokarev To: qemu-stable@nongnu.org Cc: qemu-devel@nongnu.org, Peter Maydell , Thomas Huth Subject: [PATCH v8.0.1 10/36] hw/net/msf2-emac: Don't modify descriptor in-place in emac_store_desc() Date: Wed, 17 May 2023 11:00:30 +0300 Message-Id: <20230517080056.3623993-10-mjt@msgid.tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: <<20230517073442.3622973-0-mjt@msgid.tls.msk.ru> References: <20230517073442.3622973-0-mjt@msgid.tls.msk.ru> MIME-Version: 1.0 Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Peter Maydell The msf2-emac ethernet controller has functions emac_load_desc() and emac_store_desc() which read and write the in-memory descriptor blocks and handle conversion between guest and host endianness. As currently written, emac_store_desc() does the endianness conversion in-place; this means that it effectively consumes the input EmacDesc struct, because on a big-endian host the fields will be overwritten with the little-endian versions of their values. Unfortunately, in all the callsites the code continues to access fields in the EmacDesc struct after it has called emac_store_desc() -- specifically, it looks at the d.next field. The effect of this is that on a big-endian host networking doesn't work because the address of the next descriptor is corrupted. We could fix this by making the callsite avoid using the struct; but it's more robust to have emac_store_desc() leave its input alone. (emac_load_desc() also does an in-place conversion, but here this is fine, because the function is supposed to be initializing the struct.) Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Thomas Huth Message-id: 20230424151919.1333299-1-peter.maydell@linaro.org (cherry picked from commit d565f58b38424e9a390a7ea33ff7477bab693fda) Signed-off-by: Michael Tokarev --- hw/net/msf2-emac.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/hw/net/msf2-emac.c b/hw/net/msf2-emac.c index 7ccd3e5142..db3a04deb1 100644 --- a/hw/net/msf2-emac.c +++ b/hw/net/msf2-emac.c @@ -118,14 +118,18 @@ static void emac_load_desc(MSF2EmacState *s, EmacDesc *d, hwaddr desc) d->next = le32_to_cpu(d->next); } -static void emac_store_desc(MSF2EmacState *s, EmacDesc *d, hwaddr desc) +static void emac_store_desc(MSF2EmacState *s, const EmacDesc *d, hwaddr desc) { - /* Convert from host endianness into LE. */ - d->pktaddr = cpu_to_le32(d->pktaddr); - d->pktsize = cpu_to_le32(d->pktsize); - d->next = cpu_to_le32(d->next); - - address_space_write(&s->dma_as, desc, MEMTXATTRS_UNSPECIFIED, d, sizeof *d); + EmacDesc outd; + /* + * Convert from host endianness into LE. We use a local struct because + * calling code may still want to look at the fields afterwards. + */ + outd.pktaddr = cpu_to_le32(d->pktaddr); + outd.pktsize = cpu_to_le32(d->pktsize); + outd.next = cpu_to_le32(d->next); + + address_space_write(&s->dma_as, desc, MEMTXATTRS_UNSPECIFIED, &outd, sizeof outd); } static void msf2_dma_tx(MSF2EmacState *s) From patchwork Wed May 17 08:00:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Tokarev X-Patchwork-Id: 682901 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp230007wrt; Wed, 17 May 2023 01:08:04 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ728iOz1h9LyCtL99JRt1niGhXBaltardATzLej0ya0sdoNgsi8EoXB7bW5qJDsEukJWM0H X-Received: by 2002:a05:622a:54f:b0:3ef:2c95:9d04 with SMTP id m15-20020a05622a054f00b003ef2c959d04mr63570982qtx.65.1684310883822; Wed, 17 May 2023 01:08:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684310883; cv=none; d=google.com; s=arc-20160816; b=FWZNz29InErCWKvEjwMptfYSc3Z0G3ezY0mn/75Cf9lzJ2hovfwyg8fhTIbt78dmEw NRDcXp5Pw7E8rhSzN1F0b1pImsXKGIZbEHuD80/2UsX03Ey+yuMZYBbsoOAgZJX5jdrf ZYTBI+Wfd7kvreQnv8lcGMrr7k5tW/udWb/uKx2ZMCNOfbGtxoSZcaAs1bR0sjBcoqBF isWZtQwg7uPtRIuevin9Jo2vdtB9ZtC+VB7KgMtDYtQ3hODoEvuz6kCrjAWS1G+yGjCT ODApuZGXF/egQonhd29lmUwltP/j2xTliFmIXDj7t3qW/zktNL53ZkdiwsdfK4qrDWvG Qoog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=pNDtB9NAMSVLZ9MxNwbwXA0d37pjs5xSOZmC+cb9cw0=; b=plkXLUViQ5YkxMLzL+ZZcTtVHimglOzM/RmoaQ6b0oStkSmizriLban3MluHJx2ooM RW0SD/D9eN1ozHX7SO4vbE9fcpLaLLX9gwt7O0tAUoMTAMtyuYtr4ArvqmR5Fm90CnsX ScS/k9TV27DyuL/EzNQLJ8p3SFnvz3nMdPoFCRqrwcbcQzYwx2+At9PgatA3dra1q6fH priYc7PtelX+rNlrRILIl+FZWotEROsxKJHRjVkHzPTEOrXdgaKQiEfdGnkfPIb6hyvF HlecWW2gmJJzNsAsYrmkVmWGtkw9hqnmMbnZEjmhi9C6ZJ5pMeXNacxUtvNFFj99FwSk oygA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g5-20020ae9e105000000b007577da49327si996184qkm.398.2023.05.17.01.08.03 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 17 May 2023 01:08:03 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pzC6e-0002eQ-Os; Wed, 17 May 2023 04:01:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzC6M-00023c-Gd; Wed, 17 May 2023 04:01:42 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzC6F-0000Zi-I3; Wed, 17 May 2023 04:01:38 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id B03E96756; Wed, 17 May 2023 11:00:58 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 3C8DA5E0E; Wed, 17 May 2023 11:00:58 +0300 (MSK) Received: (nullmailer pid 3624117 invoked by uid 1000); Wed, 17 May 2023 08:00:56 -0000 From: Michael Tokarev To: qemu-stable@nongnu.org Cc: qemu-devel@nongnu.org, Peter Maydell , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH v8.0.1 13/36] hw/arm/raspi: Use arm_write_bootloader() to write boot code Date: Wed, 17 May 2023 11:00:33 +0300 Message-Id: <20230517080056.3623993-13-mjt@msgid.tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: <<20230517073442.3622973-0-mjt@msgid.tls.msk.ru> References: <20230517073442.3622973-0-mjt@msgid.tls.msk.ru> MIME-Version: 1.0 Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Peter Maydell When writing the secondary-CPU stub boot loader code to the guest, use arm_write_bootloader() instead of directly calling rom_add_blob_fixed(). This fixes a bug on big-endian hosts, because arm_write_bootloader() will correctly byte-swap the host-byte-order array values into the guest-byte-order to write into the guest memory. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Tested-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé Message-id: 20230424152717.1333930-4-peter.maydell@linaro.org (cherry picked from commit 0acbdb4c4ab6b0a09f159bae4899b0737cf64242) Signed-off-by: Michael Tokarev --- hw/arm/raspi.c | 64 +++++++++++++++++++++++++++----------------------- 1 file changed, 34 insertions(+), 30 deletions(-) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 92d068d1f9..a7d287b1a8 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -16,6 +16,7 @@ #include "qemu/units.h" #include "qemu/cutils.h" #include "qapi/error.h" +#include "hw/arm/boot.h" #include "hw/arm/bcm2836.h" #include "hw/registerfields.h" #include "qemu/error-report.h" @@ -124,20 +125,22 @@ static const char *board_type(uint32_t board_rev) static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info) { - static const uint32_t smpboot[] = { - 0xe1a0e00f, /* mov lr, pc */ - 0xe3a0fe00 + (BOARDSETUP_ADDR >> 4), /* mov pc, BOARDSETUP_ADDR */ - 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5;get core ID */ - 0xe7e10050, /* ubfx r0, r0, #0, #2 ;extract LSB */ - 0xe59f5014, /* ldr r5, =0x400000CC ;load mbox base */ - 0xe320f001, /* 1: yield */ - 0xe7953200, /* ldr r3, [r5, r0, lsl #4] ;read mbox for our core*/ - 0xe3530000, /* cmp r3, #0 ;spin while zero */ - 0x0afffffb, /* beq 1b */ - 0xe7853200, /* str r3, [r5, r0, lsl #4] ;clear mbox */ - 0xe12fff13, /* bx r3 ;jump to target */ - 0x400000cc, /* (constant: mailbox 3 read/clear base) */ + static const ARMInsnFixup smpboot[] = { + { 0xe1a0e00f }, /* mov lr, pc */ + { 0xe3a0fe00 + (BOARDSETUP_ADDR >> 4) }, /* mov pc, BOARDSETUP_ADDR */ + { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5;get core ID */ + { 0xe7e10050 }, /* ubfx r0, r0, #0, #2 ;extract LSB */ + { 0xe59f5014 }, /* ldr r5, =0x400000CC ;load mbox base */ + { 0xe320f001 }, /* 1: yield */ + { 0xe7953200 }, /* ldr r3, [r5, r0, lsl #4] ;read mbox for our core */ + { 0xe3530000 }, /* cmp r3, #0 ;spin while zero */ + { 0x0afffffb }, /* beq 1b */ + { 0xe7853200 }, /* str r3, [r5, r0, lsl #4] ;clear mbox */ + { 0xe12fff13 }, /* bx r3 ;jump to target */ + { 0x400000cc }, /* (constant: mailbox 3 read/clear base) */ + { 0, FIXUP_TERMINATOR } }; + static const uint32_t fixupcontext[FIXUP_MAX] = { 0 }; /* check that we don't overrun board setup vectors */ QEMU_BUILD_BUG_ON(SMPBOOT_ADDR + sizeof(smpboot) > MVBAR_ADDR); @@ -145,9 +148,8 @@ static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info) QEMU_BUILD_BUG_ON((BOARDSETUP_ADDR & 0xf) != 0 || (BOARDSETUP_ADDR >> 4) >= 0x100); - rom_add_blob_fixed_as("raspi_smpboot", smpboot, sizeof(smpboot), - info->smp_loader_start, - arm_boot_address_space(cpu, info)); + arm_write_bootloader("raspi_smpboot", arm_boot_address_space(cpu, info), + info->smp_loader_start, smpboot, fixupcontext); } static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info) @@ -161,26 +163,28 @@ static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info) * the primary CPU goes into the kernel. We put these variables inside * a rom blob, so that the reset for ROM contents zeroes them for us. */ - static const uint32_t smpboot[] = { - 0xd2801b05, /* mov x5, 0xd8 */ - 0xd53800a6, /* mrs x6, mpidr_el1 */ - 0x924004c6, /* and x6, x6, #0x3 */ - 0xd503205f, /* spin: wfe */ - 0xf86678a4, /* ldr x4, [x5,x6,lsl #3] */ - 0xb4ffffc4, /* cbz x4, spin */ - 0xd2800000, /* mov x0, #0x0 */ - 0xd2800001, /* mov x1, #0x0 */ - 0xd2800002, /* mov x2, #0x0 */ - 0xd2800003, /* mov x3, #0x0 */ - 0xd61f0080, /* br x4 */ + static const ARMInsnFixup smpboot[] = { + { 0xd2801b05 }, /* mov x5, 0xd8 */ + { 0xd53800a6 }, /* mrs x6, mpidr_el1 */ + { 0x924004c6 }, /* and x6, x6, #0x3 */ + { 0xd503205f }, /* spin: wfe */ + { 0xf86678a4 }, /* ldr x4, [x5,x6,lsl #3] */ + { 0xb4ffffc4 }, /* cbz x4, spin */ + { 0xd2800000 }, /* mov x0, #0x0 */ + { 0xd2800001 }, /* mov x1, #0x0 */ + { 0xd2800002 }, /* mov x2, #0x0 */ + { 0xd2800003 }, /* mov x3, #0x0 */ + { 0xd61f0080 }, /* br x4 */ + { 0, FIXUP_TERMINATOR } }; + static const uint32_t fixupcontext[FIXUP_MAX] = { 0 }; static const uint64_t spintables[] = { 0, 0, 0, 0 }; - rom_add_blob_fixed_as("raspi_smpboot", smpboot, sizeof(smpboot), - info->smp_loader_start, as); + arm_write_bootloader("raspi_smpboot", as, info->smp_loader_start, + smpboot, fixupcontext); rom_add_blob_fixed_as("raspi_spintables", spintables, sizeof(spintables), SPINTABLE_ADDR, as); } From patchwork Wed May 17 08:00:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Tokarev X-Patchwork-Id: 682909 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp231171wrt; Wed, 17 May 2023 01:11:17 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7NmiQyutLdxpIrfaKsWssKCKf/eF6M8KQfjOE9G7nzsDhr7mLHTG9BojGT588iGlVUWfgN X-Received: by 2002:a05:622a:211:b0:3ef:3511:f494 with SMTP id b17-20020a05622a021100b003ef3511f494mr69471734qtx.16.1684311076796; Wed, 17 May 2023 01:11:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684311076; cv=none; d=google.com; s=arc-20160816; b=0jBOMGhQRDNbiQ3T25qpG3TqCcPvdHMdauPyGesnxQ3DllZzY3Ix9Erk7nfGQk0xHp MTQAip0xERnK0h7IY7X3f5iQMC9g9IDHGYDx8tHeIuAE+6epYXPt4lze2v908daIA8rD 2oPd59wST3kzBHqAcfSxkDrpOXRLMT1nNkWoK8yv4p5nHu3Qol5KMhPB9/DSEr2HOfyC EY0/j/5t7Zuu5xqdJfUHI2XDJtHM5H/ook/cTrKsP2VZEQwqtIZV3t5BoCH9Now1cBXW jb8OOrKLRl6LQn7J3kNuGldoI95kp5X5lVZJPhCP5h8AXfmglOnryzvBWQEwX5XZ4hVw dKWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=GamS3+Kc+NwOXwImuX97lvHh6uivd76pqWR7sL14SgE=; b=q3RyuA26jacLVe9afluFBxThzbyGkVRR2z7E8Nwjt/0TWoR1ieJLDju2i8zaFI+npd rXCaU5Bq8Z1+x7Vh1nwnFhfqmX9npVJcIsTGdyvmmmtNqXUPUi5Yb5i+2k9JK3baM1G0 wiJGJAd/z+/qe5Ed4BkNFGgljgkMn8K6orAe5P+/DB3rq2ckAPLrWxHTnhuZ2O6F25rw et9gkeO9yu2VKb9BTyIs3gNa1FzhwE+I3bB4HAMW7TahjOkUiIr7ST+qB8n4+Wfe7XI4 g0XI1N3c60zFM9nAhdBGfUyO5EjibnKMsv37FFozqL3fpe34gK4Sqw2ufjhZ2jPYgz+C mMlg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t17-20020ac85891000000b003f3908aec16si12361680qta.687.2023.05.17.01.11.16 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 17 May 2023 01:11:16 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pzC6c-0002Yq-RB; Wed, 17 May 2023 04:01:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzC6J-00022j-W5; Wed, 17 May 2023 04:01:36 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzC6F-0000Zj-IY; Wed, 17 May 2023 04:01:35 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id D70166757; Wed, 17 May 2023 11:00:58 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 5D47E5E0F; Wed, 17 May 2023 11:00:58 +0300 (MSK) Received: (nullmailer pid 3624120 invoked by uid 1000); Wed, 17 May 2023 08:00:56 -0000 From: Michael Tokarev To: qemu-stable@nongnu.org Cc: qemu-devel@nongnu.org, Peter Maydell , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v8.0.1 14/36] hw/intc/allwinner-a10-pic: Don't use set_bit()/clear_bit() Date: Wed, 17 May 2023 11:00:34 +0300 Message-Id: <20230517080056.3623993-14-mjt@msgid.tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: <<20230517073442.3622973-0-mjt@msgid.tls.msk.ru> References: <20230517073442.3622973-0-mjt@msgid.tls.msk.ru> MIME-Version: 1.0 Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Peter Maydell The Allwinner PIC model uses set_bit() and clear_bit() to update the values in its irq_pending[] array when an interrupt arrives. However it is using these functions wrongly: they work on an array of type 'long', and it is passing an array of type 'uint32_t'. Because the code manually figures out the right array element, this works on little-endian hosts and on 32-bit big-endian hosts, where bits 0..31 in a 'long' are in the same place as they are in a 'uint32_t'. However it breaks on 64-bit big-endian hosts. Remove the use of set_bit() and clear_bit() in favour of using deposit32() on the array element. This fixes a bug where on big-endian 64-bit hosts the guest kernel would hang early on in bootup. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé Message-id: 20230424152833.1334136-1-peter.maydell@linaro.org (cherry picked from commit 2c5fa0778c3b4307f9f3af7f27886c46d129c62f) Signed-off-by: Michael Tokarev --- hw/intc/allwinner-a10-pic.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c index 8cca124807..4875e68ba6 100644 --- a/hw/intc/allwinner-a10-pic.c +++ b/hw/intc/allwinner-a10-pic.c @@ -49,12 +49,9 @@ static void aw_a10_pic_update(AwA10PICState *s) static void aw_a10_pic_set_irq(void *opaque, int irq, int level) { AwA10PICState *s = opaque; + uint32_t *pending_reg = &s->irq_pending[irq / 32]; - if (level) { - set_bit(irq % 32, (void *)&s->irq_pending[irq / 32]); - } else { - clear_bit(irq % 32, (void *)&s->irq_pending[irq / 32]); - } + *pending_reg = deposit32(*pending_reg, irq % 32, 1, level); aw_a10_pic_update(s); } From patchwork Wed May 17 08:00:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Tokarev X-Patchwork-Id: 682905 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp230955wrt; Wed, 17 May 2023 01:10:39 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5MC+/RtUz3XBTC2P6o1WtLi8EGtsN/LdBiYGw0fKEch/G4075FplpyfsC05bpSaR4bkBxf X-Received: by 2002:a05:6214:d62:b0:621:65de:f600 with SMTP id 2-20020a0562140d6200b0062165def600mr2797443qvs.1.1684311039674; Wed, 17 May 2023 01:10:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684311039; cv=none; d=google.com; s=arc-20160816; b=f0uAOf0Asc3Su7hU0pPhzxfnatUFmdBeSwaUjnJg/Ejm288iFOWVQScbaKNnDYKqAV 3yxni9XmQXzKtuIfTmOOgAU+UmkzdWateQh7V3xGITNrBUSWeqO9mRzPpEgaOcs7ASvR JK0YrVVyPdH7IhuuUfOpd5drf6WeKzcEISwGd2j357yqVXTuoq7ihiXKYGi12k8VgOGD y6L4H+L/vLPUWovCRqcQlx0WMBQmD5FLo3JnEagNoyLeWV2jVgzVZF3iR2ZxgoTMj+YA gExhvrsnuJflSum4Vw/SISrrVdZpAf9D1fGTuopp1iriv0009M8oYuVPsrXPSmQ3Scoz ZROA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=5uyCqt+kSqvrAy3CmYf02oTnnSowM/C777Dckwlk7tQ=; b=U2zsC9I5kzN5gkz8xycvDPi6W9igSpy2BxQrE5J2lF8Q4YFUnmMev/B453uY/nrZGr kSQmGJfahW2cBimCpHDjRjZb7Pw24yyQcf8wyYI1hvlMPMa6ccndz5DBLfXUnsRxdJ8Q zlV6yJ0iGX3VgI5s5DoUZmyQgRq3Pe2RpxAFjvbNZu6niivgShdLkINE4Qdm754M4i4D NiemFgLGQLTavgWaia2SulZtTu2742mrmdVQkKEBh8btQ67QuXmImWmU7F0nnIu6pmpK tySxTUFyUrgx2NeYLts+pqRX99xvm04tW3lMFE6FgofsJilhtJku8vg+04LYu7ivH2/p kCqg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f8-20020a0562141d2800b005ef34880c8fsi12875851qvd.15.2023.05.17.01.10.39 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 17 May 2023 01:10:39 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pzC6u-000301-5e; Wed, 17 May 2023 04:02:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzC6O-00023r-CQ; Wed, 17 May 2023 04:01:42 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzC6L-0000aq-3d; Wed, 17 May 2023 04:01:39 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id F15666758; Wed, 17 May 2023 11:00:58 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 835E55E10; Wed, 17 May 2023 11:00:58 +0300 (MSK) Received: (nullmailer pid 3624123 invoked by uid 1000); Wed, 17 May 2023 08:00:56 -0000 From: Michael Tokarev To: qemu-stable@nongnu.org Cc: qemu-devel@nongnu.org, Peter Maydell , Richard Henderson Subject: [PATCH v8.0.1 15/36] target/arm: Define and use new load_cpu_field_low32() Date: Wed, 17 May 2023 11:00:35 +0300 Message-Id: <20230517080056.3623993-15-mjt@msgid.tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: <<20230517073442.3622973-0-mjt@msgid.tls.msk.ru> References: <20230517073442.3622973-0-mjt@msgid.tls.msk.ru> MIME-Version: 1.0 Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Peter Maydell In several places in the 32-bit Arm translate.c, we try to use load_cpu_field() to load from a CPUARMState field into a TCGv_i32 where the field is actually 64-bit. This works on little-endian hosts, but gives the wrong half of the register on big-endian. Add a new load_cpu_field_low32() which loads the low 32 bits of a 64-bit field into a TCGv_i32. The new macro includes a compile-time check against accidentally using it on a field of the wrong size. Use it to fix the two places in the code where we were using load_cpu_field() on a 64-bit field. This fixes a bug where on big-endian hosts the guest would crash after executing an ERET instruction, and a more corner case one where some UNDEFs for attempted accesses to MSR banked registers from Secure EL1 might go to the wrong EL. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230424153909.1419369-2-peter.maydell@linaro.org (cherry picked from commit 7f3a3d3dc433dc06c0adb480729af80f9c8e3739) Signed-off-by: Michael Tokarev --- target/arm/tcg/translate.c | 4 ++-- target/arm/translate-a32.h | 7 +++++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 3c8401e908..7468476724 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -2816,7 +2816,7 @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn, if (arm_dc_feature(s, ARM_FEATURE_AARCH64) && dc_isar_feature(aa64_sel2, s)) { /* Target EL is EL<3 minus SCR_EL3.EEL2> */ - tcg_el = load_cpu_field(cp15.scr_el3); + tcg_el = load_cpu_field_low32(cp15.scr_el3); tcg_gen_sextract_i32(tcg_el, tcg_el, ctz32(SCR_EEL2), 1); tcg_gen_addi_i32(tcg_el, tcg_el, 3); } else { @@ -6396,7 +6396,7 @@ static bool trans_ERET(DisasContext *s, arg_ERET *a) } if (s->current_el == 2) { /* ERET from Hyp uses ELR_Hyp, not LR */ - tmp = load_cpu_field(elr_el[2]); + tmp = load_cpu_field_low32(elr_el[2]); } else { tmp = load_reg(s, 14); } diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h index 5339c22f1e..99eea85fa8 100644 --- a/target/arm/translate-a32.h +++ b/target/arm/translate-a32.h @@ -61,6 +61,13 @@ static inline TCGv_i32 load_cpu_offset(int offset) #define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name)) +/* Load from the low half of a 64-bit field to a TCGv_i32 */ +#define load_cpu_field_low32(name) \ + ({ \ + QEMU_BUILD_BUG_ON(sizeof_field(CPUARMState, name) != 8); \ + load_cpu_offset(offsetoflow32(CPUARMState, name)); \ + }) + void store_cpu_offset(TCGv_i32 var, int offset, int size); #define store_cpu_field(var, name) \ From patchwork Wed May 17 08:00:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Tokarev X-Patchwork-Id: 682904 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp230537wrt; Wed, 17 May 2023 01:09:39 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6+rpWNaDq/M6BYSWHphPliSuDSn0mLHskb4GdzPQEulVMKrarm405R7r01vI2psVa9B3fm X-Received: by 2002:a05:622a:1d6:b0:3f4:e7e4:177b with SMTP id t22-20020a05622a01d600b003f4e7e4177bmr36841111qtw.18.1684310978935; Wed, 17 May 2023 01:09:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684310978; cv=none; d=google.com; s=arc-20160816; b=L8aoj5eesdvA9GetQVUI9dyygrWa9eCeXGjo3KTUvMppwLE8Kym0SS5WwHZp5KZ/a9 Yx7mZNZ+0AeJsq/aOb01MnD+myZyDj/SdONhgIXcMryLx7YM5gw58irVX0U4OUynK0sY t/10/tg1yRqeYzI04WRu/2bgVdOcCvmjO12VOdHPHt9NUvSpRN0hxnaEhrMdZuml8Rzu Ccem8rYo8XvTCEOVEWqkgFJI5Hdan7MEV9QKGJkT76SHNUKlGu8C5vicxyr4cuvmcmlE TAEp1IJrU95jCQJCNMnbkgVpdt5twnPIrHdTYI44YW/fruExEdlD7ne7BENFlD9mUNlf sQrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=st4YeFb46gn8GbtUKGsA7Jgn8+LUCCZa3DkET/ODoYs=; b=sNF8vb/YJpeRhqJ+UiB9i/CGu+2husHStH+ThgCt7HpezVGPZATX7K40weOgO8jz52 qQwH6/bv3q6GC4md7YhOzAHyVlYkg3/7pAf87q7D0DEFfgZQUoUtddQ+p3lq+TYxpqR1 w5fa45m5YQ5OKqLjscnxI0HGZQl7k6ZDD/YvZ3kgrZb/j8JHFTT3CIcPwrdoGu1DZX8+ eiOUiaDTJYcPjcE/h7A5hVdUzx8oITmixC6yH0HU7hF/LX5MRSG/xhO+yttPI4TQEJPP og3x8uo0AnOXgB85fA2NfKRuFqvqihuUjZ0/Xn9XjSw3YRAUXOUCuB7ZGPrll0D+WMn6 wKBg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id z21-20020ac87f95000000b003f5142b1776si5992832qtj.799.2023.05.17.01.09.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 17 May 2023 01:09:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pzC6g-0002h3-TJ; Wed, 17 May 2023 04:01:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzC6S-00025C-K0; Wed, 17 May 2023 04:01:46 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzC6L-0000ar-BE; Wed, 17 May 2023 04:01:44 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 344176759; Wed, 17 May 2023 11:00:59 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 9D9A15E11; Wed, 17 May 2023 11:00:58 +0300 (MSK) Received: (nullmailer pid 3624126 invoked by uid 1000); Wed, 17 May 2023 08:00:56 -0000 From: Michael Tokarev To: qemu-stable@nongnu.org Cc: qemu-devel@nongnu.org, Peter Maydell , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Subject: [PATCH v8.0.1 16/36] hw/sd/allwinner-sdhost: Correctly byteswap descriptor fields Date: Wed, 17 May 2023 11:00:36 +0300 Message-Id: <20230517080056.3623993-16-mjt@msgid.tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: <<20230517073442.3622973-0-mjt@msgid.tls.msk.ru> References: <20230517073442.3622973-0-mjt@msgid.tls.msk.ru> MIME-Version: 1.0 Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Peter Maydell In allwinner_sdhost_process_desc() we just read directly from guest memory into a host TransferDescriptor struct and back. This only works on little-endian hosts. Abstract the reading and writing of descriptors into functions that handle the byte-swapping so that TransferDescriptor structs as seen by the rest of the code are always in host-order. This fixes a failure of one of the avocado tests on s390. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Thomas Huth Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Message-id: 20230424165053.1428857-2-peter.maydell@linaro.org (cherry picked from commit 3e20d90824c262de6887aa1bc52af94db69e4310) Signed-off-by: Michael Tokarev --- hw/sd/allwinner-sdhost.c | 31 ++++++++++++++++++++++++++----- 1 file changed, 26 insertions(+), 5 deletions(-) diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c index 51e5e90830..92a0f42708 100644 --- a/hw/sd/allwinner-sdhost.c +++ b/hw/sd/allwinner-sdhost.c @@ -302,6 +302,30 @@ static void allwinner_sdhost_auto_stop(AwSdHostState *s) } } +static void read_descriptor(AwSdHostState *s, hwaddr desc_addr, + TransferDescriptor *desc) +{ + uint32_t desc_words[4]; + dma_memory_read(&s->dma_as, desc_addr, &desc_words, sizeof(desc_words), + MEMTXATTRS_UNSPECIFIED); + desc->status = le32_to_cpu(desc_words[0]); + desc->size = le32_to_cpu(desc_words[1]); + desc->addr = le32_to_cpu(desc_words[2]); + desc->next = le32_to_cpu(desc_words[3]); +} + +static void write_descriptor(AwSdHostState *s, hwaddr desc_addr, + const TransferDescriptor *desc) +{ + uint32_t desc_words[4]; + desc_words[0] = cpu_to_le32(desc->status); + desc_words[1] = cpu_to_le32(desc->size); + desc_words[2] = cpu_to_le32(desc->addr); + desc_words[3] = cpu_to_le32(desc->next); + dma_memory_write(&s->dma_as, desc_addr, &desc_words, sizeof(desc_words), + MEMTXATTRS_UNSPECIFIED); +} + static uint32_t allwinner_sdhost_process_desc(AwSdHostState *s, hwaddr desc_addr, TransferDescriptor *desc, @@ -312,9 +336,7 @@ static uint32_t allwinner_sdhost_process_desc(AwSdHostState *s, uint32_t num_bytes = max_bytes; uint8_t buf[1024]; - /* Read descriptor */ - dma_memory_read(&s->dma_as, desc_addr, desc, sizeof(*desc), - MEMTXATTRS_UNSPECIFIED); + read_descriptor(s, desc_addr, desc); if (desc->size == 0) { desc->size = klass->max_desc_size; } else if (desc->size > klass->max_desc_size) { @@ -356,8 +378,7 @@ static uint32_t allwinner_sdhost_process_desc(AwSdHostState *s, /* Clear hold flag and flush descriptor */ desc->status &= ~DESC_STATUS_HOLD; - dma_memory_write(&s->dma_as, desc_addr, desc, sizeof(*desc), - MEMTXATTRS_UNSPECIFIED); + write_descriptor(s, desc_addr, desc); return num_done; } From patchwork Wed May 17 08:00:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Tokarev X-Patchwork-Id: 682900 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp229849wrt; Wed, 17 May 2023 01:07:38 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5ffECGAjDUZf8m4FjchE6vm2YBEFG5ejveNNKmOjY+bcYnH4v3NhNs6AVhJ3cGB9toY4vN X-Received: by 2002:ac8:7f4a:0:b0:3f4:ffa5:6570 with SMTP id g10-20020ac87f4a000000b003f4ffa56570mr30822482qtk.35.1684310858331; Wed, 17 May 2023 01:07:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684310858; cv=none; d=google.com; s=arc-20160816; b=KsVZyiCfluZReih20wTodAhp2qbVBPsDxBkaLzGdD/EzAZSY38WFVpNUJ5SjRvQ70s 1JesHEOrnpRPgGtBxC/CMpwAhoKPZDfcL0445gRDZyiF9Hp/b/fGrPttfM/xS+eSqk6c 3Beb+Ya698tMaym+ftf6osrU+RDQCkd3EunjRF5ZwOKdfS4WHEeMsEUWlkVkV88swmHZ nF6v/5lLD3Oo4wEmVzLo0FHMEbSuKWA77Mlb+iVin1XTUdhT+ApmyZTx0aJbOfEe0Rzn SxADOvUuYGN+y4wglaERbW5KF0F8WOjNJwnM7zk9A96I31/Lv01NWbnI7KNS5p1AIkYT ToSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=nmYjWVdsdWRP9AkrP7vrJgAdTmkQvwdd4ABhceVdbWk=; b=imdDpmHTqMgatKRtViIqVdvS/auxWD93gjBjJ8IOLy8eldqxp/H3QibHsTLOBV8cv4 Kh9T0clSi77BmDLd+fKfwEY9BV7WIpHgwWV4YOx6o2sdTseA4g2i3D+8kJg0dnEXlff7 qdkW2sX0IHxH8QtvzgrV8BM3baW5909jjWItuDHR5BmdqF6tkksbYjCdt0GDSDrsvf9o EdyupivM7Ng7qCzVjfQ36dITduG4V18XTujORnaYmQ/dkNviVzqq22BoGFGAr3WK3D95 iOp1PVKvZ3WP81KteZ10cIi9V4ZJkvxDVTB12C42edVO8OjQOdD3ZNNRqfM0Srnjhv70 s6Eg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h1-20020a37c441000000b0074dffa24a66si1023363qkm.170.2023.05.17.01.07.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 17 May 2023 01:07:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pzC6h-0002i0-AI; Wed, 17 May 2023 04:01:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzC6U-0002Bw-Iy; Wed, 17 May 2023 04:01:48 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzC6L-0000au-Cl; Wed, 17 May 2023 04:01:46 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 529ED675A; Wed, 17 May 2023 11:00:59 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id D54E95E12; Wed, 17 May 2023 11:00:58 +0300 (MSK) Received: (nullmailer pid 3624129 invoked by uid 1000); Wed, 17 May 2023 08:00:56 -0000 From: Michael Tokarev To: qemu-stable@nongnu.org Cc: qemu-devel@nongnu.org, Peter Maydell , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Subject: [PATCH v8.0.1 17/36] hw/net/allwinner-sun8i-emac: Correctly byteswap descriptor fields Date: Wed, 17 May 2023 11:00:37 +0300 Message-Id: <20230517080056.3623993-17-mjt@msgid.tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: <<20230517073442.3622973-0-mjt@msgid.tls.msk.ru> References: <20230517073442.3622973-0-mjt@msgid.tls.msk.ru> MIME-Version: 1.0 Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Peter Maydell In allwinner-sun8i-emac we just read directly from guest memory into a host FrameDescriptor struct and back. This only works on little-endian hosts. Reading and writing of descriptors is already abstracted into functions; make those functions also handle the byte-swapping so that TransferDescriptor structs as seen by the rest of the code are always in host-order, and fix two places that were doing ad-hoc descriptor reading without using the functions. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Thomas Huth Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Message-id: 20230424165053.1428857-3-peter.maydell@linaro.org (cherry picked from commit a4ae17e5ec512862bf73e40dfbb1e7db71f2c1e7) Signed-off-by: Michael Tokarev --- hw/net/allwinner-sun8i-emac.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/hw/net/allwinner-sun8i-emac.c b/hw/net/allwinner-sun8i-emac.c index b861d8ff35..fac4405f45 100644 --- a/hw/net/allwinner-sun8i-emac.c +++ b/hw/net/allwinner-sun8i-emac.c @@ -350,8 +350,13 @@ static void allwinner_sun8i_emac_get_desc(AwSun8iEmacState *s, FrameDescriptor *desc, uint32_t phys_addr) { - dma_memory_read(&s->dma_as, phys_addr, desc, sizeof(*desc), + uint32_t desc_words[4]; + dma_memory_read(&s->dma_as, phys_addr, &desc_words, sizeof(desc_words), MEMTXATTRS_UNSPECIFIED); + desc->status = le32_to_cpu(desc_words[0]); + desc->status2 = le32_to_cpu(desc_words[1]); + desc->addr = le32_to_cpu(desc_words[2]); + desc->next = le32_to_cpu(desc_words[3]); } static uint32_t allwinner_sun8i_emac_next_desc(AwSun8iEmacState *s, @@ -400,10 +405,15 @@ static uint32_t allwinner_sun8i_emac_tx_desc(AwSun8iEmacState *s, } static void allwinner_sun8i_emac_flush_desc(AwSun8iEmacState *s, - FrameDescriptor *desc, + const FrameDescriptor *desc, uint32_t phys_addr) { - dma_memory_write(&s->dma_as, phys_addr, desc, sizeof(*desc), + uint32_t desc_words[4]; + desc_words[0] = cpu_to_le32(desc->status); + desc_words[1] = cpu_to_le32(desc->status2); + desc_words[2] = cpu_to_le32(desc->addr); + desc_words[3] = cpu_to_le32(desc->next); + dma_memory_write(&s->dma_as, phys_addr, &desc_words, sizeof(desc_words), MEMTXATTRS_UNSPECIFIED); } @@ -638,8 +648,7 @@ static uint64_t allwinner_sun8i_emac_read(void *opaque, hwaddr offset, break; case REG_TX_CUR_BUF: /* Transmit Current Buffer */ if (s->tx_desc_curr != 0) { - dma_memory_read(&s->dma_as, s->tx_desc_curr, &desc, sizeof(desc), - MEMTXATTRS_UNSPECIFIED); + allwinner_sun8i_emac_get_desc(s, &desc, s->tx_desc_curr); value = desc.addr; } else { value = 0; @@ -652,8 +661,7 @@ static uint64_t allwinner_sun8i_emac_read(void *opaque, hwaddr offset, break; case REG_RX_CUR_BUF: /* Receive Current Buffer */ if (s->rx_desc_curr != 0) { - dma_memory_read(&s->dma_as, s->rx_desc_curr, &desc, sizeof(desc), - MEMTXATTRS_UNSPECIFIED); + allwinner_sun8i_emac_get_desc(s, &desc, s->rx_desc_curr); value = desc.addr; } else { value = 0; From patchwork Wed May 17 08:00:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Tokarev X-Patchwork-Id: 682899 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp229652wrt; Wed, 17 May 2023 01:07:04 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5mJ4y6DRoHVWY20qJQr51arCh9rtakJbOqu7pSmOcrVD+dOoPogJDLTig/wSBYyoIlT6NC X-Received: by 2002:a05:622a:1455:b0:3f3:9013:5839 with SMTP id v21-20020a05622a145500b003f390135839mr2239786qtx.23.1684310824375; Wed, 17 May 2023 01:07:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684310824; cv=none; d=google.com; s=arc-20160816; b=IN2NhuMVyAPp+Yl8Xf1SoyVlak/46mhwtw7daDBFormg34/9vQltyYH7se+sECu4fw w2uQdKSUHSNj8YvPA+dGfAxq0GBVtTkI8d88r0CQWJm9NvJQeoqoN3xaRjxnEUJU7ugO 3r1AsAUVmbx9kgbrRL1KLiuh6tMH8Tyu3mkF2wivab1wHkyWfX4TAAf6wBPccvAUSPwb ntVGjI7ipL7QZb+Z39vPvVr1jPgQjvazrTraRW9+ufltpGKiRMJcA3UjH4SOnXLRsel6 pmUhlYbf/nXA3W0bpyX3fC7kbHFCwl1eoyT1q4wVh1SQuNDJWy9qz+XHzdzfZK36Si1V ilFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=vPqRupbs22Sh3V43PtNGIjpixBlVvIdwr/MZVmu8Qn0=; b=b1ncHY+BW6T+O5p8E0ZM5NLYsPw+IBRLIiTvwi88Ju3kxRbklhheBPfTkZTYNiTV38 hKapC1E2cb4PYWuij28VcQHE2eRlddHBYwdGYhgvIEDT7ORkjJ25JdbKe4EjHwDD33pr NdfVpZxsbj+4Ii465yQi0MUcbgWRlUpxLRg1TNu+GqFku4nwm8dh30k8idIl4qKr13pw N+Kj+n8dn5lroRdLl3/iG+oZK/K2Y+YJFwBrdOChgXijwM555vcjmTJxpWqcP5+nS1i/ c2DowNA8B0nisFxDfNj0FZTaeVVbvmuMfF6np9wKbvTcXHmwJu5jole7umZ8CRkiO4iq u5Bw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d21-20020a05622a15d500b003e398af5dcdsi12021130qty.599.2023.05.17.01.07.04 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 17 May 2023 01:07:04 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pzC6k-0002my-UX; Wed, 17 May 2023 04:02:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzC6d-0002cw-Oi; Wed, 17 May 2023 04:01:55 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzC6b-0000ko-QF; Wed, 17 May 2023 04:01:55 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id BE56C6765; Wed, 17 May 2023 11:01:00 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 4D94C5E1D; Wed, 17 May 2023 11:01:00 +0300 (MSK) Received: (nullmailer pid 3624163 invoked by uid 1000); Wed, 17 May 2023 08:00:56 -0000 From: Michael Tokarev To: qemu-stable@nongnu.org Cc: qemu-devel@nongnu.org, Richard Henderson , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v8.0.1 28/36] accel/tcg: Fix atomic_mmu_lookup for reads Date: Wed, 17 May 2023 11:00:48 +0300 Message-Id: <20230517080056.3623993-28-mjt@msgid.tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: <<20230517073442.3622973-0-mjt@msgid.tls.msk.ru> References: <20230517073442.3622973-0-mjt@msgid.tls.msk.ru> MIME-Version: 1.0 Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson A copy-paste bug had us looking at the victim cache for writes. Cc: qemu-stable@nongnu.org Reported-by: Peter Maydell Signed-off-by: Richard Henderson Fixes: 08dff435e2 ("tcg: Probe the proper permissions for atomic ops") Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Message-Id: <20230505204049.352469-1-richard.henderson@linaro.org> (cherry picked from commit 8c313254e61ed47a1bf4a2db714b25cdd94fbcce) Signed-off-by: Michael Tokarev --- accel/tcg/cputlb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index e984a98dc4..145fba45b2 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1830,7 +1830,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, } else /* if (prot & PAGE_READ) */ { tlb_addr = tlbe->addr_read; if (!tlb_hit(tlb_addr, addr)) { - if (!VICTIM_TLB_HIT(addr_write, addr)) { + if (!VICTIM_TLB_HIT(addr_read, addr)) { tlb_fill(env_cpu(env), addr, size, MMU_DATA_LOAD, mmu_idx, retaddr); index = tlb_index(env, mmu_idx, addr); From patchwork Wed May 17 08:00:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Tokarev X-Patchwork-Id: 682906 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp230987wrt; Wed, 17 May 2023 01:10:43 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5yvVxu1paQWQhR5/dgiTZ/lvcfGFERVQKj9ZGFwkYZu26kFUy94X7voySWzA7BD17UZvgC X-Received: by 2002:ac8:5b0a:0:b0:3f5:3d3d:d1b5 with SMTP id m10-20020ac85b0a000000b003f53d3dd1b5mr10744153qtw.27.1684311042790; Wed, 17 May 2023 01:10:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684311042; cv=none; d=google.com; s=arc-20160816; b=uhNcvi8SZY3nE+QO3ugZIvaico4UUVrT67UTWIf7B3A6C+wZNbO2XX6Z30m2WI8+UM 55yjfeaxu+8YjS60rAci/0RZA/H2AY7uZN5TKnOQrOWR8Y+4r0QWP7NyNS/li/RJouGv +V7Q5Kz36oBfBGUa12GSm9WilK/63duOowDPtD5fK39k99scwcTil8W3ar9OtFOiSEiO +ghxLdvOjRztP1wCB9k7dOmhGfkHZuxfvd9CSJLpgGkt2t6ezLhQ5UEBb7Lzg1+KzX33 xyDk0JwrpMrTRyidy1Uiz8obJDpNWTT+3iuvc3x166DmKCpd24ehImOdUi/GPsYFxRkG MWrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=Z1Ny1nazzYrm3i/IkafocB+A2yRkG2CLtlqkRiHkwo4=; b=H5y4UAah63Bwv9u9bP0Rr4vy80Wt/xnlXBg4BHZhpv2aA47XOmwG2X736xyUcMM90P jHhNDmKXJ/adFe3p0aTw9WtOW8m1R+jIyQs+NZfQXSIFvN6F78TXnmeAtp3HJmuRYVTq 3x/XgP1YzK1c8K8yQRY4BHP/34QfCRAH7WQ1t2Rmk5h+xO3ESrMbEJzCUvSUQ9/4cA9z 4YUvhVIMAprtApkKw+slYx0AS6vFzAPKiZTilF3Dl0sl/Jj8bfn+rzN/rquEoC6P8slg KoYDLuv0BQ34N8xW3/8sScKL9LqsmXhnSjoS2MmI778Ac/u1GfE/iVxyt+1GeMKcmopy 7SBw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f18-20020ac87f12000000b003f3940c6a77si12537496qtk.10.2023.05.17.01.10.42 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 17 May 2023 01:10:42 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pzC6p-0002tB-VB; Wed, 17 May 2023 04:02:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzC6g-0002hK-TU; Wed, 17 May 2023 04:01:58 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzC6d-0000lD-2P; Wed, 17 May 2023 04:01:58 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id D8FA16766; Wed, 17 May 2023 11:01:00 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 6B02C5E1E; Wed, 17 May 2023 11:01:00 +0300 (MSK) Received: (nullmailer pid 3624166 invoked by uid 1000); Wed, 17 May 2023 08:00:56 -0000 From: Michael Tokarev To: qemu-stable@nongnu.org Cc: qemu-devel@nongnu.org, Peter Maydell , Richard Henderson Subject: [PATCH v8.0.1 29/36] target/arm: Fix handling of SW and NSW bits for stage 2 walks Date: Wed, 17 May 2023 11:00:49 +0300 Message-Id: <20230517080056.3623993-29-mjt@msgid.tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: <<20230517073442.3622973-0-mjt@msgid.tls.msk.ru> References: <20230517073442.3622973-0-mjt@msgid.tls.msk.ru> MIME-Version: 1.0 Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Peter Maydell We currently don't correctly handle the VSTCR_EL2.SW and VTCR_EL2.NSW configuration bits. These allow configuration of whether the stage 2 page table walks for Secure IPA and NonSecure IPA should do their descriptor reads from Secure or NonSecure physical addresses. (This is separate from how the translation table base address and other parameters are set: an NS IPA always uses VTTBR_EL2 and VTCR_EL2 for its base address and walk parameters, regardless of the NSW bit, and similarly for Secure.) Provide a new function ptw_idx_for_stage_2() which returns the MMU index to use for descriptor reads, and use it to set up the .in_ptw_idx wherever we call get_phys_addr_lpae(). For a stage 2 walk, wherever we call get_phys_addr_lpae(): * .in_ptw_idx should be ptw_idx_for_stage_2() of the .in_mmu_idx * .in_secure should be true if .in_mmu_idx is Stage2_S This allows us to correct S1_ptw_translate() so that it consistently always sets its (out_secure, out_phys) to the result it gets from the S2 walk (either by calling get_phys_addr_lpae() or by TLB lookup). This makes better conceptual sense because the S2 walk should return us an (address space, address) tuple, not an address that we then randomly assign to S or NS. Our previous handling of SW and NSW was broken, so guest code trying to use these bits to put the s2 page tables in the "other" address space wouldn't work correctly. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1600 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230504135425.2748672-3-peter.maydell@linaro.org (cherry picked from commit fcc0b0418fff655f20fd0cf86a1bbdc41fd2e7c6) Signed-off-by: Michael Tokarev --- target/arm/ptw.c | 76 ++++++++++++++++++++++++++++++++---------------- 1 file changed, 51 insertions(+), 25 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 6d72950a79..00399a2e9c 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -103,6 +103,37 @@ ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) return stage_1_mmu_idx(arm_mmu_idx(env)); } +/* + * Return where we should do ptw loads from for a stage 2 walk. + * This depends on whether the address we are looking up is a + * Secure IPA or a NonSecure IPA, which we know from whether this is + * Stage2 or Stage2_S. + * If this is the Secure EL1&0 regime we need to check the NSW and SW bits. + */ +static ARMMMUIdx ptw_idx_for_stage_2(CPUARMState *env, ARMMMUIdx stage2idx) +{ + bool s2walk_secure; + + /* + * We're OK to check the current state of the CPU here because + * (1) we always invalidate all TLBs when the SCR_EL3.NS bit changes + * (2) there's no way to do a lookup that cares about Stage 2 for a + * different security state to the current one for AArch64, and AArch32 + * never has a secure EL2. (AArch32 ATS12NSO[UP][RW] allow EL3 to do + * an NS stage 1+2 lookup while the NS bit is 0.) + */ + if (!arm_is_secure_below_el3(env) || !arm_el_is_aa64(env, 3)) { + return ARMMMUIdx_Phys_NS; + } + if (stage2idx == ARMMMUIdx_Stage2_S) { + s2walk_secure = !(env->cp15.vstcr_el2 & VSTCR_SW); + } else { + s2walk_secure = !(env->cp15.vtcr_el2 & VTCR_NSW); + } + return s2walk_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; + +} + static bool regime_translation_big_endian(CPUARMState *env, ARMMMUIdx mmu_idx) { return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0; @@ -220,7 +251,6 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, ARMMMUIdx mmu_idx = ptw->in_mmu_idx; ARMMMUIdx s2_mmu_idx = ptw->in_ptw_idx; uint8_t pte_attrs; - bool pte_secure; ptw->out_virt = addr; @@ -232,8 +262,8 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, if (regime_is_stage2(s2_mmu_idx)) { S1Translate s2ptw = { .in_mmu_idx = s2_mmu_idx, - .in_ptw_idx = is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS, - .in_secure = is_secure, + .in_ptw_idx = ptw_idx_for_stage_2(env, s2_mmu_idx), + .in_secure = s2_mmu_idx == ARMMMUIdx_Stage2_S, .in_debug = true, }; GetPhysAddrResult s2 = { }; @@ -244,12 +274,12 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, } ptw->out_phys = s2.f.phys_addr; pte_attrs = s2.cacheattrs.attrs; - pte_secure = s2.f.attrs.secure; + ptw->out_secure = s2.f.attrs.secure; } else { /* Regime is physical. */ ptw->out_phys = addr; pte_attrs = 0; - pte_secure = is_secure; + ptw->out_secure = s2_mmu_idx == ARMMMUIdx_Phys_S; } ptw->out_host = NULL; ptw->out_rw = false; @@ -270,7 +300,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, ptw->out_phys = full->phys_addr | (addr & ~TARGET_PAGE_MASK); ptw->out_rw = full->prot & PAGE_WRITE; pte_attrs = full->pte_attrs; - pte_secure = full->attrs.secure; + ptw->out_secure = full->attrs.secure; #else g_assert_not_reached(); #endif @@ -293,11 +323,6 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, } } - /* Check if page table walk is to secure or non-secure PA space. */ - ptw->out_secure = (is_secure - && !(pte_secure - ? env->cp15.vstcr_el2 & VSTCR_SW - : env->cp15.vtcr_el2 & VTCR_NSW)); ptw->out_be = regime_translation_big_endian(env, mmu_idx); return true; @@ -2713,7 +2738,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, hwaddr ipa; int s1_prot, s1_lgpgsz; bool is_secure = ptw->in_secure; - bool ret, ipa_secure, s2walk_secure; + bool ret, ipa_secure; ARMCacheAttrs cacheattrs1; bool is_el0; uint64_t hcr; @@ -2727,20 +2752,11 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, ipa = result->f.phys_addr; ipa_secure = result->f.attrs.secure; - if (is_secure) { - /* Select TCR based on the NS bit from the S1 walk. */ - s2walk_secure = !(ipa_secure - ? env->cp15.vstcr_el2 & VSTCR_SW - : env->cp15.vtcr_el2 & VTCR_NSW); - } else { - assert(!ipa_secure); - s2walk_secure = false; - } is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0; - ptw->in_mmu_idx = s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; - ptw->in_ptw_idx = s2walk_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; - ptw->in_secure = s2walk_secure; + ptw->in_mmu_idx = ipa_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; + ptw->in_secure = ipa_secure; + ptw->in_ptw_idx = ptw_idx_for_stage_2(env, ptw->in_mmu_idx); /* * S1 is done, now do S2 translation. @@ -2848,6 +2864,16 @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, ptw->in_ptw_idx = is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; break; + case ARMMMUIdx_Stage2: + case ARMMMUIdx_Stage2_S: + /* + * Second stage lookup uses physical for ptw; whether this is S or + * NS may depend on the SW/NSW bits if this is a stage 2 lookup for + * the Secure EL2&0 regime. + */ + ptw->in_ptw_idx = ptw_idx_for_stage_2(env, mmu_idx); + break; + case ARMMMUIdx_E10_0: s1_mmu_idx = ARMMMUIdx_Stage1_E0; goto do_twostage; @@ -2871,7 +2897,7 @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, /* fall through */ default: - /* Single stage and second stage uses physical for ptw. */ + /* Single stage uses physical for ptw. */ ptw->in_ptw_idx = is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; break; } From patchwork Wed May 17 08:00:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Tokarev X-Patchwork-Id: 682907 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp231046wrt; Wed, 17 May 2023 01:10:54 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4bvubGRUfuJh40Z3snuj2VRVIkYEf5gcZGTqjHTDeonK2M9G7NKQr1hUNp8T0/r+liI1yW X-Received: by 2002:ad4:5baa:0:b0:623:4ca9:5b25 with SMTP id 10-20020ad45baa000000b006234ca95b25mr19068822qvq.31.1684311054335; Wed, 17 May 2023 01:10:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684311054; cv=none; d=google.com; s=arc-20160816; b=SWCYiag9CKLoJC0COWg0RLgU1avDvAdhMhzC2vXCQRxam0RZ0YzP3zSlqJfMBmC2fs 26uhRd7zCClCbhR7Q1eiYqOgxGKVR+sUeE1sOt89dv1m1o0AOF37kuvibEpz/w1I4YXY 5UvCUcNX47OLrbkfIt7Cj9W+CfMZdfqBK6fMEhBTko8ICp8jmluQromTG8jwfYwSRhEr 0Rxqd0i8ZBEDUgLEQHc35zboGrzz9UTw3vko3Y7FUvNKx+uvlOhUeV0T0nXMyyqEf1XR dZB7fBZ1rqH7QPaSMHqZaPoFDmEjqkbu8YPcQ2PP1T7fwZ5huw/gScpQHFp9rE9aYt4b S2Mg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=pyIKR+Sxjb/8RbEjcoEwFf53Yb0wH2PhssiGeiA7Ucg=; b=G1HhG+sjBlOhKGSx4wSxhvsGAwjDbIO3oNoQVOfxyviBXuX5DbKlN4sBPKNcnjAiqt V+DQuOvT5uLedXoPqKPOll3NtTTPBKfTjTlNtXXpK+jRqQRMWsxcCBOBG+H45DkS8rWN pXwNRTSl+WmFb9bigVHD3RfZEE0GJRvn5vjH2E8UYni46EdGCOuditLfgzdkxGWAqR3s L0DLe4n4lE+ZTx9OQQWtQEb33ie9lUJeKgK2xjsY2R0fqC7wZ622qCyM5irs+z5+Wh7j lby5iSwTwoaQiWeGh1VuE0ja1+R30//uk3OmsBjEAiIoI6+ae3XwKAh4saROoHxkkM8b LiJA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id kk22-20020a056214509600b0062117ba718esi12531506qvb.560.2023.05.17.01.10.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 17 May 2023 01:10:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pzC6n-0002nz-Hn; Wed, 17 May 2023 04:02:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzC6g-0002h6-Nl; Wed, 17 May 2023 04:01:58 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzC6d-0000lC-0W; Wed, 17 May 2023 04:01:58 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id F13C36767; Wed, 17 May 2023 11:01:00 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 855B45E1F; Wed, 17 May 2023 11:01:00 +0300 (MSK) Received: (nullmailer pid 3624169 invoked by uid 1000); Wed, 17 May 2023 08:00:56 -0000 From: Michael Tokarev To: qemu-stable@nongnu.org Cc: qemu-devel@nongnu.org, Peter Maydell , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Subject: [PATCH v8.0.1 30/36] ui: Fix pixel colour channel order for PNG screenshots Date: Wed, 17 May 2023 11:00:50 +0300 Message-Id: <20230517080056.3623993-30-mjt@msgid.tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: <<20230517073442.3622973-0-mjt@msgid.tls.msk.ru> References: <20230517073442.3622973-0-mjt@msgid.tls.msk.ru> MIME-Version: 1.0 Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Peter Maydell When we take a PNG screenshot the ordering of the colour channels in the data is not correct, resulting in the image having weird colouring compared to the actual display. (Specifically, on a little-endian host the blue and red channels are swapped; on big-endian everything is wrong.) This happens because the pixman idea of the pixel data and the libpng idea differ. PIXMAN_a8r8g8b8 defines that pixels are 32-bit values, with A in bits 24-31, R in bits 16-23, G in bits 8-15 and B in bits 0-7. This means that on little-endian systems the bytes in memory are B G R A and on big-endian systems they are A R G B libpng, on the other hand, thinks of pixels as being a series of values for each channel, so its format PNG_COLOR_TYPE_RGB_ALPHA always wants bytes in the order R G B A This isn't the same as the pixman order for either big or little endian hosts. The alpha channel is also unnecessary bulk in the output PNG file, because there is no alpha information in a screenshot. To handle the endianness issue, we already define in ui/qemu-pixman.h various PIXMAN_BE_* and PIXMAN_LE_* values that give consistent byte-order pixel channel formats. So we can use PIXMAN_BE_r8g8b8 and PNG_COLOR_TYPE_RGB, which both have an in-memory byte order of R G B and 3 bytes per pixel. (PPM format screenshots get this right; they already use the PIXMAN_BE_r8g8b8 format.) Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1622 Fixes: 9a0a119a382867 ("Added parameter to take screenshot with screendump as PNG") Signed-off-by: Peter Maydell Reviewed-by: Marc-André Lureau Message-id: 20230502135548.2451309-1-peter.maydell@linaro.org (cherry picked from commit cd22a0f520f471e3bd33bc19cf3b2fa772cdb2a8) Signed-off-by: Michael Tokarev --- ui/console.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ui/console.c b/ui/console.c index 6e8a3cdc62..e173731e20 100644 --- a/ui/console.c +++ b/ui/console.c @@ -311,7 +311,7 @@ static bool png_save(int fd, pixman_image_t *image, Error **errp) png_struct *png_ptr; png_info *info_ptr; g_autoptr(pixman_image_t) linebuf = - qemu_pixman_linebuf_create(PIXMAN_a8r8g8b8, width); + qemu_pixman_linebuf_create(PIXMAN_BE_r8g8b8, width); uint8_t *buf = (uint8_t *)pixman_image_get_data(linebuf); FILE *f = fdopen(fd, "wb"); int y; @@ -341,7 +341,7 @@ static bool png_save(int fd, pixman_image_t *image, Error **errp) png_init_io(png_ptr, f); png_set_IHDR(png_ptr, info_ptr, width, height, 8, - PNG_COLOR_TYPE_RGB_ALPHA, PNG_INTERLACE_NONE, + PNG_COLOR_TYPE_RGB, PNG_INTERLACE_NONE, PNG_COMPRESSION_TYPE_BASE, PNG_FILTER_TYPE_BASE); png_write_info(png_ptr, info_ptr); From patchwork Wed May 17 08:00:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Tokarev X-Patchwork-Id: 682902 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp230506wrt; Wed, 17 May 2023 01:09:35 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6mHVahrbxH0sJvb8x946OAx1zfpKIwQ2UvLLhke8IdjB9Or11eldStydQ+ruG4bme5PtFR X-Received: by 2002:a05:6214:e6e:b0:623:6880:a5d7 with SMTP id jz14-20020a0562140e6e00b006236880a5d7mr12494241qvb.45.1684310975189; Wed, 17 May 2023 01:09:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684310975; cv=none; d=google.com; s=arc-20160816; b=GfsqsEp85NL4Waorky2pvNi5RjIZmgYgxQsc+NLfNgk3v1iD109hMkH3BM3UKWokQA 5SdUhK8cwVNHJ9GdNbbAdnTfYPfZbmc55kjCDVFBt9yMqDpYiNO2SVhotPugV6Bay//g TUwyjTPC271P4BAyp+pwT37V8LaAeHAJMyYIOcp9J/uZz842N+g2r3xSWdJ2Ar6h6KW1 U4IW1CvDrFEH2/ButinTc3wdvDR4+maxGds9q71mNoseQUHTry4NR6wmrxkKoYECITn3 hZ5/RAVDcpnMjkPuSIbmcjE37LIPSpo32CJ1jMkA1YEbEt0a6eDLlFW4vY7js2CDVHtP UZ6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=u3mYnpOgcT7uzQIX5h1QmAiDURjziaAvc/VfR4aNcKk=; b=cEecd/0TrLA5hnJi8vkGdMpT+x9B0dhTJJbR5bPBYuX6C09vLgEsk13W3+RL91kjmD cosjdDLvIBkm9San7EYNj8hEYxjlQ9NxSCe1FKq5EdZVLaF7vm4Da2l5+lbfeDICDpSp wP3BhAW7MreEnbq0Ht9dqfxWks3YyG+BGvah2G8/O/HhYF9ILd6Seyvo8+RmxBhnwUVX K+GWSjzbLwr0ypWmBE/ePf14O4WjlF61J+Odrdj5FWdSnCIpaQKmKSUw5DHIRsK5cyx6 Y2dqwD7yV6hihTjN+4pLUiftMNNnWaSorSh9htya4ps8bLjGolipiO3toixvnPzQVI3T NyqA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id kj3-20020a056214528300b005f0f0c359c9si12868071qvb.11.2023.05.17.01.09.35 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 17 May 2023 01:09:35 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pzC6v-0003A4-Rx; Wed, 17 May 2023 04:02:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzC6h-0002jM-PN; Wed, 17 May 2023 04:01:59 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzC6f-0000lf-CM; Wed, 17 May 2023 04:01:59 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 19BA26768; Wed, 17 May 2023 11:01:01 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 9D8255E20; Wed, 17 May 2023 11:01:00 +0300 (MSK) Received: (nullmailer pid 3624172 invoked by uid 1000); Wed, 17 May 2023 08:00:56 -0000 From: Michael Tokarev To: qemu-stable@nongnu.org Cc: qemu-devel@nongnu.org, Peter Maydell , Richard Henderson Subject: [PATCH v8.0.1 31/36] target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check Date: Wed, 17 May 2023 11:00:51 +0300 Message-Id: <20230517080056.3623993-31-mjt@msgid.tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: <<20230517073442.3622973-0-mjt@msgid.tls.msk.ru> References: <20230517073442.3622973-0-mjt@msgid.tls.msk.ru> MIME-Version: 1.0 Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Peter Maydell In check_s2_mmu_setup() we have a check that is attempting to implement the part of AArch64.S2MinTxSZ that is specific to when EL1 is AArch32: if !s1aarch64 then // EL1 is AArch32 min_txsz = Min(min_txsz, 24); Unfortunately we got this wrong in two ways: (1) The minimum txsz corresponds to a maximum inputsize, but we got the sense of the comparison wrong and were faulting for all inputsizes less than 40 bits (2) We try to implement this as an extra check that happens after we've done the same txsz checks we would do for an AArch64 EL1, but in fact the pseudocode is *loosening* the requirements, so that txsz values that would fault for an AArch64 EL1 do not fault for AArch32 EL1, because it does Min(old_min, 24), not Max(old_min, 24). You can see this also in the text of the Arm ARM in table D8-8, which shows that where the implemented PA size is less than 40 bits an AArch32 EL1 is still OK with a configured stage2 T0SZ for a 40 bit IPA, whereas if EL1 is AArch64 then the T0SZ must be big enough to constrain the IPA to the implemented PA size. Because of part (2), we can't do this as a separate check, but have to integrate it into aa64_va_parameters(). Add a new argument to that function to indicate that EL1 is 32-bit. All the existing callsites except the one in get_phys_addr_lpae() can pass 'false', because they are either doing a lookup for a stage 1 regime or else they don't care about the tsz/tsz_oob fields. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1627 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230509092059.3176487-1-peter.maydell@linaro.org (cherry picked from commit 478dccbb99db0bf8f00537dd0b4d0de88d5cb537) Signed-off-by: Michael Tokarev --- target/arm/gdbstub64.c | 2 +- target/arm/helper.c | 15 +++++++++++++-- target/arm/internals.h | 12 +++++++++++- target/arm/ptw.c | 14 ++------------ target/arm/tcg/pauth_helper.c | 6 +++--- 5 files changed, 30 insertions(+), 19 deletions(-) diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index c1f7e8c934..d7b79a6589 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -233,7 +233,7 @@ int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg) ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); ARMVAParameters param; - param = aa64_va_parameters(env, -is_high, mmu_idx, is_data); + param = aa64_va_parameters(env, -is_high, mmu_idx, is_data, false); return gdb_get_reg64(buf, pauth_ptr_mask(param)); } default: diff --git a/target/arm/helper.c b/target/arm/helper.c index 2297626bfb..0b7fd2e7e6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4904,7 +4904,7 @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, unsigned int page_size_granule, page_shift, num, scale, exponent; /* Extract one bit to represent the va selector in use. */ uint64_t select = sextract64(value, 36, 1); - ARMVAParameters param = aa64_va_parameters(env, select, mmuidx, true); + ARMVAParameters param = aa64_va_parameters(env, select, mmuidx, true, false); TLBIRange ret = { }; ARMGranuleSize gran; @@ -11193,7 +11193,8 @@ static ARMGranuleSize sanitize_gran_size(ARMCPU *cpu, ARMGranuleSize gran, } ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, - ARMMMUIdx mmu_idx, bool data) + ARMMMUIdx mmu_idx, bool data, + bool el1_is_aa32) { uint64_t tcr = regime_tcr(env, mmu_idx); bool epd, hpd, tsz_oob, ds, ha, hd; @@ -11289,6 +11290,16 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, } } + if (stage2 && el1_is_aa32) { + /* + * For AArch32 EL1 the min txsz (and thus max IPA size) requirements + * are loosened: a configured IPA of 40 bits is permitted even if + * the implemented PA is less than that (and so a 40 bit IPA would + * fault for an AArch64 EL1). See R_DTLMN. + */ + min_tsz = MIN(min_tsz, 24); + } + if (tsz > max_tsz) { tsz = max_tsz; tsz_oob = true; diff --git a/target/arm/internals.h b/target/arm/internals.h index c2c70d5918..f82b3db411 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1091,8 +1091,18 @@ typedef struct ARMVAParameters { ARMGranuleSize gran : 2; } ARMVAParameters; +/** + * aa64_va_parameters: Return parameters for an AArch64 virtual address + * @env: CPU + * @va: virtual address to look up + * @mmu_idx: determines translation regime to use + * @data: true if this is a data access + * @el1_is_aa32: true if we are asking about stage 2 when EL1 is AArch32 + * (ignored if @mmu_idx is for a stage 1 regime; only affects tsz/tsz_oob) + */ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, - ARMMMUIdx mmu_idx, bool data); + ARMMMUIdx mmu_idx, bool data, + bool el1_is_aa32); int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx); int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx); diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 00399a2e9c..48f5992348 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1122,17 +1122,6 @@ static int check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint64_t tcr, sl0 = extract32(tcr, 6, 2); if (is_aa64) { - /* - * AArch64.S2InvalidTxSZ: While we checked tsz_oob near the top of - * get_phys_addr_lpae, that used aa64_va_parameters which apply - * to aarch64. If Stage1 is aarch32, the min_txsz is larger. - * See AArch64.S2MinTxSZ, where min_tsz is 24, translated to - * inputsize is 64 - 24 = 40. - */ - if (iasize < 40 && !arm_el_is_aa64(&cpu->env, 1)) { - goto fail; - } - /* * AArch64.S2InvalidSL: Interpretation of SL depends on the page size, * so interleave AArch64.S2StartLevel. @@ -1272,7 +1261,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, int ps; param = aa64_va_parameters(env, address, mmu_idx, - access_type != MMU_INST_FETCH); + access_type != MMU_INST_FETCH, + !arm_el_is_aa64(env, 1)); level = 0; /* diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index de067fa716..62af569341 100644 --- a/target/arm/tcg/pauth_helper.c +++ b/target/arm/tcg/pauth_helper.c @@ -293,7 +293,7 @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, ARMPACKey *key, bool data) { ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); - ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data); + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data, false); uint64_t pac, ext_ptr, ext, test; int bot_bit, top_bit; @@ -355,7 +355,7 @@ static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, ARMPACKey *key, bool data, int keynumber) { ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); - ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data); + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data, false); int bot_bit, top_bit; uint64_t pac, orig_ptr, test; @@ -379,7 +379,7 @@ static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, static uint64_t pauth_strip(CPUARMState *env, uint64_t ptr, bool data) { ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); - ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data); + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data, false); return pauth_original_ptr(ptr, param); } From patchwork Wed May 17 08:00:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Tokarev X-Patchwork-Id: 682910 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp231363wrt; Wed, 17 May 2023 01:11:56 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6aMNsK5l52eoo8309wwMd9tFfPfixVzKWbuVCQ/XIl/ze4nWTNMZV11g8PwIy2sbUDzWyc X-Received: by 2002:a05:622a:24b:b0:3f4:f210:959b with SMTP id c11-20020a05622a024b00b003f4f210959bmr31759014qtx.12.1684311116130; Wed, 17 May 2023 01:11:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684311116; cv=none; d=google.com; s=arc-20160816; b=AaaCsAWSMyXrGLw19w5dK9mR+F9azbQSDVB1uyVrnDBGKrVnaR2AVH0rBOPg1hmmwT RwezTsjQNFBoTLbeyoTZ11U9WwWXXMhKhk4FAgc+iG30kSUSzEE7xj8li/Dcv2Jp3XAD osqqpQG4qgY4P8Loe31fz+T2KAiFUvKiwC8Te3TdE/DrH7eCEXLuNNGJlb1CBP3P9/3n K3i9TKYQ6NhMVtLTbWt7qisTEwqN7jadBMkhranjEfnTvWN7LCtMLI6Cj74AaheSkWb1 1nd/PAhoMnhLsHN+B12oapEikFnAP/srn19Esqh2MORXhZF44bTOXNrUr6IkWNr/QZAE E2tQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=6rU50hwLLA3/v+Dtuo0MSIOKwUKr42PlhvOY/mjsj/M=; b=Agnkq/GcmTdkL50mywaRS7BZnc50UDfvFoiSoS1CHQ830GxAXN1Y80JDTaBjLRoMvX FzgbmqYUl1gOfb8Tj0FEZtT9BuL4fqNdMCvAL9RviFwLy8XPS7E8TqiQBc6w9m5PFdkY WriL0htcUUKuH0ts1ILgSCrhrd1iZOpSkFQC6KzwhyEr8jB9c6cBZdv3H+ySSmwzazzI 0+sqi5Ur20JXp7+Ho1ulxSRSS9YWjZwYQ9QR4dvmT71w2Bbuqp0dL9LflZI8oRePc98Z Q+tcpDCh4ndA71U26s2ASEB2rv3FiWh5V61dAbkUdgJZaqdibs6/pcadZyBmHGbAzxyA cfOg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t2-20020a05622a148200b003f38c9bd035si12508816qtx.782.2023.05.17.01.11.55 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 17 May 2023 01:11:56 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pzC73-0003ZK-4t; Wed, 17 May 2023 04:02:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzC6t-0002wS-Gy; Wed, 17 May 2023 04:02:11 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzC6j-0000mV-QN; Wed, 17 May 2023 04:02:11 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id B8C79676D; Wed, 17 May 2023 11:01:01 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 48C3A5E25; Wed, 17 May 2023 11:01:01 +0300 (MSK) Received: (nullmailer pid 3624187 invoked by uid 1000); Wed, 17 May 2023 08:00:56 -0000 From: Michael Tokarev To: qemu-stable@nongnu.org Cc: qemu-devel@nongnu.org, Richard Henderson Subject: [PATCH v8.0.1 36/36] tcg/i386: Set P_REXW in tcg_out_addi_ptr Date: Wed, 17 May 2023 11:00:56 +0300 Message-Id: <20230517080056.3623993-36-mjt@msgid.tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: <<20230517073442.3622973-0-mjt@msgid.tls.msk.ru> References: <20230517073442.3622973-0-mjt@msgid.tls.msk.ru> MIME-Version: 1.0 Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson The REXW bit must be set to produce a 64-bit pointer result; the bit is disabled in 32-bit mode, so we can do this unconditionally. Fixes: 7d9e1ee424b0 ("tcg/i386: Adjust assert in tcg_out_addi_ptr") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1592 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1642 Signed-off-by: Richard Henderson (cherry picked from commit 988998503bc6d8c03fbea001a0513e8372fddf28) Signed-off-by: Michael Tokarev --- tcg/i386/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 5a151fe64a..5c7c180799 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1083,7 +1083,7 @@ static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, { /* This function is only used for passing structs by reference. */ tcg_debug_assert(imm == (int32_t)imm); - tcg_out_modrm_offset(s, OPC_LEA, rd, rs, imm); + tcg_out_modrm_offset(s, OPC_LEA | P_REXW, rd, rs, imm); } static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val)