From patchwork Thu May 18 22:39:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 683489 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2FAD8C77B7D for ; Thu, 18 May 2023 22:40:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229966AbjERWkF (ORCPT ); Thu, 18 May 2023 18:40:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229767AbjERWkF (ORCPT ); Thu, 18 May 2023 18:40:05 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F296E5F for ; Thu, 18 May 2023 15:40:04 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C6F4C65185 for ; Thu, 18 May 2023 22:40:03 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0AEF2C433D2; Thu, 18 May 2023 22:40:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684449603; bh=0iyL9k1Jaj64q4oxVb6SvqoQrp+wDnfG/2eO7QyZsgU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=orfkk0dIDs0uERDJ62xbr2p1Pks35ZbpWpfqb2RMnxs2lSeqTYO6DOdWxnJhcq6HW f2UHqN1EGUfz4pXXjVX1ksqKyKUS27qJ5Si5LUG15IdA2W6OQPEVEzWm/Pl/vWvTmA 7JPP7Fm+938J1ddpX9Y7MWkNWFBeKICZkxkKU4TLxotii9dHrGQDvA0HZ7L9LkYCOe JyvnGYYdHIsiy2a+MJQjSL21bVjnOzH4TC/mGA5aSNMUceI9KD3NI7QvBw+2steXcD dLH7wA/oEAwNggef6MVjV4j91ahlSlYaRWyevbqS3qDAHKp7YFM2oeo+NAWY3pFfRb NT5fzpqjCTRCQ== From: Conor Dooley To: palmer@dabbelt.com Cc: conor@kernel.org, Conor Dooley , Paul Walmsley , Andrew Jones , Sunil V L , Yangyu Chen , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v2 1/8] RISC-V: simplify register width check in ISA string parsing Date: Thu, 18 May 2023 23:39:02 +0100 Message-Id: <20230518-resale-slashing-b84875213dc6@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230518-moneybags-rebalance-1484db493d6a@spud> References: <20230518-moneybags-rebalance-1484db493d6a@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1695; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=Aq4T7VznL+Hvu6R8rvm8DMqHfewRhohUdvadLXgTZkI=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDClpK9nzj3nY7C1eue77v6tXvRbpWN2a/Xf240tsDa+FR A1nZ8c5dJSyMIhxMMiKKbIk3u5rkVr/x2WHc89bmDmsTCBDGLg4BWAiG1kY/inJ9VxKXVcalBar cTRF68W0V1stn0tIM/1d/OZ+heN6NiOG/yW2nRcqn3Dy3Ff9LeN3U1baSu2vrtZkmxcqZ7eUvol 6xggA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Saving off the `isa` pointer to a temp variable, followed by checking if it has been incremented is a bit of an odd pattern. Perhaps it was done to avoid a funky looking if statement mixed with the ifdeffery. Now that we use IS_ENABLED() here just return from the parser as soon as we detect a mismatch between the string and the currently running kernel. Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley --- arch/riscv/kernel/cpufeature.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index cb32658180da..00df7a3a3931 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -115,7 +115,6 @@ void __init riscv_fill_hwcap(void) for_each_of_cpu_node(node) { unsigned long this_hwcap = 0; DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); - const char *temp; rc = riscv_of_processor_hartid(node, &hartid); if (rc < 0) @@ -126,14 +125,14 @@ void __init riscv_fill_hwcap(void) continue; } - temp = isa; - if (IS_ENABLED(CONFIG_32BIT) && !strncasecmp(isa, "rv32", 4)) - isa += 4; - else if (IS_ENABLED(CONFIG_64BIT) && !strncasecmp(isa, "rv64", 4)) - isa += 4; - /* The riscv,isa DT property must start with rv64 or rv32 */ - if (temp == isa) + if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32", 4)) continue; + + if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64", 4)) + continue; + + isa += 4; + bitmap_zero(this_isa, RISCV_ISA_EXT_MAX); for (; *isa; ++isa) { const char *ext = isa++; From patchwork Thu May 18 22:39:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 683488 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC563C77B7D for ; Thu, 18 May 2023 22:40:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229767AbjERWkL (ORCPT ); Thu, 18 May 2023 18:40:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50464 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229508AbjERWkK (ORCPT ); Thu, 18 May 2023 18:40:10 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D289E6E for ; Thu, 18 May 2023 15:40:09 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 06ECF652B1 for ; Thu, 18 May 2023 22:40:09 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 403D4C4339E; Thu, 18 May 2023 22:40:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684449608; bh=9JfENNR9tgTK4UNoFGHEIVOabute+dkxlDAuBXGtQfY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QB0M+oGr1rOKswGvnr1C1iL1UiQbWGKJuDv1CinMsLyBHci9L/DWgl4qPPmz+7gru PC14tSSVtgI0V3i1n2Ologpb3OByMA9+zCzftqxrWmZp951DtVr0cwfaLp6ldIMb4C /W6GKiBKQiXWBSJz6+y//8e+46ngZpoZtUQZc7qSHy67r5sEPUOC4XMWWkWrPcWTKv cHJB/MQmkIKZEarQS/ihxSdAsPkKZJoxzXaA1Om9p+0rwwBJ1+MXKUiq5S2Av2CCrl RqMxabhOM6c3b/ZdUaLSKSjxT4TR87jjMZN9vJ1omgc20TfHN/iyhns6WFfZTyAZEJ K1zdY78/BO/rg== From: Conor Dooley To: palmer@dabbelt.com Cc: conor@kernel.org, Conor Dooley , Paul Walmsley , Andrew Jones , Sunil V L , Yangyu Chen , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v2 3/8] RISC-V: split early & late of_node to hartid mapping Date: Thu, 18 May 2023 23:39:04 +0100 Message-Id: <20230518-president-stride-c199d1001579@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230518-moneybags-rebalance-1484db493d6a@spud> References: <20230518-moneybags-rebalance-1484db493d6a@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3273; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=mqXlw0fgDUn4br2UCAGz540cPsRpVLpHCsPCQP13VEQ=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDClpKzk2culaM+bWTqqZtXvtoq7Yrr51woW7ZdnLtdP+e 844aePcUcrCIMbBICumyJJ4u69Fav0flx3OPW9h5rAygQxh4OIUgIn4FzMy/F8qOVvFIf1vs+ee v3kVDxbIbi/Ib1q77VDrlV1rCr693MLI8OzVe76rR+4rvGCYcYC3zpC/8tOJukpub80z/ZcYTqq EcgMA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Some back and forth with Drew [1] about riscv_fill_hwcap() resulted in the realisation that it is not very useful to parse the DT & perform validation of riscv,isa every time we would like to get the id for a hart. Although it is no longer called in riscv_fill_hwcap(), riscv_of_processor_hartid() is called in several other places. Notably in setup_smp() it forms part of the logic for filling the mask of possible CPUs. Since a possible CPU must have passed this basic validation of riscv,isa, a repeat validation is not required. Rename riscv_of_processor_id() to riscv_early_of_processor_id(), which will be called from setup_smp() & introduce a new riscv_of_processor_id() which makes use of the pre-populated mask of possible cpus. Link: https://lore.kernel.org/linux-riscv/xvdswl3iyikwvamny7ikrxo2ncuixshtg3f6uucjahpe3xpc5c@ud4cz4fkg5dj/ [1] Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley --- arch/riscv/include/asm/processor.h | 1 + arch/riscv/kernel/cpu.c | 22 +++++++++++++++++++++- arch/riscv/kernel/smpboot.c | 2 +- 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index 94a0590c6971..3479f9fca4b0 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -75,6 +75,7 @@ static inline void wait_for_interrupt(void) struct device_node; int riscv_of_processor_hartid(struct device_node *node, unsigned long *hartid); +int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hartid); int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid); extern void riscv_fill_hwcap(void); diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index f4dadbfecd04..7030a5004f8e 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -20,6 +20,26 @@ * isn't an enabled and valid RISC-V hart node. */ int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) +{ + int cpu; + + *hart = (unsigned long)of_get_cpu_hwid(node, 0); + if (*hart == ~0UL) { + pr_warn("Found CPU without hart ID\n"); + return -ENODEV; + } + + cpu = riscv_hartid_to_cpuid(*hart); + if (cpu < 0) + return cpu; + + if (!cpu_possible(cpu)) + return -ENODEV; + + return 0; +} + +int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hart) { const char *isa; @@ -28,7 +48,7 @@ int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) return -ENODEV; } - *hart = (unsigned long) of_get_cpu_hwid(node, 0); + *hart = (unsigned long)of_get_cpu_hwid(node, 0); if (*hart == ~0UL) { pr_warn("Found CPU without hart ID\n"); return -ENODEV; diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 445a4efee267..626238200010 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -81,7 +81,7 @@ void __init setup_smp(void) cpu_set_ops(0); for_each_of_cpu_node(dn) { - rc = riscv_of_processor_hartid(dn, &hart); + rc = riscv_early_of_processor_hartid(dn, &hart); if (rc < 0) continue; From patchwork Thu May 18 22:39:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 683487 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0A30C77B73 for ; Thu, 18 May 2023 22:40:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229508AbjERWkQ (ORCPT ); Thu, 18 May 2023 18:40:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50566 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230220AbjERWkQ (ORCPT ); Thu, 18 May 2023 18:40:16 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A50D5E6B for ; Thu, 18 May 2023 15:40:14 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 3982365290 for ; Thu, 18 May 2023 22:40:14 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7611BC4339B; Thu, 18 May 2023 22:40:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684449613; bh=ypjNYLjW+D7UXqDeV7BW4n9xdA8f+pquBC6t0rUOM2Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TRGgB1D9F10gnbSRtaCw0ZmGfoB8QCrg0UZgV0ymIOdAzKgnBBG4js8HxunGJRYPn GQ85QjENjGd20j2UXV9OpeGyp7HY43yb4Iu2e8qZKPiBeLwNW7RLnWzvhiV8O5P44j 1a6TVbBXcpHB9tUZnqBMhmV/EbAIFIAK3x/u4yBYdbsXKgFW7dcEamYv5TEi5kGmgV 6ycrwJ5AvW3gE8GGGu7FENWINRvayfkY5Na3+ffMmYK6groHYd8Tbbg7Vn8LXRhOtm H3jARotuWdHsOo3d/h4zw2w63SB1lGOGpLo/RlthYVhvKraIQFGQbmK5IEqmgefoRR /MjLJyb93YDTw== From: Conor Dooley To: palmer@dabbelt.com Cc: conor@kernel.org, Conor Dooley , Paul Walmsley , Andrew Jones , Sunil V L , Yangyu Chen , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v2 5/8] RISC-V: rework comments in ISA string parser Date: Thu, 18 May 2023 23:39:06 +0100 Message-Id: <20230518-tactless-ascent-6b74f1119336@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230518-moneybags-rebalance-1484db493d6a@spud> References: <20230518-moneybags-rebalance-1484db493d6a@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4612; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=MzEbrG92FOqTlvRzWi1g8GTF0L/yzRwWLOI3UI52hnc=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDClpKzlYrNzSPpW1/Yy5Iymr2MD8JeDNjgdzfPbfSf07y d7x2qFFHaUsDGIcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZjIBH2G/w52Rut/dXN9jql+ tuWN34mr0z1WLVnR0/pJKsk84sxS130Mf4Uei/fE3GT5mK824VRbX/G2k4YJLRYuW6QPM368+yA jmxMA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley I have found these comments to not be at all helpful whenever I look at the parser. Further, the comments in the default case (single letter parser) are not quite right either. Group the comments into a larger one at the start of each case, that attempts to explain things at a higher level. Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley --- arch/riscv/kernel/cpufeature.c | 70 ++++++++++++++++++++++++++++------ 1 file changed, 59 insertions(+), 11 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index a79c5c52a174..cc5189c7c64e 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -146,7 +146,7 @@ void __init riscv_fill_hwcap(void) switch (*ext) { case 's': - /** + /* * Workaround for invalid single-letter 's' & 'u'(QEMU). * No need to set the bit in riscv_isa as 's' & 'u' are * not valid ISA extensions. It works until multi-letter @@ -163,53 +163,101 @@ void __init riscv_fill_hwcap(void) case 'X': case 'z': case 'Z': + /* + * Before attempting to parse the extension itself, we find its end. + * As multi-letter extensions must be split from other multi-letter + * extensions with an "_", the end of a multi-letter extension will + * either be the null character or the "_" at the start of the next + * multi-letter extension. + * + * Next, as the extensions version is currently ignored, we + * eliminate that portion. This is done by parsing backwards from + * the end of the extension, removing any numbers. This may be a + * major or minor number however, so the process is repeated if a + * minor number was found. + * + * ext_end is intended to represent the first character *after* the + * name portion of an extension, but will be decremented to the last + * character itself while eliminating the extensions version number. + * A simple re-increment solves this problem. + */ ext_long = true; - /* Multi-letter extension must be delimited */ for (; *isa && *isa != '_'; ++isa) if (unlikely(!isalnum(*isa))) ext_err = true; - /* Parse backwards */ + ext_end = isa; if (unlikely(ext_err)) break; + if (!isdigit(ext_end[-1])) break; - /* Skip the minor version */ + while (isdigit(*--ext_end)) ; - if (tolower(ext_end[0]) != 'p' - || !isdigit(ext_end[-1])) { - /* Advance it to offset the pre-decrement */ + + if (tolower(ext_end[0]) != 'p' || !isdigit(ext_end[-1])) { ++ext_end; break; } - /* Skip the major version */ + while (isdigit(*--ext_end)) ; + ++ext_end; break; default: + /* + * Things are a little easier for single-letter extensions, as they + * are parsed forwards. + * + * After checking that our starting position is valid, we need to + * ensure that, when isa was incremented at the start of the loop, + * that it arrived at the start of the next extension. + * + * If we are already on a non-digit, there is nothing to do. Either + * we have a multi-letter extension's _, or the start of an + * extension. + * + * Otherwise we have found the current extension's major version + * number. Parse past it, and a subsequent p/minor version number + * if present. The `p` extension must not appear immediately after + * a number, so there is no fear of missing it. + * + */ if (unlikely(!isalpha(*ext))) { ext_err = true; break; } - /* Find next extension */ + if (!isdigit(*isa)) break; - /* Skip the minor version */ + while (isdigit(*++isa)) ; + if (tolower(*isa) != 'p') break; + if (!isdigit(*++isa)) { --isa; break; } - /* Skip the major version */ + while (isdigit(*++isa)) ; + break; } + + /* + * The parser expects that at the start of an iteration isa points to the + * character before the start of the next extension. This will not be the + * case if we have just parsed a single-letter extension and the next + * extension is not a multi-letter extension prefixed with an "_". It is + * also not the case at the end of the string, where it will point to the + * terminating null character. + */ if (*isa != '_') --isa; From patchwork Thu May 18 22:39:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 683486 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF67BC7EE29 for ; Thu, 18 May 2023 22:40:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230389AbjERWkV (ORCPT ); Thu, 18 May 2023 18:40:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50634 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230299AbjERWkU (ORCPT ); Thu, 18 May 2023 18:40:20 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2397EE64 for ; Thu, 18 May 2023 15:40:20 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id AC045652BB for ; Thu, 18 May 2023 22:40:19 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AB7C1C4339E; Thu, 18 May 2023 22:40:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684449619; bh=vFxtHREVJ9UNBDng1m71MFH7Sb5ddr33ZSLOi8jzDkE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iZAiGKpLFBCWpXjnHOa0G1uBBP6KR0AVjLr3F3bOIs50/DE+ordRlvZ+wXweBWtHX 8Uefj8GUC51cJShihnA0CDlTaEYh+0qfD1OhCfBlEZdk1ye0rW6ZY/7qhM9gK3Zn+5 Dc+NjD7HRCODaVds/NAWofa+rGrVvH2sgFWxFPqoWNJOoTggFb9uXljbANRxwl3nnr 9Y/Felf32eGyBcYagmm7HPvp6gkvnaiUMTQM2RardFd+pKxrXkEwEoZxu63i+hsPGB R5hBOap+FdNV5co0HXg4lglkGxQjLPiIbhZwipQN2BWRLuiRnq+uFoJuxnAlx3UcZ5 cqJi2RlO/1YHQ== From: Conor Dooley To: palmer@dabbelt.com Cc: conor@kernel.org, Conor Dooley , Paul Walmsley , Andrew Jones , Sunil V L , Yangyu Chen , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Palmer Dabbelt Subject: [PATCH v2 7/8] dt-bindings: riscv: explicitly mention assumption of Zicntr & Zihpm support Date: Thu, 18 May 2023 23:39:08 +0100 Message-Id: <20230518-earthy-subduing-0ccc26d9c99a@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230518-moneybags-rebalance-1484db493d6a@spud> References: <20230518-moneybags-rebalance-1484db493d6a@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1333; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=FqaBAVwOvKHQOTc+2d9mFz4gWPu5PBX8oewfgU7Ysuc=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDClpKzk3xnye17G69sI9nzOFoiUMsk2HeFdarN6zUWnJN YWOamnhjlIWBjEOBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAEzEV4WR4W71PF2xltPzuuIF zwqzPyi8Jspt7zll5SHZ5m3VV95Pms7IsCG6wZB9oenG2QfEl645saoh6eTC3YmlzPee+e2+xGw 1lxMA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Similar to commit 41ebfc91f785 ("dt-bindings: riscv: explicitly mention assumption of Zicsr & Zifencei support"), the Zicntr and Zihpm extensions also used to be part of the base ISA but were removed after the bindings were merged. Document the assumption of their presence in the base ISA. Suggested-by: Palmer Dabbelt Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/cpus.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index db5253a2a74a..d5208881a1fb 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -89,8 +89,8 @@ properties: Due to revisions of the ISA specification, some deviations have arisen over time. Notably, riscv,isa was defined prior to the creation of the - Zicsr and Zifencei extensions and thus "i" implies - "zicsr_zifencei". + Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i" + implies "zicntr_zicsr_zifencei_zihpm". While the isa strings in ISA specification are case insensitive, letters in the riscv,isa string must be all