From patchwork Sun May 21 22:28:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 684629 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3FF98C7EE26 for ; Sun, 21 May 2023 22:29:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231266AbjEUW3j (ORCPT ); Sun, 21 May 2023 18:29:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39692 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230522AbjEUW3j (ORCPT ); Sun, 21 May 2023 18:29:39 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5BCA1EB; Sun, 21 May 2023 15:29:36 -0700 (PDT) Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34LMTWjw002765; Sun, 21 May 2023 22:29:32 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=yqXyJG1HvKAMceeyFhkxJNpVZG5RWBoYtTKY16iS8CY=; b=GZMFGP9n9JF1Dk9Z4i7IEtgDIRrBQsfVpOCFUohOwGquyYsqYe/0gIhcCXv+tT2EJU+7 s/IXbBuAsRv5/+YFbB9hdCN6wVDoT93YGQ/6ofSk4y1MLMFdgWQLTC/nELjkywKYcKdm zo/mBAmxv7ScQa3c27FBKDx4viXdA+F0YIt/H6a/HwdwGoXKtlPG0XTkSCSjHFW/y/yQ 6JX7g9ASL724CkBN125bSTL+26l2LFvzJjiQiVkgDOHy22XtVhqrom978rGVThavyLEF 0bIkK6Fdq+WtBPq1/obIQa5xQ6OnCEeqRXDaHSSZyMSXIkiKFZ6hBbdJBKz7SjvOQJxT Og== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qpkjujf3s-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 21 May 2023 22:29:32 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34LMTU5S011992 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 21 May 2023 22:29:30 GMT Received: from mmanikan-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Sun, 21 May 2023 15:29:23 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH V2 02/13] dt-bindings: mailbox: qcom: Add IPQ5018 APCS compatible Date: Mon, 22 May 2023 03:58:41 +0530 Message-ID: <20230521222852.5740-3-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230521222852.5740-1-quic_mmanikan@quicinc.com> References: <20230521222852.5740-1-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: pTYfU-PZquQsRerAw5KiGG79M5_pACiH X-Proofpoint-ORIG-GUID: pTYfU-PZquQsRerAw5KiGG79M5_pACiH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-21_17,2023-05-17_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 lowpriorityscore=0 malwarescore=0 mlxscore=0 suspectscore=0 mlxlogscore=981 priorityscore=1501 adultscore=0 impostorscore=0 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305210202 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add compatible for the Qualcomm IPQ5018 APCS block. Signed-off-by: Manikanta Mylavarapu --- Changes in V2: - As suggested by Kathirvan & Krzysztof, used fallback mechanism similar to IPQ5332 .../devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml index 32d7bbc98cac..d2e25ff6db7f 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -18,6 +18,7 @@ properties: oneOf: - items: - enum: + - qcom,ipq5018-apcs-apps-global - qcom,ipq5332-apcs-apps-global - qcom,ipq8074-apcs-apps-global - qcom,ipq9574-apcs-apps-global From patchwork Sun May 21 22:28:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 684628 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A524C7EE26 for ; Sun, 21 May 2023 22:30:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231157AbjEUWaL (ORCPT ); Sun, 21 May 2023 18:30:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40274 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230171AbjEUWaK (ORCPT ); Sun, 21 May 2023 18:30:10 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77AA01A7; Sun, 21 May 2023 15:29:51 -0700 (PDT) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34LMMXoU005232; Sun, 21 May 2023 22:29:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=1YCZ/5wb97tOLkbFCh5KgOXccZ7Df9knHccpxVjxQUg=; b=B7mq9Gys1KcXx3qZ7Q37m+Pl6veQNX6YeGc10Xb82Y7j64ghObvbzJI1Q68bmHP/c6zS iC/2bwgo4hSrFbGyBastLQmouc2/+hTtalG4NNguvipeA/4Omk4lwL44K+bkZqVaE/Ev Rx3ao5inG3oPtFY7CKt/oT3iTtKtNThRCCqOHwSDylvReyOES8Wqbq45n+E9w681WS8M surtnOXArXzV6f8FFL6WfUJm/Olq8YnUm11wtz0KnxMDW31c5bEa6iVwXh8EyMdOceBx Fa/B/GDPML1vgkZGIALKZbXUSLZasSPib0Z7FltlhzIZd59eBQZ5ogHIWPzEPkz91dnj Bg== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qpqctt5uc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 21 May 2023 22:29:46 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34LMTjNt012022 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 21 May 2023 22:29:45 GMT Received: from mmanikan-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Sun, 21 May 2023 15:29:38 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH V2 04/13] dt-bindings: clock: qcom: gcc-ipq5018: remove q6 clocks macros Date: Mon, 22 May 2023 03:58:43 +0530 Message-ID: <20230521222852.5740-5-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230521222852.5740-1-quic_mmanikan@quicinc.com> References: <20230521222852.5740-1-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: SYTOSjVrT9cO1ripsdvKpxxAUVgbfqBO X-Proofpoint-GUID: SYTOSjVrT9cO1ripsdvKpxxAUVgbfqBO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-21_17,2023-05-17_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 bulkscore=0 suspectscore=0 impostorscore=0 malwarescore=0 priorityscore=1501 mlxlogscore=999 clxscore=1015 lowpriorityscore=0 phishscore=0 mlxscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305210203 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Since Q6 firmware takes care of bring up clocks in multipd model, remove bring up clock macros. Signed-off-by: Manikanta Mylavarapu --- include/dt-bindings/clock/qcom,gcc-ipq5018.h | 21 -------------------- 1 file changed, 21 deletions(-) -- 2.17.1 diff --git a/include/dt-bindings/clock/qcom,gcc-ipq5018.h b/include/dt-bindings/clock/qcom,gcc-ipq5018.h index f3de2fdfeea1..89d81fa1a758 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq5018.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq5018.h @@ -74,15 +74,8 @@ #define GCC_PCIE1_AXI_S_CLK 65 #define GCC_PCIE1_PIPE_CLK 66 #define GCC_PRNG_AHB_CLK 67 -#define GCC_Q6_AXIM_CLK 68 -#define GCC_Q6_AXIM2_CLK 69 -#define GCC_Q6_AXIS_CLK 70 -#define GCC_Q6_AHB_CLK 71 -#define GCC_Q6_AHB_S_CLK 72 #define GCC_Q6_TSCTR_1TO2_CLK 73 #define GCC_Q6SS_ATBM_CLK 74 -#define GCC_Q6SS_PCLKDBG_CLK 75 -#define GCC_Q6SS_TRIG_CLK 76 #define GCC_QDSS_AT_CLK 77 #define GCC_QDSS_CFG_AHB_CLK 78 #define GCC_QDSS_DAP_AHB_CLK 79 @@ -109,7 +102,6 @@ #define GCC_SYS_NOC_PCIE1_AXI_CLK 100 #define GCC_SYS_NOC_QDSS_STM_AXI_CLK 101 #define GCC_SYS_NOC_USB0_AXI_CLK 102 -#define GCC_SYS_NOC_WCSS_AHB_CLK 103 #define GCC_UBI0_AXI_CLK 104 #define GCC_UBI0_CFG_CLK 105 #define GCC_UBI0_CORE_CLK 106 @@ -127,19 +119,6 @@ #define GCC_USB0_MOCK_UTMI_CLK 118 #define GCC_USB0_PHY_CFG_AHB_CLK 119 #define GCC_USB0_SLEEP_CLK 120 -#define GCC_WCSS_ACMT_CLK 121 -#define GCC_WCSS_AHB_S_CLK 122 -#define GCC_WCSS_AXI_M_CLK 123 -#define GCC_WCSS_AXI_S_CLK 124 -#define GCC_WCSS_DBG_IFC_APB_BDG_CLK 125 -#define GCC_WCSS_DBG_IFC_APB_CLK 126 -#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 127 -#define GCC_WCSS_DBG_IFC_ATB_CLK 128 -#define GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK 129 -#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 130 -#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 131 -#define GCC_WCSS_DBG_IFC_NTS_CLK 132 -#define GCC_WCSS_ECAHB_CLK 133 #define GCC_XO_CLK 134 #define GCC_XO_CLK_SRC 135 #define GMAC0_RX_CLK_SRC 136 From patchwork Sun May 21 22:28:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 684627 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6B96C7EE2E for ; Sun, 21 May 2023 22:30:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231329AbjEUWah (ORCPT ); Sun, 21 May 2023 18:30:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231190AbjEUWag (ORCPT ); Sun, 21 May 2023 18:30:36 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 59D69198; Sun, 21 May 2023 15:30:13 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34LMNFZc024542; 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Sun, 21 May 2023 22:30:00 GMT Received: from mmanikan-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Sun, 21 May 2023 15:29:53 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH V2 06/13] clk: qcom: ipq5018: remove q6 bring up clocks Date: Mon, 22 May 2023 03:58:45 +0530 Message-ID: <20230521222852.5740-7-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230521222852.5740-1-quic_mmanikan@quicinc.com> References: <20230521222852.5740-1-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: iVat257bFjWbLGtxVBieiEQbAc4IiXkr X-Proofpoint-GUID: iVat257bFjWbLGtxVBieiEQbAc4IiXkr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-21_17,2023-05-17_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 suspectscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 phishscore=0 mlxscore=0 bulkscore=0 mlxlogscore=999 lowpriorityscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305210203 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Since Q6 firmware takes care of it's bring up clocks in multipd model, remove from gcc driver. Signed-off-by: Manikanta Mylavarapu --- drivers/clk/qcom/gcc-ipq5018.c | 414 --------------------------------- 1 file changed, 414 deletions(-) -- 2.17.1 diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c index 7ac93b1d6b3f..0dab7d94a3ae 100644 --- a/drivers/clk/qcom/gcc-ipq5018.c +++ b/drivers/clk/qcom/gcc-ipq5018.c @@ -2225,159 +2225,6 @@ static struct clk_branch gcc_prng_ahb_clk = { }, }; -static struct clk_branch gcc_q6_ahb_clk = { - .halt_reg = 0x59138, - .clkr = { - .enable_reg = 0x59138, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_q6_ahb_clk", - .parent_hws = (const struct clk_hw *[]) { - &wcss_ahb_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_q6_ahb_s_clk = { - .halt_reg = 0x5914C, - .clkr = { - .enable_reg = 0x5914C, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_q6_ahb_s_clk", - .parent_hws = (const struct clk_hw *[]) { - &wcss_ahb_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_q6_axim_clk = { - .halt_reg = 0x5913C, - .clkr = { - .enable_reg = 0x5913C, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_q6_axim_clk", - .parent_hws = (const struct clk_hw *[]) { - &q6_axi_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_q6_axim2_clk = { - .halt_reg = 0x59150, - .clkr = { - .enable_reg = 0x59150, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_q6_axim2_clk", - .parent_hws = (const struct clk_hw *[]) { - &q6_axi_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_q6_axis_clk = { - .halt_reg = 0x59154, - .clkr = { - .enable_reg = 0x59154, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_q6_axis_clk", - .parent_hws = (const struct clk_hw *[]) { - &system_noc_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_q6_tsctr_1to2_clk = { - .halt_reg = 0x59148, - .clkr = { - .enable_reg = 0x59148, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_q6_tsctr_1to2_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_tsctr_div2_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_q6ss_atbm_clk = { - .halt_reg = 0x59144, - .clkr = { - .enable_reg = 0x59144, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_q6ss_atbm_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_at_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_q6ss_pclkdbg_clk = { - .halt_reg = 0x59140, - .clkr = { - .enable_reg = 0x59140, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_q6ss_pclkdbg_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_dap_sync_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_q6ss_trig_clk = { - .halt_reg = 0x59128, - .clkr = { - .enable_reg = 0x59128, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_q6ss_trig_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_dap_sync_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_qdss_at_clk = { .halt_reg = 0x29024, .clkr = { @@ -2803,23 +2650,6 @@ static struct clk_branch gcc_sys_noc_usb0_axi_clk = { }, }; -static struct clk_branch gcc_sys_noc_wcss_ahb_clk = { - .halt_reg = 0x26034, - .clkr = { - .enable_reg = 0x26034, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_sys_noc_wcss_ahb_clk", - .parent_hws = (const struct clk_hw *[]) { - &wcss_ahb_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_ubi0_axi_clk = { .halt_reg = 0x68200, .halt_check = BRANCH_HALT_DELAY, @@ -3134,227 +2964,6 @@ static struct clk_branch gcc_usb0_pipe_clk = { }, }; -static struct clk_branch gcc_wcss_acmt_clk = { - .halt_reg = 0x59064, - .clkr = { - .enable_reg = 0x59064, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_wcss_acmt_clk", - .parent_hws = (const struct clk_hw *[]) { - &wcss_ahb_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_ahb_s_clk = { - .halt_reg = 0x59034, - .clkr = { - .enable_reg = 0x59034, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_wcss_ahb_s_clk", - .parent_hws = (const struct clk_hw *[]) { - &wcss_ahb_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_axi_m_clk = { - .halt_reg = 0x5903C, - .clkr = { - .enable_reg = 0x5903C, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_wcss_axi_m_clk", - .parent_hws = (const struct clk_hw *[]) { - &system_noc_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_axi_s_clk = { - .halt_reg = 0x59068, - .clkr = { - .enable_reg = 0x59068, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_wi_s_clk", - .parent_hws = (const struct clk_hw *[]) { - &system_noc_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_apb_bdg_clk = { - .halt_reg = 0x59050, - .clkr = { - .enable_reg = 0x59050, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_apb_bdg_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_dap_sync_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = { - .halt_reg = 0x59040, - .clkr = { - .enable_reg = 0x59040, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_apb_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_dap_sync_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_atb_bdg_clk = { - .halt_reg = 0x59054, - .clkr = { - .enable_reg = 0x59054, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_atb_bdg_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_at_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = { - .halt_reg = 0x59044, - .clkr = { - .enable_reg = 0x59044, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_atb_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_at_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_dapbus_bdg_clk = { - .halt_reg = 0x59060, - .clkr = { - .enable_reg = 0x59060, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_dapbus_bdg_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_dap_sync_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = { - .halt_reg = 0x5905C, - .clkr = { - .enable_reg = 0x5905C, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_dapbus_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_dap_sync_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_nts_bdg_clk = { - .halt_reg = 0x59058, - .clkr = { - .enable_reg = 0x59058, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_nts_bdg_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_tsctr_div2_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = { - .halt_reg = 0x59048, - .clkr = { - .enable_reg = 0x59048, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_nts_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_tsctr_div2_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_ecahb_clk = { - .halt_reg = 0x59038, - .clkr = { - .enable_reg = 0x59038, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_wcss_ecahb_clk", - .parent_hws = (const struct clk_hw *[]) { - &wcss_ahb_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_hw *gcc_ipq5018_hws[] = { &gpll0_out_main_div2.hw, &pcnoc_clk_src.hw, @@ -3444,15 +3053,6 @@ static struct clk_regmap *gcc_ipq5018_clks[] = { [GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr, [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr, [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, - [GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr, - [GCC_Q6_AXIM2_CLK] = &gcc_q6_axim2_clk.clkr, - [GCC_Q6_AXIS_CLK] = &gcc_q6_axis_clk.clkr, - [GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr, - [GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr, - [GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr, - [GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr, - [GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr, - [GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr, [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr, [GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr, [GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr, @@ -3479,7 +3079,6 @@ static struct clk_regmap *gcc_ipq5018_clks[] = { [GCC_SYS_NOC_PCIE1_AXI_CLK] = &gcc_sys_noc_pcie1_axi_clk.clkr, [GCC_SYS_NOC_QDSS_STM_AXI_CLK] = &gcc_sys_noc_qdss_stm_axi_clk.clkr, [GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr, - [GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr, [GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr, [GCC_UBI0_CFG_CLK] = &gcc_ubi0_cfg_clk.clkr, [GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr, @@ -3497,19 +3096,6 @@ static struct clk_regmap *gcc_ipq5018_clks[] = { [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr, [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr, [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr, - [GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr, - [GCC_WCSS_AHB_S_CLK] = &gcc_wcss_ahb_s_clk.clkr, - [GCC_WCSS_AXI_M_CLK] = &gcc_wcss_axi_m_clk.clkr, - [GCC_WCSS_AXI_S_CLK] = &gcc_wcss_axi_s_clk.clkr, - [GCC_WCSS_DBG_IFC_APB_BDG_CLK] = &gcc_wcss_dbg_ifc_apb_bdg_clk.clkr, - [GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr, - [GCC_WCSS_DBG_IFC_ATB_BDG_CLK] = &gcc_wcss_dbg_ifc_atb_bdg_clk.clkr, - [GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr, - [GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK] = &gcc_wcss_dbg_ifc_dapbus_bdg_clk.clkr, - [GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr, - [GCC_WCSS_DBG_IFC_NTS_BDG_CLK] = &gcc_wcss_dbg_ifc_nts_bdg_clk.clkr, - [GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr, - [GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr, [GCC_XO_CLK] = &gcc_xo_clk.clkr, [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr, [GMAC0_RX_CLK_SRC] = &gmac0_rx_clk_src.clkr, From patchwork Sun May 21 22:28:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 684626 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83EDBC7EE30 for ; Sun, 21 May 2023 22:30:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231365AbjEUWav (ORCPT ); Sun, 21 May 2023 18:30:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231374AbjEUWat (ORCPT ); Sun, 21 May 2023 18:30:49 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED71B106; Sun, 21 May 2023 15:30:33 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34LMMJ4m023140; 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Sun, 21 May 2023 22:30:15 GMT Received: from mmanikan-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Sun, 21 May 2023 15:30:07 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH V2 08/13] firmware: qcom_scm: ipq5018: Add WCSS AHB pd support Date: Mon, 22 May 2023 03:58:47 +0530 Message-ID: <20230521222852.5740-9-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230521222852.5740-1-quic_mmanikan@quicinc.com> References: <20230521222852.5740-1-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: _Y6t_qYZjboKxdPhmdHXt2gNOWXIidGy X-Proofpoint-GUID: _Y6t_qYZjboKxdPhmdHXt2gNOWXIidGy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-21_17,2023-05-17_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 suspectscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 phishscore=0 mlxscore=0 bulkscore=0 mlxlogscore=999 lowpriorityscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305210203 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support to power up, down & load userpd firmware. Signed-off-by: Manikanta Mylavarapu --- Changes in V2: - This patch is generated by Strip off SCM code changes from here https://lore.kernel.org/linux-arm-msm/1678164097-13247-9-git-send-email-quic_mmanikan@quicinc.com/ drivers/firmware/qcom_scm.c | 114 +++++++++++++++++++++++++ drivers/firmware/qcom_scm.h | 6 ++ include/linux/firmware/qcom/qcom_scm.h | 3 + 3 files changed, 123 insertions(+) -- 2.17.1 diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index fde33acd46b7..c617e9e671ec 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -643,6 +643,120 @@ int qcom_scm_pas_shutdown(u32 peripheral) } EXPORT_SYMBOL(qcom_scm_pas_shutdown); +/** + * qti_scm_int_radio_powerup - Bring up WCSS AHB userpd + * + * @peripheral: peripheral id + * + * Return 0 on success. + */ +int qti_scm_int_radio_powerup(u32 peripheral) +{ + int ret; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_PD_LOAD_SVC_ID, + .cmd = QCOM_SCM_INT_RAD_PWR_UP_CMD_ID, + .arginfo = QCOM_SCM_ARGS(1), + .args[0] = peripheral, + .owner = ARM_SMCCC_OWNER_SIP, + }; + struct qcom_scm_res res; + + ret = qcom_scm_clk_enable(); + if (ret) + return ret; + + ret = qcom_scm_bw_enable(); + if (ret) + return ret; + + ret = qcom_scm_call(__scm->dev, &desc, &res); + qcom_scm_bw_disable(); + qcom_scm_clk_disable(); + + return ret ? : res.result[0]; +} +EXPORT_SYMBOL(qti_scm_int_radio_powerup); + +/** + * qti_scm_int_radio_powerdown() - Shut down WCSS AHB userpd + * + * @peripheral: peripheral id + * + * Returns 0 on success. + */ +int qti_scm_int_radio_powerdown(u32 peripheral) +{ + int ret; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_PD_LOAD_SVC_ID, + .cmd = QCOM_SCM_INT_RAD_PWR_DN_CMD_ID, + .arginfo = QCOM_SCM_ARGS(1), + .args[0] = peripheral, + .owner = ARM_SMCCC_OWNER_SIP, + }; + struct qcom_scm_res res; + + ret = qcom_scm_clk_enable(); + if (ret) + return ret; + + ret = qcom_scm_bw_enable(); + if (ret) + return ret; + + ret = qcom_scm_call(__scm->dev, &desc, &res); + qcom_scm_bw_disable(); + qcom_scm_clk_disable(); + + return ret ? : res.result[0]; +} +EXPORT_SYMBOL(qti_scm_int_radio_powerdown); + +/** + * qti_scm_pdseg_memcpy_v2() - copy userpd PIL segments data to dma blocks + * + * @peripheral: peripheral id + * @phno: program header no + * @dma: handle of dma region + * @seg_cnt: no of dma blocks + * + * Returns 0 if trustzone successfully loads userpd PIL segments from dma + * blocks to DDR + */ +int qti_scm_pdseg_memcpy_v2(u32 peripheral, int phno, dma_addr_t dma, + int seg_cnt) +{ + int ret; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_PD_LOAD_SVC_ID, + .cmd = QCOM_SCM_PD_LOAD_V2_CMD_ID, + .arginfo = QCOM_SCM_ARGS(4, QCOM_SCM_VAL, QCOM_SCM_VAL, + QCOM_SCM_RW, QCOM_SCM_VAL), + .args[0] = peripheral, + .args[1] = phno, + .args[2] = dma, + .args[3] = seg_cnt, + .owner = ARM_SMCCC_OWNER_SIP, + }; + struct qcom_scm_res res; + + ret = qcom_scm_clk_enable(); + if (ret) + return ret; + + ret = qcom_scm_bw_enable(); + if (ret) + return ret; + + ret = qcom_scm_call(__scm->dev, &desc, &res); + qcom_scm_bw_disable(); + qcom_scm_clk_disable(); + + return ret ? : res.result[0]; +} +EXPORT_SYMBOL(qti_scm_pdseg_memcpy_v2); + /** * qcom_scm_pas_supported() - Check if the peripheral authentication service is * available for the given peripherial diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index e6e512bd57d1..99e3ab2f1986 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -132,6 +132,12 @@ extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc, #define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x03 #define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x02 +#define QCOM_SCM_PD_LOAD_SVC_ID 0x2 +#define QCOM_SCM_PD_LOAD_CMD_ID 0x16 +#define QCOM_SCM_PD_LOAD_V2_CMD_ID 0x19 +#define QCOM_SCM_INT_RAD_PWR_UP_CMD_ID 0x17 +#define QCOM_SCM_INT_RAD_PWR_DN_CMD_ID 0x18 + #define QCOM_SCM_SVC_WAITQ 0x24 #define QCOM_SCM_WAITQ_RESUME 0x02 #define QCOM_SCM_WAITQ_GET_WQ_CTX 0x03 diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmware/qcom/qcom_scm.h index 250ea4efb7cb..488d6eccb5a4 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -81,6 +81,9 @@ extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, extern int qcom_scm_pas_auth_and_reset(u32 peripheral); extern int qcom_scm_pas_shutdown(u32 peripheral); extern bool qcom_scm_pas_supported(u32 peripheral); +int qti_scm_int_radio_powerup(u32 peripheral); +int qti_scm_int_radio_powerdown(u32 peripheral); +int qti_scm_pdseg_memcpy_v2(u32 peripheral, int phno, dma_addr_t dma, int seg_cnt); extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val); extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val); From patchwork Sun May 21 22:28:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 684625 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70DA8C7EE2E for ; Sun, 21 May 2023 22:31:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231511AbjEUWbb (ORCPT ); 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Sun, 21 May 2023 22:30:45 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34LMUiuH026839 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 21 May 2023 22:30:44 GMT Received: from mmanikan-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Sun, 21 May 2023 15:30:37 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH V2 12/13] arm64: dts: qcom: ipq5018: Add RDP432-c1 board support Date: Mon, 22 May 2023 03:58:51 +0530 Message-ID: <20230521222852.5740-13-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230521222852.5740-1-quic_mmanikan@quicinc.com> References: <20230521222852.5740-1-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: SbYtfswi2Bra9PUdrD-uffKZG38reukA X-Proofpoint-GUID: SbYtfswi2Bra9PUdrD-uffKZG38reukA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-21_17,2023-05-17_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 clxscore=1015 mlxlogscore=999 phishscore=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 malwarescore=0 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305210203 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add initial device tree support for the RDP432-C1 board. Signed-off-by: Manikanta Mylavarapu --- Changes in V2: - Renamed mp03.5-c1 to RDP432-c1 - Removed boot-args - Resolved dt-binding error's arch/arm64/boot/dts/qcom/Makefile | 1 + .../arm64/boot/dts/qcom/ipq5018-rdp432-c1.dts | 49 +++++++++++++++++++ 2 files changed, 50 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq5018-rdp432-c1.dts -- 2.17.1 diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 259bd57c6064..bb9164de75b0 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-mi01.2.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c1.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c1.dts new file mode 100644 index 000000000000..7fe28d9859b0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c1.dts @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * IPQ5018 RDP432-C1 board device tree source + * + * Copyright (c) 2023, The Linux Foundation. All rights reserved. + */ + +/dts-v1/; + +#include "ipq5018.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ5018/AP-RDP432.1-C1"; + compatible = "qcom,ipq5018-rdp432-c1", "qcom,ipq5018"; + + aliases { + serial0 = &blsp1_uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&blsp1_uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&q6v5_wcss { + pd-2 { + firmware-name = "IPQ5018/q6_fw.mdt"; + status = "okay"; + }; + + pd-3 { + firmware-name = "IPQ5018/q6_fw.mdt"; + status = "okay"; + }; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&xo_board_clk { + clock-frequency = <24000000>; +};