From patchwork Wed Jun 12 09:17:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 166530 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp3437428ilk; Wed, 12 Jun 2019 02:20:41 -0700 (PDT) X-Google-Smtp-Source: APXvYqyyXW/h/VhGciWkw0Fg2kOS7aIkrt7bjJGlq0CvgS3VfLbDZqtxpeQzOnZJAKqs0YHwHSCx X-Received: by 2002:a17:902:341:: with SMTP id 59mr27154403pld.20.1560331241396; Wed, 12 Jun 2019 02:20:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560331241; cv=none; d=google.com; s=arc-20160816; b=W+bj+gyvQDhoZh/Jd3XSRzJZFWr1gblugyFMbl0gITSdiQdxwcS5WNGTSzgvWWFI9c /KyNhobo4Y0hg/W/DM/Dp1/sAJymNR/boyUdyLd4awsGkJDjM8utLy8BRTwd/DanxxwW 6PGKr64hVFBYcXWtFIPz6dQ4q5jFbjtfo200A+kKN4wx7Lay+bSyG2XrdGHjqoLYjiRZ Jnj7ftopxVUgg+qXIgrIFfU+CCbgRniYvCh+DkAvxGEPkqKiQsVkoP439AYGC0nVmCPc ghYubg63E8AWBUqxFP85vMHYyeBrbtgwWrOjD2wNW1k5QzYX23MpTB1Cid0bV0mJnkOJ N8Ng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=XbuM2eVHoWF9USVPnlQZ8xEOlii/92ocRo4RZHR7iQ8=; b=oif4B2p+MH2ODBZGXg+V9FCWJV6x5Nq55ao5h3laUA4a2WBidZfXHwSzlirNdYrOqm Bw+bOdQbhiAFnOSYk04Dpp+2tmLd6BsZKs6tu+gMJFDq/ohC6yiwtkoSFi/HtLAssJA1 f6+mlxhdahnC2GdnsmZ9prTzZQfvKVxctEpoz9k4QAXT/JVbkhGPMbvQKn44hVKB5VT5 S3W2GfQmtkUDjgs8IBER8u1tXp6QxFtdBA9vqeVjb59FFFXWxfhxuUnA5xSl9YkZaVmb KHWpEYSYC5LGeBu1JkIXGTY8SUcHU4RmiOD3fw1/izfDuYatDWf+U+xU/kCUgDEJO5R+ AT4A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=swWChb+N; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s12si7195384plr.338.2019.06.12.02.20.41; Wed, 12 Jun 2019 02:20:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=swWChb+N; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2408703AbfFLJUk (ORCPT + 15 others); Wed, 12 Jun 2019 05:20:40 -0400 Received: from mail.kernel.org ([198.145.29.99]:38586 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2406714AbfFLJUk (ORCPT ); Wed, 12 Jun 2019 05:20:40 -0400 Received: from localhost.localdomain (unknown [106.200.205.167]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 9DCC1208C2; Wed, 12 Jun 2019 09:20:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1560331239; bh=BfsGQZR4Ybb+MkIRvK9Va0OCM+SFEMOozdC+GsS/y6I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=swWChb+NB4og5PUkGnpGHlutKPUPZT76YPFHjo3uPjuurts+S/nJuEDrkjCLXwtNb IoYS8brvJ2yA2fmWLTwk9YlWeuk5NvW5BapobvQiUkYWOSYk0AvyqF4upVCXrDHepL QFNdsCzsBjPJkvxi/LilB2qax/TdhMsKzVlYu9y4= From: Vinod Koul To: Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , Andy Gross , David Brown , Michael Turquette , linux-clk@vger.kernel.org Subject: [PATCH v2 1/5] clk: qcom: clk-alpha-pll: Remove unnecessary cast Date: Wed, 12 Jun 2019 14:47:18 +0530 Message-Id: <20190612091722.9377-2-vkoul@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190612091722.9377-1-vkoul@kernel.org> References: <20190612091722.9377-1-vkoul@kernel.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We have couple of instances in the driver with unnecessary u64 casts, drop them. Signed-off-by: Vinod Koul --- drivers/clk/qcom/clk-alpha-pll.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.20.1 diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 0ced4a5a9a17..b48707693ffd 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -832,7 +832,7 @@ static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, int div; /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */ - div = DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1; + div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1; return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, @@ -1094,7 +1094,7 @@ static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw, return -EINVAL; } - div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); + div = DIV_ROUND_UP_ULL(parent_rate, rate); for (i = 0; i < pll->num_post_div; i++) { if (pll->post_div_table[i].div == div) { val = pll->post_div_table[i].val; From patchwork Wed Jun 12 09:17:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 166531 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp3437503ilk; Wed, 12 Jun 2019 02:20:45 -0700 (PDT) X-Google-Smtp-Source: APXvYqxUbWy8J23GPsjfEOVmu2Qo0tVUX9gySYEXMv3lyNu4kpCi+Kj3vfGMcy/LaXqP4cU0XsrD X-Received: by 2002:a65:5347:: with SMTP id w7mr24099389pgr.375.1560331244994; Wed, 12 Jun 2019 02:20:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560331244; cv=none; d=google.com; s=arc-20160816; b=UeL6pnDd7E0XrrxZDLiLBSNecdNxaiasnbbv+xAYaryCTxwlRY+phf2aM1+GNrGM5n fksN0dxYNS5jltMRkkIks0CAFKvKdInGuVTHoTzVIRsyvEmy8TPkNWxI+ibhjC1HgNtX 1tXJWce2Anau7ZDXx8CTwaG8keOMOB9HVGqtzF/7S+jEjFjjCTzXGTSf+MVuyrFxcC4g zHzVhRE3dVZ/Kc1kdUfBB54GJ7hS+LKF8EALHoSgSp61UESX8xX931ieZUN7JTpEIIfG u7orHU6QJcVzlVcofu9WTzw2QpFIHZUWsVM0OQW6MiGmVjSNRsOSXAbY8y6CdMO/aPDS caWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=uYMR6wA+E+lwNCadUs2KtZoOSNRKVjjkyI8Kr0KZq1w=; b=eQgEu4gjwJigs9hEUkYaRYxgPJ159wr3PqoClhYpfqWFmdFN4Z91xdpuOiWV30i7J2 bjh9i0BLjw//D8kko3G2wh4pqIMHRBXTIfAM5cErl5k2/hmPWp1aih+UqkSqZOj2seuZ 498IHu6kjNvLPDmUG2W8OYBC71xrXwJYN+fycrIYELvOFOJIY26rvp4keBIy9ZZ8rzaG KPIkX3X48KmqHNhjXOEbsUrsGjrFA4Sz9/sxq3RYWzRY6Fw+wUfV2YVxozERxVIVIxum tW3U8SQQEW3cnveMn+Tko5HJGWEkeVLFfxpaBmXZELCym2ZUhD2WnKA2R36ZZDZbWIfs yuhQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=ucwNcsF9; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s12si7195384plr.338.2019.06.12.02.20.44; Wed, 12 Jun 2019 02:20:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=ucwNcsF9; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2436598AbfFLJUn (ORCPT + 15 others); Wed, 12 Jun 2019 05:20:43 -0400 Received: from mail.kernel.org ([198.145.29.99]:38622 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2408705AbfFLJUn (ORCPT ); Wed, 12 Jun 2019 05:20:43 -0400 Received: from localhost.localdomain (unknown [106.200.205.167]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 751B120874; Wed, 12 Jun 2019 09:20:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1560331242; bh=wOMJ9aM4tSyEIdMjxMkyFSSJTeyrR+hlsRS+FtmB2EE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ucwNcsF9fFzm52dfqMbOLO2bEYmFH2ojYb2pLQaRNl8tZalYQ21g5hlWX+TRnGMK+ 8wwDQ03J27J5NUNO/H+QuF/AkyfY2CSjOkeOVYUbbUyomGgXPRZGCzMgMXchFW1nZ+ o3LH3+8wGo3o5nt6JFZmMItEe9braSOyEQSY6X2A= From: Vinod Koul To: Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , Andy Gross , David Brown , Michael Turquette , linux-clk@vger.kernel.org Subject: [PATCH v2 2/5] clk: qcom: clk-alpha-pll: Remove post_div_table checks Date: Wed, 12 Jun 2019 14:47:19 +0530 Message-Id: <20190612091722.9377-3-vkoul@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190612091722.9377-1-vkoul@kernel.org> References: <20190612091722.9377-1-vkoul@kernel.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We want users to code properly and fix the post_div_table missing and not reply on core to check. So remove the post_div_table check. Signed-off-by: Vinod Koul --- drivers/clk/qcom/clk-alpha-pll.c | 15 --------------- 1 file changed, 15 deletions(-) -- 2.20.1 Reviewed-by: Bjorn Andersson diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index b48707693ffd..2c6773188761 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -1036,11 +1036,6 @@ static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw, u32 i, div = 1, val; int ret; - if (!pll->post_div_table) { - pr_err("Missing the post_div_table for the PLL\n"); - return -EINVAL; - } - ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); if (ret) return ret; @@ -1063,11 +1058,6 @@ static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw, { struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); - if (!pll->post_div_table) { - pr_err("Missing the post_div_table for the PLL\n"); - return -EINVAL; - } - return divider_round_rate(hw, rate, prate, pll->post_div_table, pll->width, CLK_DIVIDER_ROUND_CLOSEST); } @@ -1089,11 +1079,6 @@ static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw, if (val & PLL_VOTE_FSM_ENA) return 0; - if (!pll->post_div_table) { - pr_err("Missing the post_div_table for the PLL\n"); - return -EINVAL; - } - div = DIV_ROUND_UP_ULL(parent_rate, rate); for (i = 0; i < pll->num_post_div; i++) { if (pll->post_div_table[i].div == div) { From patchwork Wed Jun 12 09:17:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 166532 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp3437529ilk; Wed, 12 Jun 2019 02:20:47 -0700 (PDT) X-Google-Smtp-Source: APXvYqxl+x4YKTEPircho7CVMuL3Zo6yhnYjFbmk9mT4DNQyakPwOGMH8b078UHHdUCSS+0ayuj8 X-Received: by 2002:a17:902:724:: with SMTP id 33mr78866189pli.49.1560331247262; Wed, 12 Jun 2019 02:20:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560331247; cv=none; d=google.com; s=arc-20160816; b=sZRw/963YV68+7rL+j2iC+D3awrpx+I9CQ6Srx63B9Ys70N2IIbuBQT3COdFGAZpg1 UMLiT5AFf9lbvE6tB0i34FyJFKPLaIFxLu3E1+fu4POcauIVbAqacMTAc7ufvrAq//xA S4d3Rxh0Lo75sIfllHp8WcUa9kJryupS8Cz2oZzlwmIz8/kVNC/tNZ4Y86ZAxnBaobYz yEGTd+JGClMLahGrTymFnAoRSiuTrtGadkC1SU+P5rFXPbrpK0i7aRsH0cOhmeL7H6w8 RFT51TXiGotARWJJUtgFq2L92pmVWBGRbv+6GQuwfOGtUz9rM5KsYRU4P9EEiDQuL31M vmGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ET6NOPKxMpXESQQ+kJYuXGZOCzJWGDcLzry0/0vkjb4=; b=RpTTF0MZmbXJqIkslMyD+fLt/iFuIpNaNRpAVvIRovQDjL9yejXyH9//ib4fE0I8ug xap7Ut0CICnJz3mal86xTMXncJo720kQfoSZlwLOQIx4uW6hyioq4kNpI4lrV95i8oKl CQvdz2rd+MKvR5yoiIkRDaNzM71CVLZBOE6fupik1Ie/SuWBP3VqY0C6IJ2IZQgbLabG QJlrqgljxEWLBkECx1AVdEW2cJN/TZTVy8sRlVWGiEBQV6PjJyFeg9XFH/F1Uj8hb/TA tlT2N0HRVr1HwRqbHM/5zVxlB+PgeR6vfwzLMvaMKSzgD9GuofjfvSwvwAkdGa4G0Il0 05PA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=zoewmHeG; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s12si7195384plr.338.2019.06.12.02.20.46; Wed, 12 Jun 2019 02:20:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=zoewmHeG; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2436774AbfFLJUq (ORCPT + 15 others); Wed, 12 Jun 2019 05:20:46 -0400 Received: from mail.kernel.org ([198.145.29.99]:38650 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2436698AbfFLJUq (ORCPT ); Wed, 12 Jun 2019 05:20:46 -0400 Received: from localhost.localdomain (unknown [106.200.205.167]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 4DFC0208C2; Wed, 12 Jun 2019 09:20:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1560331245; bh=TqalOT6RU4JOZfiDL0C0YDqOJnKe84kysLBlQSgfPkk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=zoewmHeGO9DB/fz1vs803+8fAvzoU8zc7sIgynnTGpzwYQk3Jaww4vopBQH1yVEVW S9VhrszpMLQ0LqQqkL+iARmMAhpCsvXquEi2t0YsqHk44BczOnItK76CtGsHnpegip x4i4WxAIQXCqkwrDQGvdIZxdPfg7vW4YSqo9AlyM= From: Vinod Koul To: Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , Andy Gross , David Brown , Michael Turquette , linux-clk@vger.kernel.org Subject: [PATCH v2 3/5] clk: qcom: gcc-qcs404: Add MODULE_ALIAS Date: Wed, 12 Jun 2019 14:47:20 +0530 Message-Id: <20190612091722.9377-4-vkoul@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190612091722.9377-1-vkoul@kernel.org> References: <20190612091722.9377-1-vkoul@kernel.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org MODULE_ALIAS was missing for this driver which can be built as a module, so add the MODULE_ALIAS. Signed-off-by: Vinod Koul --- drivers/clk/qcom/gcc-qcs404.c | 1 + 1 file changed, 1 insertion(+) -- 2.20.1 diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index a54807eb3b28..eb3ac7a26fb8 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -2828,3 +2828,4 @@ module_exit(gcc_qcs404_exit); MODULE_DESCRIPTION("Qualcomm GCC QCS404 Driver"); MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:gcc-qcs404"); From patchwork Wed Jun 12 09:17:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 166533 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp3437628ilk; Wed, 12 Jun 2019 02:20:52 -0700 (PDT) X-Google-Smtp-Source: APXvYqz/ESIXtuyKYPI7lgBI7QBBXXRIkreyoGKmfWSIuqOgh5BFG1HDrdT2YhTVl59WbxK55wlC X-Received: by 2002:a62:2c8e:: with SMTP id s136mr41170169pfs.3.1560331252176; Wed, 12 Jun 2019 02:20:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560331252; cv=none; d=google.com; s=arc-20160816; b=wqZHdEesIWJSRb9J0OM/MM8kW8onGnOwm7zEINiY9NBIYbuKE5IoVln1UT+DIUyIvc kXha1ofbn2LLRcbDG+n+qOSbS198GveE4Sf0m8a3AiuPQCTutR8KigVK5lJXAZNGCSZF Cdslu96vuzxdQjegCRnp5gflP5TZiQJHjrYhyrhuaA43Mc7F0s9+Kh3eglqjEoMHXonX ShP9a8zhB+yYeSo3nZUjl0Wr8OlEauJvWGwK0ZhRVcbGVHW4FYkz8zd241NxRJgsw03n GSwewDYXKqlnzTOZBBz1vll87Vpvg6OjWSDZgLXKgZIQQaYvbj4t5YcOa4sYNrOQ2fr3 Hx7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=pqqAFL+qJzXlYedmJzfBd8hjBg6a5nK435+BT7WIEMg=; b=MwV1SG9W5LZj/Qbz0QPNhcs3xhGWD8rA5wvRKmnnFe9TpF9rdM1u7YgjbjKUYnoXN2 DM0QI09EiABifnPL4l0Xqix5HGPO6oT2FJ/noctjCcHGzDF/brTAzN3/HVA14w0mo3mZ Ho6GzlKo3AmYGQt7/3IX0KKZEp7ODxcKNDpPSu+1sUsJ3kELVW9y/JIe3EcwEgDXgis7 lqiqERKLLr8T8BEXSlohFI0Yh1iDgSq0kYFfcs22DyOILvzQz63+ttLDL27Dd5aw4DHK jSXPCqk/tBkBicE0V3varU9RVdH4qGmuxDlCLf6nJPf+bFwlTQEM1G6BLovxjdHHUzT+ JUBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=IOse1PXl; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s12si7195384plr.338.2019.06.12.02.20.51; Wed, 12 Jun 2019 02:20:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=IOse1PXl; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2437168AbfFLJUu (ORCPT + 15 others); Wed, 12 Jun 2019 05:20:50 -0400 Received: from mail.kernel.org ([198.145.29.99]:38674 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2436698AbfFLJUu (ORCPT ); Wed, 12 Jun 2019 05:20:50 -0400 Received: from localhost.localdomain (unknown [106.200.205.167]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 2F9F120874; Wed, 12 Jun 2019 09:20:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1560331249; bh=K07r5YTCrJokUqoNcVsCrflmcJKBzGbfdpM/dUQeBmw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IOse1PXlbnIWzL11Z56cg4rvCjzB5I8bXjExgcErlx/VJMFqN1DreRba06GraXiE7 El44AHwRG/fVivMTCWcmEFiZOr+tINWC5XNH57uoSYjg5bV4zaBiYye988OMtAo2uj 3NHlMnaHD+oWpGM/56a3M7br6+HkxsAjFNifhyW0= From: Vinod Koul To: Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Deepak Katragadda , Andy Gross , David Brown , Michael Turquette , linux-clk@vger.kernel.org, Taniya Das , Vinod Koul Subject: [PATCH v2 4/5] clk: qcom: clk-alpha-pll: Add support for Trion PLLs Date: Wed, 12 Jun 2019 14:47:21 +0530 Message-Id: <20190612091722.9377-5-vkoul@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190612091722.9377-1-vkoul@kernel.org> References: <20190612091722.9377-1-vkoul@kernel.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Deepak Katragadda Add programming sequence support for managing the Trion PLLs. Signed-off-by: Deepak Katragadda Signed-off-by: Taniya Das [vkoul: Fix style and format issues convert to use pll type infrastructure remove unnecessary checks in code remove unused code] Signed-off-by: Vinod Koul --- drivers/clk/qcom/clk-alpha-pll.c | 228 +++++++++++++++++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 7 + 2 files changed, 235 insertions(+) -- 2.20.1 diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 2c6773188761..30210f5c6726 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -32,6 +32,7 @@ # define PLL_LOCK_DET BIT(31) #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL]) +#define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL]) #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL]) #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U]) @@ -44,14 +45,17 @@ # define PLL_VCO_MASK 0x3 #define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U]) +#define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1]) #define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL]) #define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U]) +#define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U11]) #define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL]) #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U]) #define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS]) #define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE]) #define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC]) +#define PLL_CAL_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_VAL]) const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [CLK_ALPHA_PLL_TYPE_DEFAULT] = { @@ -96,6 +100,22 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_OPMODE] = 0x2c, [PLL_OFF_FRAC] = 0x38, }, + [CLK_ALPHA_PLL_TYPE_TRION] = { + [PLL_OFF_L_VAL] = 0x04, + [PLL_OFF_CAL_L_VAL] = 0x08, + [PLL_OFF_USER_CTL] = 0x0c, + [PLL_OFF_USER_CTL_U] = 0x10, + [PLL_OFF_USER_CTL_U1] = 0x14, + [PLL_OFF_CONFIG_CTL] = 0x18, + [PLL_OFF_CONFIG_CTL_U] = 0x1c, + [PLL_OFF_CONFIG_CTL_U1] = 0x20, + [PLL_OFF_TEST_CTL] = 0x24, + [PLL_OFF_TEST_CTL_U] = 0x28, + [PLL_OFF_STATUS] = 0x30, + [PLL_OFF_OPMODE] = 0x38, + [PLL_OFF_ALPHA_VAL] = 0x40, + [PLL_OFF_CAL_VAL] = 0x44, + }, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); @@ -120,6 +140,10 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); #define FABIA_PLL_OUT_MASK 0x7 #define FABIA_PLL_RATE_MARGIN 500 +#define TRION_PLL_STANDBY 0x0 +#define TRION_PLL_RUN 0x1 +#define TRION_PLL_OUT_MASK 0x7 + #define pll_alpha_width(p) \ ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH) @@ -730,6 +754,130 @@ static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate, return alpha_huayra_pll_round_rate(rate, *prate, &l, &a); } +static int trion_pll_is_enabled(struct clk_alpha_pll *pll, + struct regmap *regmap) +{ + u32 mode_regval, opmode_regval; + int ret; + + ret = regmap_read(regmap, PLL_MODE(pll), &mode_regval); + ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_regval); + if (ret) + return 0; + + return ((opmode_regval & TRION_PLL_RUN) && (mode_regval & PLL_OUTCTRL)); +} + +static int clk_trion_pll_is_enabled(struct clk_hw *hw) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + + return trion_pll_is_enabled(pll, pll->clkr.regmap); +} + +static int clk_trion_pll_enable(struct clk_hw *hw) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + struct regmap *regmap = pll->clkr.regmap; + u32 val; + int ret; + + ret = regmap_read(regmap, PLL_MODE(pll), &val); + if (ret) + return ret; + + /* If in FSM mode, just vote for it */ + if (val & PLL_VOTE_FSM_ENA) { + ret = clk_enable_regmap(hw); + if (ret) + return ret; + return wait_for_pll_enable_active(pll); + } + + /* Set operation mode to RUN */ + regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_RUN); + + ret = wait_for_pll_enable_lock(pll); + if (ret) + return ret; + + /* Enable the PLL outputs */ + ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), + TRION_PLL_OUT_MASK, TRION_PLL_OUT_MASK); + if (ret) + return ret; + + /* Enable the global PLL outputs */ + return regmap_update_bits(regmap, PLL_MODE(pll), + PLL_OUTCTRL, PLL_OUTCTRL); +} + +static void clk_trion_pll_disable(struct clk_hw *hw) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + struct regmap *regmap = pll->clkr.regmap; + u32 val; + int ret; + + ret = regmap_read(regmap, PLL_MODE(pll), &val); + if (ret) + return; + + /* If in FSM mode, just unvote it */ + if (val & PLL_VOTE_FSM_ENA) { + clk_disable_regmap(hw); + return; + } + + /* Disable the global PLL output */ + ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); + if (ret) + return; + + /* Disable the PLL outputs */ + ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), + TRION_PLL_OUT_MASK, 0); + if (ret) + return; + + /* Place the PLL mode in STANDBY */ + regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_STANDBY); + regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); +} + +static unsigned long +clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + struct regmap *regmap = pll->clkr.regmap; + u32 l, frac; + u64 prate = parent_rate; + + regmap_read(regmap, PLL_L_VAL(pll), &l); + regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac); + + return alpha_pll_calc_rate(prate, l, frac, ALPHA_REG_16BIT_WIDTH); +} + +static long clk_trion_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + unsigned long min_freq, max_freq; + u32 l; + u64 a; + + rate = alpha_pll_round_rate(rate, *prate, + &l, &a, ALPHA_REG_16BIT_WIDTH); + if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) + return rate; + + min_freq = pll->vco_table[0].min_freq; + max_freq = pll->vco_table[pll->num_vco - 1].max_freq; + + return clamp(rate, min_freq, max_freq); +} + const struct clk_ops clk_alpha_pll_ops = { .enable = clk_alpha_pll_enable, .disable = clk_alpha_pll_disable, @@ -760,6 +908,15 @@ const struct clk_ops clk_alpha_pll_hwfsm_ops = { }; EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops); +const struct clk_ops clk_trion_fixed_pll_ops = { + .enable = clk_trion_pll_enable, + .disable = clk_trion_pll_disable, + .is_enabled = clk_trion_pll_is_enabled, + .recalc_rate = clk_trion_pll_recalc_rate, + .round_rate = clk_trion_pll_round_rate, +}; +EXPORT_SYMBOL_GPL(clk_trion_fixed_pll_ops); + static unsigned long clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -1053,6 +1210,77 @@ static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw, return (parent_rate / div); } +static unsigned long +clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); + struct regmap *regmap = pll->clkr.regmap; + u32 i, div = 1, val; + + regmap_read(regmap, PLL_USER_CTL(pll), &val); + + val >>= pll->post_div_shift; + val &= PLL_POST_DIV_MASK(pll); + + for (i = 0; i < pll->num_post_div; i++) { + if (pll->post_div_table[i].val == val) { + div = pll->post_div_table[i].div; + break; + } + } + + return (parent_rate / div); +} + +static long +clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); + + return divider_round_rate(hw, rate, prate, pll->post_div_table, + pll->width, CLK_DIVIDER_ROUND_CLOSEST); +}; + +static int +clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); + struct regmap *regmap = pll->clkr.regmap; + int i, val = 0, div, ret; + + /* + * If the PLL is in FSM mode, then treat the set_rate callback + * as a no-operation. + */ + ret = regmap_read(regmap, PLL_MODE(pll), &val); + if (ret) + return ret; + + if (val & PLL_VOTE_FSM_ENA) + return 0; + + div = DIV_ROUND_UP_ULL(parent_rate, rate); + for (i = 0; i < pll->num_post_div; i++) { + if (pll->post_div_table[i].div == div) { + val = pll->post_div_table[i].val; + break; + } + } + + return regmap_update_bits(regmap, PLL_USER_CTL(pll), + PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, + val << PLL_POST_DIV_SHIFT); +} + +const struct clk_ops clk_trion_pll_postdiv_ops = { + .recalc_rate = clk_trion_pll_postdiv_recalc_rate, + .round_rate = clk_trion_pll_postdiv_round_rate, + .set_rate = clk_trion_pll_postdiv_set_rate, +}; +EXPORT_SYMBOL_GPL(clk_trion_pll_postdiv_ops); + static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 66755f0f84fc..15f27f4b06df 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -13,22 +13,27 @@ enum { CLK_ALPHA_PLL_TYPE_HUAYRA, CLK_ALPHA_PLL_TYPE_BRAMMO, CLK_ALPHA_PLL_TYPE_FABIA, + CLK_ALPHA_PLL_TYPE_TRION, CLK_ALPHA_PLL_TYPE_MAX, }; enum { PLL_OFF_L_VAL, + PLL_OFF_CAL_L_VAL, PLL_OFF_ALPHA_VAL, PLL_OFF_ALPHA_VAL_U, PLL_OFF_USER_CTL, PLL_OFF_USER_CTL_U, + PLL_OFF_USER_CTL_U1, PLL_OFF_CONFIG_CTL, PLL_OFF_CONFIG_CTL_U, + PLL_OFF_CONFIG_CTL_U1, PLL_OFF_TEST_CTL, PLL_OFF_TEST_CTL_U, PLL_OFF_STATUS, PLL_OFF_OPMODE, PLL_OFF_FRAC, + PLL_OFF_CAL_VAL, PLL_OFF_MAX_REGS }; @@ -117,5 +122,7 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); +extern const struct clk_ops clk_trion_fixed_pll_ops; +extern const struct clk_ops clk_trion_pll_postdiv_ops; #endif