From patchwork Wed May 24 12:35:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 685449 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6DA83C77B73 for ; Wed, 24 May 2023 12:35:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233732AbjEXMfz (ORCPT ); Wed, 24 May 2023 08:35:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55016 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229611AbjEXMfy (ORCPT ); Wed, 24 May 2023 08:35:54 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7471F1A1; Wed, 24 May 2023 05:35:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1684931752; x=1716467752; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=svc+MUbCNh1HWMRjrkRtGTVh6jhiE35L5mkZPeE4ezc=; b=2NTlpjO5jcKVSP++iKsqD6s6EawOZp3tVPj8Xy8HDVAqYfZ7HSLQXC6a VcVDdaYooewHTBKSyy/cV89WaZJixnB9G5EcyCzwoSpoCSyg0mkmHG0h8 hXWA4zszsyAFNis2rGmroxN1tymkzjC5OIkWyO1aaPovELVIl7adPp8G5 MWok+pF9FRQ3bV+IiGFbF+fiCRo31f9o1ywnvC25MMezdkEsnQC2uL1u3 lC41UJHPR8x3SO4l9/231IRAV6Hi0LACTu3E1XfgXfBoNmG2ICv5Dplxs zNHNVyNZJUpqNn685kJtFbI0cmolbfnwhMUY2k3Hg5gpBtE3zJWfI84LW w==; X-IronPort-AV: E=Sophos;i="6.00,189,1681196400"; d="scan'208";a="214683067" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 24 May 2023 05:35:51 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Wed, 24 May 2023 05:35:51 -0700 Received: from m18063-ThinkPad-T460p.mchp-main.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Wed, 24 May 2023 05:35:48 -0700 From: Claudiu Beznea To: , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH v2 3/4] dt-bindings: power: reset: atmel,sama5d2-shdwc: convert to yaml Date: Wed, 24 May 2023 15:35:27 +0300 Message-ID: <20230524123528.439082-4-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230524123528.439082-1-claudiu.beznea@microchip.com> References: <20230524123528.439082-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert Atmel SAMA5D2 shutdown controller to YAML. SAMA7G5 SHDWC DT node (available in arch/arm/boot/dts/sama7g5.dtsi) has syscon along with its compatible. There is no usage of this syscon in the current code but it may be necessary in future as some registers of SHDWC are accessed in different drivers (at91-sama5d2_shdwc.c and arch/arm/mach-at91/pm.c). Thus update the YAML with it to make DT checkers happy. Signed-off-by: Claudiu Beznea --- .../devicetree/bindings/arm/atmel-sysregs.txt | 63 ---------- .../power/reset/atmel,sama5d2-shdwc.yaml | 115 ++++++++++++++++++ 2 files changed, 115 insertions(+), 63 deletions(-) create mode 100644 Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index e6b2fb291b45..67a66bf74895 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -52,69 +52,6 @@ Example: reg = <0xe3804000 0x1000>; }; -SHDWC SAMA5D2-Compatible Shutdown Controller - -1) shdwc node - -required properties: -- compatible: should be "atmel,sama5d2-shdwc", "microchip,sam9x60-shdwc" or - "microchip,sama7g5-shdwc" -- reg: should contain registers location and length -- clocks: phandle to input clock. -- #address-cells: should be one. The cell is the wake-up input index. -- #size-cells: should be zero. - -optional properties: - -- debounce-delay-us: minimum wake-up inputs debouncer period in - microseconds. It's usually a board-related property. -- atmel,wakeup-rtc-timer: boolean to enable Real-Time Clock wake-up. - -optional microchip,sam9x60-shdwc or microchip,sama7g5-shdwc properties: -- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. - -The node contains child nodes for each wake-up input that the platform uses. - -2) input nodes - -Wake-up input nodes are usually described in the "board" part of the Device -Tree. Note also that input 0 is linked to the wake-up pin and is frequently -used. - -Required properties: -- reg: should contain the wake-up input index [0 - 15]. - -Optional properties: -- atmel,wakeup-active-high: boolean, the corresponding wake-up input described - by the child, forces the wake-up of the core power supply on a high level. - The default is to be active low. - -Example: - -On the SoC side: - shdwc@f8048010 { - compatible = "atmel,sama5d2-shdwc"; - reg = <0xf8048010 0x10>; - clocks = <&clk32k>; - #address-cells = <1>; - #size-cells = <0>; - atmel,wakeup-rtc-timer; - }; - -On the board side: - shdwc@f8048010 { - debounce-delay-us = <976>; - - input@0 { - reg = <0>; - }; - - input@1 { - reg = <1>; - atmel,wakeup-active-high; - }; - }; - Special Function Registers (SFR) Special Function Registers (SFR) manage specific aspects of the integrated diff --git a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml new file mode 100644 index 000000000000..31a16a354a3a --- /dev/null +++ b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/reset/atmel,sama5d2-shdwc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel SAMA5D2 SHDWC Shutdown Controller + +maintainers: + - Claudiu Beznea + +description: + Atmel SHDWC shutdown controller controls the power supplies VDDIO and VDDCORE + and the wake-up detection on debounced input lines. + +properties: + compatible: + oneOf: + - items: + - const: microchip,sama7g5-shdwc + - const: syscon + - items: + enum: + - atmel,sama5d2-shdwc + - microchip,sam9x60-shdwc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + debounce-delay-us: + description: + Minimum wake-up inputs debouncer period in microseconds. It is usually a + board-related property. + + atmel,wakeup-rtc-timer: + description: enable real-time clock wake-up + type: boolean + +patternProperties: + "^input@[0-15]$": + description: + Wake-up input nodes. These are usually described in the "board" part of + the Device Tree. Note also that input 0 is linked to the wake-up pin and + is frequently used. + type: object + properties: + reg: + description: contains the wake-up input index + minimum: 0 + maximum: 15 + + atmel,wakeup-active-high: + description: + The corresponding wake-up input described by the child forces the + wake-up of the core power supply on a high level. The default is to + be active low. + type: boolean + + required: + - reg + + additionalProperties: false + +required: + - compatible + - reg + - clocks + +allOf: + - if: + properties: + compatible: + contains: + enum: + - microchip,sam9x60-shdwc + - microchip,sama7g5-shdwc + then: + properties: + atmel,wakeup-rtt-timer: + description: enable real-time timer wake-up + type: boolean + +unevaluatedProperties: false + +examples: + - | + shdwc: poweroff@f8048010 { + compatible = "atmel,sama5d2-shdwc"; + reg = <0xf8048010 0x10>; + clocks = <&clk32k>; + #address-cells = <1>; + #size-cells = <0>; + atmel,wakeup-rtc-timer; + debounce-delay-us = <976>; + + input@0 { + reg = <0>; + }; + + input@1 { + reg = <1>; + atmel,wakeup-active-high; + }; + }; + +... From patchwork Wed May 24 12:35:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 685448 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9578DC7EE23 for ; Wed, 24 May 2023 12:36:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233961AbjEXMgP (ORCPT ); Wed, 24 May 2023 08:36:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55404 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233936AbjEXMgK (ORCPT ); Wed, 24 May 2023 08:36:10 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 28963135; Wed, 24 May 2023 05:36:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1684931761; x=1716467761; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hX0vBHxCDkOd3pRwjtiOcZRwcusvy0J39jQkffoEfYY=; b=Nea7OuSvTKoz5lOcEKauR8MoCAlE8XXA+FaN2eJn8Qon4TXK7RdYVzTe 65j9JELXtOOAZEdW/omX7DxV1IBvPTMU4zYKRph8uPWZyXZJ9hMcqadZC AzeOVB0Y36xotRJpqa1rhSlf4Rr4v6tsgRkxAkE/HJJZe7J5RBOsaO9+i F+/+6drivFlxY+a1ih4jOx/y6KP+yhlnQCw6uX2KM8jNkG8mLs11CrU2j g/QNTaIb/jVDzGm7C3kVWHjFps8UOSC4uSZNNEash1O8RMe5l3c3ddWis uzW6g1BXlTGGIekYcaTZDMoVjlCzy8tBLu0ZI6BJGz9tavXEJnItR5F9r A==; X-IronPort-AV: E=Sophos;i="6.00,189,1681196400"; d="scan'208";a="214683144" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 24 May 2023 05:36:00 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Wed, 24 May 2023 05:35:55 -0700 Received: from m18063-ThinkPad-T460p.mchp-main.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Wed, 24 May 2023 05:35:52 -0700 From: Claudiu Beznea To: , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH v2 4/4] MAINTAINERS: add documentation file for Microchip SAMA5D2 shutdown controller Date: Wed, 24 May 2023 15:35:28 +0300 Message-ID: <20230524123528.439082-5-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230524123528.439082-1-claudiu.beznea@microchip.com> References: <20230524123528.439082-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add documentation file for SAMA5D2 shutdown controller. Signed-off-by: Claudiu Beznea --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 74a6b6b13d84..cdf4b41cf62b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13811,6 +13811,7 @@ F: include/dt-bindings/iio/adc/at91-sama5d2_adc.h MICROCHIP SAMA5D2-COMPATIBLE SHUTDOWN CONTROLLER M: Claudiu Beznea S: Supported +F: Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml F: drivers/power/reset/at91-sama5d2_shdwc.c MICROCHIP SPI DRIVER