From patchwork Fri Jun 14 03:07:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166739 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1505201ilk; Thu, 13 Jun 2019 20:11:58 -0700 (PDT) X-Google-Smtp-Source: APXvYqwtQmvRbPAmaU38E7qbWeN4VKChlC2r+I/0Zxro46/YCNMIqaQPgpvf1C4LGr9N/lE8h99J X-Received: by 2002:a17:90a:d582:: with SMTP id v2mr8456498pju.22.1560481918178; Thu, 13 Jun 2019 20:11:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560481918; cv=none; d=google.com; s=arc-20160816; b=U17x9Stc5r3iCHmXVPCA03/73KDN2q5H7ZwTwl3W8eSsIXmR9aVD3DwQJqstenP4t7 z0u1x3gMSs99tfaxPB1piOhCDkhZDvO+gFRrlSmhxY4q91tPFvNEwUCVnM5rWGpNgdKw TffdAcJMI1v9sx3tYOik0obDU71dsRP6iQ/xvdAFsX5qtNxF+fPI+0gSGn0AQshlXAFB D5aFuP2Ta3X9AMHmWPEY/4osyrjM1wPgBi2cP4ch6eIbzev8p+4KSOk4t3uGc9eShAra HgVnq73vfjIbX6FHCX1kR0w3qVUQygyfoo/ea0ESdNQLGc4eCm5cXWZVQJTHCzgArYhb SJMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=t+8ZINgorfc9/vHqnYTLmiCH63MmZJ4ah1lcUclNBnY=; b=dPfd+zCQnUStLtibBLCNWz+apqrx05vP00zPxCn3Hn7HS5s/1ASLg/N5QtPgWsVIss VHXAoZoH4s1Bsgc2BxsbgtTj06lR3gA5NDKYZEDDypmqwAOrqJIe35SiGTtSEQQsgUnj awcXy+yFpLbmdQP6xJSwA6EXtPPFzqweTEDbI+ns66TVS9j8vskuunq48yifJaQBUIoc zzJHXhciNccH2ywEJ+ueJnC5L70Zs6d3YZkZ0r9JS6H4V+u0ZIWBa1+14L/KIWB4kXHm ZbZbTdragVZl4LqZ4IF+sPDw0ASkU5Nv3z2EDVzjIiKbpbaCLNV/MxMzUdId7m1n8ZHm hvjA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sNIF4Taq; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e8si1073936plb.420.2019.06.13.20.11.57; Thu, 13 Jun 2019 20:11:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sNIF4Taq; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725834AbfFNDL5 (ORCPT + 14 others); Thu, 13 Jun 2019 23:11:57 -0400 Received: from mail-pg1-f193.google.com ([209.85.215.193]:42573 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725819AbfFNDL5 (ORCPT ); Thu, 13 Jun 2019 23:11:57 -0400 Received: by mail-pg1-f193.google.com with SMTP id l19so664578pgh.9 for ; Thu, 13 Jun 2019 20:11:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=t+8ZINgorfc9/vHqnYTLmiCH63MmZJ4ah1lcUclNBnY=; b=sNIF4TaqtWZx+SWXbKFuSQaAHyH/3etk8jvo0f9cyStxOLJ7UvQrp3TwDEOw197rwO 98mN3sbimtbmJkPhi84RBjFB0UN2qrwienlr/AJgSjaPpIAWaX+3frMl5trjF+1LjlC7 k+5S98Sj+bieeo9G1hY6QVkFVZW1w6gGdz/v0owtlM8lV/YHFr9ZDCWLMyLz6Arljf+h zQc27CMZcJzoHdGRaiI2x8pU1bCcsCzzCi4eepW4MYwrdIcpbHUUBM1gMzCjZ8yFVNPi D7GLLGrHEi/XtWbRyH7DR9nFwnu6aPy2106vuNB4XahxgkFzg4j79VhVCpyfl8td3Jq4 3I6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=t+8ZINgorfc9/vHqnYTLmiCH63MmZJ4ah1lcUclNBnY=; b=g8faW3pzzh6ysNe7APshV+SMr4wcjxtBa4i9CFwKyWZdE3HltGxErktOOKztoIHB69 49NblGhnP90uNHp7sNNUBkiDUDWBwR/nlfq0Q8t14hrJ4xJnlwL+QscaY8zP7ZjtdZ/D rQ74QgPQJ3EWEwvYgxPMw05p5AgTYqAutEQzOdmdSCx9JPjK4mgwHB3znRzfuyel8EKL iz1jGYK4Uigua04N/4zPnETQELSN45djH/Pm8nDVQavWvGYTz7ykHxj8MGmovzaIQOCA JoakgC+HutdxaucOlIm/pdPZn+iT1V6JTWfLaZTJNut9aUzRNR0VWMgab0RDm90euZ5M SmJQ== X-Gm-Message-State: APjAAAWbOoS3cxVhp2KCHCn41xNbub8wIPn0OkdY64UsnGOvG5lK4csW 6+EGKMAdbsW554nDJEChVZU/zg== X-Received: by 2002:a17:90a:19d:: with SMTP id 29mr8971505pjc.71.1560481916646; Thu, 13 Jun 2019 20:11:56 -0700 (PDT) Received: from localhost ([122.172.66.84]) by smtp.gmail.com with ESMTPSA id 12sm1107859pgw.55.2019.06.13.20.11.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jun 2019 20:11:56 -0700 (PDT) From: Viresh Kumar To: linux-arm-kernel@lists.infradead.org, Julien Thierry Cc: Viresh Kumar , stable@vger.kernel.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 01/45] arm64: barrier: Add CSDB macros to control data-value prediction Date: Fri, 14 Jun 2019 08:37:44 +0530 Message-Id: <9cbf3ace67c45ddb00ea1a1567d20f6954fbc15e.1560480942.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Will Deacon commit 669474e772b952b14f4de4845a1558fd4c0414a4 upstream. For CPUs capable of data value prediction, CSDB waits for any outstanding predictions to architecturally resolve before allowing speculative execution to continue. Provide macros to expose it to the arch code. Reviewed-by: Mark Rutland Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/assembler.h | 7 +++++++ arch/arm64/include/asm/barrier.h | 2 ++ 2 files changed, 9 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index f68abb17aa4b..683c2875278f 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -95,6 +95,13 @@ dmb \opt .endm +/* + * Value prediction barrier + */ + .macro csdb + hint #20 + .endm + #define USER(l, x...) \ 9999: x; \ .section __ex_table,"a"; \ diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h index f2d2c0bbe21b..574486634c62 100644 --- a/arch/arm64/include/asm/barrier.h +++ b/arch/arm64/include/asm/barrier.h @@ -28,6 +28,8 @@ #define dmb(opt) asm volatile("dmb " #opt : : : "memory") #define dsb(opt) asm volatile("dsb " #opt : : : "memory") +#define csdb() asm volatile("hint #20" : : : "memory") + #define mb() dsb(sy) #define rmb() dsb(ld) #define wmb() dsb(st) From patchwork Fri Jun 14 03:07:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166740 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1505231ilk; Thu, 13 Jun 2019 20:12:01 -0700 (PDT) X-Google-Smtp-Source: APXvYqzLhMdWiLQlaVXQpzzOhnTqeH0O+KRg9mBDmXop5aOcYL2mqDrkJQ0vIxRYn1dScCoueZJR X-Received: by 2002:a63:d512:: with SMTP id c18mr11620464pgg.239.1560481921391; Thu, 13 Jun 2019 20:12:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560481921; cv=none; d=google.com; s=arc-20160816; b=X3jYDN+UcKl9rvX9KhucQhIlS6qy4tXC2zOBZ5IwktvQ15+hNbFYKboOpwd/Eeudgc //0LuzmchGw83CFMoa+noEZxSDIx+Z1OCEgF6iDNONbIFUUw0fYqDtpeqvaTPQGVc8YQ LA6OMZBliMStRGPtBrxYQjSpiB4xhaKwxTgtuZq7Hygzia8TxCc03L79SI4YB+aGBiGt kJKCJtO0rO6W8qRaJNy0lWlcspGgOTEZpjB8mpSH+tJRBC9GW8oozu+DKaFe5MGRcvZE IDuMA0hmCehLzZ/WcxxEfRyAEG9VsWxjM2Kvxs1REDgueuLlvgtoRhqNYXwPcRY2nlbk JDBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=QZmd1kVLh8a0enxFfoIC/p5hW82ft4CjkM7ASI4iKD4=; b=uNOEfMolB+5Deb+U3pmguX0eUAGMmfDLWVIEPK/4zNrLVhwgoPej6MrlQGX7cdlOwD v6K2khRGL9iWeS99bVu98EBAZnMKW3ko/EBCE8jbbuduj371nbl/5XdVCxLBh2xgU7vy TakhwsphOT8Va2npvFXHniNG2JZDWrr4d/mtXFK5FwtBVQwpkvmae6jkddtRD7oEZWf/ 07UpoSsKjqPGxRjSIoKAq1+V4ZV9Fb6dndM8IqnZQ9HWRwaZ7FE1mNgS/BcKRxvghH9C GFquwnVSGn2ayl4EFHRKZVEbHDkPcMe7RBiE3BOlgAUYhIzxGTp2OXP3HCJ44tH1zAIu pm0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EvZ8YJG4; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Provide an optimised, assembly implementation of array_index_mask_nospec() for arm64 so that the compiler is not in a position to transform the code in ways which affect its ability to inhibit speculation (e.g. by introducing conditional branches). This is similar to the sequence used by x86, modulo architectural differences in the carry/borrow flags. Reviewed-by: Mark Rutland Signed-off-by: Robin Murphy Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/barrier.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h index 574486634c62..7c25e3e11b6d 100644 --- a/arch/arm64/include/asm/barrier.h +++ b/arch/arm64/include/asm/barrier.h @@ -37,6 +37,27 @@ #define dma_rmb() dmb(oshld) #define dma_wmb() dmb(oshst) +/* + * Generate a mask for array_index__nospec() that is ~0UL when 0 <= idx < sz + * and 0 otherwise. + */ +#define array_index_mask_nospec array_index_mask_nospec +static inline unsigned long array_index_mask_nospec(unsigned long idx, + unsigned long sz) +{ + unsigned long mask; + + asm volatile( + " cmp %1, %2\n" + " sbc %0, xzr, xzr\n" + : "=r" (mask) + : "r" (idx), "Ir" (sz) + : "cc"); + + csdb(); + return mask; +} + #define smp_mb() dmb(ish) #define smp_rmb() dmb(ishld) #define smp_wmb() dmb(ishst) From patchwork Fri Jun 14 03:07:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166741 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1505260ilk; Thu, 13 Jun 2019 20:12:03 -0700 (PDT) X-Google-Smtp-Source: APXvYqzK4ILd7TI6WW066QncsgTp+fKnTqvVutiMYTZAOjtqPPtrloV4hWscQyIF3Bf6M/Wx/aEN X-Received: by 2002:a17:90a:fa07:: with SMTP id cm7mr8855994pjb.115.1560481923901; Thu, 13 Jun 2019 20:12:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560481923; cv=none; d=google.com; s=arc-20160816; b=jirs3yHegUAN/N4yDHsHMmUeS++v197fH40Dj3SEmoxbw6MrrDNEeEk8GjwqAjhYTD 6DhSD09z+ELROWBb4wllFSGaUffajGYYzpFSCpc8UdZoHjCn7rQf3yRxJCxi4/V/Fvyn ostOcofw5Dex+jHi1pD7WHRUHeAM8pkJPh1owUUHNyELED9PnYGEbmidgJr9ZCmdvzSr nbYsHBSApJcH2LScbg2dgOV4oqzO8m+a5usFI6E0+mWApq47Qvd4xz9LsE+6gM3CrNpE VWxLMUUA5YTO/YNV1fB6LzgQYzJ6MTApE89Nq0FSg8tKBg6zyWh1FhR0ckbhqSVlAHlT bJFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=q2UDagaQQzh/lIVkivR+vaM0gPa+GGbgrufLmqcYVmM=; b=CL/kaxu0xEWdPYJgXc86OGqAcxOzJpc0pGGi/5WuDv6OAaKvLMU0c7Cz/wE1OoTBGP m0WR7f2so/K+bvWCc3pw1G+F3Mbj6rKaju2ikCxGELMDDrOCqgikQkDn6RJdawXAwW6p pc8hHaVi04mfx4Xs84ZQGujvn66oipSnwDP7Vjx3CPCB/62PI0Tz8c1iLEl0Xx20cIdW eH4u57cZVY9nmU+6h9flCLC5tWCeFRwMAGMwFwCZusmlJJmSIqy69Lgjmj/XpAjPizhF Zqz7stLYQNjalUYYk0VZ8hPNt7FZws0bn3OyyKzVN8TDnw6t0mj/dmXzNoImSWw5uc5V 4boA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=z3CUixoa; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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ILP32 series [1] introduces the dependency on for TASK_SIZE macro. Which in turn requires , and include , giving a circular dependency, because TASK_SIZE is currently located in . In other architectures, TASK_SIZE is defined in , and moving TASK_SIZE there fixes the problem. Discussion: https://patchwork.kernel.org/patch/9929107/ [1] https://github.com/norov/linux/tree/ilp32-next CC: Will Deacon CC: Laura Abbott Cc: Ard Biesheuvel Cc: Catalin Marinas Cc: James Morse Suggested-by: Mark Rutland Signed-off-by: Yury Norov Signed-off-by: Will Deacon Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/memory.h | 15 --------------- arch/arm64/include/asm/processor.h | 21 +++++++++++++++++++++ arch/arm64/kernel/entry.S | 2 +- 3 files changed, 22 insertions(+), 16 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h index b42b930cc19a..959a1e9188fe 100644 --- a/arch/arm64/include/asm/memory.h +++ b/arch/arm64/include/asm/memory.h @@ -43,8 +43,6 @@ * (VA_BITS - 1)) * VA_BITS - the maximum number of bits for virtual addresses. * VA_START - the first kernel virtual address. - * TASK_SIZE - the maximum size of a user space task. - * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area. * The module space lives between the addresses given by TASK_SIZE * and PAGE_OFFSET - it must be within 128MB of the kernel text. */ @@ -58,19 +56,6 @@ #define PCI_IO_END (MODULES_VADDR - SZ_2M) #define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE) #define FIXADDR_TOP (PCI_IO_START - SZ_2M) -#define TASK_SIZE_64 (UL(1) << VA_BITS) - -#ifdef CONFIG_COMPAT -#define TASK_SIZE_32 UL(0x100000000) -#define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \ - TASK_SIZE_32 : TASK_SIZE_64) -#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \ - TASK_SIZE_32 : TASK_SIZE_64) -#else -#define TASK_SIZE TASK_SIZE_64 -#endif /* CONFIG_COMPAT */ - -#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 4)) /* * Physical vs virtual RAM address space conversion. These are diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index b1126eea73ae..12d5b2b97f04 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -19,6 +19,10 @@ #ifndef __ASM_PROCESSOR_H #define __ASM_PROCESSOR_H +#define TASK_SIZE_64 (UL(1) << VA_BITS) + +#ifndef __ASSEMBLY__ + /* * Default implementation of macro that returns current * instruction pointer ("program counter"). @@ -35,6 +39,22 @@ #include #include +/* + * TASK_SIZE - the maximum size of a user space task. + * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area. + */ +#ifdef CONFIG_COMPAT +#define TASK_SIZE_32 UL(0x100000000) +#define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \ + TASK_SIZE_32 : TASK_SIZE_64) +#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \ + TASK_SIZE_32 : TASK_SIZE_64) +#else +#define TASK_SIZE TASK_SIZE_64 +#endif /* CONFIG_COMPAT */ + +#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 4)) + #define STACK_TOP_MAX TASK_SIZE_64 #ifdef CONFIG_COMPAT #define AARCH32_VECTORS_BASE 0xffff0000 @@ -186,4 +206,5 @@ static inline void spin_lock_prefetch(const void *x) int cpu_enable_pan(void *__unused); +#endif /* __ASSEMBLY__ */ #endif /* __ASM_PROCESSOR_H */ diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 586326981769..c849be9231bb 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -27,7 +27,7 @@ #include #include #include -#include +#include #include #include #include From patchwork Fri Jun 14 03:07:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166743 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1505315ilk; Thu, 13 Jun 2019 20:12:09 -0700 (PDT) X-Google-Smtp-Source: APXvYqxr5bkifMOhD3DbCUQ7sA/yQPgdBLP5p3xEeCtHCF+bHJRIwBQ7g/awcZmaicl2XMXU4eCA X-Received: by 2002:a17:902:860c:: with SMTP id f12mr91338980plo.127.1560481929796; Thu, 13 Jun 2019 20:12:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560481929; cv=none; d=google.com; s=arc-20160816; b=Wrvbd+aDeszincOG2zs7ahVFNAU1EVYU9FweRlB84YdlYSVZ2ZDDh4/6TCiba1vxb6 MlMXsLWsx9d0SxXbXc8rJToNqgHHFHVaVH0YJo+8gLqrqtCywCmkdHsAOcW3FC76D5Fy KA8YWGB6kDBVx1AFmSM3Mqglak01K8psRISqcmFcfrsu7HJIipNIxvzw+a5Ii9iB+3e3 FjEmTPBP+laMS/MJOnGg/FcswKUCkLqheR8yUU9sVCldJ6EBu219GzrcQa5lj2oA4aIp aitU8hl7TIyj26k46pPo5I6j0WzehBJ+NS3IzCAoDar3pw5ahAtgDZIAt/dF+SqKj11d Pejg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=jM3DSSQ5QlZXEONoZT9K+P8C++Y23zetJjpY6WsFYS8=; b=UAgJMFWtiGxXjnMce5d9RXqI+xkmVS6WX3afUAm0Q85dUR8nEpusQFuwHk0BkQTcYt ex//943hR+sHJFsdEpGNjgO+EZVeMk/k2NrZ1Hn5Ry1phIfdN+5T9Lva7TmrzUKttJ42 /DP6jbCWE8rTT4H4vk/33n0lqmw5igj+gIYAHEYoGPn+V1CXucCPY4Us+Pr+aHvkbMvN /sJAUtHp4tefFRneDNrH91KqPG23B3/cVnrlk+Y9Zg7X5MB7P5Gs8MVuJ37F5wJ+Jvj8 7Gg9CxTTvSenztRnOvRtHv6eX34G+O15RHVp5rKK8rhYerVr3snPLuWx8HqzjneaVUeQ RxQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hBCJXZ9T; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e8si1073936plb.420.2019.06.13.20.12.09; Thu, 13 Jun 2019 20:12:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hBCJXZ9T; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725868AbfFNDMJ (ORCPT + 14 others); Thu, 13 Jun 2019 23:12:09 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:45611 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725819AbfFNDMJ (ORCPT ); Thu, 13 Jun 2019 23:12:09 -0400 Received: by mail-pf1-f194.google.com with SMTP id r1so476411pfq.12 for ; Thu, 13 Jun 2019 20:12:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jM3DSSQ5QlZXEONoZT9K+P8C++Y23zetJjpY6WsFYS8=; b=hBCJXZ9T5rigkGtisPLeaNWQAqyrRUj2ZgHPm2y7iDH6diBfYxhmzU8hOKt3ZaXamK 2Y1OGoXRoCAyflZlrfyE5IE48ZTOh8LM2OefFE5Hf+DNft2GN4OqskqBGJGsmugNMdFt zBEOm41x2PhNvmk0ARTG4AVFrStmDOxF/T9Rt9tNs9bKaaQ8ERB0NIlaWVvRxvqwEayX iLI/2ihNHk1NZ9eAlfuHKsihkm2KIHRT3d2QNEZv5sZx+XWTM8KFPOnsl82rRx9Qt5XT WNuhFgOeqQo/1ujIDrC/tQQx4oz5TCckXqLulhZWVW5SX/U+V/cniN5fSXvOdIQ5VkP+ UqsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jM3DSSQ5QlZXEONoZT9K+P8C++Y23zetJjpY6WsFYS8=; b=UDmbb2B4eNmAHyMKq5OnLBisUmKX2g7UPY9Gyc+fK9e0npRWlhuSuJO4QBCnxuk2Xx LQUQ3QSQtEo4xKIF9LrO3Ssp9pXf8t+8nfL0+jJ3/lZVsjwYKKLXs54lbmaBmaVIay5e po7OS1uUVeZbpcidbGtSCOpNytDD/GSIrZeNgxNMgJgUf46/qYvcb7ZZkrPPyQ71XI0I QM3OffSeXwrhhm7mb4iXGFg9NkazuM60W/uw4spn+p6ZQf4Ytc85DBwJ6f7gI3SMiaZu dRtx9CF5bZ3dFdcaygEDZtaSmmjVqCJ/xlWtRjxGA8T3tlWdU7o61lUGlsAEgzdD7COI sZvw== X-Gm-Message-State: APjAAAVCzKA/rBI7WnIshc5gqfDdyafX6q4DZho9MtHrjqbfmTSEpg6Y t/rKMX0FynrPuqcQPJqCZW9YKg== X-Received: by 2002:aa7:8e54:: with SMTP id d20mr7531785pfr.16.1560481927612; Thu, 13 Jun 2019 20:12:07 -0700 (PDT) Received: from localhost ([122.172.66.84]) by smtp.gmail.com with ESMTPSA id l20sm1008268pff.102.2019.06.13.20.12.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jun 2019 20:12:07 -0700 (PDT) From: Viresh Kumar To: linux-arm-kernel@lists.infradead.org, Julien Thierry Cc: Viresh Kumar , stable@vger.kernel.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 05/45] arm64: Make USER_DS an inclusive limit Date: Fri, 14 Jun 2019 08:37:48 +0530 Message-Id: <86a5655ffd342f6f62ae1280cd5131868abfa6de.1560480942.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Robin Murphy commit 51369e398d0d33e8f524314e672b07e8cf870e79 upstream. Currently, USER_DS represents an exclusive limit while KERNEL_DS is inclusive. In order to do some clever trickery for speculation-safe masking, we need them both to behave equivalently - there aren't enough bits to make KERNEL_DS exclusive, so we have precisely one option. This also happens to correct a longstanding false negative for a range ending on the very top byte of kernel memory. Mark Rutland points out that we've actually got the semantics of addresses vs. segments muddled up in most of the places we need to amend, so shuffle the {USER,KERNEL}_DS definitions around such that we can correct those properly instead of just pasting "-1"s everywhere. Signed-off-by: Robin Murphy Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas [ 4.4: Dropped changes from fault.c and fixed minor rebase conflict ] Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/processor.h | 3 ++ arch/arm64/include/asm/uaccess.h | 45 +++++++++++++++++------------- arch/arm64/kernel/entry.S | 4 +-- 3 files changed, 31 insertions(+), 21 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index 12d5b2b97f04..c49597ae529d 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -21,6 +21,9 @@ #define TASK_SIZE_64 (UL(1) << VA_BITS) +#define KERNEL_DS UL(-1) +#define USER_DS (TASK_SIZE_64 - 1) + #ifndef __ASSEMBLY__ /* diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index 829fa6d3e561..c625cc5531fc 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -56,10 +56,7 @@ struct exception_table_entry extern int fixup_exception(struct pt_regs *regs); -#define KERNEL_DS (-1UL) #define get_ds() (KERNEL_DS) - -#define USER_DS TASK_SIZE_64 #define get_fs() (current_thread_info()->addr_limit) static inline void set_fs(mm_segment_t fs) @@ -87,22 +84,32 @@ static inline void set_fs(mm_segment_t fs) * Returns 1 if the range is valid, 0 otherwise. * * This is equivalent to the following test: - * (u65)addr + (u65)size <= current->addr_limit - * - * This needs 65-bit arithmetic. + * (u65)addr + (u65)size <= (u65)current->addr_limit + 1 */ -#define __range_ok(addr, size) \ -({ \ - unsigned long __addr = (unsigned long __force)(addr); \ - unsigned long flag, roksum; \ - __chk_user_ptr(addr); \ - asm("adds %1, %1, %3; ccmp %1, %4, #2, cc; cset %0, ls" \ - : "=&r" (flag), "=&r" (roksum) \ - : "1" (__addr), "Ir" (size), \ - "r" (current_thread_info()->addr_limit) \ - : "cc"); \ - flag; \ -}) +static inline unsigned long __range_ok(unsigned long addr, unsigned long size) +{ + unsigned long limit = current_thread_info()->addr_limit; + + __chk_user_ptr(addr); + asm volatile( + // A + B <= C + 1 for all A,B,C, in four easy steps: + // 1: X = A + B; X' = X % 2^64 + " adds %0, %0, %2\n" + // 2: Set C = 0 if X > 2^64, to guarantee X' > C in step 4 + " csel %1, xzr, %1, hi\n" + // 3: Set X' = ~0 if X >= 2^64. For X == 2^64, this decrements X' + // to compensate for the carry flag being set in step 4. For + // X > 2^64, X' merely has to remain nonzero, which it does. + " csinv %0, %0, xzr, cc\n" + // 4: For X < 2^64, this gives us X' - C - 1 <= 0, where the -1 + // comes from the carry in being clear. Otherwise, we are + // testing X' - C == 0, subject to the previous adjustments. + " sbcs xzr, %0, %1\n" + " cset %0, ls\n" + : "+r" (addr), "+r" (limit) : "Ir" (size) : "cc"); + + return addr; +} /* * When dealing with data aborts, watchpoints, or instruction traps we may end @@ -111,7 +118,7 @@ static inline void set_fs(mm_segment_t fs) */ #define untagged_addr(addr) sign_extend64(addr, 55) -#define access_ok(type, addr, size) __range_ok(addr, size) +#define access_ok(type, addr, size) __range_ok((unsigned long)(addr), size) #define user_addr_max get_fs /* diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index c849be9231bb..4c5013b09dcb 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -96,10 +96,10 @@ .else add x21, sp, #S_FRAME_SIZE get_thread_info tsk - /* Save the task's original addr_limit and set USER_DS (TASK_SIZE_64) */ + /* Save the task's original addr_limit and set USER_DS */ ldr x20, [tsk, #TI_ADDR_LIMIT] str x20, [sp, #S_ORIG_ADDR_LIMIT] - mov x20, #TASK_SIZE_64 + mov x20, #USER_DS str x20, [tsk, #TI_ADDR_LIMIT] .endif /* \el == 0 */ mrs x22, elr_el1 From patchwork Fri Jun 14 03:07:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166744 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1505340ilk; Thu, 13 Jun 2019 20:12:11 -0700 (PDT) X-Google-Smtp-Source: APXvYqxLrAjiGVsgw2f/gH9OZR0ID2oHslgB5NbKtIloQdxjeUbD8vSyKkvGNwcCgpOn6gPtbnv6 X-Received: by 2002:a17:902:e312:: with SMTP id cg18mr24143589plb.212.1560481931649; Thu, 13 Jun 2019 20:12:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560481931; cv=none; d=google.com; s=arc-20160816; b=C7hOY/JXaoF6r0SDJjqkLdYAbFPvTUaXjfKIjkrnZTLtPA0UcSr0aZw5mZVqFZD1ET 2NYWHJcjlQUDgbT/Knj5s73nw+fXIvW+3oQ5lJfPG4BgNdXp31ZExMleYVFPMSFM0VaD 3YsdbuV5GONL0WzliKv5NMe4EDF83rrEEYHNnyp+QvcrWW2hKresoM6DjN2rimFUuI8q Z2CFIAfWtR8wjm70cxskbvhbRU+Icj6Krw4MxBiwgG+ibgJHh0vg07MzFsMxKwLY42C/ eaf2BCZsG4woi1c8wIh9LWs++CqqDnUHk7dbMPmfQOHI7bg340HM2zssCBYF3aIadVlr GYsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=oplH30x1zLW/kw5XTQuFI7s72sVvdi1RahKBb4zAIVI=; b=IhiVjzQcC6CHEdFOBjGJEpNywJeOtVVUpDNfaNrdg3CoFVt/UrTSQPQcnmoZyMCO17 1stMk3wNuUZ91TfMMkJ/RWSv16IPt//jx0GxkJhrBpn1tnHaX+JDoze22SMbdHyV7tS5 2m04OsfGTIWpZDn3T85hFHVOcC4t4N4ZrBIhevdl/18pdRtgk6wEUpVO+wAIN3IX8+yb 9/w1mR7rr1blU80IaknbofdPVgx3h/7xV3ZB2lsHngrJzs7IInrDdMFqtBPhDwLh8JTw Q4lf0MM7oYSJ3t020D6LIcMlYK1hJc4GJCyAmBnM65UyDQyv/27ucnJPJGEr7JUELe+p H84w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Yzltk8JB; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e8si1073936plb.420.2019.06.13.20.12.11; Thu, 13 Jun 2019 20:12:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Yzltk8JB; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725942AbfFNDML (ORCPT + 14 others); Thu, 13 Jun 2019 23:12:11 -0400 Received: from mail-pf1-f193.google.com ([209.85.210.193]:35932 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725819AbfFNDMK (ORCPT ); Thu, 13 Jun 2019 23:12:10 -0400 Received: by mail-pf1-f193.google.com with SMTP id r7so499782pfl.3 for ; Thu, 13 Jun 2019 20:12:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oplH30x1zLW/kw5XTQuFI7s72sVvdi1RahKBb4zAIVI=; b=Yzltk8JB8mBXf0jZiiOn54g5/T0KcQ7kKV+UgQ9lpUwSlLs7Pt5kZUz7O8VRM5Gywr a6759AUaffVtNH/TQGwSHY5oA17fJKXMnvPoFyntQBTfIscQNfo17nFck1DVJjrDtGmA +OsNTrb2LaV2WQoX5sd/qPiJek55dGs814vb4bBwWTlq1ot6VHkqG7m98hfa/cY12zOZ NVjM5NrthLLacQzOfmEqJDxiugx32DoJGjZw/qboBQpDb5iGkEpwkxHwzJmyDijrFmnK zlGHBFAbNvl6JKVjnyBkeDwcgVbmq34wRQMm7GRnJ59Qelhe/pLC0cpTAsYd2dtksl3m bQxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oplH30x1zLW/kw5XTQuFI7s72sVvdi1RahKBb4zAIVI=; b=gxbg4wdEJPL7LAHOOen286EmXDz1Ot08WA4YDWzkDYAksMftUWLDhJ1jfbehxqRUkj 2z9yzeuBRyzbNMfM+aijXiK+Z43rjqS6enhmBx+Aa5W7rEk/clYkZsq561BYZve+hFzh xhYBu1vz0NxEVXH8iqO257kZGGk0Cleauy5C+2Giq13wukkI8C13RnWpwG5l5+aYcjQZ xUk/CskgK/ZDIjRHepBb0qouvxirPKn/w/bI7rqnmgiOd7WhnVMCFUuDhP5wpSFctxvt s7GgOB+awEQYkV/mww7iG2/FMvs/8nnXZ7SvQaYeSNJt2fFg7eOLOXC5+34B/F3LPBZ6 GGpw== X-Gm-Message-State: APjAAAW0CLpmvCxZcRE47ZVbVJtKFzjQCaCHJ1nvkGkW4boegOxx8621 6PeDgE/jCFKa42fX1AzbPhkfnA== X-Received: by 2002:a63:dc15:: with SMTP id s21mr34323601pgg.215.1560481930079; Thu, 13 Jun 2019 20:12:10 -0700 (PDT) Received: from localhost ([122.172.66.84]) by smtp.gmail.com with ESMTPSA id y1sm1198391pjw.5.2019.06.13.20.12.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jun 2019 20:12:09 -0700 (PDT) From: Viresh Kumar To: linux-arm-kernel@lists.infradead.org, Julien Thierry Cc: Viresh Kumar , stable@vger.kernel.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 06/45] arm64: Use pointer masking to limit uaccess speculation Date: Fri, 14 Jun 2019 08:37:49 +0530 Message-Id: <33a351b8683ca17c3d6ed3711d2c6fe2ae1a36f3.1560480942.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Robin Murphy commit 4d8efc2d5ee4c9ccfeb29ee8afd47a8660d0c0ce upstream. Similarly to x86, mitigate speculation past an access_ok() check by masking the pointer against the address limit before use. Even if we don't expect speculative writes per se, it is plausible that a CPU may still speculate at least as far as fetching a cache line for writing, hence we also harden put_user() and clear_user() for peace of mind. Signed-off-by: Robin Murphy Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/uaccess.h | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index c625cc5531fc..75363d723262 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -121,6 +121,26 @@ static inline unsigned long __range_ok(unsigned long addr, unsigned long size) #define access_ok(type, addr, size) __range_ok((unsigned long)(addr), size) #define user_addr_max get_fs +/* + * Sanitise a uaccess pointer such that it becomes NULL if above the + * current addr_limit. + */ +#define uaccess_mask_ptr(ptr) (__typeof__(ptr))__uaccess_mask_ptr(ptr) +static inline void __user *__uaccess_mask_ptr(const void __user *ptr) +{ + void __user *safe_ptr; + + asm volatile( + " bics xzr, %1, %2\n" + " csel %0, %1, xzr, eq\n" + : "=&r" (safe_ptr) + : "r" (ptr), "r" (current_thread_info()->addr_limit) + : "cc"); + + csdb(); + return safe_ptr; +} + /* * The "__xxx" versions of the user access functions do not verify the address * space - it must have been done previously with a separate "access_ok()" @@ -193,7 +213,7 @@ do { \ __typeof__(*(ptr)) __user *__p = (ptr); \ might_fault(); \ access_ok(VERIFY_READ, __p, sizeof(*__p)) ? \ - __get_user((x), __p) : \ + __p = uaccess_mask_ptr(__p), __get_user((x), __p) : \ ((x) = 0, -EFAULT); \ }) @@ -259,7 +279,7 @@ do { \ __typeof__(*(ptr)) __user *__p = (ptr); \ might_fault(); \ access_ok(VERIFY_WRITE, __p, sizeof(*__p)) ? \ - __put_user((x), __p) : \ + __p = uaccess_mask_ptr(__p), __put_user((x), __p) : \ -EFAULT; \ }) @@ -297,7 +317,7 @@ static inline unsigned long __must_check copy_in_user(void __user *to, const voi static inline unsigned long __must_check clear_user(void __user *to, unsigned long n) { if (access_ok(VERIFY_WRITE, to, n)) - n = __clear_user(to, n); + n = __clear_user(__uaccess_mask_ptr(to), n); return n; } From patchwork Fri Jun 14 03:07:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166745 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1505367ilk; Thu, 13 Jun 2019 20:12:14 -0700 (PDT) X-Google-Smtp-Source: APXvYqzNboZE4pzWOUvecc1dR8hyV8lc7Q4M1NtkNyr/Rid/alSltE9hDsU4J52ssq/+Cj704/AG X-Received: by 2002:a17:902:b94a:: with SMTP id h10mr91088076pls.265.1560481934175; Thu, 13 Jun 2019 20:12:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560481934; cv=none; d=google.com; s=arc-20160816; b=VxCgaQg+82EKpMHzAOx8UkHPXlAzuVc+lrdU3u37eeOzl2w4d85iASGd5KtsyPHvWj XOF2Co+4UFhKI3hPBkuAQ5m2u9gLxvWayfeioFhghv2ZKiU2IzxQoA9VHOQH9cvxCwMu St9Ry/VXgbR6F96AhZbQWFXfnlFaAaASndWzFlPJgX0Ibhf57cEYpddtil6mNc1TsnCW C8TJv92XAv7ZQr4bxvtuZumnNZAN+mIrPZnTCej6qA6p96pcSwxpybalW5PY/8yQfJk1 JrFIEfIGvyJq5fl/7x8BYX9n2Xjlnva1uEuWHony6fYaQiLyNyAiofyqqNGvFCVxW1d4 c2IA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=1IdhsUs/fdllTh2EJ+ScRqWrO1uX9GsPUvP6PugnTR0=; b=FclJviWZBUvypoYVORHJ30SN/OH1DCYQYUGBIps8y/y1v30ZGZzDClR0mT2jVScSJi 9j2sAVr3ZL5gLZY6Cn91qq6u5O8rjow0S3fXy4yiI9ZYSo+ES4eQMHdZaBdIkYbJbT9J zECA1TZsn5Oo9TY34Vnx5cCQUMyG1/J+ac5bJaks1qcj9SlR1It7brqjIxYlpqp8hqev PbQIIO9J8Kw/puywrBENaIPEfvz2vfxD7C6BeP+uNs3r6s+ddr3AdAlNswGWLT3n5JFS 9DkNrInm7UOPQVEQewJFLrc1TwC/0dL/gX9NCuAwgKKq3Brkhx6zoIApAXByPuiMOLVn 90Gw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CeEm6Q1H; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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In a similar manner to array_index_mask_nospec, this patch introduces an assembly macro (mask_nospec64) which can be used to bound a value under speculation. This macro is then used to ensure that the indirect branch through the syscall table is bounded under speculation, with out-of-range addresses speculating as calls to sys_io_setup (0). Reviewed-by: Mark Rutland Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas [ v4.4: use existing scno & sc_nr definitions ] Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/assembler.h | 11 +++++++++++ arch/arm64/kernel/entry.S | 1 + 2 files changed, 12 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index 683c2875278f..2b30363a3a89 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -102,6 +102,17 @@ hint #20 .endm +/* + * Sanitise a 64-bit bounded index wrt speculation, returning zero if out + * of bounds. + */ + .macro mask_nospec64, idx, limit, tmp + sub \tmp, \idx, \limit + bic \tmp, \tmp, \idx + and \idx, \idx, \tmp, asr #63 + csdb + .endm + #define USER(l, x...) \ 9999: x; \ .section __ex_table,"a"; \ diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 4c5013b09dcb..e6aec982dea9 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -697,6 +697,7 @@ el0_svc_naked: // compat entry point b.ne __sys_trace cmp scno, sc_nr // check upper syscall limit b.hs ni_sys + mask_nospec64 scno, sc_nr, x19 // enforce bounds for syscall number ldr x16, [stbl, scno, lsl #3] // address in the syscall table blr x16 // call sys_* routine b ret_fast_syscall From patchwork Fri Jun 14 03:07:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166746 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1505402ilk; Thu, 13 Jun 2019 20:12:17 -0700 (PDT) X-Google-Smtp-Source: APXvYqwEpbNq0Ke22hOizvE9F6++awskSrmo2oVxSnluS/0f7guvvN/pOwdJW/QC21jFkcgSUxNt X-Received: by 2002:a63:5726:: with SMTP id l38mr34992645pgb.344.1560481936948; Thu, 13 Jun 2019 20:12:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560481936; cv=none; d=google.com; s=arc-20160816; b=bwCCJm4J/p2QBDQ3e4CCS0GiEpX2nkz2QKGpKZe95CJE2vJQTQm3Vv+HhhMq4s4Tuq 15bWz1CfXd83RRVZY4hv53LtUBLUuUvX7oroRnn9Pkh1XStTbeFSDk6Fn3r2oqIxYjiY UJVGhZFSTuimKXau6Jy4FE9pN5U2G3QvgoCTHAGEeC+TUr635uW1V3F53Mgf+JQYZyIA YN2ebUj/otF69VAiVnIKaYURNIHll3EBMtFuUCcwI8/mRdCuXZtCMPC6v4NbV+pZfbNQ emrccaHfg3nRfbZv9xOBbtpZuJ1vhrxw8hEdMTnXYzUrzLKkOI4zwCf3xEZgRyL6XhSz mpvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=gNlfncScxDREAT7VjTEXAFzdaeKYbTqQ4JYCBMZ7gaA=; b=PHiT/8BNrFK9Xb2LFEK7QkNQ/ko7qIOKfzpG8Yv4ck5MaL2he3GW/qz8j0LEX6DX8O TnY6lgObjqE1bqtvEfchJ3It3IxKa7JuvxMhfmi8eg5wSJZzVs9HF1RZnuEHPywB/G3m hICh77QcoQkXcIKr09jkGceWteVE1dd+1Qw1uyDEF0tC3LCMSevYRaikcqyIb1uonAlw on9j6MX/VaNKd960LC6iHell3iQi9Qek30QtIqRH5Ik/Q9QJ3g3LTvr9lnfhYNF2EnOQ zM8CHQ1/UT4PYLgw4uU0s+hR7XUT287JvxZdn9E+6Tt+BrXI0I2HJE3euo9JQA8UfJtp oGiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wDBo+IsE; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e8si1073936plb.420.2019.06.13.20.12.16; Thu, 13 Jun 2019 20:12:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wDBo+IsE; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725981AbfFNDMQ (ORCPT + 14 others); Thu, 13 Jun 2019 23:12:16 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:45352 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725819AbfFNDMQ (ORCPT ); Thu, 13 Jun 2019 23:12:16 -0400 Received: by mail-pg1-f195.google.com with SMTP id s21so654929pga.12 for ; Thu, 13 Jun 2019 20:12:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gNlfncScxDREAT7VjTEXAFzdaeKYbTqQ4JYCBMZ7gaA=; b=wDBo+IsE5CxYBr/gG7jlwGTkzvTi/KgR2RgJSMhJe7bSxoaXzF0+TdDNJK6dLehXAQ KEE7UfEPuEEdzLtOeDJj3d79e7YtVNq/zUYfIVHlxutsUIdQWnMOok8xzhUVGO/wTU68 ulCOJAXaMZaEp6vk5Lt1C67hIvkuulYIejzeRyCLcBuX3IVSZwH8JSIlylhk7jf5ZZAp ekJFzgWJkOPfXRXpgRLg5XEs6n3l8kd4NqIboYgsZw8aMww1p5p+juY2j8+fPoHS7L27 QCdRJg5NSWYQy3xOzfV5YkvCjGSfOV9srWU2QmGPVppmd2e1TGCJfqCvS3ceOE1+BmUc vgBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gNlfncScxDREAT7VjTEXAFzdaeKYbTqQ4JYCBMZ7gaA=; b=YsqKHugJFKF64pqYBz4Ekr4RpHUVH5do3LIEaSH44EZOP1r6N7AuLHNSOKXFDvlYJF G8f6KfgbR1qmBV6A0kfRiAEGQm4UKjnAxBf2SjmodWb597URVxjMwyle0do+Vml+hKBa RizgKW6cdl4q+9RDR+GHpbK4TJ7IhwaAWgdBANmZqtEMDZi/CJTR+oPBEA64Z2xFzSqT FbFSaHRVVAyN6w82JYt/272gvFLsQwM1HYnZLN9HmYaU7KjW2rYqJ/ifwyH4AG2M3efr levUnNnflThquLqyMxB4oETAmDahlponzxYX3LMd0X+DSt4Yc4D0RhYNNom45sXsWuH9 uuwQ== X-Gm-Message-State: APjAAAUVBKClRp3PnISZp+Owwd7Wrd4nF1U4GrhsvKTvWuKTU+j92D/Z biDx1xmGQZ//SPJ0bG1XbOf6wg== X-Received: by 2002:a63:e60b:: with SMTP id g11mr13414619pgh.172.1560481935400; Thu, 13 Jun 2019 20:12:15 -0700 (PDT) Received: from localhost ([122.172.66.84]) by smtp.gmail.com with ESMTPSA id g8sm1048468pfi.8.2019.06.13.20.12.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jun 2019 20:12:14 -0700 (PDT) From: Viresh Kumar To: linux-arm-kernel@lists.infradead.org, Julien Thierry Cc: Viresh Kumar , stable@vger.kernel.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 08/45] arm64: uaccess: Prevent speculative use of the current addr_limit Date: Fri, 14 Jun 2019 08:37:51 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Will Deacon commit c2f0ad4fc089cff81cef6a13d04b399980ecbfcc upstream. A mispredicted conditional call to set_fs could result in the wrong addr_limit being forwarded under speculation to a subsequent access_ok check, potentially forming part of a spectre-v1 attack using uaccess routines. This patch prevents this forwarding from taking place, but putting heavy barriers in set_fs after writing the addr_limit. Reviewed-by: Mark Rutland Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/uaccess.h | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index 75363d723262..fc11c50af558 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -62,6 +62,13 @@ extern int fixup_exception(struct pt_regs *regs); static inline void set_fs(mm_segment_t fs) { current_thread_info()->addr_limit = fs; + + /* + * Prevent a mispredicted conditional call to set_fs from forwarding + * the wrong address limit to access_ok under speculation. + */ + dsb(nsh); + isb(); } #define segment_eq(a, b) ((a) == (b)) From patchwork Fri Jun 14 03:07:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166747 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1505437ilk; Thu, 13 Jun 2019 20:12:19 -0700 (PDT) X-Google-Smtp-Source: APXvYqyu1S+xNQVqMVvqLmBJ6Hr1VxVMWzNp4subNmrE3iOX9pG1/ftdZt2OzKm4UOMrLbIZeTIs X-Received: by 2002:aa7:8007:: with SMTP id j7mr32204796pfi.154.1560481939669; Thu, 13 Jun 2019 20:12:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560481939; cv=none; d=google.com; s=arc-20160816; b=wLUtrsA0OoslslTP9mS6AcbkW+9bZj9E4jTfLN2LFOhixoSu+Fmt2NYJRH6+0RVcMj knSPVYuFEy+qufqc3ghF+WGMrhyI47yt9j1RoXG1Y/O6vOLyKNa2WPu0CxAEEp+4cdH8 d+4tkEkjeyAkcLVpI5lS5FB4U1KjpO6J6uw7oesHeQvCtWEA03i9bQpLVDfHvv/++no9 Z/EUWHxt6LcDetfCFu0tzVOvzQ6bM0RYk2y5PEKVUSIMNVkISpBsR8rQg3ubWE0k40zK Mn+n67PW3GYGQq8oAebkPCiqFJDxDUBxLYTJUtVspC1PJLocdHb5G7IsRz3TwwVjjZnt X1/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Lt3w372XAiP2T5A3AE8p2nBAFVuCKsgxbI6J0UJSdP8=; b=ktWLnpoMs7zuIQ7waI66H+k5KEeBtbaIiub4PGfHv04rhbzPPNZFOir2R2sww23SGW uMdQhOWs9ipr90+AW2uimWEc2zogZY4wxSRu9n4pMjgaOz0tS6Vt7udWreQka9B0gWnh Mph6mtZI2qg0IQ11kY58c9e8mPQf+wK8DXazLBsMTOKG2tkqGHDBYA/6spS1o6q3PH3i aU459aOzy2aRvL4F0gWFuNK4clcaAmGO5I6AtA6ULqnQvQ0czzLcK6xfrsQZ9VhqnJKc +eVj/PiFF3/DGK7HmPstrUYMlTHIHt/qT8zueP6mPPLLHsiaj4g/ILzPk8Y+UlqXy3ei EE8A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ARF6EuIO; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e8si1073936plb.420.2019.06.13.20.12.19; Thu, 13 Jun 2019 20:12:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ARF6EuIO; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726030AbfFNDMT (ORCPT + 14 others); Thu, 13 Jun 2019 23:12:19 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:36175 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725819AbfFNDMS (ORCPT ); Thu, 13 Jun 2019 23:12:18 -0400 Received: by mail-pl1-f195.google.com with SMTP id w10so185551plz.3 for ; Thu, 13 Jun 2019 20:12:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Lt3w372XAiP2T5A3AE8p2nBAFVuCKsgxbI6J0UJSdP8=; b=ARF6EuIOrYoCPrmP9r2NO8meY7IeSPACptb2qiSC3sZkkfZa+YnowaYv5BXUGvg14G C6EkcuPeGocTfXv3Ut4XUoAz74Qf4c/opqiS12y2PM49RuCirdTuRfuexd7PCUPelcWM seJw+buAjTHBvaLeXrb//UjwS3FIMYl+J0ppj3mNRrBFUjiV76zkc/cIeqUYJrMLNiQK Y+o4x5bUuJEAKR+I26nOky6nQqJVT7l01L7J+YkEL/W+Nn8ihvvgxos25+rssBLI28Qz pGM5oTBZTZ7Amfmd7RlRVOjJZNYjzjF09r/6nTXVZKIOiFQM2FgaLmhhA/lsVMGV+uFf 3vEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Lt3w372XAiP2T5A3AE8p2nBAFVuCKsgxbI6J0UJSdP8=; b=bBdbalL0NtOS05raNvpNZa184AJB4qztYb8lnl4hpxvcu4/5+qdh5/zfoqU2OQ92ZD 7XUTRvK/v/qGs5axN+Gcp8SGFkCW0DIt8r3t246wy/Jzlp36g8Is7sNmuJzoTGz2RR39 W9Pi7oDW7SfjAGJciaSFiECoOKNv6HQydBDe//d9Qpmh5/uaUIRY3bP23Ix/U9yllD6x p8xVn05Phnx4jy83HzetLKfKJ5lIbS146q9NS6ArkHuGqRo8AbrtuFnqvUyowuKBNizM 8hqqD4N8eO3UatJUJqs/ZbXSfM07H4v3pUjaaa/PwLW6SaoSwibcW/5DyJtrL3u/F/Q2 QOSg== X-Gm-Message-State: APjAAAWsEI3jS0A62bkJLyR5+XDqqUQkJx1JJhflTsOD6BuTaI/3G13c wUEpZiMd1Tfq6SfioZVbR6oFrw== X-Received: by 2002:a17:902:121:: with SMTP id 30mr86998560plb.314.1560481937851; Thu, 13 Jun 2019 20:12:17 -0700 (PDT) Received: from localhost ([122.172.66.84]) by smtp.gmail.com with ESMTPSA id k20sm1051646pgh.31.2019.06.13.20.12.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jun 2019 20:12:17 -0700 (PDT) From: Viresh Kumar To: linux-arm-kernel@lists.infradead.org, Julien Thierry Cc: Viresh Kumar , stable@vger.kernel.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 09/45] arm64: uaccess: Don't bother eliding access_ok checks in __{get, put}_user Date: Fri, 14 Jun 2019 08:37:52 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Will Deacon commit 84624087dd7e3b482b7b11c170ebc1f329b3a218 upstream. access_ok isn't an expensive operation once the addr_limit for the current thread has been loaded into the cache. Given that the initial access_ok check preceding a sequence of __{get,put}_user operations will take the brunt of the miss, we can make the __* variants identical to the full-fat versions, which brings with it the benefits of address masking. The likely cost in these sequences will be from toggling PAN/UAO, which we can address later by implementing the *_unsafe versions. Reviewed-by: Robin Murphy Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas [ v4.4: Fixed conflicts around {__get_user|__put_user}_unaligned macros ] Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/uaccess.h | 62 ++++++++++++++++++-------------- 1 file changed, 36 insertions(+), 26 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index fc11c50af558..a34324436ce1 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -200,30 +200,35 @@ do { \ CONFIG_ARM64_PAN)); \ } while (0) -#define __get_user(x, ptr) \ +#define __get_user_check(x, ptr, err) \ ({ \ - int __gu_err = 0; \ - __get_user_err((x), (ptr), __gu_err); \ - __gu_err; \ + __typeof__(*(ptr)) __user *__p = (ptr); \ + might_fault(); \ + if (access_ok(VERIFY_READ, __p, sizeof(*__p))) { \ + __p = uaccess_mask_ptr(__p); \ + __get_user_err((x), __p, (err)); \ + } else { \ + (x) = 0; (err) = -EFAULT; \ + } \ }) #define __get_user_error(x, ptr, err) \ ({ \ - __get_user_err((x), (ptr), (err)); \ + __get_user_check((x), (ptr), (err)); \ (void)0; \ }) -#define __get_user_unaligned __get_user - -#define get_user(x, ptr) \ +#define __get_user(x, ptr) \ ({ \ - __typeof__(*(ptr)) __user *__p = (ptr); \ - might_fault(); \ - access_ok(VERIFY_READ, __p, sizeof(*__p)) ? \ - __p = uaccess_mask_ptr(__p), __get_user((x), __p) : \ - ((x) = 0, -EFAULT); \ + int __gu_err = 0; \ + __get_user_check((x), (ptr), __gu_err); \ + __gu_err; \ }) +#define __get_user_unaligned __get_user + +#define get_user __get_user + #define __put_user_asm(instr, reg, x, addr, err) \ asm volatile( \ "1: " instr " " reg "1, [%2]\n" \ @@ -266,30 +271,35 @@ do { \ CONFIG_ARM64_PAN)); \ } while (0) -#define __put_user(x, ptr) \ +#define __put_user_check(x, ptr, err) \ ({ \ - int __pu_err = 0; \ - __put_user_err((x), (ptr), __pu_err); \ - __pu_err; \ + __typeof__(*(ptr)) __user *__p = (ptr); \ + might_fault(); \ + if (access_ok(VERIFY_WRITE, __p, sizeof(*__p))) { \ + __p = uaccess_mask_ptr(__p); \ + __put_user_err((x), __p, (err)); \ + } else { \ + (err) = -EFAULT; \ + } \ }) #define __put_user_error(x, ptr, err) \ ({ \ - __put_user_err((x), (ptr), (err)); \ + __put_user_check((x), (ptr), (err)); \ (void)0; \ }) -#define __put_user_unaligned __put_user - -#define put_user(x, ptr) \ +#define __put_user(x, ptr) \ ({ \ - __typeof__(*(ptr)) __user *__p = (ptr); \ - might_fault(); \ - access_ok(VERIFY_WRITE, __p, sizeof(*__p)) ? \ - __p = uaccess_mask_ptr(__p), __put_user((x), __p) : \ - -EFAULT; \ + int __pu_err = 0; \ + __put_user_check((x), (ptr), __pu_err); \ + __pu_err; \ }) +#define __put_user_unaligned __put_user + +#define put_user __put_user + extern unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n); extern unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n); extern unsigned long __must_check __copy_in_user(void __user *to, const void __user *from, unsigned long n); From patchwork Fri Jun 14 03:07:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166748 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1505457ilk; Thu, 13 Jun 2019 20:12:21 -0700 (PDT) X-Google-Smtp-Source: APXvYqz3v6DmL5WRHXaT0078lb2hJyzu28vfOXDR8NBGFMSo2gc0Vb01GYKQfyScBa70xa41dPNG X-Received: by 2002:a17:902:728b:: with SMTP id d11mr61731578pll.78.1560481941802; Thu, 13 Jun 2019 20:12:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560481941; cv=none; d=google.com; s=arc-20160816; b=yTBwTTbGqNqC6mU8YoY+KwflB0Y7r2Gh41HbwAgL2e3T/vxEqjMyUUgy+V3TL2RMaf hg629VL4UMOVt/6SI0zdaanx7fzU7RKytCZZngyocCJIEus3kabBntjN/eMfGykhidj/ JsFd/MlNxfSYZXEMqH+UkgHTAHHvGGJFMgm0aPBgY13cKuk6TZFYyR9jf43/irCxSs9x YvONTIKHTpKPYt861JCwml+juAfvCa5vUaV2ph6BIYpxAZElUVddJxPXDSDGFU2TvmLU EcGTm+jcYgwYwXgRkVNuAynVP60WmCdGCzf5WEg1f4B9zfKDRrW5Ir+n4Em+3ND1wMUQ tl9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=q/AGFfvfHGuDn+dFoAxSTyRFru9zQTVknf0DUmu2KKo=; b=cKIEhobQTZjmHYElbvPUCG3t94wSGGmA08oRBgUmzgytv5bA32tz93IPC2P7ixq/qZ oF7h4xP0prqrBd1DjltcHYtpOb/VO0tGxaG/ghy5g1jCMZauc7zq8Q1MzUMvssEQnY9p 23/9Rkx9TNMz5IZQ7dUUGNannLII+4f6lRnPVP4yD++GgfSuZzGsMa0scOw9sthSu4JC qskDEKpaCzuhmlR4hyUR7vCzGF/fIhYhDRCOMtCloj/XdBIm0ZNy0j9jHrK4wZ7hYRyd Xv3JX2CwmBIupwYAo3UOTsGcNYUx95xDW5a00Zb86TlN6hjY62DOvUgC2K7PvLH5QAaA MkWQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EXoJEH53; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Memory access coded in an assembly won't be seen by KASAN as a compiler can instrument only C code. Add kasan_check_[read,write]() API which is going to be used to check a certain memory range. Link: http://lkml.kernel.org/r/1462538722-1574-3-git-send-email-aryabinin@virtuozzo.com Signed-off-by: Andrey Ryabinin Acked-by: Alexander Potapenko Cc: Dmitry Vyukov Cc: Ingo Molnar Cc: "H. Peter Anvin" Cc: Thomas Gleixner Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds [ v4.4: Fixed MAINTAINERS conflict and added whole kasan entry ] Signed-off-by: Viresh Kumar --- MAINTAINERS | 14 ++++++++++++++ include/linux/kasan-checks.h | 12 ++++++++++++ mm/kasan/kasan.c | 12 ++++++++++++ 3 files changed, 38 insertions(+) create mode 100644 include/linux/kasan-checks.h -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/MAINTAINERS b/MAINTAINERS index f4d4a5544dc1..2a8826732967 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5982,6 +5982,20 @@ S: Maintained F: Documentation/hwmon/k8temp F: drivers/hwmon/k8temp.c +KASAN +M: Andrey Ryabinin +R: Alexander Potapenko +R: Dmitry Vyukov +L: kasan-dev@googlegroups.com +S: Maintained +F: arch/*/include/asm/kasan.h +F: arch/*/mm/kasan_init* +F: Documentation/kasan.txt +F: include/linux/kasan*.h +F: lib/test_kasan.c +F: mm/kasan/ +F: scripts/Makefile.kasan + KCONFIG M: "Yann E. MORIN" L: linux-kbuild@vger.kernel.org diff --git a/include/linux/kasan-checks.h b/include/linux/kasan-checks.h new file mode 100644 index 000000000000..b7f8aced7870 --- /dev/null +++ b/include/linux/kasan-checks.h @@ -0,0 +1,12 @@ +#ifndef _LINUX_KASAN_CHECKS_H +#define _LINUX_KASAN_CHECKS_H + +#ifdef CONFIG_KASAN +void kasan_check_read(const void *p, unsigned int size); +void kasan_check_write(const void *p, unsigned int size); +#else +static inline void kasan_check_read(const void *p, unsigned int size) { } +static inline void kasan_check_write(const void *p, unsigned int size) { } +#endif + +#endif diff --git a/mm/kasan/kasan.c b/mm/kasan/kasan.c index b7397b459960..3ad31df33e76 100644 --- a/mm/kasan/kasan.c +++ b/mm/kasan/kasan.c @@ -274,6 +274,18 @@ static __always_inline void check_memory_region(unsigned long addr, void __asan_loadN(unsigned long addr, size_t size); void __asan_storeN(unsigned long addr, size_t size); +void kasan_check_read(const void *p, unsigned int size) +{ + check_memory_region((unsigned long)p, size, false, _RET_IP_); +} +EXPORT_SYMBOL(kasan_check_read); + +void kasan_check_write(const void *p, unsigned int size) +{ + check_memory_region((unsigned long)p, size, true, _RET_IP_); +} +EXPORT_SYMBOL(kasan_check_write); + #undef memset void *memset(void *addr, int c, size_t len) { From patchwork Fri Jun 14 03:07:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166749 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1505495ilk; Thu, 13 Jun 2019 20:12:25 -0700 (PDT) X-Google-Smtp-Source: APXvYqxNhWTIHQABfC2SBxI4zhmWt4ukToFrmmuIljF/oXrDGzoS34OsrCdKhLMqlgCbtFs76O7m X-Received: by 2002:a62:198e:: with SMTP id 136mr92936190pfz.180.1560481945264; Thu, 13 Jun 2019 20:12:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560481945; cv=none; d=google.com; s=arc-20160816; b=bx5UkLGZMhE8XgENpDFFMqbh0gq2u/r0F/rB4iz5Jhtj5f4PqxLOc3lzxLld9zXfKy Vd15KC1xejV5fgLKMRC5bFjJ62GwbkIDeVPyvjNwj28MSQqJuakSUDkCecxnDY+uI0fx yEGh7h3bG05T7hZC81J25AZaxIfiWLqq+IdUDTrXmGOVoG2DwwBHF7chC4dJCOoos0Rn 4s3hdlIbi3QkXgCtLQaet/7q6+hKUMzDnxE13Z717Gqh9G0bPCKPCY0BxSPtE8loxCjC iXMVPMj+8vesXL0vOaDV3CM1/wIImsXAKemUI79XrDP6dqk6GMP6/XtSZ6xY6voPX7ZQ YfAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=t0RCljGeD4tzeQJetzsGgy9r5JSUQjn098IzF6ZdUW0=; b=fIMFeyFUtIBpCbWuqI2EPDpKUSrUkDRpBa9aoMddWjHSUd7pwgDGt8Q8yn7pV9/HQC fed1T8WrJ3LLNagz6XXjA+PsTf28/605mnnz1iqS/QE3ZJSpQIW15y3jPDYhxiO8Yxzc l/2k78Lgfb6G8V1PXSz0pTZu0dhLZAyphKJsqae3sdRlNP6hPcWPyFLzwfqSaTXpRQXN TZXXyCqbIQer3cCU5sLGWFAIwL3+Unn4zJe/ch/1ej7CEA+B8oNK+HOzftbXpFchszzX 87BYVEJU3KhIpgb17vri3fH5ycsd0zBWsV14bRsM9g1UHyFZ6QYa2PdzTyZ+IvM/zjhM rLew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EnlNIWxb; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e8si1073936plb.420.2019.06.13.20.12.25; Thu, 13 Jun 2019 20:12:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EnlNIWxb; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726283AbfFNDMY (ORCPT + 14 others); Thu, 13 Jun 2019 23:12:24 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:43234 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725819AbfFNDMY (ORCPT ); Thu, 13 Jun 2019 23:12:24 -0400 Received: by mail-pf1-f194.google.com with SMTP id i189so482789pfg.10 for ; Thu, 13 Jun 2019 20:12:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=t0RCljGeD4tzeQJetzsGgy9r5JSUQjn098IzF6ZdUW0=; b=EnlNIWxbtRThqYC1UTEAMR6ZJHxB7MpeNcyku2RIUxsBNKOca6sb1cLziSGn027QKB xznFwEiVWEV8QHdgGzBQHOdJP4StFOzj+T+DkX9dTluJJf8uG+du5rxm1et9ARIS4deq 66iFIpfeZzOLGx1fURdbEC387LYqMrJQSrtZLWzTDvQchdMd1/rZXOX3E/SOVTzo6dCL xuHUISGzQnmY2wjzUcLfRKDKV7ZobrQBu81lBSzvcyKSlwqFr+8EckIrP2mAwjn1Evh5 Bl9CmZx5NM0LTXYNykjnVOtsoLVfbdR7BydQbSayQDn36dpSKcpA4Ry6vcT2xzpM4fFG s2Dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=t0RCljGeD4tzeQJetzsGgy9r5JSUQjn098IzF6ZdUW0=; b=Zy51fU71vlIv7e30Mb2YLRPFXs5lEvgSyayFBj4Kt0HbqlXV67DYR7nSTnRxOxIOpE FzLIPBcNuQjx4msz11+pcwuD04xowOmbzV7n+BMS3D9RmgVICcGl7Lq67HF7xcnj5Mh8 Qtal1Y7zrT1uLfVcwNI1B83+Av8ANpXfPJ3TrXY6fH9UtEeP+k4i2shi8gEiyc0FVlIx RbJaOlWKlIFSaFflLUAR1T/6WfWBFjg5mYM7Ib5K7GujP4vSYXZLwM7UZ1kj2UBpaKH+ e67BDCgkfFbre8YEbFGCE3N5emydEwpoZguDOngZuRlUa/SyEvikWIfiJFGyeWZOTyR0 30EQ== X-Gm-Message-State: APjAAAW13qoJkS1tdfkWWqN/PmsKYrIVhl1DmQaAivCWvR+4qYMet2oW PEU3gef4Yqa5h7/BrF2asebhXA== X-Received: by 2002:a63:68b:: with SMTP id 133mr32205733pgg.385.1560481943068; Thu, 13 Jun 2019 20:12:23 -0700 (PDT) Received: from localhost ([122.172.66.84]) by smtp.gmail.com with ESMTPSA id n140sm1075830pfd.132.2019.06.13.20.12.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jun 2019 20:12:22 -0700 (PDT) From: Viresh Kumar To: linux-arm-kernel@lists.infradead.org, Julien Thierry Cc: Viresh Kumar , stable@vger.kernel.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 11/45] arm64: kasan: instrument user memory access API Date: Fri, 14 Jun 2019 08:37:54 +0530 Message-Id: <565bddf471412bbd64d0ece7f9d91b9c937cae19.1560480942.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Yang Shi commit bffe1baff5d57521b0c41b6997c41ff1993e9818 upstream. The upstream commit 1771c6e1a567ea0ba2cccc0a4ffe68a1419fd8ef ("x86/kasan: instrument user memory access API") added KASAN instrument to x86 user memory access API, so added such instrument to ARM64 too. Define __copy_to/from_user in C in order to add kasan_check_read/write call, rename assembly implementation to __arch_copy_to/from_user. Tested by test_kasan module. Acked-by: Andrey Ryabinin Reviewed-by: Mark Rutland Tested-by: Mark Rutland Signed-off-by: Yang Shi Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/uaccess.h | 25 +++++++++++++++++++++---- arch/arm64/kernel/arm64ksyms.c | 4 ++-- arch/arm64/lib/copy_from_user.S | 4 ++-- arch/arm64/lib/copy_to_user.S | 4 ++-- 4 files changed, 27 insertions(+), 10 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index a34324436ce1..693a0d784534 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -22,6 +22,7 @@ * User space memory access functions */ #include +#include #include #include @@ -300,15 +301,29 @@ do { \ #define put_user __put_user -extern unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n); -extern unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n); +extern unsigned long __must_check __arch_copy_from_user(void *to, const void __user *from, unsigned long n); +extern unsigned long __must_check __arch_copy_to_user(void __user *to, const void *from, unsigned long n); extern unsigned long __must_check __copy_in_user(void __user *to, const void __user *from, unsigned long n); extern unsigned long __must_check __clear_user(void __user *addr, unsigned long n); +static inline unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n) +{ + kasan_check_write(to, n); + return __arch_copy_from_user(to, from, n); +} + +static inline unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n) +{ + kasan_check_read(from, n); + return __arch_copy_to_user(to, from, n); +} + static inline unsigned long __must_check copy_from_user(void *to, const void __user *from, unsigned long n) { + kasan_check_write(to, n); + if (access_ok(VERIFY_READ, from, n)) - n = __copy_from_user(to, from, n); + n = __arch_copy_from_user(to, from, n); else /* security hole - plug it */ memset(to, 0, n); return n; @@ -316,8 +331,10 @@ static inline unsigned long __must_check copy_from_user(void *to, const void __u static inline unsigned long __must_check copy_to_user(void __user *to, const void *from, unsigned long n) { + kasan_check_read(from, n); + if (access_ok(VERIFY_WRITE, to, n)) - n = __copy_to_user(to, from, n); + n = __arch_copy_to_user(to, from, n); return n; } diff --git a/arch/arm64/kernel/arm64ksyms.c b/arch/arm64/kernel/arm64ksyms.c index 3b6d8cc9dfe0..c654df05b7d7 100644 --- a/arch/arm64/kernel/arm64ksyms.c +++ b/arch/arm64/kernel/arm64ksyms.c @@ -33,8 +33,8 @@ EXPORT_SYMBOL(copy_page); EXPORT_SYMBOL(clear_page); /* user mem (segment) */ -EXPORT_SYMBOL(__copy_from_user); -EXPORT_SYMBOL(__copy_to_user); +EXPORT_SYMBOL(__arch_copy_from_user); +EXPORT_SYMBOL(__arch_copy_to_user); EXPORT_SYMBOL(__clear_user); EXPORT_SYMBOL(__copy_in_user); diff --git a/arch/arm64/lib/copy_from_user.S b/arch/arm64/lib/copy_from_user.S index 4699cd74f87e..281e75db899a 100644 --- a/arch/arm64/lib/copy_from_user.S +++ b/arch/arm64/lib/copy_from_user.S @@ -66,7 +66,7 @@ .endm end .req x5 -ENTRY(__copy_from_user) +ENTRY(__arch_copy_from_user) ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(0)), ARM64_HAS_PAN, \ CONFIG_ARM64_PAN) add end, x0, x2 @@ -75,7 +75,7 @@ ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(1)), ARM64_HAS_PAN, \ CONFIG_ARM64_PAN) mov x0, #0 // Nothing to copy ret -ENDPROC(__copy_from_user) +ENDPROC(__arch_copy_from_user) .section .fixup,"ax" .align 2 diff --git a/arch/arm64/lib/copy_to_user.S b/arch/arm64/lib/copy_to_user.S index 7512bbbc07ac..db4d187de61f 100644 --- a/arch/arm64/lib/copy_to_user.S +++ b/arch/arm64/lib/copy_to_user.S @@ -65,7 +65,7 @@ .endm end .req x5 -ENTRY(__copy_to_user) +ENTRY(__arch_copy_to_user) ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(0)), ARM64_HAS_PAN, \ CONFIG_ARM64_PAN) add end, x0, x2 @@ -74,7 +74,7 @@ ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(1)), ARM64_HAS_PAN, \ CONFIG_ARM64_PAN) mov x0, #0 ret -ENDPROC(__copy_to_user) +ENDPROC(__arch_copy_to_user) .section .fixup,"ax" .align 2 From patchwork Fri Jun 14 03:07:55 2019 Content-Type: text/plain; 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Like we've done for get_user and put_user, ensure that user pointers are masked before invoking the underlying __arch_{clear,copy_*}_user operations. Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas [ v4.4: fixup for v4.4 style uaccess primitives ] Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/uaccess.h | 20 ++++++++++++-------- arch/arm64/kernel/arm64ksyms.c | 4 ++-- arch/arm64/lib/clear_user.S | 6 +++--- arch/arm64/lib/copy_in_user.S | 4 ++-- 4 files changed, 19 insertions(+), 15 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index 693a0d784534..a25b8726ffa9 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -303,19 +303,20 @@ do { \ extern unsigned long __must_check __arch_copy_from_user(void *to, const void __user *from, unsigned long n); extern unsigned long __must_check __arch_copy_to_user(void __user *to, const void *from, unsigned long n); -extern unsigned long __must_check __copy_in_user(void __user *to, const void __user *from, unsigned long n); -extern unsigned long __must_check __clear_user(void __user *addr, unsigned long n); +extern unsigned long __must_check __arch_copy_in_user(void __user *to, const void __user *from, unsigned long n); static inline unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n) { kasan_check_write(to, n); - return __arch_copy_from_user(to, from, n); + return __arch_copy_from_user(to, __uaccess_mask_ptr(from), n); + } static inline unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n) { kasan_check_read(from, n); - return __arch_copy_to_user(to, from, n); + return __arch_copy_to_user(__uaccess_mask_ptr(to), from, n); + } static inline unsigned long __must_check copy_from_user(void *to, const void __user *from, unsigned long n) @@ -338,22 +339,25 @@ static inline unsigned long __must_check copy_to_user(void __user *to, const voi return n; } -static inline unsigned long __must_check copy_in_user(void __user *to, const void __user *from, unsigned long n) +static inline unsigned long __must_check __copy_in_user(void __user *to, const void __user *from, unsigned long n) { if (access_ok(VERIFY_READ, from, n) && access_ok(VERIFY_WRITE, to, n)) - n = __copy_in_user(to, from, n); + n = __arch_copy_in_user(__uaccess_mask_ptr(to), __uaccess_mask_ptr(from), n); return n; } +#define copy_in_user __copy_in_user #define __copy_to_user_inatomic __copy_to_user #define __copy_from_user_inatomic __copy_from_user -static inline unsigned long __must_check clear_user(void __user *to, unsigned long n) +extern unsigned long __must_check __arch_clear_user(void __user *to, unsigned long n); +static inline unsigned long __must_check __clear_user(void __user *to, unsigned long n) { if (access_ok(VERIFY_WRITE, to, n)) - n = __clear_user(__uaccess_mask_ptr(to), n); + n = __arch_clear_user(__uaccess_mask_ptr(to), n); return n; } +#define clear_user __clear_user extern long strncpy_from_user(char *dest, const char __user *src, long count); diff --git a/arch/arm64/kernel/arm64ksyms.c b/arch/arm64/kernel/arm64ksyms.c index c654df05b7d7..abe4e0984dbb 100644 --- a/arch/arm64/kernel/arm64ksyms.c +++ b/arch/arm64/kernel/arm64ksyms.c @@ -35,8 +35,8 @@ EXPORT_SYMBOL(clear_page); /* user mem (segment) */ EXPORT_SYMBOL(__arch_copy_from_user); EXPORT_SYMBOL(__arch_copy_to_user); -EXPORT_SYMBOL(__clear_user); -EXPORT_SYMBOL(__copy_in_user); +EXPORT_SYMBOL(__arch_clear_user); +EXPORT_SYMBOL(__arch_copy_in_user); /* physical memory */ EXPORT_SYMBOL(memstart_addr); diff --git a/arch/arm64/lib/clear_user.S b/arch/arm64/lib/clear_user.S index a9723c71c52b..fc6bb0f83511 100644 --- a/arch/arm64/lib/clear_user.S +++ b/arch/arm64/lib/clear_user.S @@ -24,7 +24,7 @@ .text -/* Prototype: int __clear_user(void *addr, size_t sz) +/* Prototype: int __arch_clear_user(void *addr, size_t sz) * Purpose : clear some user memory * Params : addr - user memory address to clear * : sz - number of bytes to clear @@ -32,7 +32,7 @@ * * Alignment fixed up by hardware. */ -ENTRY(__clear_user) +ENTRY(__arch_clear_user) ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(0)), ARM64_HAS_PAN, \ CONFIG_ARM64_PAN) mov x2, x1 // save the size for fixup return @@ -57,7 +57,7 @@ USER(9f, strb wzr, [x0] ) ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(1)), ARM64_HAS_PAN, \ CONFIG_ARM64_PAN) ret -ENDPROC(__clear_user) +ENDPROC(__arch_clear_user) .section .fixup,"ax" .align 2 diff --git a/arch/arm64/lib/copy_in_user.S b/arch/arm64/lib/copy_in_user.S index 81c8fc93c100..0219aa85b3cc 100644 --- a/arch/arm64/lib/copy_in_user.S +++ b/arch/arm64/lib/copy_in_user.S @@ -67,7 +67,7 @@ .endm end .req x5 -ENTRY(__copy_in_user) +ENTRY(__arch_copy_in_user) ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(0)), ARM64_HAS_PAN, \ CONFIG_ARM64_PAN) add end, x0, x2 @@ -76,7 +76,7 @@ ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(1)), ARM64_HAS_PAN, \ CONFIG_ARM64_PAN) mov x0, #0 ret -ENDPROC(__copy_in_user) +ENDPROC(__arch_copy_in_user) .section .fixup,"ax" .align 2 From patchwork Fri Jun 14 03:07:56 2019 Content-Type: text/plain; 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In order to invoke the CPU capability ->matches callback from the ->enable callback for applying local-CPU workarounds, we need a handle on the capability structure. This patch passes a pointer to the capability structure to the ->enable callback. Reviewed-by: Suzuki K Poulose Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas [ v4.4: Use &caps[i] instead as caps isn't incremented ] Signed-off-by: Viresh Kumar --- arch/arm64/kernel/cpufeature.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index c1eddc07d996..c7a2827658fd 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -780,7 +780,7 @@ static void enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps) * uses an IPI, giving us a PSTATE that disappears when * we return. */ - stop_machine(caps[i].enable, NULL, cpu_online_mask); + stop_machine(caps[i].enable, (void *)&caps[i], cpu_online_mask); } #ifdef CONFIG_HOTPLUG_CPU @@ -894,7 +894,7 @@ void verify_local_cpu_capabilities(void) if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i])) fail_incapable_cpu("arm64_features", &caps[i]); if (caps[i].enable) - caps[i].enable(NULL); + caps[i].enable((void *)&caps[i]); } for (i = 0, caps = arm64_hwcaps; caps[i].desc; i++) { From patchwork Fri Jun 14 03:07:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166752 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1505579ilk; Thu, 13 Jun 2019 20:12:32 -0700 (PDT) X-Google-Smtp-Source: APXvYqzvGzM/NMS6iRKa77W4xN7BSRhpwTYaWllASvK4jh+RXC8LBft09vsUJYkBqx7VgGfdIU+N X-Received: by 2002:a17:90a:258b:: with SMTP id k11mr8359683pje.110.1560481952739; Thu, 13 Jun 2019 20:12:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560481952; cv=none; d=google.com; s=arc-20160816; b=gcfk+d97axXUOEgECiXv42d3W3PjQtq5vpAvF2+izutA/z8rIac+NQJO+EC95/sGEE q1FEYP+zbYrUw8ZDx+g1q7uTtcMIJBIt/l2rgVH5rfJtidCqKPYboCKWTAdMJEeGWvaG ScQzL7gd1N+Xqi2Z2XB8dJbEISSFS3kfzt7BzrW9Y9zcMMNQcWa7MB0nD3v9rjwq4G8x Mg173+BvG+TirIrJPZI21MuU+ESucu8xhKu9QNsb/0P+45FmPSoFInfaqbq4uXl6iR1Y 1t3Wu8PJu2klW8eL4ZsTpdSavcVQ6Tm9JFBXGJTKUozTyGBP3bBnt2CjA5L20Dl72LxM qf2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tUK8ETga6k61l9Q+/z8rY6SIV6XG+DcjRuCd/1NWAIQ=; b=qKzHA8G+2fQoe2G4Jof4Q8AMaOl1uqaCaXjxkghjmK7Cakksya32MorIuS3jsKuOHW gTDr4Dxbk+eIptto+3a3jNX2I7kWPe7p3tsgoGVvh3xq5yAFyFZ+z4nR5qwNWhvMdQrG vo23SHRWyEXSFpapaXDJ6SKpB/eXl+lRuQdSU0D+W/isn4WVbbNCpaUXAHYQC3jrKmQY JXgQOtXh4VyK3O1i75HegRPi4Gns0+swQ1hGFVFoPTi0Wa1oscQMyMbHZtJtnhPlndRO 6Vr8LZ7IOWRVgUsI5+nnwk50xXujS6LH3CqoZZVqQeLrSXe9ZfzthrSHJ2BRrrHsNfAH tnSw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=G2wmSB0w; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e8si1073936plb.420.2019.06.13.20.12.32; Thu, 13 Jun 2019 20:12:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=G2wmSB0w; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726429AbfFNDMc (ORCPT + 14 others); Thu, 13 Jun 2019 23:12:32 -0400 Received: from mail-pl1-f196.google.com ([209.85.214.196]:41526 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725819AbfFNDMc (ORCPT ); Thu, 13 Jun 2019 23:12:32 -0400 Received: by mail-pl1-f196.google.com with SMTP id s24so372145plr.8 for ; Thu, 13 Jun 2019 20:12:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tUK8ETga6k61l9Q+/z8rY6SIV6XG+DcjRuCd/1NWAIQ=; b=G2wmSB0wl3ZSst3wBKM0lmkGVB3EAHRbdwUzF55iA5Zc7PyVUPSzOlglM3cYPWwRdH kG5s+Oc45ZUBoFc7mYCpXBsXAu5XGmy/7ktcJKN5fvs5gGGo+RUG59zBtu0U0c7OD1G5 rCdw3QRLYuHQN2CR2z5SNEW280SeN+8hmo3JnWq17WmQ0XAbAnBQB+8kSzeiv2GOos6N i3DZfvNnVkzqtXL9ayx0CfRlKWcSGFcOx2QhOmHPWcoJi1efyzQBp+8/rbWneAGyAo7p 6b75570FcqLite+nlTb86LYO3NmyJ9+l6P9/g2w84R7+Ws1R4y+j1181T/YYXzDR4xsa qF2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tUK8ETga6k61l9Q+/z8rY6SIV6XG+DcjRuCd/1NWAIQ=; b=rFT4DWeanzrXN6Ghm8M0Y4Ne7Lw35GQxAVDj5ZqeqC5QlMSBi0Un+k30Pt8Cai/LMv XjAbOm63q0ruZ34vtm4hWqDl7Mfbs6WPYtXt39jMFB5bT9JT/mXlnWKfszUlUQoQjXif 2sLng9nRRnMMzbO3/OUzsopi35+sH44HQ83hnC9+CPBN2+HdDdhXavPpAKUalBonVhYX JhCG0Bc3PTNqVIcDPpMGAAwBlWlUOOcnw1gYdFyt77BZwGU5R+hbQlkhbY7PTqedxQ11 XonOhV+h00A2XjzPDmB2A193eR4XekrgIh0ykaxH1UAx7efwtmOHbJC/SIXpb0UtATrA uBNw== X-Gm-Message-State: APjAAAUVFiHnTvjGKjGWPSau1J7rT4+OWWuWcBh29kyAf2lYZbAfB+bA EgJi19+rAvmxoqUe/qjl/faqRA== X-Received: by 2002:a17:902:522:: with SMTP id 31mr86143113plf.296.1560481951066; Thu, 13 Jun 2019 20:12:31 -0700 (PDT) Received: from localhost ([122.172.66.84]) by smtp.gmail.com with ESMTPSA id p68sm1036348pfb.80.2019.06.13.20.12.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jun 2019 20:12:30 -0700 (PDT) From: Viresh Kumar To: linux-arm-kernel@lists.infradead.org, Julien Thierry Cc: Viresh Kumar , stable@vger.kernel.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 14/45] drivers/firmware: Expose psci_get_version through psci_ops structure Date: Fri, 14 Jun 2019 08:37:57 +0530 Message-Id: <5f5b6ed2828ebd885fa4bc8e764483d81f419bc5.1560480942.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Will Deacon commit d68e3ba5303f7e1099f51fdcd155f5263da8569b upstream. Entry into recent versions of ARM Trusted Firmware will invalidate the CPU branch predictor state in order to protect against aliasing attacks. This patch exposes the PSCI "VERSION" function via psci_ops, so that it can be invoked outside of the PSCI driver where necessary. Acked-by: Lorenzo Pieralisi Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- drivers/firmware/psci.c | 2 ++ include/linux/psci.h | 1 + 2 files changed, 3 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c index ae70d2485ca1..290f8982e7b3 100644 --- a/drivers/firmware/psci.c +++ b/drivers/firmware/psci.c @@ -305,6 +305,8 @@ static void __init psci_init_migrate(void) static void __init psci_0_2_set_functions(void) { pr_info("Using standard PSCI v0.2 function IDs\n"); + psci_ops.get_version = psci_get_version; + psci_function_id[PSCI_FN_CPU_SUSPEND] = PSCI_FN_NATIVE(0_2, CPU_SUSPEND); psci_ops.cpu_suspend = psci_cpu_suspend; diff --git a/include/linux/psci.h b/include/linux/psci.h index 12c4865457ad..04b4d92c7791 100644 --- a/include/linux/psci.h +++ b/include/linux/psci.h @@ -25,6 +25,7 @@ bool psci_power_state_loses_context(u32 state); bool psci_power_state_is_valid(u32 state); struct psci_operations { + u32 (*get_version)(void); int (*cpu_suspend)(u32 state, unsigned long entry_point); int (*cpu_off)(u32 state); int (*cpu_on)(unsigned long cpuid, unsigned long entry_point); From patchwork Fri Jun 14 03:07:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166753 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1505612ilk; Thu, 13 Jun 2019 20:12:35 -0700 (PDT) X-Google-Smtp-Source: APXvYqxW1t6cf+1vO3r8M/CG+mXzT8pCnK1hui0GoiGraksTYcF5q8lTkBkxrK0ePKKhr6TO+aRH X-Received: by 2002:a17:90a:1ac5:: with SMTP id p63mr8594926pjp.25.1560481955333; Thu, 13 Jun 2019 20:12:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560481955; cv=none; d=google.com; s=arc-20160816; b=W7m4r+FAnUYGtQatZax4aTKrHUUQ88dnFH0wWJJ93vkY2h/fQlWdIlyCJAKhcBig+E ZFLcJWCVFDFMrOISXGdcyWTIbYar9VUPexossIvGuDT9Zs+fJyEGpdRpmCFYMJ4PC48A 47pae4PQLWF6XkOiDQQKttHQKvkm0TdYDlwYsOTCx2Vo2mz2d4R+kB/BBP1YLkjLU9Le +40IK8pRDJXWAsKxNJ9aWJ3BJnKbj32btnbVMSucMhXy4rUVm9gX+ciYIFl0vfAlmo6i 2i0ZCaKfVNVqyVG7xmsfpnJYE68I9Oefzt/Rdd2Eh0fmO5zaCDTmY46ETFDq8Ztor7DN sM9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Cnuqc1YlBQBZ4RWPKzaqy9DfMXgSoNZrvvTdeydR7XY=; b=UNLhmv6f4maj9QSjosYZBj0auJMtfzaY0B7R3o45o5WEZ9FUNe3Jvwn2q1ySRl7sRy jLpdYxar3pjUNY4u5GWGT32/WjqadIc74a3DrtvfcDKfqCsJ52V/kY/uwJfvsyM+rxZH x38vA8PamctXZUj/afRJ/UILRxtBJHHZJVcmLfeSwop4jP+5EqtlELy91RnMcyXc7WgW PfyR8ygIFwsWOyyAs4Ra9EFT+gAuA5rfVAQIPcjY2n8u63YRwWLNbB+WuW2cTa4NSUiy 98ugtZu6Pu0gYgbyIAbdFeruRX39snJsWPAfP+d4SXvTc4tF9ga5BerxDnfte40Ry1ZR 1/qA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bCx056PQ; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e8si1073936plb.420.2019.06.13.20.12.35; Thu, 13 Jun 2019 20:12:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bCx056PQ; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726447AbfFNDMe (ORCPT + 14 others); Thu, 13 Jun 2019 23:12:34 -0400 Received: from mail-pl1-f194.google.com ([209.85.214.194]:39800 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725819AbfFNDMe (ORCPT ); Thu, 13 Jun 2019 23:12:34 -0400 Received: by mail-pl1-f194.google.com with SMTP id b7so373869pls.6 for ; Thu, 13 Jun 2019 20:12:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Cnuqc1YlBQBZ4RWPKzaqy9DfMXgSoNZrvvTdeydR7XY=; b=bCx056PQTrtu4bcBdGQja4CHWdjoDe+5H+fLVBYU88hpCO0mdINyMFmiKguyS9D9RA ME26/gyKidKHOT6sc2fheDDmaUJ0eWshUQVYcqitEEOshB0SeFtS/fpdh0VOETgQSUrE furCIjr9M9DUKfdzkgNQVVHORPVTjYraCnjBkAm5yNTA8mes84LCT7IpFkgDSD4SpROE fMYNjTQ9OonP/wgTkKipTtd21c24O2/kCzcFzEdw5dKeswwnJYuIlKf8QLudP8C1WKyQ Oj5KaXiQ5v9trrdDY0ftykarsxdOhpRb4VZqVabajO83FiVDvAnSavu1yR+F0apB6hzm YW6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Cnuqc1YlBQBZ4RWPKzaqy9DfMXgSoNZrvvTdeydR7XY=; b=Dpy+8claWpwjJkK14CsEoF+nOiE+/WPPxLn3Nn9zF85hKY8AqXy/SeVWoi93S+sLNW pzYHYkbpfIVAYtqJhAfEYigB4N0DFjSgTydpHCKvhcAu8XUS+2mvSr623bbflSlO+Uwx UstNcwsPzANRlt/YZHJm29mxtvxNYcqkYd9Y2yJevdyzifVqN5cBu0j5v31WA7bnwLN+ 32WLfCx0xqq4DJ8pfqDJ88OB5xYhzpNGN4wW8iCjbheEgf7RuOyk4lsiOFjY9o5fndQd gCZi/AU/uXu+8T+bwgjbAZZVHTGpgJbwB6UAShhgfpWYvtCBo5LZBSHpRyMU6j0uJ4j5 oY1w== X-Gm-Message-State: APjAAAXiI5JHINEznm5igtDGGiGjfJxJXsPPwrVeaZZS+pFyzhEpWGja DT4H6v0+s7W1m5apCKeqMmcFwg== X-Received: by 2002:a17:902:8203:: with SMTP id x3mr7315832pln.304.1560481953855; Thu, 13 Jun 2019 20:12:33 -0700 (PDT) Received: from localhost ([122.172.66.84]) by smtp.gmail.com with ESMTPSA id d9sm1097756pgj.34.2019.06.13.20.12.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jun 2019 20:12:33 -0700 (PDT) From: Viresh Kumar To: linux-arm-kernel@lists.infradead.org, Julien Thierry Cc: Viresh Kumar , stable@vger.kernel.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 15/45] arm64: Factor out TTBR0_EL1 post-update workaround into a specific asm macro Date: Fri, 14 Jun 2019 08:37:58 +0530 Message-Id: <75c8ebf74edaebb1a62190c9ae1f39c609963f06.1560480942.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Catalin Marinas commit f33bcf03e6079668da6bf4eec4a7dcf9289131d0 upstream. This patch takes the errata workaround code out of cpu_do_switch_mm into a dedicated post_ttbr0_update_workaround macro which will be reused in a subsequent patch. Cc: Will Deacon Cc: James Morse Cc: Kees Cook Reviewed-by: Mark Rutland Signed-off-by: Catalin Marinas [ v4.4: Included cpufeature.h and adapted to use alternative_if_not ] Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/assembler.h | 18 ++++++++++++++++++ arch/arm64/mm/proc.S | 11 +---------- 2 files changed, 19 insertions(+), 10 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index 2b30363a3a89..8ab46508e836 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -23,6 +23,7 @@ #ifndef __ASM_ASSEMBLER_H #define __ASM_ASSEMBLER_H +#include #include #include #include @@ -282,4 +283,21 @@ lr .req x30 // link register .Ldone\@: .endm +/* + * Errata workaround post TTBR0_EL1 update. + */ + .macro post_ttbr0_update_workaround +#ifdef CONFIG_CAVIUM_ERRATUM_27456 +alternative_if_not ARM64_WORKAROUND_CAVIUM_27456 + ret + nop + nop + nop +alternative_else + ic iallu + dsb nsh + isb +#endif + .endm + #endif /* __ASM_ASSEMBLER_H */ diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index f09636738007..4eb1084e203a 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -139,17 +139,8 @@ ENTRY(cpu_do_switch_mm) bfi x0, x1, #48, #16 // set the ASID msr ttbr0_el1, x0 // set TTBR0 isb -alternative_if_not ARM64_WORKAROUND_CAVIUM_27456 + post_ttbr0_update_workaround ret - nop - nop - nop -alternative_else - ic iallu - dsb nsh - isb - ret -alternative_endif ENDPROC(cpu_do_switch_mm) .section ".text.init", #alloc, #execinstr From patchwork Fri Jun 14 03:07:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166754 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1505646ilk; Thu, 13 Jun 2019 20:12:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqxRttCHMMCBlDA91aFdNiH1jEoFjyP2N56yFmsQp2XuHS+XsmJCB+XGN1Hs3bnaWr9bSWPH X-Received: by 2002:a17:902:be10:: with SMTP id r16mr28999706pls.294.1560481958034; Thu, 13 Jun 2019 20:12:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560481958; cv=none; d=google.com; s=arc-20160816; b=V4Kjgn8CvIlj9DGFzhlqbFiSXSTib6YfN/wUjGOarK+fCWuciKThz+UZhuo5HZJsnr yercgvaq/ZcwJM8/qe/xAnSLdlETk2/DbaXl4n+x2Wone6wz+TdPhSdR03oxKSc0mqQq 0uIMaUtL++26y9QbIW9CtuoOzNPZPwSi20DmDw1Y+ejsertVyWwFA2UvFT2tHAvfb6jL 8VWTN+mCMlZj6c2ifuWwGOTTK12eiGaXwis1ChZd9oGCTImKRf6mBxY4DjxzgJGk9M35 Yz5VbgXRKghwlqY82d+4KkB9LzaRj8BP+6wRuQYqKxDTdZydhcCTKEODZ5TJt8+o+/Z8 6sQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=FJU6AKZYmaWbov8SdJbQnRPRbYy33d5KJviuZzujVLk=; b=jWtnovbkeMm8f8pe2OrJDo1YohtqIvntK7A1mSCFcsz68dXNZbql7yVrPUdZ0GMm6i 7+KWmHqYJgnLUe0jjs6y4mzFfoH0qmBXIatVnsQACxzE2oJe3Vx/n5nk//QpP4gZ/zkk rHu9ZVvi1mDDbbcBkSfKcWlxvzAapodKNZclxoJE4QeL28PillMFzTGVlr469A1GsPik h1Gazt1S1n3otzYbZoTIs62UctGNZynY7mCt18FQ5E5OeAJmFD2/eemjTqpR4ccHUIi4 4uyd7fwWAGHdHo7rIrG7NvDNHIUNia8mlnQ2wmWdMcze5IvQb7S9BcS6s+pbUSmRDEgE OCrg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YrcvAeSG; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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We will soon need to invoke a CPU-specific function pointer after changing page tables, so move post_ttbr_update_workaround out into C code to make this possible. Signed-off-by: Marc Zyngier Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas [ v4.4: Removed cpufeature.h, included alternative.h, dropped entry.S changes and adapted to drop alternative_if_not ] Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/assembler.h | 18 ------------------ arch/arm64/mm/context.c | 10 ++++++++++ arch/arm64/mm/proc.S | 3 +-- 3 files changed, 11 insertions(+), 20 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index 8ab46508e836..2b30363a3a89 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -23,7 +23,6 @@ #ifndef __ASM_ASSEMBLER_H #define __ASM_ASSEMBLER_H -#include #include #include #include @@ -283,21 +282,4 @@ lr .req x30 // link register .Ldone\@: .endm -/* - * Errata workaround post TTBR0_EL1 update. - */ - .macro post_ttbr0_update_workaround -#ifdef CONFIG_CAVIUM_ERRATUM_27456 -alternative_if_not ARM64_WORKAROUND_CAVIUM_27456 - ret - nop - nop - nop -alternative_else - ic iallu - dsb nsh - isb -#endif - .endm - #endif /* __ASM_ASSEMBLER_H */ diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index e87f53ff5f58..492d2968fa8f 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -22,6 +22,7 @@ #include #include +#include #include #include #include @@ -185,6 +186,15 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) cpu_switch_mm(mm->pgd, mm); } +/* Errata workaround post TTBRx_EL1 update. */ +asmlinkage void post_ttbr_update_workaround(void) +{ + asm(ALTERNATIVE("nop; nop; nop", + "ic iallu; dsb nsh; isb", + ARM64_WORKAROUND_CAVIUM_27456, + CONFIG_CAVIUM_ERRATUM_27456)); +} + static int asids_init(void) { int fld = cpuid_feature_extract_field(read_cpuid(ID_AA64MMFR0_EL1), 4); diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 4eb1084e203a..a70b712ca94a 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -139,8 +139,7 @@ ENTRY(cpu_do_switch_mm) bfi x0, x1, #48, #16 // set the ASID msr ttbr0_el1, x0 // set TTBR0 isb - post_ttbr0_update_workaround - ret + b post_ttbr_update_workaround // Back to C code... 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Add scope parameter to the arm64_cpu_capabilities::matches(), so that this can be reused for checking the capability on a given CPU vs the system wide. The system uses the default scope associated with the capability for initialising the CPU_HWCAPs and ELF_HWCAPs. Cc: James Morse Cc: Marc Zyngier Cc: Andre Przywara Cc: Will Deacon Reviewed-by: Catalin Marinas Signed-off-by: Suzuki K Poulose Signed-off-by: Will Deacon [ v4.4: Changes made according to 4.4 codebase ] Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/cpufeature.h | 9 ++- arch/arm64/kernel/cpu_errata.c | 5 +- arch/arm64/kernel/cpufeature.c | 105 +++++++++++++++------------- 3 files changed, 70 insertions(+), 49 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index ad83c245781c..4c31e14c0f0e 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -74,10 +74,17 @@ struct arm64_ftr_reg { struct arm64_ftr_bits *ftr_bits; }; +/* scope of capability check */ +enum { + SCOPE_SYSTEM, + SCOPE_LOCAL_CPU, +}; + struct arm64_cpu_capabilities { const char *desc; u16 capability; - bool (*matches)(const struct arm64_cpu_capabilities *); + int def_scope; /* default scope */ + bool (*matches)(const struct arm64_cpu_capabilities *caps, int scope); int (*enable)(void *); /* Called on all active CPUs */ union { struct { /* To be used for erratum handling only */ diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index a3e846a28b05..0971d80d3623 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -29,10 +29,12 @@ MIDR_ARCHITECTURE_MASK) static bool __maybe_unused -is_affected_midr_range(const struct arm64_cpu_capabilities *entry) +is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope) { u32 midr = read_cpuid_id(); + WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); + if ((midr & CPU_MODEL_MASK) != entry->midr_model) return false; @@ -42,6 +44,7 @@ is_affected_midr_range(const struct arm64_cpu_capabilities *entry) } #define MIDR_RANGE(model, min, max) \ + .def_scope = SCOPE_LOCAL_CPU, \ .matches = is_affected_midr_range, \ .midr_model = model, \ .midr_range_min = min, \ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index c7a2827658fd..79c1cd9f15c2 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -589,6 +589,48 @@ u64 read_system_reg(u32 id) return regp->sys_val; } +/* + * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated. + * Read the system register on the current CPU + */ +static u64 __raw_read_system_reg(u32 sys_id) +{ + switch (sys_id) { + case SYS_ID_PFR0_EL1: return (u64)read_cpuid(ID_PFR0_EL1); + case SYS_ID_PFR1_EL1: return (u64)read_cpuid(ID_PFR1_EL1); + case SYS_ID_DFR0_EL1: return (u64)read_cpuid(ID_DFR0_EL1); + case SYS_ID_MMFR0_EL1: return (u64)read_cpuid(ID_MMFR0_EL1); + case SYS_ID_MMFR1_EL1: return (u64)read_cpuid(ID_MMFR1_EL1); + case SYS_ID_MMFR2_EL1: return (u64)read_cpuid(ID_MMFR2_EL1); + case SYS_ID_MMFR3_EL1: return (u64)read_cpuid(ID_MMFR3_EL1); + case SYS_ID_ISAR0_EL1: return (u64)read_cpuid(ID_ISAR0_EL1); + case SYS_ID_ISAR1_EL1: return (u64)read_cpuid(ID_ISAR1_EL1); + case SYS_ID_ISAR2_EL1: return (u64)read_cpuid(ID_ISAR2_EL1); + case SYS_ID_ISAR3_EL1: return (u64)read_cpuid(ID_ISAR3_EL1); + case SYS_ID_ISAR4_EL1: return (u64)read_cpuid(ID_ISAR4_EL1); + case SYS_ID_ISAR5_EL1: return (u64)read_cpuid(ID_ISAR4_EL1); + case SYS_MVFR0_EL1: return (u64)read_cpuid(MVFR0_EL1); + case SYS_MVFR1_EL1: return (u64)read_cpuid(MVFR1_EL1); + case SYS_MVFR2_EL1: return (u64)read_cpuid(MVFR2_EL1); + + case SYS_ID_AA64PFR0_EL1: return (u64)read_cpuid(ID_AA64PFR0_EL1); + case SYS_ID_AA64PFR1_EL1: return (u64)read_cpuid(ID_AA64PFR0_EL1); + case SYS_ID_AA64DFR0_EL1: return (u64)read_cpuid(ID_AA64DFR0_EL1); + case SYS_ID_AA64DFR1_EL1: return (u64)read_cpuid(ID_AA64DFR0_EL1); + case SYS_ID_AA64MMFR0_EL1: return (u64)read_cpuid(ID_AA64MMFR0_EL1); + case SYS_ID_AA64MMFR1_EL1: return (u64)read_cpuid(ID_AA64MMFR1_EL1); + case SYS_ID_AA64ISAR0_EL1: return (u64)read_cpuid(ID_AA64ISAR0_EL1); + case SYS_ID_AA64ISAR1_EL1: return (u64)read_cpuid(ID_AA64ISAR1_EL1); + + case SYS_CNTFRQ_EL0: return (u64)read_cpuid(CNTFRQ_EL0); + case SYS_CTR_EL0: return (u64)read_cpuid(CTR_EL0); + case SYS_DCZID_EL0: return (u64)read_cpuid(DCZID_EL0); + default: + BUG(); + return 0; + } +} + #include static bool @@ -600,19 +642,24 @@ feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) } static bool -has_cpuid_feature(const struct arm64_cpu_capabilities *entry) +has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) { u64 val; - val = read_system_reg(entry->sys_reg); + WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); + if (scope == SCOPE_SYSTEM) + val = read_system_reg(entry->sys_reg); + else + val = __raw_read_system_reg(entry->sys_reg); + return feature_matches(val, entry); } -static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry) +static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) { bool has_sre; - if (!has_cpuid_feature(entry)) + if (!has_cpuid_feature(entry, scope)) return false; has_sre = gic_enable_sre(); @@ -627,6 +674,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { { .desc = "GIC system register CPU interface", .capability = ARM64_HAS_SYSREG_GIC_CPUIF, + .def_scope = SCOPE_SYSTEM, .matches = has_useable_gicv3_cpuif, .sys_reg = SYS_ID_AA64PFR0_EL1, .field_pos = ID_AA64PFR0_GIC_SHIFT, @@ -636,6 +684,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { { .desc = "Privileged Access Never", .capability = ARM64_HAS_PAN, + .def_scope = SCOPE_SYSTEM, .matches = has_cpuid_feature, .sys_reg = SYS_ID_AA64MMFR1_EL1, .field_pos = ID_AA64MMFR1_PAN_SHIFT, @@ -647,6 +696,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { { .desc = "LSE atomic instructions", .capability = ARM64_HAS_LSE_ATOMICS, + .def_scope = SCOPE_SYSTEM, .matches = has_cpuid_feature, .sys_reg = SYS_ID_AA64ISAR0_EL1, .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT, @@ -656,6 +706,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { { .desc = "32-bit EL0 Support", .capability = ARM64_HAS_32BIT_EL0, + .def_scope = SCOPE_SYSTEM, .matches = has_cpuid_feature, .sys_reg = SYS_ID_AA64PFR0_EL1, .field_pos = ID_AA64PFR0_EL0_SHIFT, @@ -667,6 +718,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { #define HWCAP_CAP(reg, field, min_value, type, cap) \ { \ .desc = #cap, \ + .def_scope = SCOPE_SYSTEM, \ .matches = has_cpuid_feature, \ .sys_reg = reg, \ .field_pos = field, \ @@ -745,7 +797,7 @@ static void setup_cpu_hwcaps(void) const struct arm64_cpu_capabilities *hwcaps = arm64_hwcaps; for (i = 0; hwcaps[i].desc; i++) - if (hwcaps[i].matches(&hwcaps[i])) + if (hwcaps[i].matches(&hwcaps[i], hwcaps[i].def_scope)) cap_set_hwcap(&hwcaps[i]); } @@ -755,7 +807,7 @@ void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps, int i; for (i = 0; caps[i].desc; i++) { - if (!caps[i].matches(&caps[i])) + if (!caps[i].matches(&caps[i], caps[i].def_scope)) continue; if (!cpus_have_cap(caps[i].capability)) @@ -800,47 +852,6 @@ static inline void set_sys_caps_initialised(void) sys_caps_initialised = true; } -/* - * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated. - */ -static u64 __raw_read_system_reg(u32 sys_id) -{ - switch (sys_id) { - case SYS_ID_PFR0_EL1: return (u64)read_cpuid(ID_PFR0_EL1); - case SYS_ID_PFR1_EL1: return (u64)read_cpuid(ID_PFR1_EL1); - case SYS_ID_DFR0_EL1: return (u64)read_cpuid(ID_DFR0_EL1); - case SYS_ID_MMFR0_EL1: return (u64)read_cpuid(ID_MMFR0_EL1); - case SYS_ID_MMFR1_EL1: return (u64)read_cpuid(ID_MMFR1_EL1); - case SYS_ID_MMFR2_EL1: return (u64)read_cpuid(ID_MMFR2_EL1); - case SYS_ID_MMFR3_EL1: return (u64)read_cpuid(ID_MMFR3_EL1); - case SYS_ID_ISAR0_EL1: return (u64)read_cpuid(ID_ISAR0_EL1); - case SYS_ID_ISAR1_EL1: return (u64)read_cpuid(ID_ISAR1_EL1); - case SYS_ID_ISAR2_EL1: return (u64)read_cpuid(ID_ISAR2_EL1); - case SYS_ID_ISAR3_EL1: return (u64)read_cpuid(ID_ISAR3_EL1); - case SYS_ID_ISAR4_EL1: return (u64)read_cpuid(ID_ISAR4_EL1); - case SYS_ID_ISAR5_EL1: return (u64)read_cpuid(ID_ISAR4_EL1); - case SYS_MVFR0_EL1: return (u64)read_cpuid(MVFR0_EL1); - case SYS_MVFR1_EL1: return (u64)read_cpuid(MVFR1_EL1); - case SYS_MVFR2_EL1: return (u64)read_cpuid(MVFR2_EL1); - - case SYS_ID_AA64PFR0_EL1: return (u64)read_cpuid(ID_AA64PFR0_EL1); - case SYS_ID_AA64PFR1_EL1: return (u64)read_cpuid(ID_AA64PFR0_EL1); - case SYS_ID_AA64DFR0_EL1: return (u64)read_cpuid(ID_AA64DFR0_EL1); - case SYS_ID_AA64DFR1_EL1: return (u64)read_cpuid(ID_AA64DFR0_EL1); - case SYS_ID_AA64MMFR0_EL1: return (u64)read_cpuid(ID_AA64MMFR0_EL1); - case SYS_ID_AA64MMFR1_EL1: return (u64)read_cpuid(ID_AA64MMFR1_EL1); - case SYS_ID_AA64ISAR0_EL1: return (u64)read_cpuid(ID_AA64ISAR0_EL1); - case SYS_ID_AA64ISAR1_EL1: return (u64)read_cpuid(ID_AA64ISAR1_EL1); - - case SYS_CNTFRQ_EL0: return (u64)read_cpuid(CNTFRQ_EL0); - case SYS_CTR_EL0: return (u64)read_cpuid(CTR_EL0); - case SYS_DCZID_EL0: return (u64)read_cpuid(DCZID_EL0); - default: - BUG(); - return 0; - } -} - /* * Park the CPU which doesn't have the capability as advertised * by the system. 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Aliasing attacks against CPU branch predictors can allow an attacker to redirect speculative control flow on some CPUs and potentially divulge information from one context to another. This patch adds initial skeleton code behind a new Kconfig option to enable implementation-specific mitigations against these attacks for CPUs that are affected. Co-developed-by: Marc Zyngier Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas [ v4.4: Changes made according to 4.4 codebase ] Signed-off-by: Viresh Kumar --- arch/arm64/Kconfig | 17 +++++++ arch/arm64/include/asm/cpufeature.h | 3 +- arch/arm64/include/asm/mmu.h | 39 +++++++++++++++ arch/arm64/include/asm/sysreg.h | 2 + arch/arm64/kernel/Makefile | 5 ++ arch/arm64/kernel/bpi.S | 55 +++++++++++++++++++++ arch/arm64/kernel/cpu_errata.c | 74 +++++++++++++++++++++++++++++ arch/arm64/kernel/cpufeature.c | 3 +- arch/arm64/kernel/entry.S | 8 ++-- arch/arm64/mm/context.c | 2 + arch/arm64/mm/fault.c | 16 +++++++ 11 files changed, 219 insertions(+), 5 deletions(-) create mode 100644 arch/arm64/kernel/bpi.S -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index f18b8c26a959..5fa01073566b 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -624,6 +624,23 @@ config FORCE_MAX_ZONEORDER However for 4K, we choose a higher default value, 11 as opposed to 10, giving us 4M allocations matching the default size used by generic code. +config HARDEN_BRANCH_PREDICTOR + bool "Harden the branch predictor against aliasing attacks" if EXPERT + default y + help + Speculation attacks against some high-performance processors rely on + being able to manipulate the branch predictor for a victim context by + executing aliasing branches in the attacker context. Such attacks + can be partially mitigated against by clearing internal branch + predictor state and limiting the prediction logic in some situations. + + This config option will take CPU-specific actions to harden the + branch predictor against aliasing attacks and may rely on specific + instruction sequences or control bits being set by the system + firmware. + + If unsure, say Y. + menuconfig ARMV8_DEPRECATED bool "Emulate deprecated/obsolete ARMv8 instructions" depends on COMPAT diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 4c31e14c0f0e..ff3753127a30 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -32,8 +32,9 @@ #define ARM64_WORKAROUND_834220 7 #define ARM64_WORKAROUND_CAVIUM_27456 8 #define ARM64_HAS_32BIT_EL0 9 +#define ARM64_HARDEN_BRANCH_PREDICTOR 10 -#define ARM64_NCAPS 10 +#define ARM64_NCAPS 11 #ifndef __ASSEMBLY__ diff --git a/arch/arm64/include/asm/mmu.h b/arch/arm64/include/asm/mmu.h index 990124a67eeb..8d0129210416 100644 --- a/arch/arm64/include/asm/mmu.h +++ b/arch/arm64/include/asm/mmu.h @@ -16,6 +16,8 @@ #ifndef __ASM_MMU_H #define __ASM_MMU_H +#include + typedef struct { atomic64_t id; void *vdso; @@ -28,6 +30,43 @@ typedef struct { */ #define ASID(mm) ((mm)->context.id.counter & 0xffff) +typedef void (*bp_hardening_cb_t)(void); + +struct bp_hardening_data { + int hyp_vectors_slot; + bp_hardening_cb_t fn; +}; + +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR +extern char __bp_harden_hyp_vecs_start[], __bp_harden_hyp_vecs_end[]; + +DECLARE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data); + +static inline struct bp_hardening_data *arm64_get_bp_hardening_data(void) +{ + return this_cpu_ptr(&bp_hardening_data); +} + +static inline void arm64_apply_bp_hardening(void) +{ + struct bp_hardening_data *d; + + if (!cpus_have_cap(ARM64_HARDEN_BRANCH_PREDICTOR)) + return; + + d = arm64_get_bp_hardening_data(); + if (d->fn) + d->fn(); +} +#else +static inline struct bp_hardening_data *arm64_get_bp_hardening_data(void) +{ + return NULL; +} + +static inline void arm64_apply_bp_hardening(void) { } +#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */ + extern void paging_init(void); extern void __iomem *early_io_map(phys_addr_t phys, unsigned long virt); extern void init_mem_pgprot(void); diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 50150320f80d..523b089fb408 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -95,6 +95,8 @@ #define ID_AA64ISAR0_AES_SHIFT 4 /* id_aa64pfr0 */ +#define ID_AA64PFR0_CSV2_SHIFT 56 +#define ID_AA64PFR0_SVE_SHIFT 32 #define ID_AA64PFR0_GIC_SHIFT 24 #define ID_AA64PFR0_ASIMD_SHIFT 20 #define ID_AA64PFR0_FP_SHIFT 16 diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index 474691f8b13a..aa8f28210219 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -42,7 +42,12 @@ arm64-obj-$(CONFIG_PCI) += pci.o arm64-obj-$(CONFIG_ARMV8_DEPRECATED) += armv8_deprecated.o arm64-obj-$(CONFIG_ACPI) += acpi.o +ifeq ($(CONFIG_KVM),y) +arm64-obj-$(CONFIG_HARDEN_BRANCH_PREDICTOR) += bpi.o +endif + obj-y += $(arm64-obj-y) vdso/ + obj-m += $(arm64-obj-m) head-y := head.o extra-y += $(head-y) vmlinux.lds diff --git a/arch/arm64/kernel/bpi.S b/arch/arm64/kernel/bpi.S new file mode 100644 index 000000000000..06a931eb2673 --- /dev/null +++ b/arch/arm64/kernel/bpi.S @@ -0,0 +1,55 @@ +/* + * Contains CPU specific branch predictor invalidation sequences + * + * Copyright (C) 2018 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +.macro ventry target + .rept 31 + nop + .endr + b \target +.endm + +.macro vectors target + ventry \target + 0x000 + ventry \target + 0x080 + ventry \target + 0x100 + ventry \target + 0x180 + + ventry \target + 0x200 + ventry \target + 0x280 + ventry \target + 0x300 + ventry \target + 0x380 + + ventry \target + 0x400 + ventry \target + 0x480 + ventry \target + 0x500 + ventry \target + 0x580 + + ventry \target + 0x600 + ventry \target + 0x680 + ventry \target + 0x700 + ventry \target + 0x780 +.endm + + .align 11 +ENTRY(__bp_harden_hyp_vecs_start) + .rept 4 + vectors __kvm_hyp_vector + .endr +ENTRY(__bp_harden_hyp_vecs_end) diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 0971d80d3623..6c5e9e462629 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -43,6 +43,80 @@ is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope) return (midr >= entry->midr_range_min && midr <= entry->midr_range_max); } +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR +#include +#include + +DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data); + +#ifdef CONFIG_KVM +static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start, + const char *hyp_vecs_end) +{ + void *dst = __bp_harden_hyp_vecs_start + slot * SZ_2K; + int i; + + for (i = 0; i < SZ_2K; i += 0x80) + memcpy(dst + i, hyp_vecs_start, hyp_vecs_end - hyp_vecs_start); + + flush_icache_range((uintptr_t)dst, (uintptr_t)dst + SZ_2K); +} + +static void __install_bp_hardening_cb(bp_hardening_cb_t fn, + const char *hyp_vecs_start, + const char *hyp_vecs_end) +{ + static int last_slot = -1; + static DEFINE_SPINLOCK(bp_lock); + int cpu, slot = -1; + + spin_lock(&bp_lock); + for_each_possible_cpu(cpu) { + if (per_cpu(bp_hardening_data.fn, cpu) == fn) { + slot = per_cpu(bp_hardening_data.hyp_vectors_slot, cpu); + break; + } + } + + if (slot == -1) { + last_slot++; + BUG_ON(((__bp_harden_hyp_vecs_end - __bp_harden_hyp_vecs_start) + / SZ_2K) <= last_slot); + slot = last_slot; + __copy_hyp_vect_bpi(slot, hyp_vecs_start, hyp_vecs_end); + } + + __this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot); + __this_cpu_write(bp_hardening_data.fn, fn); + spin_unlock(&bp_lock); +} +#else +static void __install_bp_hardening_cb(bp_hardening_cb_t fn, + const char *hyp_vecs_start, + const char *hyp_vecs_end) +{ + __this_cpu_write(bp_hardening_data.fn, fn); +} +#endif /* CONFIG_KVM */ + +static void install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry, + bp_hardening_cb_t fn, + const char *hyp_vecs_start, + const char *hyp_vecs_end) +{ + u64 pfr0; + + if (!entry->matches(entry, SCOPE_LOCAL_CPU)) + return; + + pfr0 = read_cpuid(ID_AA64PFR0_EL1); + if (cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_CSV2_SHIFT)) + return; + + __install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end); +} +#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */ + #define MIDR_RANGE(model, min, max) \ .def_scope = SCOPE_LOCAL_CPU, \ .matches = is_affected_midr_range, \ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 79c1cd9f15c2..ab847c4fabcb 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -83,7 +83,8 @@ static struct arm64_ftr_bits ftr_id_aa64isar0[] = { }; static struct arm64_ftr_bits ftr_id_aa64pfr0[] = { - ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0), + ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 28, 0), ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0), ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index e6aec982dea9..05bfc71639fc 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -495,13 +495,15 @@ ENDPROC(el1_irq) * Instruction abort handling */ mrs x26, far_el1 - // enable interrupts before calling the main handler - enable_dbg_and_irq + msr daifclr, #(8 | 4 | 1) +#ifdef CONFIG_TRACE_IRQFLAGS + bl trace_hardirqs_off +#endif ct_user_exit mov x0, x26 orr x1, x25, #1 << 24 // use reserved ISS bit for instruction aborts mov x2, sp - bl do_mem_abort + bl do_el0_ia_bp_hardening b ret_to_user el0_fpsimd_acc: /* diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index 492d2968fa8f..be42bd3dca5c 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -193,6 +193,8 @@ asmlinkage void post_ttbr_update_workaround(void) "ic iallu; dsb nsh; isb", ARM64_WORKAROUND_CAVIUM_27456, CONFIG_CAVIUM_ERRATUM_27456)); + + arm64_apply_bp_hardening(); } static int asids_init(void) diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index 89abdf9af4e6..1878c881a247 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -535,6 +535,22 @@ asmlinkage void __exception do_mem_abort(unsigned long addr, unsigned int esr, arm64_notify_die("", regs, &info, esr); } +asmlinkage void __exception do_el0_ia_bp_hardening(unsigned long addr, + unsigned int esr, + struct pt_regs *regs) +{ + /* + * We've taken an instruction abort from userspace and not yet + * re-enabled IRQs. If the address is a kernel address, apply + * BP hardening prior to enabling IRQs and pre-emption. + */ + if (addr > TASK_SIZE) + arm64_apply_bp_hardening(); + + local_irq_enable(); + do_mem_abort(addr, esr, regs); +} + /* * Handle stack alignment exceptions. */ From patchwork Fri Jun 14 03:08:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166757 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1505753ilk; Thu, 13 Jun 2019 20:12:45 -0700 (PDT) X-Google-Smtp-Source: APXvYqw4DXVcUi0UYYMAFyGzVltbRYBSMiemKda8QTYxkkdTIZERSdfZmNN6UdM+ovsOg/Md7+yw X-Received: by 2002:a17:902:860c:: with SMTP id f12mr91340746plo.127.1560481965873; Thu, 13 Jun 2019 20:12:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560481965; cv=none; d=google.com; s=arc-20160816; b=OJD9oeaPEKmCuPEXq86lVBocOemjNtnGs1h5NiNYII6I2PlnlKuX+LHKDPGzQijzyn KMuZ5YBsrMoAPEwYEGHWEV6X+NX7DAymtCqpfY+NQ+k/gOpbd9lMxomJkJSt6aBDrocI vYPH4u6yoSOdSywIBja4i6k8V+ZsgBotuVb6Xt9jGTtk4ciuw0yVMQooBYnmxEcjQr7n uYRHJd1+CO9VXQ1Nq1/Sk6dT5h0f5HmqD4W9Ef30xEMjYvwgC/aHA3iyngk5pgfLJ3qe ntoAwm1XhheBZG0i/F/P7cfw6TDd3cRYx3n3HN3n6y3P3060CZTT8+dQMzjubAyzMmj0 LcVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=7MRMdAKqkkU6zuM8WMZXIs4D8fug3sxafZUJy2Rr9SE=; b=urlAhEmU/un3SoRLpf4z+hfc0/jRpgzOV+MG70SkNhrou9s2yRx0B7i02FI5z0n1P1 JtHzF6stLY5+Lztg29Bg4NDlbbc8qBt4NRkIEuv1Y3/OmHs3lkjo6tUmVrpN/GW2KIWT G+dUBU3Ufia5NE4uScQx0vo2s9R1FzEieJONtBtKvIqVTCW1dQSBtSxxW/DilaGX1Lwf /07scvp7nI6f6/aBq+lIfe36MjaYN2Srgx044o3rnIg0DNkOvosi86A5syWZ+3GXkbnN 2dQ7yF94QRSow48jDNnrvGmp1nH95GfU3Oacj6KTfaeERitzfEDsVqYroGj/fRgms8vi SdEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zIBaeowz; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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We call arm64_apply_bp_hardening() from post_ttbr_update_workaround, which has the unexpected consequence of being triggered on every exception return to userspace when ARM64_SW_TTBR0_PAN is selected, even if no context switch actually occured. This is a bit suboptimal, and it would be more logical to only invalidate the branch predictor when we actually switch to a different mm. In order to solve this, move the call to arm64_apply_bp_hardening() into check_and_switch_context(), where we're guaranteed to pick a different mm context. Acked-by: Will Deacon Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/mm/context.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index be42bd3dca5c..de5afc27b4e6 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -183,6 +183,8 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) raw_spin_unlock_irqrestore(&cpu_asid_lock, flags); switch_mm_fastpath: + arm64_apply_bp_hardening(); + cpu_switch_mm(mm->pgd, mm); } @@ -193,8 +195,6 @@ asmlinkage void post_ttbr_update_workaround(void) "ic iallu; dsb nsh; isb", ARM64_WORKAROUND_CAVIUM_27456, CONFIG_CAVIUM_ERRATUM_27456)); - - arm64_apply_bp_hardening(); } static int asids_init(void) From patchwork Fri Jun 14 03:08:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166758 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1505786ilk; Thu, 13 Jun 2019 20:12:48 -0700 (PDT) X-Google-Smtp-Source: APXvYqwHwO7tvYGqMHl5TiK5/7hA1xNZEobroB49DLviMa9Td2GiMhGQeuZh18iVkIgFlPkOEDHu X-Received: by 2002:a17:902:467:: with SMTP id 94mr35193777ple.131.1560481968464; Thu, 13 Jun 2019 20:12:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560481968; cv=none; d=google.com; s=arc-20160816; b=UDHZSLOD4v7hFw+V4qKEn8LhdampEwNKK3ncnvWm0QC1qaQLecXzNrdatIc4iNie3l veLx1B+c5gLLgTKu6SmWyjSWED8vaYzbl5+EnR9tt2RlbWj+MPvhUTZs+vxeEFz4XJ4Y 7HFLHa/Rjm/2hj7VmA5WimuYteGm5dD7sqY6qpj0OyAgLU+wPEvO3XPBeyS8QisNBjgo 6ZIzLpGBD9sTCKM1x2VRe+Atr+fXAhPe/7CFMXVwi4h/8klLzNtAb0g7aGOuTBOXFs6o 8jhe/1pDIe6nt95W1jvmdx4XlkfxMz/+sxxeIG9UmERB+am5OQ0Xure54dw7A3auQVvs 9mHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=EmoJPia4REdmsbQ4H3ol9/VbnaPc01q7ugk/yi36Irk=; b=JgEdJjzE2hLvZmEO1Ak81sk2ENNiFrYF9PaBhNGLCNc7UHqRxfcED/xgbBU9ogui3l 06QXz21tnelC0xpw3gecZiIJeJqmNXimQS2RHngdZh6uKOzEa0pK9q6YH7bS41L3nHnL niYB+Ecj/r7K5B44nXF1RMBLC/LvESG9Z1k60QqXz7KXAAjZ0PnoDfBLMcc5l1oY6zzW ivtWuGAbekmK5/xWSe+FX1vz8CqYHzN9kFH97uRVsrWWiSCnLvtpYIHP+KatsJKD+2mt YwituWWjQx7HI6g6PnGTnsulf/1p4j3ko2FumAnLv/u0WQBJbPFxN4gUM7hqJL0Bm/2B jSAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PkSwe6ZM; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Certain architectures may have the kernel image mapped separately to alias the linear map. Introduce a macro lm_alias to translate a kernel image symbol into its linear alias. This is used in part with work to add CONFIG_DEBUG_VIRTUAL support for arm64. Reviewed-by: Mark Rutland Tested-by: Mark Rutland Signed-off-by: Laura Abbott Signed-off-by: Will Deacon Signed-off-by: Viresh Kumar --- include/linux/mm.h | 4 ++++ 1 file changed, 4 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/include/linux/mm.h b/include/linux/mm.h index 251adf4d8a71..f86fdf015c74 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -59,6 +59,10 @@ extern int sysctl_legacy_va_layout; #define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x), 0)) #endif +#ifndef lm_alias +#define lm_alias(x) __va(__pa_symbol(x)) +#endif + /* * To prevent common memory management code establishing * a zero page mapping on a read fault. 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[209.132.180.67]) by mx.google.com with ESMTP id e8si1073936plb.420.2019.06.13.20.12.50; Thu, 13 Jun 2019 20:12:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QEkL+VfU; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726622AbfFNDMu (ORCPT + 14 others); Thu, 13 Jun 2019 23:12:50 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:46585 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725819AbfFNDMu (ORCPT ); Thu, 13 Jun 2019 23:12:50 -0400 Received: by mail-pg1-f196.google.com with SMTP id v9so654172pgr.13 for ; Thu, 13 Jun 2019 20:12:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=y6GazOWQm4IOOc6xrMbLHqM6mIdOvxmzg2BIOtMFGqg=; b=QEkL+VfUuFHaUPoZrhk6ZT7Pxpl8boNF2CaYbIXPqGr11CT0iqDp494FCeQ9FYUKy0 k0ubcLU/OTtf72r0prvbE+Pdx5ECXxAEt8TO0W+6j10IaET7QsRQF7sgH6R/FLUnxZxW uG1aw0NYax+CHYI1AxUrR+v5etyy29g+yZJe0VgZ/t4zvTsQjLp33CRoLuMo0n3C1zk5 O4oE8SuXkXi/ufe9/gZVe98tHnfBcXIOQIBlQaSAIvZrdxv0NJFhcKl/Wu/nmZyHU9sH U6OblEjWNokjRmkhk3t0y+3HeyI66oGIKcdBgZSypchbQ97DwMOm54PQqRX+uYwxEi4l JyNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=y6GazOWQm4IOOc6xrMbLHqM6mIdOvxmzg2BIOtMFGqg=; b=EerC5hCjKiDXxcSEWi12Rc7Q738CmPP/Ur1eUMOeMQf9ypFAAk/rXmSWUs6OsA1oA9 FZbpY9NVCD9IpPWy9ISLV3okOKvNO9ATCNZ45a1RD7OZeCpXw1chaWFBK7V4ZXC5afUr NXP5ubIR2MYhqRxid4LnoEUFl2zkyaXT9t4rm/EWiQjo+Kt6RDRi6IRKs/xQP8qQSYDQ 4fMgbvBmK6AMTo2FskM10OlpHx68b1fSqNIpmd0xVAJ/AUcm1jbxf8IMuF1/6tbeJiRQ jA1BOWhQrB5alZff5DIQwBzfdX5dr8yG2NuBqKNbZESFkRVJJ24AXpEH6NLXnpooTqgG 1B/Q== X-Gm-Message-State: APjAAAXhmM6DP4Xutw0LYyiylx7HPQIhUfygQjp9l2PQHeJ6SSuIobxq K9V4qpak6hvMlIklShq3BFoG5w== X-Received: by 2002:a65:42ca:: with SMTP id l10mr33032835pgp.181.1560481969628; Thu, 13 Jun 2019 20:12:49 -0700 (PDT) Received: from localhost ([122.172.66.84]) by smtp.gmail.com with ESMTPSA id s9sm1131106pjp.7.2019.06.13.20.12.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jun 2019 20:12:49 -0700 (PDT) From: Viresh Kumar To: linux-arm-kernel@lists.infradead.org, Julien Thierry Cc: Viresh Kumar , stable@vger.kernel.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 21/45] arm64: entry: Apply BP hardening for high-priority synchronous exceptions Date: Fri, 14 Jun 2019 08:38:04 +0530 Message-Id: <342eec766d9748b0c9fb4a5da48220052a5426e6.1560480942.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Will Deacon commit 5dfc6ed27710c42cbc15db5c0d4475699991da0a upstream. Software-step and PC alignment fault exceptions have higher priority than instruction abort exceptions, so apply the BP hardening hooks there too if the user PC appears to reside in kernel space. Reported-by: Dan Hettena Reviewed-by: Marc Zyngier Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas [ v4.4: Resolved rebase conflicts ] Signed-off-by: Viresh Kumar --- arch/arm64/kernel/entry.S | 6 ++++-- arch/arm64/mm/fault.c | 9 +++++++++ 2 files changed, 13 insertions(+), 2 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 05bfc71639fc..42a141f01f3b 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -530,8 +530,10 @@ ENDPROC(el1_irq) * Stack or PC alignment exception handling */ mrs x26, far_el1 - // enable interrupts before calling the main handler - enable_dbg_and_irq + enable_dbg +#ifdef CONFIG_TRACE_IRQFLAGS + bl trace_hardirqs_off +#endif ct_user_exit mov x0, x26 mov x1, x25 diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index 1878c881a247..082f385b6592 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -561,6 +561,12 @@ asmlinkage void __exception do_sp_pc_abort(unsigned long addr, struct siginfo info; struct task_struct *tsk = current; + if (user_mode(regs)) { + if (instruction_pointer(regs) > TASK_SIZE) + arm64_apply_bp_hardening(); + local_irq_enable(); + } + if (show_unhandled_signals && unhandled_signal(tsk, SIGBUS)) pr_info_ratelimited("%s[%d]: %s exception: pc=%p sp=%p\n", tsk->comm, task_pid_nr(tsk), @@ -621,6 +627,9 @@ asmlinkage int __exception do_debug_exception(unsigned long addr_if_watchpoint, if (interrupts_enabled(regs)) trace_hardirqs_off(); + if (user_mode(regs) && instruction_pointer(regs) > TASK_SIZE) + arm64_apply_bp_hardening(); + if (!inf->fn(addr_if_watchpoint, esr, regs)) { rv = 1; } else { From patchwork Fri Jun 14 03:08:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166760 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1505862ilk; Thu, 13 Jun 2019 20:12:54 -0700 (PDT) X-Google-Smtp-Source: APXvYqwt0KrTSRK+e+Iwhpvj+vvhpMBsqZ25srUVsf6n2+nqQomup/Z16QzUbHxyL3B+/c+1W4nk X-Received: by 2002:a17:902:25ab:: with SMTP id y40mr34848779pla.268.1560481973936; Thu, 13 Jun 2019 20:12:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560481973; cv=none; d=google.com; s=arc-20160816; b=HK8rHvsKsv0x9XyHsqgYEE9WVe00WmzptDNEQ4nGI5Th/R/CfXFTE6yn8hshY40hLE ZVWrImkcGHj+R+M48S4mIpmnB/ICR3Fb11MaCivvnYPAjBJPpdMaT6UWR0kR5dUS8OBD TH9LhD4gm+moUsu4ZDOyjaEfnWIqKAg5tkpJwwF0mSo0XHwuC5W+oq2XOjlr5wD1nqpE KabYm/NULLg97071wh0Tw6ZY8cVEy2/Lg+lj2/YcZfd1frAOXsAk9xpG51LZcVF6yYQ9 NSOqpPAYZnp9cIwu3TmyuDbuCrrFC1mFF3StX2y0p6i06PLE1wac2l8UYyD3txPSV33S Me8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kL4bvpTkIxzXH8Y5LirqPgKQFts/fgCJz2Uk/H1BBsA=; b=idN/60LISC2G52WFaZH4pYoxi0Gh8PFKAGeBLhOgrEX/QT6g2yo3fRzlFmbPKGeT27 EOUeaLFB7TtKmCycdNFDr89517+uVrkqgYalspmgVYMzBs6H3S3UdXMOq8g1Q7KzPUEf SGy4iyUOVBi7AEl8HRmbZ4ei73Vychx+qCOCKQyB8zGFVcXbBkWCUaTT+Wn2ncE3bN+J FsMbC+0o5VFxLVwS46tohdf9OYRDHhaN4heqDxGCXAiAwtHD66x0HKNcXRTrcLqNK9My A2+b3X8EMI+jwcrEmokTzcJ8lpF9i2IDHVSbv2WzgjpU80jPf22DRL27MC16adX2QXjr FyuQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=u+88Jdi7; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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It is possible to take an IRQ from EL0 following a branch to a kernel address in such a way that the IRQ is prioritised over the instruction abort. Whilst an attacker would need to get the stars to align here, it might be sufficient with enough calibration so perform BP hardening in the rare case that we see a kernel address in the ELR when handling an IRQ from EL0. Reported-by: Dan Hettena Reviewed-by: Marc Zyngier Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/kernel/entry.S | 5 +++++ arch/arm64/mm/fault.c | 6 ++++++ 2 files changed, 11 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 42a141f01f3b..1548be9732ce 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -582,6 +582,11 @@ ENDPROC(el0_sync) #endif ct_user_exit +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR + tbz x22, #55, 1f + bl do_el0_irq_bp_hardening +1: +#endif irq_handler #ifdef CONFIG_TRACE_IRQFLAGS diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index 082f385b6592..9ff48d083c4c 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -535,6 +535,12 @@ asmlinkage void __exception do_mem_abort(unsigned long addr, unsigned int esr, arm64_notify_die("", regs, &info, esr); } +asmlinkage void __exception do_el0_irq_bp_hardening(void) +{ + /* PC has already been checked in entry.S */ + arm64_apply_bp_hardening(); +} + asmlinkage void __exception do_el0_ia_bp_hardening(unsigned long addr, unsigned int esr, struct pt_regs *regs) From patchwork Fri Jun 14 03:08:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166761 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1505897ilk; Thu, 13 Jun 2019 20:12:56 -0700 (PDT) X-Google-Smtp-Source: APXvYqzSrDyC0F3S0nrlOe10PRFXRsImIe9LlcoBpiSDXP8p/ym0RU+tsROiEEDFmXOBIoH30Fad X-Received: by 2002:a17:902:e312:: with SMTP id cg18mr24145769plb.212.1560481976825; Thu, 13 Jun 2019 20:12:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560481976; cv=none; d=google.com; s=arc-20160816; b=cERvCuL19Obl3SjA7hcYIi4WbJI/MLHt3Em4+VNwGad6qR3MfCIqBZE8qhAD5idWfQ lAF+Gr7lgRFZ35cKcIkvvgGe4nYsiK3XzCf/qN6f0ZLDkaKAiD/7NeVj+n2SUT1aaO4M Pzs6rsBMZStKx5hJLKqMCFFN4sDcgiVwC4X0u5DbutZdyhw8c/03EoXXutj9a0ibkAxM 9gJdnEUWF+LNoa2Nu9fhjnteJZ/Jg9oBP/LKphEP2FmqNnoBptm2FJCgipVzATlRwECz 1ETXH6mLhPG90y4WQWuidl7Yi6zWjJXFc3P3YVBs/saV3N37AslkGSIL9U8lXaEuRRgV m1mw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=D7dDso9mEizkFlSNIpcQXEVsYMAg+0dXCi9osCif4dQ=; b=038vvcTKlBSraUmI33Iivpz1mtZiPV5+isdKHfE5o9uDa10DvHUem8MevSGOFRSc+K qpXbI9FN+TVt9/i34mLDcJ/dC6QuG4TMEcpRN9XOYHSel3SADF1E9RIf54OLNj2oRCNl Ik+nfmGuIJ3+d+6OOmOwpliwJn7k+H6kBeyuG0lv9yVMmSyc8XA17ODsK9OfDMTwrXHa w7IqIyZqJ/viF4aNTTs5dVvNPCU/t+AChshTqtZ9vChbOdlP1+rOwplkMry9CycfOxQv Y/ObkBGuxYGbnEXEYfIEXjuyuoen37qAZCSuELYAIBmVpjcL00Wuo+otYqdsoe7UaMr9 luNQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fKikLlZu; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Hook up MIDR values for the Cortex-A72 and Cortex-A75 CPUs, since they will soon need MIDR matches for hardening the branch predictor. Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas [ v4.4: Add A73 values as well ] Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/cputype.h | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index f43e10cfeda2..2a1f44646048 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -77,14 +77,20 @@ #define ARM_CPU_PART_AEM_V8 0xD0F #define ARM_CPU_PART_FOUNDATION 0xD00 #define ARM_CPU_PART_CORTEX_A57 0xD07 +#define ARM_CPU_PART_CORTEX_A72 0xD08 #define ARM_CPU_PART_CORTEX_A53 0xD03 #define ARM_CPU_PART_CORTEX_A55 0xD05 +#define ARM_CPU_PART_CORTEX_A73 0xD09 +#define ARM_CPU_PART_CORTEX_A75 0xD0A #define APM_CPU_PART_POTENZA 0x000 #define CAVIUM_CPU_PART_THUNDERX 0x0A1 #define MIDR_CORTEX_A55 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55) +#define MIDR_CORTEX_A72 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) +#define MIDR_CORTEX_A73 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73) +#define MIDR_CORTEX_A75 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75) #ifndef __ASSEMBLY__ From patchwork Fri Jun 14 03:08:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166762 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1505927ilk; Thu, 13 Jun 2019 20:12:59 -0700 (PDT) X-Google-Smtp-Source: APXvYqzd9YJ9SCfjMY3QygsQFTdGyuAh5S+UrXFLdb0o2e/ujntRnyJ2AK7lvejgQPIqFVGpJU7N X-Received: by 2002:a17:90a:258b:: with SMTP id k11mr8360912pje.110.1560481979703; Thu, 13 Jun 2019 20:12:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560481979; cv=none; d=google.com; s=arc-20160816; b=vsHGVDYfy05ZNiJsbcnwJHPURpJBWd/uGYnzNOwNtp0u1Kga2fIIGAcZ1nkW4NhN8+ QoOYmpvTl4hh6yzoTIun6/NrMJwZ9EYXQDVEM+id4Dw5pkmYMKI4OaEjKeJuSKLaKCVs 2LGunA9Vl7BSfREtsd2MI6QysPiV8o3eZmGkmPWaU6e9xS5Awm+6TMY6dxsIqsxhwJB1 kO6kQkuM/KyBYaKLfCblg9d4YUtUbx537fupnJMG+llFzF+LZmm/8AEgKIKQp8tijBkB 0R4Q856xrY7K9oRsSilN4fKmhyZ3+E6YWR8kDan9ovsf62wVuLZ7PrIRbX0g3dZCYiRy Y//w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=y7D7di+hWLJT4S7T0euG3Tl4lwmsE/s4d/bbuco5Z4Y=; b=kQPJh8ftu5Fyz1G4pOylkVbNRllL3kC3mQXgKOJky2qLgU5ZbMRzyVs8axbqz3I9zf dzrwwWcMSMJ3AegdXPLIu7UPRqwYgnTkecAZpSACoBpa0H1n58BbsRRMyjMnFKGBZXfO TaSwS5uq0vFAKfO9xI3jObG+tFcQLqnjRB5Tp+hUFeqv+8TaxMm9CNklpVEiQIbGZwA8 G5giueZ4u1XjB5hWkCI21hJnsS287s98VCSQ+IhD2BmxKHXFhH/Z548P+bYVJ1TxWAMr iIGhsxlPqxr2YkoKkgw/3NSa5nVpgR3ciLOqJjMp9XzbduIb0/s9vR8R6nmHd1W/xhXz j1CA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tn9ttUjC; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e8si1073936plb.420.2019.06.13.20.12.59; Thu, 13 Jun 2019 20:12:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tn9ttUjC; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726637AbfFNDM7 (ORCPT + 14 others); Thu, 13 Jun 2019 23:12:59 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:40821 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725819AbfFNDM6 (ORCPT ); Thu, 13 Jun 2019 23:12:58 -0400 Received: by mail-pg1-f194.google.com with SMTP id d30so672413pgm.7 for ; Thu, 13 Jun 2019 20:12:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=y7D7di+hWLJT4S7T0euG3Tl4lwmsE/s4d/bbuco5Z4Y=; b=tn9ttUjCo/EPvIMutHSe21ptFw26CO8lMLTifKPIv38gL7+JQt+HP8TJghUQmKKFpp ZpLfHPaBsCa8fyB29TufhWsnLm1JxOkQqGXQjeEfNqHl3WjYf9Hi3tk2zMM/90BPaJCv PK4MM1eqbM5VvFktAiQ4S8uIcW3nVE8Sb0TcB9CJLZ+2C9LNRmiSvf4Gcy/TutPKIDJO 6oRlTUHT+FdhBjMC+pgPt/ZadHh8hc8RVYcm5dPXTdWWLOaiaxFcRx7YhawcoLH7lJEs Z1PptH6hyBln/IZcxEGZcPwBuo4jSo3oywpV2aRUTn9Gn40jGiSFEryl9gCr02qIa/Ut I4ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=y7D7di+hWLJT4S7T0euG3Tl4lwmsE/s4d/bbuco5Z4Y=; b=pXXI+p3z0HMGKorA/P4d/o6AAYR3+vmDGdNkgnYlY0gtFkLsHM7ZO4eNSmlXKbgjaF X/7xRpKQz6J/H6E6wLlHPz//cxBzSKJIAwxMxADK3gTjdN+6TZOsstTSy4ee4+ohu5J4 gHi0dfxreMukk219Jb8tGnyRx8E2nRPjaiEk4VlN0u4abYTDznfYrhwdUt71osPppckg i/1GtDkmBmNxk+pTL+ZUncg3PXkjfPHV/ncX/ndRt+krrfAHaMDol+KOLjK/JLI/wF8R +Vkc8ctQkoP2SUpmO38+oheYrhZQPRf9u+bvRpTqW6RlI3QismVOHK0ifRk/gLHOYO5C pD6w== X-Gm-Message-State: APjAAAV47caU2BCdxfV0iLcVQiD1m2XdFBwtZ4qMYrU0JtoCUJCeDwOc n4puwOVrCEwTugw1CJsq/TsxSQ== X-Received: by 2002:a63:140c:: with SMTP id u12mr33588467pgl.378.1560481978109; Thu, 13 Jun 2019 20:12:58 -0700 (PDT) Received: from localhost ([122.172.66.84]) by smtp.gmail.com with ESMTPSA id g5sm1064300pjt.14.2019.06.13.20.12.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jun 2019 20:12:57 -0700 (PDT) From: Viresh Kumar To: linux-arm-kernel@lists.infradead.org, Julien Thierry Cc: Viresh Kumar , stable@vger.kernel.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 24/45] arm64: cpu_errata: Allow an erratum to be match for all revisions of a core Date: Fri, 14 Jun 2019 08:38:07 +0530 Message-Id: <1b836bac823d576986a9e893e2d2509776ff3565.1560480942.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit 06f1494f837da8997d670a1ba87add7963b08922 upstream. Some minor erratum may not be fixed in further revisions of a core, leading to a situation where the workaround needs to be updated each time an updated core is released. Introduce a MIDR_ALL_VERSIONS match helper that will work for all versions of that MIDR, once and for all. Acked-by: Thomas Gleixner Acked-by: Mark Rutland Acked-by: Daniel Lezcano Reviewed-by: Suzuki K Poulose Signed-off-by: Marc Zyngier Signed-off-by: Viresh Kumar --- arch/arm64/kernel/cpu_errata.c | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 6c5e9e462629..c05135cd53fe 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -124,6 +124,13 @@ static void install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry, .midr_range_min = min, \ .midr_range_max = max +#define MIDR_ALL_VERSIONS(model) \ + .def_scope = SCOPE_LOCAL_CPU, \ + .matches = is_affected_midr_range, \ + .midr_model = model, \ + .midr_range_min = 0, \ + .midr_range_max = (MIDR_VARIANT_MASK | MIDR_REVISION_MASK) + const struct arm64_cpu_capabilities arm64_errata[] = { #if defined(CONFIG_ARM64_ERRATUM_826319) || \ defined(CONFIG_ARM64_ERRATUM_827319) || \ From patchwork Fri Jun 14 03:08:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166763 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1505968ilk; Thu, 13 Jun 2019 20:13:02 -0700 (PDT) X-Google-Smtp-Source: APXvYqzX9wj+MqL4yIxtc0LeKB/p/EYCpCLSioKxKam59UHqEh4E2MpWEUi5JDwdr0F0ZxlvaufZ X-Received: by 2002:a63:ec02:: with SMTP id j2mr34697328pgh.340.1560481982484; Thu, 13 Jun 2019 20:13:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560481982; cv=none; d=google.com; s=arc-20160816; b=jgoLbuJKRAQCHIP3PpeFs5QIsdfYLCk3SJZLoh69vGcDV6oCTWX22jhGHB86dUZ5r/ jsWsMHI98y5jj0kynj6oAuSh10q6EpeHWMWttR6ypnu+bfYosiI3eEmMFHeVPhOADsK3 AMN28PmWR5PskPNM8xk5neLT2kFdOv0zWfWffgP9qX5ushlftYubjNMUYeWbAJBdDXlW SWbHqCNWdklU6eds/gR7pQy/D1lCenW6h71R1mhyNS3To0EMetcS1ke7ykBDWrUbHGXR G+iFPlaz9REyyCQR+c7baIA0tzKsZkyz0QXpoFn3ObFRZWJpxXYBwPg3b1HdukpLtvfI e98w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=PiIAa6Q4cfsybCsVqpR97J+SEY4HmIlUIBQq6F4zyFg=; b=e2eTLq7txTA0O0mwBA4zMap/egiqhZ/nL1p6YjiOCNLvKZ9v7wr1UP0K1bMu8Tt/nY cFt5/14M6jeqdChFPvx+wUsZrqXmMsjqJ837tRDHPjcW2cnr9hvekPlTDaLH44MWDgi8 A1+dxbiJlD5zmas6bS/Gb1RhoHBIR31XU53KhmkKyyvjtJ9KBiB5rybk0dK+qc6tL7bs C96SAHjLnyGjnTgfBJabNf0Zdz4zf/5I2mIOLscILpp7ypwo0PJypdAK5pGY0eSBFUO3 eIN/4OZ3y6O74wNPjT94dJLrYLEZkqg1yi8PgW4R8nkjGqRXekpLT5aPVNkqjT4s6llS uBjA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=txKgJlWM; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Cortex-A57, A72, A73 and A75 are susceptible to branch predictor aliasing and can theoretically be attacked by malicious code. This patch implements a PSCI-based mitigation for these CPUs when available. The call into firmware will invalidate the branch predictor state, preventing any malicious entries from affecting other victim contexts. Co-developed-by: Marc Zyngier Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/kernel/bpi.S | 24 +++++++++++++++++++ arch/arm64/kernel/cpu_errata.c | 42 ++++++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/bpi.S b/arch/arm64/kernel/bpi.S index 06a931eb2673..dec95bd82e31 100644 --- a/arch/arm64/kernel/bpi.S +++ b/arch/arm64/kernel/bpi.S @@ -53,3 +53,27 @@ ENTRY(__bp_harden_hyp_vecs_start) vectors __kvm_hyp_vector .endr ENTRY(__bp_harden_hyp_vecs_end) +ENTRY(__psci_hyp_bp_inval_start) + sub sp, sp, #(8 * 18) + stp x16, x17, [sp, #(16 * 0)] + stp x14, x15, [sp, #(16 * 1)] + stp x12, x13, [sp, #(16 * 2)] + stp x10, x11, [sp, #(16 * 3)] + stp x8, x9, [sp, #(16 * 4)] + stp x6, x7, [sp, #(16 * 5)] + stp x4, x5, [sp, #(16 * 6)] + stp x2, x3, [sp, #(16 * 7)] + stp x0, x1, [sp, #(16 * 8)] + mov x0, #0x84000000 + smc #0 + ldp x16, x17, [sp, #(16 * 0)] + ldp x14, x15, [sp, #(16 * 1)] + ldp x12, x13, [sp, #(16 * 2)] + ldp x10, x11, [sp, #(16 * 3)] + ldp x8, x9, [sp, #(16 * 4)] + ldp x6, x7, [sp, #(16 * 5)] + ldp x4, x5, [sp, #(16 * 6)] + ldp x2, x3, [sp, #(16 * 7)] + ldp x0, x1, [sp, #(16 * 8)] + add sp, sp, #(8 * 18) +ENTRY(__psci_hyp_bp_inval_end) diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index c05135cd53fe..aa9cd47b5c6f 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -50,6 +50,8 @@ is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope) DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data); #ifdef CONFIG_KVM +extern char __psci_hyp_bp_inval_start[], __psci_hyp_bp_inval_end[]; + static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start, const char *hyp_vecs_end) { @@ -91,6 +93,9 @@ static void __install_bp_hardening_cb(bp_hardening_cb_t fn, spin_unlock(&bp_lock); } #else +#define __psci_hyp_bp_inval_start NULL +#define __psci_hyp_bp_inval_end NULL + static void __install_bp_hardening_cb(bp_hardening_cb_t fn, const char *hyp_vecs_start, const char *hyp_vecs_end) @@ -115,6 +120,21 @@ static void install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry, __install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end); } + +#include + +static int enable_psci_bp_hardening(void *data) +{ + const struct arm64_cpu_capabilities *entry = data; + + if (psci_ops.get_version) + install_bp_hardening_cb(entry, + (bp_hardening_cb_t)psci_ops.get_version, + __psci_hyp_bp_inval_start, + __psci_hyp_bp_inval_end); + + return 0; +} #endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */ #define MIDR_RANGE(model, min, max) \ @@ -192,6 +212,28 @@ const struct arm64_cpu_capabilities arm64_errata[] = { MIDR_RANGE(MIDR_THUNDERX, 0x00, (1 << MIDR_VARIANT_SHIFT) | 1), }, +#endif +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), + .enable = enable_psci_bp_hardening, + }, + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), + .enable = enable_psci_bp_hardening, + }, + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), + .enable = enable_psci_bp_hardening, + }, + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), + .enable = enable_psci_bp_hardening, + }, #endif { } From patchwork Fri Jun 14 03:08:09 2019 Content-Type: text/plain; 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Add Broadcom Vulcan implementor ID and part ID in cputype.h. This is to document the values. Signed-off-by: Jayachandran C Acked-by: Will Deacon Acked-by: Catalin Marinas Signed-off-by: Florian Fainelli Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/cputype.h | 3 +++ 1 file changed, 3 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 2a1f44646048..c6976dd6c32a 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -73,6 +73,7 @@ #define ARM_CPU_IMP_ARM 0x41 #define ARM_CPU_IMP_APM 0x50 #define ARM_CPU_IMP_CAVIUM 0x43 +#define ARM_CPU_IMP_BRCM 0x42 #define ARM_CPU_PART_AEM_V8 0xD0F #define ARM_CPU_PART_FOUNDATION 0xD00 @@ -87,6 +88,8 @@ #define CAVIUM_CPU_PART_THUNDERX 0x0A1 +#define BRCM_CPU_PART_VULCAN 0x516 + #define MIDR_CORTEX_A55 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55) #define MIDR_CORTEX_A72 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) #define MIDR_CORTEX_A73 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73) From patchwork Fri Jun 14 03:08:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166765 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1506029ilk; Thu, 13 Jun 2019 20:13:07 -0700 (PDT) X-Google-Smtp-Source: APXvYqxwygqwMgZU/KETtJ/RJRZ9ytUK+HIQsJJR2CLlsPnn7uhU4DUaQ7jpGLcwP9IisuWhVSnb X-Received: by 2002:a62:6083:: with SMTP id u125mr19293160pfb.208.1560481987417; Thu, 13 Jun 2019 20:13:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560481987; cv=none; d=google.com; s=arc-20160816; b=RZLUhvX6mjQjIFp0/9AUB/Aj9x1mSJU/F5tgr/GiNdMFd+dmyNEGCRfwQrgP67s9s1 bb47Niydqltq8b5UuspinIvIAjA+PrZd4QTk1Wlm5ni1rXaGmvE8ImNIim8fSSaaLoS6 kRiWDl626jJFRgheZ6aCvcyJduTorjzbEHDSshQo2pji02uaBSqSUIYmDmNvk/I5GXxl oLCEmQRNNxlyQ7IiUcRSVWCEDdkzle9eWu8ETwuzKlyogstvgCoRGvyy7cZpR0+A7D5z w3QqWI6Et2HnCZneUwvJKdCaZCn43DVjJ+PY6I8bqBnCyY5WitWCA6XeqQUQRjnRqt0t Hs4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=sBbWRB3LgLlv2c3U4FxHDhn97v+yXFInuDLMYZ1aFeE=; b=yZnp2cLjh1IZaI47nFLYdP23TwY8xQFiiARBe11drD7UfIb2ZsSZILUv/Mc04cmnZW jbAgdc4DLTlkbkq0Ab2piTZ1qBjYW3/F1m+aIdMpl7kFB7xEziM6SQXYz2huF/Gb/Nrq yG9qV0Bo51vNs6OelbyCth8cDYTlgtcQZqII3ALVfKiIHr2b3nngPhFpo3EfCNBY87Yl 7xlsSRHuHPyHizFuDkaPRcbRfozAN7xE+OsIyEmB2+39gibuTF61pwNKdg8weev3eMqN kftYbroUgl8lGivBdgmtXp9vUmuxPWm5Vs4FA4Pn49UrU5Z1t0nqdrnkemLJRTRyWjui 0aEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yCjy6+SN; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e8si1073936plb.420.2019.06.13.20.13.07; Thu, 13 Jun 2019 20:13:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yCjy6+SN; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726653AbfFNDNG (ORCPT + 14 others); Thu, 13 Jun 2019 23:13:06 -0400 Received: from mail-pl1-f196.google.com ([209.85.214.196]:42219 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725819AbfFNDNG (ORCPT ); Thu, 13 Jun 2019 23:13:06 -0400 Received: by mail-pl1-f196.google.com with SMTP id go2so371380plb.9 for ; Thu, 13 Jun 2019 20:13:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sBbWRB3LgLlv2c3U4FxHDhn97v+yXFInuDLMYZ1aFeE=; b=yCjy6+SN414F35JKkNjFkyRAIf7YsFvNN+Kz/Mi8AgDN22LOTkEocDlKSGJU+7VWoT rd7H6Kwo6rDofcCHG0iiog2QNhUUG793KzKoX2APLWphCziQ9Z0/xaLtnBnUYuMK7Z3A YetcuPTD3IMuzeKAl2gn5/DadaRWJl5utXEgxSmdTugAcYNH3N9NfiJ/JOqN1fumuopz cSs5wtE9I3gwI3CwTLfm8welw4DW0VNoCNIc3JfQ6880amhcfnmyEuyQYBPf651aQbcO 554KdaFth8cW5dCOUl05t7MeAl6hsjFFLJvqfZsKX4U3BqTDiEFM/mrfOuo9c+OoANQn NYsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sBbWRB3LgLlv2c3U4FxHDhn97v+yXFInuDLMYZ1aFeE=; b=VyjW9p8s7E0y7IB2b2bawUSJu3tGIGA23PrnL1p2xVejU6B3xyrCGZghZngx3/vRZI Y6B7RoEvKAIBYbrEJND27KyvTrMa5VwSIha4ewhFRG9dAbbKGTaheAQL9iyvp+XhTbqa h8Z1C3HIMvxBIY4Q2me1zS9tB0hjQIJxWqlhutjNMmh8C3vZ2ehlUs2njvbW6iMW9cGT p6YjYwePxE6t2EL3My+4gXPUVxEFno1qpzPYl/gv/2MTj1aT2lbt6mXmFnWQh+Tk1YLD 6+xNMLLrNcViwvQcWLfvO7utLr54zy6n2XvZo1REpL+sEBHgTOh6Q++7z5rD3KvJyFjP yjUw== X-Gm-Message-State: APjAAAUYSxTqw2OPkBJkhyDUpC44wxKhwEqa5X4unXDqikPWCqH4o0wD Nc7l7qeMPjKjRZf2JhAhHbtOZQ== X-Received: by 2002:a17:902:121:: with SMTP id 30mr87000779plb.314.1560481985859; Thu, 13 Jun 2019 20:13:05 -0700 (PDT) Received: from localhost ([122.172.66.84]) by smtp.gmail.com with ESMTPSA id o26sm1106132pgv.47.2019.06.13.20.13.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jun 2019 20:13:05 -0700 (PDT) From: Viresh Kumar To: linux-arm-kernel@lists.infradead.org, Julien Thierry Cc: Viresh Kumar , stable@vger.kernel.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 27/45] arm64: cputype: Add MIDR values for Cavium ThunderX2 CPUs Date: Fri, 14 Jun 2019 08:38:10 +0530 Message-Id: <92556442f96e9f150663637c363eb892731327b1.1560480942.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Jayachandran C commit 0d90718871fe80f019b7295ec9d2b23121e396fb upstream. Add the older Broadcom ID as well as the new Cavium ID for ThunderX2 CPUs. Signed-off-by: Jayachandran C Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/cputype.h | 3 +++ 1 file changed, 3 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index c6976dd6c32a..9cc7d485c812 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -87,6 +87,7 @@ #define APM_CPU_PART_POTENZA 0x000 #define CAVIUM_CPU_PART_THUNDERX 0x0A1 +#define CAVIUM_CPU_PART_THUNDERX2 0x0AF #define BRCM_CPU_PART_VULCAN 0x516 @@ -94,6 +95,8 @@ #define MIDR_CORTEX_A72 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) #define MIDR_CORTEX_A73 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73) #define MIDR_CORTEX_A75 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75) +#define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_PART(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2) +#define MIDR_BRCM_VULCAN MIDR_CPU_PART(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN) #ifndef __ASSEMBLY__ From patchwork Fri Jun 14 03:08:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166766 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1506054ilk; Thu, 13 Jun 2019 20:13:09 -0700 (PDT) X-Google-Smtp-Source: APXvYqytJIp8WCytQwvDOmztPtUkmResA0xDT595PakF1cbDg63drEqcPSmvwDiAd0ajGLT+es8n X-Received: by 2002:a65:5302:: with SMTP id m2mr33130646pgq.266.1560481989796; Thu, 13 Jun 2019 20:13:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560481989; cv=none; d=google.com; s=arc-20160816; b=zulPCbh4u/ok53yONHt1/ZAEI7+rveEDMi3Q/bGLyCZL53gI5B2zTgT3GhcAHvuxlB xYRRtDoxyzr3hP0zCiLFJbYLsuYP9D2SayVeZS4CE4nkL6aIYAzojpliBqkORP+VGc7L 3vPHU8LqsruS7iJ97aljHkpeYkuYo5yc/T6hwIqRSlTd9EeF97KhKLYR97Q+sXycb2ho SkZc3EKUAChjzF8GFFNsKISo14yfPKfnamv0bI+HEyICxxjjODW7qFCnq0O5e//gwc8w yzg37Tzv0+d2DcYyElo9D4rYdcwLnoDYrpAsf51SpFxTBVsFvc5zx+pj8VW+i27Acing hDww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=fVKkVoGiJxBpY/NXd6uIeAwk4xxuAE9w4l4OvZBARVM=; b=ftqzVm28fnqoRFHKJr3zQaL7vGRUQW9FZ45J+xqxXff9ssSduakEn6d9mIvmGPDb01 OHiBQDuGCZwB5CcY8zGtICS6gK4+f2g/vSdpvoIbHaE67ESAGIfYIoZsq2f3Gj9fff1F woqErkLCYjbISUlAltqH4hZQKTxZfCK5R6IkIB17J27c7SxwK5CfzxZKjlOJXui9TgT0 VWhmdzow6uE5EIzOmQcZ2iCNr3qHYlz98/lWCex5P5VzgMmi6hJxqR2tMWwvEv1MWair 7iop2aYeVRASATtYqy2lPl9SuF94IxTviBFOFpLyoObNZtgkXwLdM0gcE4hgflRuISqy tkNw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tUqDZcoU; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e8si1073936plb.420.2019.06.13.20.13.09; Thu, 13 Jun 2019 20:13:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tUqDZcoU; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726655AbfFNDNJ (ORCPT + 14 others); Thu, 13 Jun 2019 23:13:09 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:36975 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725819AbfFNDNJ (ORCPT ); Thu, 13 Jun 2019 23:13:09 -0400 Received: by mail-pg1-f195.google.com with SMTP id 20so680767pgr.4 for ; Thu, 13 Jun 2019 20:13:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fVKkVoGiJxBpY/NXd6uIeAwk4xxuAE9w4l4OvZBARVM=; b=tUqDZcoUraxwG46Xeay+MFqyETdSKrFiQ7Gh0/OWx/XXFYMi6UQB+xOalfhkzID3sX 5kLYRx6UOnuG3TSV43Q3dbf8C/niEWCUP4pE83i6ppenYnk65grSDn3DLBzvyMZvwxMk JNG2CjE1GnHwJco6jXQ9E3c5OjRxwJYoaKBcFt4wXZkMN8tvY2UJzZwLfrvYIUmEYcML xHYJe5Ztq4pKtE3UW5YQbxpePDrOedXnzsVPaOhH1ax5SWUPQWH7Q180LHhT9TJ9rJ73 c+Zjq5teYrb3dG7emzzZu0HjNPB+M+j8SFWZvoy3DfyAIPoVpcuyKxppGT/tYyOo/iC1 JhlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fVKkVoGiJxBpY/NXd6uIeAwk4xxuAE9w4l4OvZBARVM=; b=i5/W6ja05oX6xGcrzWHVsHlQ2ChIHkLobhULknsSoSUPXM1PEBAl+mQrbkifMTX0SU T+pKiBbaW35dlY0UfLdijFKpXitLud2l2HQrdfOPdo8p+Sdbk0yNHiQ57e3HZ9blloMa XABwheu1JOlpMrxl8sAaGZX2VTuzuDCqwOJLWwSNMdrUCjybt3C4ZRErN2n8Yn8fA6SJ L9i6L899NIM/Q0969CfLfMGaf8k6T7IllQQFCeUYCEX1K3HgwrKEew0LCNsKckt770Z7 OX9wd/S00LGNhz+FFqKBaeAjr/Kg70rXlWqZhrUkAMXb98/PT8vAPdmRpS5okK+R49hl 0YyA== X-Gm-Message-State: APjAAAXv91/d0YvXe7ZgVvmLbm7ZEwv3ieXyIINwWIb7ofX++XEsFhEp c8X3oWM+qUk8k1yPxYZUYDjYYw== X-Received: by 2002:a65:4c4c:: with SMTP id l12mr31225440pgr.404.1560481988190; Thu, 13 Jun 2019 20:13:08 -0700 (PDT) Received: from localhost ([122.172.66.84]) by smtp.gmail.com with ESMTPSA id r15sm1002341pfh.121.2019.06.13.20.13.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jun 2019 20:13:07 -0700 (PDT) From: Viresh Kumar To: linux-arm-kernel@lists.infradead.org, Julien Thierry Cc: Viresh Kumar , stable@vger.kernel.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 28/45] arm64: Branch predictor hardening for Cavium ThunderX2 Date: Fri, 14 Jun 2019 08:38:11 +0530 Message-Id: <3ec694103e8b96a19e776e3649ed286926978486.1560480942.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Jayachandran C commit f3d795d9b360523beca6d13ba64c2c532f601149 upstream. Use PSCI based mitigation for speculative execution attacks targeting the branch predictor. We use the same mechanism as the one used for Cortex-A CPUs, we expect the PSCI version call to have a side effect of clearing the BTBs. Acked-by: Will Deacon Signed-off-by: Jayachandran C Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/kernel/cpu_errata.c | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index aa9cd47b5c6f..da861bf24780 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -234,6 +234,16 @@ const struct arm64_cpu_capabilities arm64_errata[] = { MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), .enable = enable_psci_bp_hardening, }, + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), + .enable = enable_psci_bp_hardening, + }, + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), + .enable = enable_psci_bp_hardening, + }, #endif { } From patchwork Fri Jun 14 03:08:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166767 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1506093ilk; Thu, 13 Jun 2019 20:13:12 -0700 (PDT) X-Google-Smtp-Source: APXvYqyTVTmpjym5nlONCp7cXNMiL5+SrHRyEPDwwvVVoUeevI/XM2N2zDtvpQAVR269MGjU7Vne X-Received: by 2002:a17:902:54d:: with SMTP id 71mr88734823plf.140.1560481992793; Thu, 13 Jun 2019 20:13:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560481992; cv=none; d=google.com; s=arc-20160816; b=0O9F4a2+gOACBN8ykuD+8ilbPLvDID0kkPS2JP+Q6+34qHQIy7jT/70KTqOQSydfaH pPGhUV0GVGPAhIx/srXhvyP1wDDH0ewzT3yEzIffmniILwKKP6JZabtazbmued5FDpDW 3ieJ3Y9MWo1R2FqdBZN3G4KMS6xmxSlqKA3V8gmbbm2RpJCQk3DYRSUsYrps+74/CVgy PWjhQbsOwgbzv5eo884WPm9BOx+q/T4qnVVP4c/h6B0j7fEM5K9wZQglTpuVJWVFj1h4 PQ0CXfYop7FDfsaSvaPqi8mlnP/DsPg9JjbMgibt5jUwIJiZwztRpnap7zAr64fRBPvr jQGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=hP63VKEYPHg3zKNj3xMaZwjK56Qq/K++eO//dDzRjvk=; b=K06+P/rxEIA5ROauRkdNhcoyuaVmUyY0qbeeHVr9hIG/UQdeNzmKoaGD6k5ey56T52 slLTMSvZrnaivymy/rwC/tQrkZcltovlL6Mn3MF1GqqrRGAIlh/Jlk9rY8iwVjEiIeGh sPO8lExJ6+Ly3c/Rc+u4+uAIXhbssbnsp0ZN23MNmB8w0pZjc/8zZ9J+AUfmlSknZjzJ mF5KbEHFewN0YOv/h+DuCB0pQYwPOHhQ6cxdkBtVobJ7BvhFNDoagNN2l8jfkoaNQ3wf iQXZVvo9WCKNpMquy+heBPIWrKFHycbp13d+wB2Z2SDI/CoyfpqjK5zcdjLsh4U2l3eA n51g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="XKzO/FoV"; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e8si1073936plb.420.2019.06.13.20.13.12; Thu, 13 Jun 2019 20:13:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="XKzO/FoV"; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726442AbfFNDNM (ORCPT + 14 others); Thu, 13 Jun 2019 23:13:12 -0400 Received: from mail-pf1-f195.google.com ([209.85.210.195]:39729 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726028AbfFNDNM (ORCPT ); Thu, 13 Jun 2019 23:13:12 -0400 Received: by mail-pf1-f195.google.com with SMTP id j2so494033pfe.6 for ; Thu, 13 Jun 2019 20:13:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hP63VKEYPHg3zKNj3xMaZwjK56Qq/K++eO//dDzRjvk=; b=XKzO/FoVC0F/C4cPzxh2/w9xDeu3OZ3640Q66sWIDaYrI4StlFuJ3ZBr1yFuUuBOeD lAPWHE6wpJixcIXHSeVdX7HYeAwZ1jk4l8IId6e2YoZyHBTw1Cbhs+1ZcCD7HmWfBg9Z Mg/z8WeXnPtbWv3DcJW9vguLf6NclZdtb2PHrhx7vP4hvspjwrd/UcpBOqakQ23I8YJj wKS5TakaT13Waa8g7uoG37UWjq8U6cOWr0o3yUbZXY9T7L8MuVXzIqFMxExia6clUbSu HApz5WTgOGxo7STDNUHSQuiqTJd4DXkW5nwubO7ta7JT7OFDH/B+bGerim8MwpmMSWzp 9rRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hP63VKEYPHg3zKNj3xMaZwjK56Qq/K++eO//dDzRjvk=; b=k03OtpJM2jhqOvdgBQreux+IJvcnFYephu2AE5kjIV7Ic337jTt+AK9qGXvz+fzviU KRAnTg/ejYmjHn4R89r6vmOERl3IpMp8ZrytC+9UPCHcg5pH6xTq4u907ePlnRZUzdop dvO+pxbtyNYIuZu6kKBMpQzAJjvt8Cs6Yvg/FJojtUpn9VHKV2hSKkLuo3KnnEFlID31 JvTHSPtudMYhMCsejNrIUKQmGjNySlBKA6Z7TjZmkPpC34t1NDsdqouXlJCMRfgF8vWm 1tbI1QwcmeUn9XIymoNpnlQhsJkl/uOxXYE665Uw0T5FpWdmmqZDVp4cd5Je62uzW503 T+aA== X-Gm-Message-State: APjAAAWHIdvy63Bmp6PScQeMvxqziXOSmO8x4A2NvNnTJZUXvron4jSf G0euZLGzVEfPpZvRC1XiN13BVw== X-Received: by 2002:a63:545a:: with SMTP id e26mr33192910pgm.162.1560481991000; Thu, 13 Jun 2019 20:13:11 -0700 (PDT) Received: from localhost ([122.172.66.84]) by smtp.gmail.com with ESMTPSA id b16sm1067054pfd.12.2019.06.13.20.13.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jun 2019 20:13:10 -0700 (PDT) From: Viresh Kumar To: linux-arm-kernel@lists.infradead.org, Julien Thierry Cc: Viresh Kumar , stable@vger.kernel.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 29/45] arm64: KVM: Increment PC after handling an SMC trap Date: Fri, 14 Jun 2019 08:38:12 +0530 Message-Id: <2798950c13d82c9e5b4c9a94afe8eeeef052283a.1560480942.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit f5115e8869e1dfafac0e414b4f1664f3a84a4683 upstream. When handling an SMC trap, the "preferred return address" is set to that of the SMC, and not the next PC (which is a departure from the behaviour of an SMC that isn't trapped). Increment PC in the handler, as the guest is otherwise forever stuck... Cc: stable@vger.kernel.org Fixes: acfb3b883f6d ("arm64: KVM: Fix SMCCC handling of unimplemented SMC/HVC calls") Reviewed-by: Christoffer Dall Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/kvm/handle_exit.c | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c index 5295aef7c8f0..c43e0e100c11 100644 --- a/arch/arm64/kvm/handle_exit.c +++ b/arch/arm64/kvm/handle_exit.c @@ -51,7 +51,16 @@ static int handle_hvc(struct kvm_vcpu *vcpu, struct kvm_run *run) static int handle_smc(struct kvm_vcpu *vcpu, struct kvm_run *run) { + /* + * "If an SMC instruction executed at Non-secure EL1 is + * trapped to EL2 because HCR_EL2.TSC is 1, the exception is a + * Trap exception, not a Secure Monitor Call exception [...]" + * + * We need to advance the PC after the trap, as it would + * otherwise return to the same address... + */ vcpu_set_reg(vcpu, 0, ~0UL); + kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu)); return 1; } From patchwork Fri Jun 14 03:08:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166768 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1506132ilk; Thu, 13 Jun 2019 20:13:15 -0700 (PDT) X-Google-Smtp-Source: APXvYqw2FQn8ARvIEy2KHRyOAKVwIzs3c062vpo+/4UxKBptFP5Klyop5D4vgNavPRGjZ9nvzQV6 X-Received: by 2002:a17:902:e312:: with SMTP id cg18mr24146683plb.212.1560481995831; Thu, 13 Jun 2019 20:13:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560481995; cv=none; d=google.com; s=arc-20160816; b=wPMNuyNKJHE/vfL/ZrZJPh2wLaTkMDzm3INjFH+yebRV3zElDd1PS6m6ajUmqsf2o8 Y/B4SDP26qUz6cR24a/Hyh5Rfnn084u8FzdZ+uTYwdYfTw9sfmdf7fFgVNvYQxmjSw1P RrKIWSv2mz50VILpltnnPoYgZiDH98NmbkOBnpfmgZzhCE6GEcqeYWiO4bSsZq2gSNOB 3Fv5CKsm8VcJbFse3KlbgrTYDCNN/G09w+7NV9INRwyS4U8kSrt1BU0cfF8N4S0Jd9ck fUNM7Y4eLqZQlWKODBMWMuHyJ5sj2HiQ9XFD7Gc+nli5OxIGiq+qkXyadmWcR1LG5SZj /5wg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=RBs1rUgoU6ONwGkddceY1nFBB7cQx3Xs99bBwFEL95E=; b=BkVLMfUj4FLolS3igp+SdYf3t4Iqg7DA6ETtzpTyKBafGn8OKyQQFrdk4XKSNloo6h nr7O1pP8as2pa3pRncTDglaBeZzTqnFN6YlYA+NnPP/Jdvgx61CV/YyR+r5u+N8IqVlb ylj1lHNktggED9PT8aGidqnSTy2z1ooF4YW0H6oVzOZyZMQyDe4vWCjkkuFiIw5x+opp L7YY8yGA7ToGFub7VFzXB3I+S3GfXaOfM55pvlYNpG4XzgzrTk3/F/7ZzyKirG6WG2kp EEfrHzb1oOLuQMb0eqc+ISJ9BGkER/NKT1cbVhTMZ8CGJoMD8HlSXov38YFMJhtX0qrk R9Bg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Y+C3vCm4; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e8si1073936plb.420.2019.06.13.20.13.15; Thu, 13 Jun 2019 20:13:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Y+C3vCm4; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726028AbfFNDNP (ORCPT + 14 others); Thu, 13 Jun 2019 23:13:15 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:40845 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725819AbfFNDNO (ORCPT ); Thu, 13 Jun 2019 23:13:14 -0400 Received: by mail-pg1-f194.google.com with SMTP id d30so672774pgm.7 for ; Thu, 13 Jun 2019 20:13:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RBs1rUgoU6ONwGkddceY1nFBB7cQx3Xs99bBwFEL95E=; b=Y+C3vCm4FkAIC9ch5xg5mi8S62oaHgpJnjqQq+9lw8g9Xph7XUJlAmNDCc33ug39w6 e/FxICYL1v+gXJSPGpk4abMVGyBOrKwE/0zjP4smzzCzNga3q90iJtaLrxAMC1tz/wO4 fYKov71NsbdHsYB+kGPyzeMqqqn3qVMEdnwq5VGs/UawuNFTPwh0GTBWmOr8exKBwGM0 HCnGqmdUj/OrLoPiL3ABfRNC5FWKxQfoupQcwJe7fzwger9I++tW2np6m5KhLbY6oHqR D5K3XavaqFUz33yhK5eXM/BXTUiaxAip93SGy2tDEVN/C0lP2cPT0x1nl5fZuDHreUDV JC3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RBs1rUgoU6ONwGkddceY1nFBB7cQx3Xs99bBwFEL95E=; b=jGgIc8p+OiQ2zi+1ka4nvzB+KAuhao1VYxzsC8BWP7NajSWA7bG5pFPdTOzDujHxRR 92zkpdYAn7Drs3Dvps7HyB4zHjmx0SeWm4WYhf3dTyrjr+ybCooueooIIEZ6EpM0sJA3 cd89EwqDKKTX/YJ1HujeDUPk9hplrl8YK+gcga6eKkglyCaUU1+fQrKJxRcLM6AaEzBH qA+cPBcN7tMO0zXgp7C4/Ctdl8QFoY8l/0d3RaM571WDdTpGpg/OpOcUHQfH04KZpbxl /LdsiTOgKhR3RFCdGziJcX15VRGyuCQ0i9UlnjPNlyvReYJdL1Vv8fo1A1Wnf9U0QQEh fwNQ== X-Gm-Message-State: APjAAAVaBWlLqJxq73Xo4ACAVv7Rw5GvHmtXs/wnUlcNjpbup+sG7lV2 +QTIa8XmxT6l9ohZU5T/aqVtXg== X-Received: by 2002:a63:1617:: with SMTP id w23mr25538091pgl.183.1560481993805; Thu, 13 Jun 2019 20:13:13 -0700 (PDT) Received: from localhost ([122.172.66.84]) by smtp.gmail.com with ESMTPSA id f17sm1131479pgv.16.2019.06.13.20.13.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jun 2019 20:13:13 -0700 (PDT) From: Viresh Kumar To: linux-arm-kernel@lists.infradead.org, Julien Thierry Cc: Viresh Kumar , stable@vger.kernel.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 30/45] arm/arm64: KVM: Consolidate the PSCI include files Date: Fri, 14 Jun 2019 08:38:13 +0530 Message-Id: <165e8628ae4e24397d1dcee69d10487d53a7df98.1560480942.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Mark Rutland commit 1a2fb94e6a771ff94f4afa22497a4695187b820c upstream. As we're about to update the PSCI support, and because I'm lazy, let's move the PSCI include file to include/kvm so that both ARM architectures can find it. Acked-by: Christoffer Dall Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas [ v4.4: account for files moved to virt/ upstream ] Signed-off-by: Viresh Kumar --- arch/arm/include/asm/kvm_psci.h | 27 ------------------- arch/arm/kvm/arm.c | 2 +- arch/arm/kvm/handle_exit.c | 2 +- arch/arm/kvm/psci.c | 3 ++- arch/arm64/kvm/handle_exit.c | 5 +++- .../asm/kvm_psci.h => include/kvm/arm_psci.h | 6 ++--- 6 files changed, 11 insertions(+), 34 deletions(-) delete mode 100644 arch/arm/include/asm/kvm_psci.h rename arch/arm64/include/asm/kvm_psci.h => include/kvm/arm_psci.h (89%) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/include/asm/kvm_psci.h b/arch/arm/include/asm/kvm_psci.h deleted file mode 100644 index 6bda945d31fa..000000000000 --- a/arch/arm/include/asm/kvm_psci.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (C) 2012 - ARM Ltd - * Author: Marc Zyngier - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef __ARM_KVM_PSCI_H__ -#define __ARM_KVM_PSCI_H__ - -#define KVM_ARM_PSCI_0_1 1 -#define KVM_ARM_PSCI_0_2 2 - -int kvm_psci_version(struct kvm_vcpu *vcpu); -int kvm_psci_call(struct kvm_vcpu *vcpu); - -#endif /* __ARM_KVM_PSCI_H__ */ diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c index d7bef2144760..96fa300cf581 100644 --- a/arch/arm/kvm/arm.c +++ b/arch/arm/kvm/arm.c @@ -28,6 +28,7 @@ #include #include #include +#include #define CREATE_TRACE_POINTS #include "trace.h" @@ -43,7 +44,6 @@ #include #include #include -#include #ifdef REQUIRES_VIRT __asm__(".arch_extension virt"); diff --git a/arch/arm/kvm/handle_exit.c b/arch/arm/kvm/handle_exit.c index 05b2f8294968..ed879e3238d3 100644 --- a/arch/arm/kvm/handle_exit.c +++ b/arch/arm/kvm/handle_exit.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include "trace.h" diff --git a/arch/arm/kvm/psci.c b/arch/arm/kvm/psci.c index 443db0c43d7c..b4acfec9b459 100644 --- a/arch/arm/kvm/psci.c +++ b/arch/arm/kvm/psci.c @@ -21,9 +21,10 @@ #include #include -#include #include +#include + #include /* diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c index c43e0e100c11..5b7fb5ab9136 100644 --- a/arch/arm64/kvm/handle_exit.c +++ b/arch/arm64/kvm/handle_exit.c @@ -22,11 +22,14 @@ #include #include +#include + #include #include #include #include -#include +#include +#include #define CREATE_TRACE_POINTS #include "trace.h" diff --git a/arch/arm64/include/asm/kvm_psci.h b/include/kvm/arm_psci.h similarity index 89% rename from arch/arm64/include/asm/kvm_psci.h rename to include/kvm/arm_psci.h index bc39e557c56c..2042bb909474 100644 --- a/arch/arm64/include/asm/kvm_psci.h +++ b/include/kvm/arm_psci.h @@ -15,8 +15,8 @@ * along with this program. If not, see . */ -#ifndef __ARM64_KVM_PSCI_H__ -#define __ARM64_KVM_PSCI_H__ +#ifndef __KVM_ARM_PSCI_H__ +#define __KVM_ARM_PSCI_H__ #define KVM_ARM_PSCI_0_1 1 #define KVM_ARM_PSCI_0_2 2 @@ -24,4 +24,4 @@ int kvm_psci_version(struct kvm_vcpu *vcpu); int kvm_psci_call(struct kvm_vcpu *vcpu); -#endif /* __ARM64_KVM_PSCI_H__ */ +#endif /* __KVM_ARM_PSCI_H__ */ From patchwork Fri Jun 14 03:08:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166769 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1506168ilk; Thu, 13 Jun 2019 20:13:17 -0700 (PDT) X-Google-Smtp-Source: APXvYqxpIotGHyJbbctts0pYaU2lkZulNkXmKYkucPp6HGCoXN9WeXxRZNX5i522A2epRNydCXpV X-Received: by 2002:a17:902:b102:: with SMTP id q2mr4234549plr.149.1560481997701; Thu, 13 Jun 2019 20:13:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560481997; cv=none; d=google.com; s=arc-20160816; b=OLEbVsEkqR0jyfK6SxW8WO4YWQyI9SN6CpMcfhlrTcYSkAZfsKVP7/4Y7Ht9wew5Tw WYedUvQ9HqmzhoGyXPsFF7eRbiibh3L8m8yifdM6pfcD0cBbqf4QIm3XjSEbIXRXb0p5 NSJw6FsT9EvKgilQKL2sJ7UNO5jSlggvl74rHhLauoMVVPuX/32A9e6M+01tHZk6JPyY QI1s303z2wdcZgKuWBzHCTkz/cvxjbDIl15CGGzrxn3nQOksd+mQeO0JohxrZH8QznXe vw94cP7zwTmE90IVxSG+VHLX40Q2m7dT9KM48o8ud6pwL5WkoY+x0A5lx9KpXHqLoynD uVQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=XnBFuCb0fKyphIKUBsr79RViQc3+zyureYjz7BI8VNo=; b=b5Jb2ye/wJXW+Y7l6SLRu5hy/5Kzz049JU4/AkyBCiPQ6z8JRK6qYkpiq1iixOXz35 1H3fjyuvQq36HbyGts3oXIGDUiRCQU6U42gl/puSepQ+WDWTRlfWjY1+TMT7FgdGA6IY ZDv0L0j0pidEOyQhyKBhVL0mtU5k0RE2wxzpvCeIX+5rz0LGVBKsZK9fkh4osPoCCuXq 38/Rjb6UifJKVQGS3bnZ2SBx5BzQzcptdvXrHt4hs134VAdQbh3Q2pwlnqoi0NzmRxoP 0d3VuZOCNelSNeYJ3cNSm3Udkea7bqr/HCFgN7Q1eNPROFp6UnwXUxVsUvU4Gfl79fXy XCcQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=esT6yODH; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e8si1073936plb.420.2019.06.13.20.13.17; Thu, 13 Jun 2019 20:13:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=esT6yODH; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726667AbfFNDNR (ORCPT + 14 others); Thu, 13 Jun 2019 23:13:17 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:41226 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725819AbfFNDNQ (ORCPT ); Thu, 13 Jun 2019 23:13:16 -0400 Received: by mail-pg1-f194.google.com with SMTP id 83so668192pgg.8 for ; Thu, 13 Jun 2019 20:13:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XnBFuCb0fKyphIKUBsr79RViQc3+zyureYjz7BI8VNo=; b=esT6yODHCOPamMcOEIHuIhACaeouPQ3yo/v5MBa40924SSSeJaG2ULGBQ/CLUoQbmw veg3oijobNEl2NP4ivxYvXTjcHUDYfsHGr/2+9D2GL74RWGecQ6ClJubOs+bsmrHIJoB VqxVAl3KoZgWOmmxvZyWzD+PZi6TQUV1y8FTil0oin6xyzux+Z8+C+N9YpzbMErJuWRd n6tm6Chwu6+Qgd1gO+m/36/+kfRl2mv6HvaLmDwJXCJGHEbqig9AEAm65vsz21clORkx yxQIP0PwTZ6U9Ik1AwiEpGGtOkI51snHExxKzeI47qdMhjoZNioe1PNPZPdOU+pf8B59 cO2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XnBFuCb0fKyphIKUBsr79RViQc3+zyureYjz7BI8VNo=; b=qA4u6ensNoQ/NSAISR9qyp0F07fyppozsbCsHKblTlNE6uJjKssU1jyfaaS7nEktL5 dmTfRYfk6P6q3cbieMVYKe/TBS+UEQb877vrwVOtvQ3jfyl5TY0aV90YM2fJstL+b2wz l5Iku8xwRh9O1Sk4zgROQJGXirC8O9Qw9ujul2TJ8vXpH31omAhO2+PtwOPHMZpdvs3G 9wedodVwMTr5+lyR51h3oTy1O2nbhskbIJulRhXGWDwgAwTagBTZekeV5YgqPS8CskV7 QycoJIQVh/kqv8IlBhDETfdN8gR7NVE9PEh89Hr4qrJanGZDH99FKaSAo2OrEn5P0Dw3 nTrQ== X-Gm-Message-State: APjAAAXs+LIYT38mTWGP9lpJFd6C0z02JdvPDc7GsHXw62EJBZimCl1M jovh7Iyr0rhU1OFBorJX7/4Qzw== X-Received: by 2002:a62:7656:: with SMTP id r83mr70618823pfc.56.1560481996220; Thu, 13 Jun 2019 20:13:16 -0700 (PDT) Received: from localhost ([122.172.66.84]) by smtp.gmail.com with ESMTPSA id x7sm1023931pfm.82.2019.06.13.20.13.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jun 2019 20:13:15 -0700 (PDT) From: Viresh Kumar To: linux-arm-kernel@lists.infradead.org, Julien Thierry Cc: Viresh Kumar , stable@vger.kernel.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 31/45] arm/arm64: KVM: Add PSCI_VERSION helper Date: Fri, 14 Jun 2019 08:38:14 +0530 Message-Id: <0a350c8f3ce33baae43c1c800ea9747e398ef0fe.1560480942.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit d0a144f12a7ca8368933eae6583c096c363ec506 upstream. As we're about to trigger a PSCI version explosion, it doesn't hurt to introduce a PSCI_VERSION helper that is going to be used everywhere. Reviewed-by: Christoffer Dall Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas [ v4.4: account for files moved to virt/ upstream ] Signed-off-by: Viresh Kumar --- arch/arm/kvm/psci.c | 4 +--- include/kvm/arm_psci.h | 6 ++++-- include/uapi/linux/psci.h | 3 +++ 3 files changed, 8 insertions(+), 5 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/kvm/psci.c b/arch/arm/kvm/psci.c index b4acfec9b459..edf3d7fdcbdb 100644 --- a/arch/arm/kvm/psci.c +++ b/arch/arm/kvm/psci.c @@ -25,8 +25,6 @@ #include -#include - /* * This is an implementation of the Power State Coordination Interface * as described in ARM document number ARM DEN 0022A. @@ -220,7 +218,7 @@ static int kvm_psci_0_2_call(struct kvm_vcpu *vcpu) * Bits[31:16] = Major Version = 0 * Bits[15:0] = Minor Version = 2 */ - val = 2; + val = KVM_ARM_PSCI_0_2; break; case PSCI_0_2_FN_CPU_SUSPEND: case PSCI_0_2_FN64_CPU_SUSPEND: diff --git a/include/kvm/arm_psci.h b/include/kvm/arm_psci.h index 2042bb909474..5659343580a3 100644 --- a/include/kvm/arm_psci.h +++ b/include/kvm/arm_psci.h @@ -18,8 +18,10 @@ #ifndef __KVM_ARM_PSCI_H__ #define __KVM_ARM_PSCI_H__ -#define KVM_ARM_PSCI_0_1 1 -#define KVM_ARM_PSCI_0_2 2 +#include + +#define KVM_ARM_PSCI_0_1 PSCI_VERSION(0, 1) +#define KVM_ARM_PSCI_0_2 PSCI_VERSION(0, 2) int kvm_psci_version(struct kvm_vcpu *vcpu); int kvm_psci_call(struct kvm_vcpu *vcpu); diff --git a/include/uapi/linux/psci.h b/include/uapi/linux/psci.h index 3d7a0fc021a7..39930ca998cd 100644 --- a/include/uapi/linux/psci.h +++ b/include/uapi/linux/psci.h @@ -87,6 +87,9 @@ (((ver) & PSCI_VERSION_MAJOR_MASK) >> PSCI_VERSION_MAJOR_SHIFT) #define PSCI_VERSION_MINOR(ver) \ ((ver) & PSCI_VERSION_MINOR_MASK) +#define PSCI_VERSION(maj, min) \ + ((((maj) << PSCI_VERSION_MAJOR_SHIFT) & PSCI_VERSION_MAJOR_MASK) | \ + ((min) & PSCI_VERSION_MINOR_MASK)) /* PSCI features decoding (>=1.0) */ #define PSCI_1_0_FEATURES_CPU_SUSPEND_PF_SHIFT 1 From patchwork Fri Jun 14 03:08:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166770 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1506209ilk; Thu, 13 Jun 2019 20:13:20 -0700 (PDT) X-Google-Smtp-Source: APXvYqw6snObMlwFg7VRy+eJvZ6fER0kB/ChzPhdHQp2aeRQslHDn0hLpBLLzeawZyrjy4yf2q3T X-Received: by 2002:a65:56c5:: with SMTP id w5mr33155747pgs.434.1560482000667; Thu, 13 Jun 2019 20:13:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560482000; cv=none; d=google.com; s=arc-20160816; b=aDxCfvrLLxDXK+AE9g16EEEji6pl+TpYLHqH+GMk6/wyiF0OeG6Y/h0i7D9mpu/LB2 ff0MOosLDl+6KRVzAvDn8vVFpsqIBjT6oXDsMp7ogLRc+Ixqmzho3JpQtuWs1EJfDnTo JjP8+QGNFPRoeezgrSx2iqUG15xq3WpNMwROQjJIEQ0QlAUo2vHeVzx8XMUQDwVzslLw DXlnFeQnBr/meL/vpXYgEGP1aOZyK0AtaOafXPwiQ/GvQo0PwLm1BNvPM6J24e738JNk u4TBmHSWRWUaBAvTVHB5AvUnA4Dta0gO51zlKjDwSAPher9z7uOWpWsIBe9mnrWtlCPQ vL0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=++nRQWY/k4E+AlroFqtDd4Bo37FS6L7rS4A4U1awWIw=; b=tqOefUED+UHjTc4KlyQImWmuY1+6B4KNOPzuCoFMSQR91TuIMK3w5BE9oMsMJANIPc Muxr2SVDtmbNBaQlVMYfhZoQcG8za4OSKCC6vcFVQf5mBl8cInPZ+qr4gb3oVSSRBehI YbZkpoApIPI9uY4r+9DWakGu2nRmgFpTPifkdyFe0ORxcXI4iHX4OP1T10T9bIZ7/8UK bCt3kWu2Gevgp5OzgOtJ0cyF07mEg3zyOnsFfdDOdZGYgONm9d3wu5SNn3USwLYXgRrZ 9fe8AbJHH/nrZC+4iLeD/JEucwJ4Gv2gMEjo+30PMzHJ5BaRFprmkB9hFZ3HbJFLBt3b MfXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vjjNcN5l; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Instead of open coding the accesses to the various registers, let's add explicit SMCCC accessors. Reviewed-by: Christoffer Dall Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas [ v4.4: account for files moved to virt/ upstream ] Signed-off-by: Viresh Kumar --- arch/arm/kvm/psci.c | 52 ++++++++++++++++++++++++++++++++++++--------- 1 file changed, 42 insertions(+), 10 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/kvm/psci.c b/arch/arm/kvm/psci.c index edf3d7fdcbdb..7ef6cdd22163 100644 --- a/arch/arm/kvm/psci.c +++ b/arch/arm/kvm/psci.c @@ -32,6 +32,38 @@ #define AFFINITY_MASK(level) ~((0x1UL << ((level) * MPIDR_LEVEL_BITS)) - 1) +static u32 smccc_get_function(struct kvm_vcpu *vcpu) +{ + return vcpu_get_reg(vcpu, 0); +} + +static unsigned long smccc_get_arg1(struct kvm_vcpu *vcpu) +{ + return vcpu_get_reg(vcpu, 1); +} + +static unsigned long smccc_get_arg2(struct kvm_vcpu *vcpu) +{ + return vcpu_get_reg(vcpu, 2); +} + +static unsigned long smccc_get_arg3(struct kvm_vcpu *vcpu) +{ + return vcpu_get_reg(vcpu, 3); +} + +static void smccc_set_retval(struct kvm_vcpu *vcpu, + unsigned long a0, + unsigned long a1, + unsigned long a2, + unsigned long a3) +{ + vcpu_set_reg(vcpu, 0, a0); + vcpu_set_reg(vcpu, 1, a1); + vcpu_set_reg(vcpu, 2, a2); + vcpu_set_reg(vcpu, 3, a3); +} + static unsigned long psci_affinity_mask(unsigned long affinity_level) { if (affinity_level <= 3) @@ -74,7 +106,7 @@ static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu) unsigned long context_id; phys_addr_t target_pc; - cpu_id = vcpu_get_reg(source_vcpu, 1) & MPIDR_HWID_BITMASK; + cpu_id = smccc_get_arg1(source_vcpu) & MPIDR_HWID_BITMASK; if (vcpu_mode_is_32bit(source_vcpu)) cpu_id &= ~((u32) 0); @@ -93,8 +125,8 @@ static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu) return PSCI_RET_INVALID_PARAMS; } - target_pc = vcpu_get_reg(source_vcpu, 2); - context_id = vcpu_get_reg(source_vcpu, 3); + target_pc = smccc_get_arg2(source_vcpu); + context_id = smccc_get_arg3(source_vcpu); kvm_reset_vcpu(vcpu); @@ -113,7 +145,7 @@ static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu) * NOTE: We always update r0 (or x0) because for PSCI v0.1 * the general puspose registers are undefined upon CPU_ON. */ - vcpu_set_reg(vcpu, 0, context_id); + smccc_set_retval(vcpu, context_id, 0, 0, 0); vcpu->arch.power_off = false; smp_mb(); /* Make sure the above is visible */ @@ -133,8 +165,8 @@ static unsigned long kvm_psci_vcpu_affinity_info(struct kvm_vcpu *vcpu) struct kvm *kvm = vcpu->kvm; struct kvm_vcpu *tmp; - target_affinity = vcpu_get_reg(vcpu, 1); - lowest_affinity_level = vcpu_get_reg(vcpu, 2); + target_affinity = smccc_get_arg1(vcpu); + lowest_affinity_level = smccc_get_arg2(vcpu); /* Determine target affinity mask */ target_affinity_mask = psci_affinity_mask(lowest_affinity_level); @@ -208,7 +240,7 @@ int kvm_psci_version(struct kvm_vcpu *vcpu) static int kvm_psci_0_2_call(struct kvm_vcpu *vcpu) { struct kvm *kvm = vcpu->kvm; - unsigned long psci_fn = vcpu_get_reg(vcpu, 0) & ~((u32) 0); + unsigned long psci_fn = smccc_get_function(vcpu); unsigned long val; int ret = 1; @@ -275,14 +307,14 @@ static int kvm_psci_0_2_call(struct kvm_vcpu *vcpu) break; } - vcpu_set_reg(vcpu, 0, val); + smccc_set_retval(vcpu, val, 0, 0, 0); return ret; } static int kvm_psci_0_1_call(struct kvm_vcpu *vcpu) { struct kvm *kvm = vcpu->kvm; - unsigned long psci_fn = vcpu_get_reg(vcpu, 0) & ~((u32) 0); + unsigned long psci_fn = smccc_get_function(vcpu); unsigned long val; switch (psci_fn) { @@ -300,7 +332,7 @@ static int kvm_psci_0_1_call(struct kvm_vcpu *vcpu) break; } - vcpu_set_reg(vcpu, 0, val); + smccc_set_retval(vcpu, val, 0, 0, 0); return 1; } From patchwork Fri Jun 14 03:08:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166771 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1506233ilk; Thu, 13 Jun 2019 20:13:22 -0700 (PDT) X-Google-Smtp-Source: APXvYqz/pw9kbf14sqQENDNqOuOkUvTzs3LVuk+ciUaT8WsFNAytzOuDALL9SQImOlBOhIkqqSrF X-Received: by 2002:a63:1a5e:: with SMTP id a30mr32743515pgm.433.1560482002749; Thu, 13 Jun 2019 20:13:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560482002; cv=none; d=google.com; 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[209.132.180.67]) by mx.google.com with ESMTP id e8si1073936plb.420.2019.06.13.20.13.22; Thu, 13 Jun 2019 20:13:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WmcnbRBl; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726701AbfFNDNW (ORCPT + 14 others); Thu, 13 Jun 2019 23:13:22 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:33548 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725819AbfFNDNW (ORCPT ); Thu, 13 Jun 2019 23:13:22 -0400 Received: by mail-pl1-f195.google.com with SMTP id c14so386346plo.0 for ; Thu, 13 Jun 2019 20:13:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yC2M+WqtpDn8WEqkn0+0Dw3Z53HTrfg3c6ZZe0WXdnU=; b=WmcnbRBlcrJ3IY9xi/BpOaVweisIwA209RaPUwI7iSrlOTsC7QIVtv11a++G0ymVy7 7/d/e7VeS1Blvy4ln/zT1GMlpYXFOnxjRGhRK46l6U0++5CH5OxVJgM3nYwedYcr1Sle oDzoFzaqUV04aFnHFxAXamISMuLuvK/1aD7zUY4r9+NCaMrNwNb4wlkrxzVumU0D9+Z6 T2iUSYDPHRgTLloTFhTVt6JlnrJ6q1Xqtd4HeF1lDvu2En8MYfAfcVMV7OrT0F4SZaXu mxcZPmSigde4P5X5BaV8Lxqw5wOkLPQPbd9ia1kHlKJKVZ0Xf1lGzFRtTLUs0my/AxvO T4Pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yC2M+WqtpDn8WEqkn0+0Dw3Z53HTrfg3c6ZZe0WXdnU=; b=JuD2gmjpPVLqEku5hc3W27LrZGTNJr/TlMzQeUnSRFcDVk+zdH9o89jkAk2DEznPJU lSE9Eday7AjHCctkSNSLCrH4DE+XglYpc1G0s7hjJt98G7IJLCeNnimzFe3eqixyW24D GDq0nw02CelWmXU+9zMOxQhKytTEXISHHJ0Gbh81mmAlqhQsLCU4tlfDmMHSSqaEpP9Y IAfV8eZp8NU1NUFYo7YsuQK5Ool4Lkkk9fPEQHV8u9FWUT6fzh5zx0cVxehiou6rfr0m umJq5ASPmrJC2OxI+hXIB7LhjLNfKrg0Wf92ZbzsLoje3VWimHfoHoNwd51X/akqQJRz clcg== X-Gm-Message-State: APjAAAXeRUnPuraxwxrY9pqTX1XGe69NS6L/BUxhCXnjNQI5Odle1q7V nQmv0oI5RjFtJAXROOgE0II43w== X-Received: by 2002:a17:902:7007:: with SMTP id y7mr36617088plk.28.1560482001151; Thu, 13 Jun 2019 20:13:21 -0700 (PDT) Received: from localhost ([122.172.66.84]) by smtp.gmail.com with ESMTPSA id r88sm1527732pjb.8.2019.06.13.20.13.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jun 2019 20:13:20 -0700 (PDT) From: Viresh Kumar To: linux-arm-kernel@lists.infradead.org, Julien Thierry Cc: Viresh Kumar , stable@vger.kernel.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 33/45] ARM: 8478/2: arm/arm64: add arm-smccc Date: Fri, 14 Jun 2019 08:38:16 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Jens Wiklander commit 98dd64f34f47ce19b388d9015f767f48393a81eb upstream. Adds helpers to do SMC and HVC based on ARM SMC Calling Convention. CONFIG_HAVE_ARM_SMCCC is enabled for architectures that may support the SMC or HVC instruction. It's the responsibility of the caller to know if the SMC instruction is supported by the platform. This patch doesn't provide an implementation of the declared functions. Later patches will bring in implementations and set CONFIG_HAVE_ARM_SMCCC for ARM and ARM64 respectively. Reviewed-by: Lorenzo Pieralisi Signed-off-by: Jens Wiklander Signed-off-by: Russell King [ v4.4: Added #ifndef __ASSEMBLY__ section to fix compilation issues ] Signed-off-by: Viresh Kumar --- drivers/firmware/Kconfig | 3 ++ include/linux/arm-smccc.h | 107 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 110 insertions(+) create mode 100644 include/linux/arm-smccc.h -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index cf478fe6b335..49a3a1185bb6 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -173,6 +173,9 @@ config QCOM_SCM_64 def_bool y depends on QCOM_SCM && ARM64 +config HAVE_ARM_SMCCC + bool + source "drivers/firmware/broadcom/Kconfig" source "drivers/firmware/google/Kconfig" source "drivers/firmware/efi/Kconfig" diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h new file mode 100644 index 000000000000..611d10580340 --- /dev/null +++ b/include/linux/arm-smccc.h @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2015, Linaro Limited + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#ifndef __LINUX_ARM_SMCCC_H +#define __LINUX_ARM_SMCCC_H + +#include +#include + +/* + * This file provides common defines for ARM SMC Calling Convention as + * specified in + * http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html + */ + +#define ARM_SMCCC_STD_CALL 0 +#define ARM_SMCCC_FAST_CALL 1 +#define ARM_SMCCC_TYPE_SHIFT 31 + +#define ARM_SMCCC_SMC_32 0 +#define ARM_SMCCC_SMC_64 1 +#define ARM_SMCCC_CALL_CONV_SHIFT 30 + +#define ARM_SMCCC_OWNER_MASK 0x3F +#define ARM_SMCCC_OWNER_SHIFT 24 + +#define ARM_SMCCC_FUNC_MASK 0xFFFF + +#define ARM_SMCCC_IS_FAST_CALL(smc_val) \ + ((smc_val) & (ARM_SMCCC_FAST_CALL << ARM_SMCCC_TYPE_SHIFT)) +#define ARM_SMCCC_IS_64(smc_val) \ + ((smc_val) & (ARM_SMCCC_SMC_64 << ARM_SMCCC_CALL_CONV_SHIFT)) +#define ARM_SMCCC_FUNC_NUM(smc_val) ((smc_val) & ARM_SMCCC_FUNC_MASK) +#define ARM_SMCCC_OWNER_NUM(smc_val) \ + (((smc_val) >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK) + +#define ARM_SMCCC_CALL_VAL(type, calling_convention, owner, func_num) \ + (((type) << ARM_SMCCC_TYPE_SHIFT) | \ + ((calling_convention) << ARM_SMCCC_CALL_CONV_SHIFT) | \ + (((owner) & ARM_SMCCC_OWNER_MASK) << ARM_SMCCC_OWNER_SHIFT) | \ + ((func_num) & ARM_SMCCC_FUNC_MASK)) + +#define ARM_SMCCC_OWNER_ARCH 0 +#define ARM_SMCCC_OWNER_CPU 1 +#define ARM_SMCCC_OWNER_SIP 2 +#define ARM_SMCCC_OWNER_OEM 3 +#define ARM_SMCCC_OWNER_STANDARD 4 +#define ARM_SMCCC_OWNER_TRUSTED_APP 48 +#define ARM_SMCCC_OWNER_TRUSTED_APP_END 49 +#define ARM_SMCCC_OWNER_TRUSTED_OS 50 +#define ARM_SMCCC_OWNER_TRUSTED_OS_END 63 + +#ifndef __ASSEMBLY__ + +/** + * struct arm_smccc_res - Result from SMC/HVC call + * @a0-a3 result values from registers 0 to 3 + */ +struct arm_smccc_res { + unsigned long a0; + unsigned long a1; + unsigned long a2; + unsigned long a3; +}; + +/** + * arm_smccc_smc() - make SMC calls + * @a0-a7: arguments passed in registers 0 to 7 + * @res: result values from registers 0 to 3 + * + * This function is used to make SMC calls following SMC Calling Convention. + * The content of the supplied param are copied to registers 0 to 7 prior + * to the SMC instruction. The return values are updated with the content + * from register 0 to 3 on return from the SMC instruction. + */ +asmlinkage void arm_smccc_smc(unsigned long a0, unsigned long a1, + unsigned long a2, unsigned long a3, unsigned long a4, + unsigned long a5, unsigned long a6, unsigned long a7, + struct arm_smccc_res *res); + +/** + * arm_smccc_hvc() - make HVC calls + * @a0-a7: arguments passed in registers 0 to 7 + * @res: result values from registers 0 to 3 + * + * This function is used to make HVC calls following SMC Calling + * Convention. The content of the supplied param are copied to registers 0 + * to 7 prior to the HVC instruction. The return values are updated with + * the content from register 0 to 3 on return from the HVC instruction. + */ +asmlinkage void arm_smccc_hvc(unsigned long a0, unsigned long a1, + unsigned long a2, unsigned long a3, unsigned long a4, + unsigned long a5, unsigned long a6, unsigned long a7, + struct arm_smccc_res *res); + +#endif /*__ASSEMBLY__*/ +#endif /*__LINUX_ARM_SMCCC_H*/ From patchwork Fri Jun 14 03:08:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166772 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1506268ilk; Thu, 13 Jun 2019 20:13:25 -0700 (PDT) X-Google-Smtp-Source: APXvYqwPF+s7wri7atdQU/iHgh33YQ6L7L+LfKjD8J82e1Kj20Ui4RBYbYgUCOdAOBcyTnhg0pOf X-Received: by 2002:a17:902:760a:: with SMTP id k10mr70788313pll.83.1560482005555; Thu, 13 Jun 2019 20:13:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560482005; cv=none; d=google.com; s=arc-20160816; b=pxHPTEwlXWlX74Oj2FoH4BW0/C6hmkOhnkNYgsvGjwrOBMqXJuaeI73oWLhRMGtMe/ hv5CwAF5Z3/lmmX7ONFM/2CJfSKG9UupsfaahiuIwKexo91xmwmY8hnStSPf0mHY6kPA 3g8uxLhL0a6Mm/xTz1e/vJkrKogZZxv11prd4a1z9yJ8MyMH/vhXxWfa+P4JX6j9Mfyw Q/yf9Fyf5WQvppncwlYoEOmpfu+N+ViO7qXUfaOVnKh92s3LFUBK9dJcZvcrIj0BjWi6 Has84OE5dcgiw59S3ijwecCMg1osM4GbNMozP62fy7vpcs7a5ym0HiEAIly9dMKgmaX8 hUsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=4cjUvWF1fG1uJf64DV9LIZ2qblEK4Qh4cwDlO2OXHlc=; b=ZM6vw3Hv1kVihAYUx9RzkNcAbcjkzEMNtJD2/4ikyZ4FcDkLHGrxHuHK1Vb6Mia/HH izg9gz2x2FZBOkxmOoQa9o6FX2dwkGWLt5rPdI3m+57iTXE+f5C69ExUR952yWDdSOgb rWXAzQRk9O21PM04pmUWJsJLknFD9FR1axSVgx9cGYITWoLwCHnA98jgHYlQw6ccsAnV FbKngKGOZCS5L7t6ZkAwKHXd23O6QEu7OQYpxrNmCnMwbWEEak+atBUGirS1tmMyuSib wAk/aruIPiKt5LIswsnGzoX0wR+NYPbn0AU2fQLkG+zSi8epkXAS9F9bfEJmkxcxqhxx 2t8g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sFWQWr9W; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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PSCI 1.0 can be trivially implemented by providing the FEATURES call on top of PSCI 0.2 and returning 1.0 as the PSCI version. We happily ignore everything else, as they are either optional or are clarifications that do not require any additional change. PSCI 1.0 is now the default until we decide to add a userspace selection API. Reviewed-by: Christoffer Dall Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas [ v4.4: account for files moved to virt/ upstream ] Signed-off-by: Viresh Kumar --- arch/arm/kvm/psci.c | 45 +++++++++++++++++++++++++++++++++++++++++- include/kvm/arm_psci.h | 3 +++ 2 files changed, 47 insertions(+), 1 deletion(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/kvm/psci.c b/arch/arm/kvm/psci.c index 7ef6cdd22163..23428a3ac69b 100644 --- a/arch/arm/kvm/psci.c +++ b/arch/arm/kvm/psci.c @@ -232,7 +232,7 @@ static void kvm_psci_system_reset(struct kvm_vcpu *vcpu) int kvm_psci_version(struct kvm_vcpu *vcpu) { if (test_bit(KVM_ARM_VCPU_PSCI_0_2, vcpu->arch.features)) - return KVM_ARM_PSCI_0_2; + return KVM_ARM_PSCI_LATEST; return KVM_ARM_PSCI_0_1; } @@ -311,6 +311,47 @@ static int kvm_psci_0_2_call(struct kvm_vcpu *vcpu) return ret; } +static int kvm_psci_1_0_call(struct kvm_vcpu *vcpu) +{ + u32 psci_fn = smccc_get_function(vcpu); + u32 feature; + unsigned long val; + int ret = 1; + + switch(psci_fn) { + case PSCI_0_2_FN_PSCI_VERSION: + val = KVM_ARM_PSCI_1_0; + break; + case PSCI_1_0_FN_PSCI_FEATURES: + feature = smccc_get_arg1(vcpu); + switch(feature) { + case PSCI_0_2_FN_PSCI_VERSION: + case PSCI_0_2_FN_CPU_SUSPEND: + case PSCI_0_2_FN64_CPU_SUSPEND: + case PSCI_0_2_FN_CPU_OFF: + case PSCI_0_2_FN_CPU_ON: + case PSCI_0_2_FN64_CPU_ON: + case PSCI_0_2_FN_AFFINITY_INFO: + case PSCI_0_2_FN64_AFFINITY_INFO: + case PSCI_0_2_FN_MIGRATE_INFO_TYPE: + case PSCI_0_2_FN_SYSTEM_OFF: + case PSCI_0_2_FN_SYSTEM_RESET: + case PSCI_1_0_FN_PSCI_FEATURES: + val = 0; + break; + default: + val = PSCI_RET_NOT_SUPPORTED; + break; + } + break; + default: + return kvm_psci_0_2_call(vcpu); + } + + smccc_set_retval(vcpu, val, 0, 0, 0); + return ret; +} + static int kvm_psci_0_1_call(struct kvm_vcpu *vcpu) { struct kvm *kvm = vcpu->kvm; @@ -353,6 +394,8 @@ static int kvm_psci_0_1_call(struct kvm_vcpu *vcpu) int kvm_psci_call(struct kvm_vcpu *vcpu) { switch (kvm_psci_version(vcpu)) { + case KVM_ARM_PSCI_1_0: + return kvm_psci_1_0_call(vcpu); case KVM_ARM_PSCI_0_2: return kvm_psci_0_2_call(vcpu); case KVM_ARM_PSCI_0_1: diff --git a/include/kvm/arm_psci.h b/include/kvm/arm_psci.h index 5659343580a3..32360432cff5 100644 --- a/include/kvm/arm_psci.h +++ b/include/kvm/arm_psci.h @@ -22,6 +22,9 @@ #define KVM_ARM_PSCI_0_1 PSCI_VERSION(0, 1) #define KVM_ARM_PSCI_0_2 PSCI_VERSION(0, 2) +#define KVM_ARM_PSCI_1_0 PSCI_VERSION(1, 0) + +#define KVM_ARM_PSCI_LATEST KVM_ARM_PSCI_1_0 int kvm_psci_version(struct kvm_vcpu *vcpu); int kvm_psci_call(struct kvm_vcpu *vcpu); From patchwork Fri Jun 14 03:08:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166773 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1506290ilk; Thu, 13 Jun 2019 20:13:28 -0700 (PDT) X-Google-Smtp-Source: APXvYqzI/ObyLfx/uGhoAeVEqrbEqQPjGBSjYCKEKysYi8pD1W0H/p+3sunOK+5EO71kywSJYMsR X-Received: by 2002:a17:902:a516:: with SMTP id s22mr51404931plq.178.1560482008513; Thu, 13 Jun 2019 20:13:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560482008; cv=none; d=google.com; s=arc-20160816; b=Qn64LqY4mx1UOUsmZp49ey+DbJadFU3IsUrqtOftEWtY9oX36yxViG5bPb8BEvyewf SyquDji3LwXXvfJwu0pTwptTuuVf+LtFIktTUdw4LyGYa9LEhof1bWa27SkXL2O58scs Th/2JO1hL/r9vtb3vWvVmqakKmVIQw1TP1oww2dwx0OeZW9TsQV6uMl4gsHM2d+VDyBN kPTB97Myujrj+S2w19sGF5Zad+a2venSxme7XxzselV8GXpQ5/jxW/3BdyAylDRNRxKT L7lZUnnaBy6jHz+6u0TVYtzW0XzARbOcs9Acd93XChMeYVHYdunX6G1dJyvTHQ+to+65 i7nw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=sZ9weVw7RciwPWpWURkguqz3JkcjVDFiI8eMy/XIk6c=; b=mVFprDS61qsWz5CW7LsOQzwbSlP9Llza/Na4d8a2y6MaeODNhLLEdLU+eFdg1qfd3X 9AfyNaKdGw42JfaPS4TOumz2xIZaZVoe9AtPbEo5tXorc/Vt5igO8ZMyh9DYmpQzE9m7 WPifKNnByqAKCBao6UFXB0JcXxcVZMlrj+MM2cod2jRyWn4/C8FIiClEQQCip2e1Ldx8 XWi2GhmzQseL3xPbDWztUHgu1QPM4glsBI05RPu3Dk5HhYTCHw3qwZ4sU/yIGqD6kk/l 1riZll8myvFAuH/ekIE+1J25Z8AHF/AKHTFj9hrB/Qes98qiPM5KQC7niFBVU9TUNxBZ Yxpg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uBa2Fanu; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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The new SMC Calling Convention (v1.1) allows for a reduced overhead when calling into the firmware, and provides a new feature discovery mechanism. Make it visible to KVM guests. Tested-by: Ard Biesheuvel Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas [ v4.4: account for files moved to virt/ upstream ] Signed-off-by: Viresh Kumar --- arch/arm/kvm/handle_exit.c | 2 +- arch/arm/kvm/psci.c | 24 +++++++++++++++++++++++- arch/arm64/kvm/handle_exit.c | 2 +- include/kvm/arm_psci.h | 2 +- include/linux/arm-smccc.h | 13 +++++++++++++ 5 files changed, 39 insertions(+), 4 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/kvm/handle_exit.c b/arch/arm/kvm/handle_exit.c index ed879e3238d3..8d8daa2861f3 100644 --- a/arch/arm/kvm/handle_exit.c +++ b/arch/arm/kvm/handle_exit.c @@ -43,7 +43,7 @@ static int handle_hvc(struct kvm_vcpu *vcpu, struct kvm_run *run) trace_kvm_hvc(*vcpu_pc(vcpu), *vcpu_reg(vcpu, 0), kvm_vcpu_hvc_get_imm(vcpu)); - ret = kvm_psci_call(vcpu); + ret = kvm_hvc_call_handler(vcpu); if (ret < 0) { vcpu_set_reg(vcpu, 0, ~0UL); return 1; diff --git a/arch/arm/kvm/psci.c b/arch/arm/kvm/psci.c index 23428a3ac69b..76821adf4fde 100644 --- a/arch/arm/kvm/psci.c +++ b/arch/arm/kvm/psci.c @@ -15,6 +15,7 @@ * along with this program. If not, see . */ +#include #include #include #include @@ -337,6 +338,7 @@ static int kvm_psci_1_0_call(struct kvm_vcpu *vcpu) case PSCI_0_2_FN_SYSTEM_OFF: case PSCI_0_2_FN_SYSTEM_RESET: case PSCI_1_0_FN_PSCI_FEATURES: + case ARM_SMCCC_VERSION_FUNC_ID: val = 0; break; default: @@ -391,7 +393,7 @@ static int kvm_psci_0_1_call(struct kvm_vcpu *vcpu) * Errors: * -EINVAL: Unrecognized PSCI function */ -int kvm_psci_call(struct kvm_vcpu *vcpu) +static int kvm_psci_call(struct kvm_vcpu *vcpu) { switch (kvm_psci_version(vcpu)) { case KVM_ARM_PSCI_1_0: @@ -404,3 +406,23 @@ int kvm_psci_call(struct kvm_vcpu *vcpu) return -EINVAL; }; } + +int kvm_hvc_call_handler(struct kvm_vcpu *vcpu) +{ + u32 func_id = smccc_get_function(vcpu); + u32 val = PSCI_RET_NOT_SUPPORTED; + + switch (func_id) { + case ARM_SMCCC_VERSION_FUNC_ID: + val = ARM_SMCCC_VERSION_1_1; + break; + case ARM_SMCCC_ARCH_FEATURES_FUNC_ID: + /* Nothing supported yet */ + break; + default: + return kvm_psci_call(vcpu); + } + + smccc_set_retval(vcpu, val, 0, 0, 0); + return 1; +} diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c index 5b7fb5ab9136..a5fa27980a1d 100644 --- a/arch/arm64/kvm/handle_exit.c +++ b/arch/arm64/kvm/handle_exit.c @@ -43,7 +43,7 @@ static int handle_hvc(struct kvm_vcpu *vcpu, struct kvm_run *run) trace_kvm_hvc_arm64(*vcpu_pc(vcpu), vcpu_get_reg(vcpu, 0), kvm_vcpu_hvc_get_imm(vcpu)); - ret = kvm_psci_call(vcpu); + ret = kvm_hvc_call_handler(vcpu); if (ret < 0) { vcpu_set_reg(vcpu, 0, ~0UL); return 1; diff --git a/include/kvm/arm_psci.h b/include/kvm/arm_psci.h index 32360432cff5..ed1dd8088f1c 100644 --- a/include/kvm/arm_psci.h +++ b/include/kvm/arm_psci.h @@ -27,6 +27,6 @@ #define KVM_ARM_PSCI_LATEST KVM_ARM_PSCI_1_0 int kvm_psci_version(struct kvm_vcpu *vcpu); -int kvm_psci_call(struct kvm_vcpu *vcpu); +int kvm_hvc_call_handler(struct kvm_vcpu *vcpu); #endif /* __KVM_ARM_PSCI_H__ */ diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index 611d10580340..da9f3916f9a9 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -60,6 +60,19 @@ #define ARM_SMCCC_OWNER_TRUSTED_OS 50 #define ARM_SMCCC_OWNER_TRUSTED_OS_END 63 +#define ARM_SMCCC_VERSION_1_0 0x10000 +#define ARM_SMCCC_VERSION_1_1 0x10001 + +#define ARM_SMCCC_VERSION_FUNC_ID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + 0, 0) + +#define ARM_SMCCC_ARCH_FEATURES_FUNC_ID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + 0, 1) + #ifndef __ASSEMBLY__ /** From patchwork Fri Jun 14 03:08:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166774 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1506309ilk; Thu, 13 Jun 2019 20:13:30 -0700 (PDT) X-Google-Smtp-Source: APXvYqxPbsxH0otkJFmedGMHJCj2smV7NH6WQdcSDQr0VmDojXnoCuFRy3TkasAdMazkY8yj2QQW X-Received: by 2002:a17:902:70cb:: with SMTP id l11mr30091687plt.343.1560482010319; Thu, 13 Jun 2019 20:13:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560482010; cv=none; d=google.com; s=arc-20160816; b=HDrsH6WbsHdlpStZv8pwPkgViVlxUUK57ZyTkN9/gURst1NkPQuRHNbUtq0eMug2jM 4nneUYi9ArsYJpLfXO+mUc3rnzmdBoIwTXOIWgiaSuA65DFc2obLmwcvVFND42A0IHy+ ivAHKtQS0xoAm9rK01Dzzgjwzv6+bal4ccj92zcFjxlNc/XFncEHzX1YhDOu0yUIszNf UNDw7PEg8yigOhYWXIUUGb7sMCguswpyi4LHFWu4+tCtXWW8b6X8K20KRpL/e0cazMMd 8qyoB5pdAsVOlnVFE+L4FY4qtkQCBIbmzBaE6G6MP15LPHxgyehubFo3yS/eZ0hdPG2+ 78WA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ciH+Cy/cnjaV+iKRh72NhJx15MiI+P9rVJovcPRWoV0=; b=jXUnWDJ+jz+MkCTgt99L/9pNa0N+JHPNEZPw8z2NfW9Wu9tYvDldOonWjwu9qDhTXa cnAEkjr0ZqSvUb5rcrjUP4qjOs/a6O17r50P8aHAUxmZUgTI/kS/9BQ0ShYCg1xqmZvX VXIZ4E30OCGEmObFyAdxtcHY3qk2JAnuS6Y4Jv3ZVYMBqYMpaqIsNznx6XtfkljgWHJ+ MxvsU1jXWRsDRLTi38Ti20ElF2yoWofZ0GkVczgUXcHdTfIg5ftF/D6TnqLUEmNa6xAo RPC6nv1uYpCC/8tGtW1jqRAnHw2DRNTMVl6qxvZhS1CEGTr2Kl+RrdfYPN22ELxMsTCY ZR6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zCj6UOkk; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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We're about to need kvm_psci_version in HYP too. So let's turn it into a static inline, and pass the kvm structure as a second parameter (so that HYP can do a kern_hyp_va on it). Tested-by: Ard Biesheuvel Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas [ v4.4: account for files moved to virt/ upstream and drop switch.c changes ] Signed-off-by: Viresh Kumar --- arch/arm/kvm/psci.c | 12 ++---------- include/kvm/arm_psci.h | 21 ++++++++++++++++++++- 2 files changed, 22 insertions(+), 11 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/kvm/psci.c b/arch/arm/kvm/psci.c index 76821adf4fde..9abf40734723 100644 --- a/arch/arm/kvm/psci.c +++ b/arch/arm/kvm/psci.c @@ -120,7 +120,7 @@ static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu) if (!vcpu) return PSCI_RET_INVALID_PARAMS; if (!vcpu->arch.power_off) { - if (kvm_psci_version(source_vcpu) != KVM_ARM_PSCI_0_1) + if (kvm_psci_version(source_vcpu, kvm) != KVM_ARM_PSCI_0_1) return PSCI_RET_ALREADY_ON; else return PSCI_RET_INVALID_PARAMS; @@ -230,14 +230,6 @@ static void kvm_psci_system_reset(struct kvm_vcpu *vcpu) kvm_prepare_system_event(vcpu, KVM_SYSTEM_EVENT_RESET); } -int kvm_psci_version(struct kvm_vcpu *vcpu) -{ - if (test_bit(KVM_ARM_VCPU_PSCI_0_2, vcpu->arch.features)) - return KVM_ARM_PSCI_LATEST; - - return KVM_ARM_PSCI_0_1; -} - static int kvm_psci_0_2_call(struct kvm_vcpu *vcpu) { struct kvm *kvm = vcpu->kvm; @@ -395,7 +387,7 @@ static int kvm_psci_0_1_call(struct kvm_vcpu *vcpu) */ static int kvm_psci_call(struct kvm_vcpu *vcpu) { - switch (kvm_psci_version(vcpu)) { + switch (kvm_psci_version(vcpu, vcpu->kvm)) { case KVM_ARM_PSCI_1_0: return kvm_psci_1_0_call(vcpu); case KVM_ARM_PSCI_0_2: diff --git a/include/kvm/arm_psci.h b/include/kvm/arm_psci.h index ed1dd8088f1c..e518e4e3dfb5 100644 --- a/include/kvm/arm_psci.h +++ b/include/kvm/arm_psci.h @@ -18,6 +18,7 @@ #ifndef __KVM_ARM_PSCI_H__ #define __KVM_ARM_PSCI_H__ +#include #include #define KVM_ARM_PSCI_0_1 PSCI_VERSION(0, 1) @@ -26,7 +27,25 @@ #define KVM_ARM_PSCI_LATEST KVM_ARM_PSCI_1_0 -int kvm_psci_version(struct kvm_vcpu *vcpu); +/* + * We need the KVM pointer independently from the vcpu as we can call + * this from HYP, and need to apply kern_hyp_va on it... + */ +static inline int kvm_psci_version(struct kvm_vcpu *vcpu, struct kvm *kvm) +{ + /* + * Our PSCI implementation stays the same across versions from + * v0.2 onward, only adding the few mandatory functions (such + * as FEATURES with 1.0) that are required by newer + * revisions. It is thus safe to return the latest. + */ + if (test_bit(KVM_ARM_VCPU_PSCI_0_2, vcpu->arch.features)) + return KVM_ARM_PSCI_LATEST; + + return KVM_ARM_PSCI_0_1; +} + + int kvm_hvc_call_handler(struct kvm_vcpu *vcpu); #endif /* __KVM_ARM_PSCI_H__ */ From patchwork Fri Jun 14 03:08:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166775 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1506343ilk; Thu, 13 Jun 2019 20:13:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqyDPaNx4x5SgdpDkl8VBD7aui64+UkNVfUpxwlmVwqcE2ZL46Ctfd1nqOpWGXN8Y84hE8L4 X-Received: by 2002:a63:3008:: with SMTP id w8mr34030643pgw.11.1560482012819; Thu, 13 Jun 2019 20:13:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560482012; cv=none; d=google.com; s=arc-20160816; b=p/ns6MxtqAcbH/LNoQkeBOzhYEFRRpQ2Eryu8nEWJBsiDoDP8WLJgsUZ3nNGQU7Z4B mAvEHXXKJF7EVcC2iKBtca36pTKUBLyHHhNsztWcB3OpR+clRHZsjO4Tei6n7bodMQCK IWXFlybrIsId2qQXXysklw2tvsEIYGrwqR1o5otOzXjl9azCFNcnPoqyfcuIU901eOOv ksJdLEdvxm6M77Af2h55Kxk0eeun4f37CTCvI/xp3qxjRoFTO8mCTtl7aNa8IJzRDPSs YJeuRp9XiiZLG0eRroaKMBvpKcGgjPxrXf71BjnCda0c+7UOiGXOWXhrNRpOAQr7XqKE n24A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=pEvDH0l3Ogb+ETQluMoz8xjNqG/my4E0M8F+Bzkpfu4=; b=Nk9Gufoka09OzN3Y6VWYOH1vsrgCQAMl566x+IXfkCM5dFGpn/eLqk/w0BPyJSISjN SE4qEPQ/+q+/Ruuj2Bksbf7yMrEJXOFRyO6yX5qGriGGdMUlZzdfRaCrOEVfO66MXFkd 5akDtGEMeZMrmD6jlOpsV+av8BOGx52hDUTB6R7puZ9eOanf8p8C60Ss8zWLyK2hG/6l LSCIdVJDCaCinlA/BXNJG2v/JMgchoaoFgdR305mKnTUlYpWzuDCI75RwKYWXei1ffo+ NaGezyH0cVyFJ/DjkesEnVT1Q6NfMR4Sll5AovYsfQVQVyo52+OT509569Ut8ml/cGIU 7m/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WlxYLpJq; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e8si1073936plb.420.2019.06.13.20.13.32; Thu, 13 Jun 2019 20:13:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WlxYLpJq; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726742AbfFNDNc (ORCPT + 14 others); Thu, 13 Jun 2019 23:13:32 -0400 Received: from mail-pl1-f194.google.com ([209.85.214.194]:44971 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726705AbfFNDNb (ORCPT ); Thu, 13 Jun 2019 23:13:31 -0400 Received: by mail-pl1-f194.google.com with SMTP id t7so366561plr.11 for ; Thu, 13 Jun 2019 20:13:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pEvDH0l3Ogb+ETQluMoz8xjNqG/my4E0M8F+Bzkpfu4=; b=WlxYLpJqqc1s7ub+NyoMG89aE24FhTuR1DAGYoyRKrh58s1SM+98OItieICpHHaYKz j2XOKW5FhK/BqeAceNAYaH9h0teSC/B9bVUzCHj9RJpo4BWpcOm90NdrPPczDsQzxdpz MLP6MnCgpO3fGdk4dtky8QiWa1xxD7FZaLq3M03BgAmDwsK+TzThlwggyJpbYd09+wLA f3rJOyNYWL2YEr+nkMmP3eYjQ7SqG+0PAWrQAbIbVYtDa65LiPe0EGfr9oaz8X+P29DU ocYxamwYeiQ8R/uyXovL8UosqdJ83KPD5Lmwg57O62ycbsMsKqTE6FISGcyBwvTfKPqu jNnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pEvDH0l3Ogb+ETQluMoz8xjNqG/my4E0M8F+Bzkpfu4=; b=cpN95f1MN27T6/L/24zxuNj9L1WB8+MpeYQl7ZiMW5QX7nLIq5FsR3u1AKsVkjHKc/ l3MaVxBEK+DDfvEBBxC0FcNkZzloJBtkssDToiaDxGlHQdPHvIZOmkdl9moYnpniY/qg p/nfaP15AXLmcfAYH9fEMf8zTB67sV0npK7/6zn9DsALV+uLdm1y+jEeRkLyamqJCagc yrAeUEW+7we2AM+29eu48ERkdqZ95PDtByAJRErIsxqiR78nyLS+ovhJbEC/Pce+GYX4 ydV5jhrsk4vFiHvfr+Z9A7jEA3+YYSK0Gvi0ykfisLjy+0qwWSPvUARbyh/VXnSo4Eg0 nIbg== X-Gm-Message-State: APjAAAUkvcKhwGRU3gBWupl4/UMWo1lzPEAF7iB5EiiYDqfOWQmdnol1 lskbK8u5Nbem+kNo7v5lnNilbQ== X-Received: by 2002:a17:902:29a7:: with SMTP id h36mr39298958plb.158.1560482011111; Thu, 13 Jun 2019 20:13:31 -0700 (PDT) Received: from localhost ([122.172.66.84]) by smtp.gmail.com with ESMTPSA id x7sm1024288pfm.82.2019.06.13.20.13.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jun 2019 20:13:30 -0700 (PDT) From: Viresh Kumar To: linux-arm-kernel@lists.infradead.org, Julien Thierry Cc: Viresh Kumar , stable@vger.kernel.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 37/45] arm64: KVM: Report SMCCC_ARCH_WORKAROUND_1 BP hardening support Date: Fri, 14 Jun 2019 08:38:20 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Mark Rutland commit 6167ec5c9145cdf493722dfd80a5d48bafc4a18a upstream. A new feature of SMCCC 1.1 is that it offers firmware-based CPU workarounds. In particular, SMCCC_ARCH_WORKAROUND_1 provides BP hardening for CVE-2017-5715. If the host has some mitigation for this issue, report that we deal with it using SMCCC_ARCH_WORKAROUND_1, as we apply the host workaround on every guest exit. Tested-by: Ard Biesheuvel Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas [ v4.4: account for files moved to virt/ upstream ] Signed-off-by: Viresh Kumar --- arch/arm/include/asm/kvm_host.h | 6 ++++++ arch/arm/kvm/psci.c | 9 ++++++++- arch/arm64/include/asm/kvm_host.h | 5 +++++ include/linux/arm-smccc.h | 5 +++++ 4 files changed, 24 insertions(+), 1 deletion(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h index 6692982c9b57..2009894d9a8a 100644 --- a/arch/arm/include/asm/kvm_host.h +++ b/arch/arm/include/asm/kvm_host.h @@ -237,4 +237,10 @@ static inline void kvm_arm_setup_debug(struct kvm_vcpu *vcpu) {} static inline void kvm_arm_clear_debug(struct kvm_vcpu *vcpu) {} static inline void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu) {} +static inline bool kvm_arm_harden_branch_predictor(void) +{ + /* No way to detect it yet, pretend it is not there. */ + return false; +} + #endif /* __ARM_KVM_HOST_H__ */ diff --git a/arch/arm/kvm/psci.c b/arch/arm/kvm/psci.c index 9abf40734723..747319490268 100644 --- a/arch/arm/kvm/psci.c +++ b/arch/arm/kvm/psci.c @@ -403,13 +403,20 @@ int kvm_hvc_call_handler(struct kvm_vcpu *vcpu) { u32 func_id = smccc_get_function(vcpu); u32 val = PSCI_RET_NOT_SUPPORTED; + u32 feature; switch (func_id) { case ARM_SMCCC_VERSION_FUNC_ID: val = ARM_SMCCC_VERSION_1_1; break; case ARM_SMCCC_ARCH_FEATURES_FUNC_ID: - /* Nothing supported yet */ + feature = smccc_get_arg1(vcpu); + switch(feature) { + case ARM_SMCCC_ARCH_WORKAROUND_1: + if (kvm_arm_harden_branch_predictor()) + val = 0; + break; + } break; default: return kvm_psci_call(vcpu); diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index a35ce7266aac..aca3a7e28777 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -258,4 +258,9 @@ void kvm_arm_setup_debug(struct kvm_vcpu *vcpu); void kvm_arm_clear_debug(struct kvm_vcpu *vcpu); void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu); +static inline bool kvm_arm_harden_branch_predictor(void) +{ + return cpus_have_cap(ARM64_HARDEN_BRANCH_PREDICTOR); +} + #endif /* __ARM64_KVM_HOST_H__ */ diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index da9f3916f9a9..1f02e4045a9e 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -73,6 +73,11 @@ ARM_SMCCC_SMC_32, \ 0, 1) +#define ARM_SMCCC_ARCH_WORKAROUND_1 \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + 0, 0x8000) + #ifndef __ASSEMBLY__ /** From patchwork Fri Jun 14 03:08:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166776 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1506373ilk; Thu, 13 Jun 2019 20:13:35 -0700 (PDT) X-Google-Smtp-Source: APXvYqwFYgQe9RsWumDdfFIs5H37FxNGxu90vqz5N77Rqbzf4+TZTGzB8orJBGqQMp2z7jbRjxz3 X-Received: by 2002:a62:6083:: with SMTP id u125mr19294584pfb.208.1560482015864; Thu, 13 Jun 2019 20:13:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560482015; cv=none; d=google.com; s=arc-20160816; b=JAQTyAQY1APTkRNPGv8BkagvSzXzEXbWC+a3/i+py/uSifFHc0MLEbAcQfuySGKjw7 bvsXjxmGlAqbTredr8pZ1nkBd2/T1fAUULKlgkow2BB80BHXSoeGxKo2+q6CKd96D2v9 6WSN6KSeKQvVxi5DsBOTPtFrgikQvVxCrTdv4Ki09BRz2F9qYl9X4uS84WbBTBwTzRxy jLXK3/5E7xnj4Vl+2gPlHLK3BA1q6hq9iZRuxZwF1Wt1R3r7cWpg93DN4OW1DEpS1wQU DnGsIGSCd6PBOOLjpl58JdCvGa5hx8BnkbbTBgg8nRErUj9TwP8qvTVdxIRHX0G4+K3g TtBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Jfnhx8qRw0jZ5LbGeW1WuYGyQJR2HfAomwQkRmg+oIk=; b=j1b60IulW+IYrIiRzkIlCty/l1UC1YG6gHZNussNqFmN87HFWtjp10fF68UoIa6gGF GL/FpcZIm+ytNm/+jeTuc/3aB0AA6QYI6konWkhQBb1NS9sgqv2LEJZUMuggfjEfQgvx cL+5wpYfs9YMeH3J42GbYDTt6rR+Z8AAo+2RqnGPgJL9J08biR7TYyKlGenUILy+CKfk DUq8VhbWKnGTsLrNl3W5lkkKs3QBXbzk2827AOF6/Q2GB8D4xWw/k4MQbYzPr/gvAgJb 5leVQnDl6Zlutw5cuEpgS2h8UO6C4jdqCEpqcGcsVrAApy4s04KTySuWnlAX2vI25OcV 8u2A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qJNBo0b4; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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We want SMCCC_ARCH_WORKAROUND_1 to be fast. As fast as possible. So let's intercept it as early as we can by testing for the function call number as soon as we've identified a HVC call coming from the guest. Tested-by: Ard Biesheuvel Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas [ v4.4: Made changes to hyp.S instead and fixed registers ] Signed-off-by: Viresh Kumar --- arch/arm64/kvm/hyp.S | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kvm/hyp.S b/arch/arm64/kvm/hyp.S index 8d3da858c257..8aa2ede8c999 100644 --- a/arch/arm64/kvm/hyp.S +++ b/arch/arm64/kvm/hyp.S @@ -15,6 +15,7 @@ * along with this program. If not, see . */ +#include #include #include @@ -974,10 +975,11 @@ el1_sync: // Guest trapped into EL2 lsr x2, x1, #ESR_ELx_EC_SHIFT cmp x2, #ESR_ELx_EC_HVC64 + ccmp x2, #ESR_ELx_EC_HVC32, #4, ne b.ne el1_trap - mrs x3, vttbr_el2 // If vttbr is valid, the 64bit guest - cbnz x3, el1_trap // called HVC + mrs x3, vttbr_el2 // If vttbr is valid, the guest + cbnz x3, el1_hvc_guest // called HVC /* Here, we're pretty sure the host called HVC. */ pop x2, x3 @@ -1003,6 +1005,20 @@ el1_sync: // Guest trapped into EL2 pop lr, xzr 2: eret +el1_hvc_guest: + /* + * Fastest possible path for ARM_SMCCC_ARCH_WORKAROUND_1. + * The workaround has already been applied on the host, + * so let's quickly get back to the guest. We don't bother + * restoring x1, as it can be clobbered anyway. + */ + ldr x1, [sp] // Guest's x0 + eor w1, w1, #ARM_SMCCC_ARCH_WORKAROUND_1 + cbnz w1, el1_trap + mov x0, x1 + add sp, sp, #16 + eret + el1_trap: /* * x1: ESR From patchwork Fri Jun 14 03:08:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166777 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1506417ilk; Thu, 13 Jun 2019 20:13:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqzPIFpF8Q93qupDY012frn78OYw03UFXAXUzgx3SbMDgrNMP95diI0wDf08kGD81aVQWsbt X-Received: by 2002:a17:902:b94a:: with SMTP id h10mr91092106pls.265.1560482018530; Thu, 13 Jun 2019 20:13:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560482018; cv=none; d=google.com; s=arc-20160816; b=EvK0pFawYNvkEpCqiJk9Iwia9scXlv/e1nmGgTtVfKQSBYOpiJzcb0ZjagRYSlt76a G0m/BtXwTHLnUJ0Nc4T45wnTuuZ5LOz5w9LHguEIBat5JoBgBEO6J/mdizdraoU9oc+N y8RavkSkKPJKWBWY3wE1h7GS0hVmeyP2/9FhzWwOor03FJcJt88ECJjxa24ypjhgazh6 xsI/m7kyh0tJH6Lt+3h4uMGWpWizrQhA2DawehiZEFpv4VIQIwRTsLLesVeBjRfkcRUW dphjLsWdVOOinwNe91j21lUt2UiJ7YtKD9OcjTfZ71nuL6ObZE06f3TNAtFSb2/n0OIj qLIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=lhetsf/v1WHqsODDPiuS8lCaAlBwJqZTnWnIuf4OhuE=; b=0A1bmAUf5a4rGh9qAnei0228IX/OfOV/Bfuh7ZI4x0nvd0N839kHqRUqQ8vZJDOP5/ ezvQ47mbMqZPxWP0Y0er1y8MO3THdmC6dfw2ZsmxvhYghCd+nTRaKb7o660VAy3ONRHF 5F/px+kiF8H4iBgfwZTr2MWoXbYM9xOEqRffZeRgUuQadDu/3RM67cnHKhQr1dHiCQxP F6p95e6S2y7Gk4A4yhddHngiMtyV/NoMqH0QTcdGQm0nPH2nk8ww2zOmkpm1VslR83+5 EmGWm6jRS4FBbHJybGvsGlpChzRFekY0p2pptD0WHBxkmZmEad7JNLgS22PFYkuVTGpG DRqg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dzAIXfjM; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e8si1073936plb.420.2019.06.13.20.13.38; Thu, 13 Jun 2019 20:13:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dzAIXfjM; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726750AbfFNDNh (ORCPT + 14 others); Thu, 13 Jun 2019 23:13:37 -0400 Received: from mail-pf1-f193.google.com ([209.85.210.193]:42971 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726705AbfFNDNh (ORCPT ); Thu, 13 Jun 2019 23:13:37 -0400 Received: by mail-pf1-f193.google.com with SMTP id q10so487408pff.9 for ; Thu, 13 Jun 2019 20:13:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lhetsf/v1WHqsODDPiuS8lCaAlBwJqZTnWnIuf4OhuE=; b=dzAIXfjMtBl0yLP99Ks992Mq6IPJZ1HUk7Cbh9sMLFPdCk0tjIbGqG2zuQ02QyxMll jM+kUdcPwm9JdTju9yvrbg8ThgOP88bOWYBqRNTKKJVn7ijo43+wsVsQbqUJItl1uuqC kl9DITbxr1DjaaV0vry/PlU/VBmSmjfWu86CuurkeLAk6rmmhbUx61UfBSdkvXJWnXHx w4RX182pDEgAvFqcb21IReDHbX6IVx3u7uvXz5GUI3/M3RcKN1eDoJ1I7TfEw5jqHGKc 445EMtA6G9UfW0AnEtq03m5nA8StW9sR8G/tiN2bQeZCRzDw4CNP02qyubxU8Axkf4CU WLmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lhetsf/v1WHqsODDPiuS8lCaAlBwJqZTnWnIuf4OhuE=; b=a/g0MvTqDO5O8CY6JbnXhaaVSyCY4mEnUWuQ4AtYSdMZfBzIE9jfaqk5cJhA7uHd3u q6fmrspFlNic2z++DTBDsqHan1/r2G3ie+bB2yb3vDRXG2Rgx5i4PdGWSsxOTyDdCLmR qzM6G7zUN8qCUh2oBg9qlqDWWJvg/ZJlDIwBl+houpTxnrr79WBEzg5uT+KJAF6QABYV LxIo1KAAhoT5IgU9o912zu/snvf4C7np1QC5XQph+I2VF9HPJ9QOrvsMzyC+dPFlAXRe aquxVjOirdc6jRqOLq1spzyDf3kmWf9jvOl6t+5sDOPl8uAao4jLwaijzdkeD6KAkiW1 hFBQ== X-Gm-Message-State: APjAAAU314s1CYPWV4Fu0Bvtqj0BQ+ekT1HSiEFCp0GY3c7zXf6uFO1g c1nf+wN359duPsxV4wNlA+LdDH5FEEY= X-Received: by 2002:a63:1b56:: with SMTP id b22mr32193643pgm.87.1560482016730; Thu, 13 Jun 2019 20:13:36 -0700 (PDT) Received: from localhost ([122.172.66.84]) by smtp.gmail.com with ESMTPSA id e22sm1107255pgb.9.2019.06.13.20.13.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jun 2019 20:13:36 -0700 (PDT) From: Viresh Kumar To: linux-arm-kernel@lists.infradead.org, Julien Thierry Cc: Viresh Kumar , stable@vger.kernel.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 39/45] firmware/psci: Expose PSCI conduit Date: Fri, 14 Jun 2019 08:38:22 +0530 Message-Id: <8b5c248d26b432206c3e019d8630da59e18dfb3d.1560480942.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit 09a8d6d48499f93e2abde691f5800081cd858726 upstream. In order to call into the firmware to apply workarounds, it is useful to find out whether we're using HVC or SMC. Let's expose this through the psci_ops. Acked-by: Lorenzo Pieralisi Reviewed-by: Robin Murphy Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- drivers/firmware/psci.c | 28 +++++++++++++++++++++++----- include/linux/psci.h | 7 +++++++ 2 files changed, 30 insertions(+), 5 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c index 290f8982e7b3..7b2665f6b38d 100644 --- a/drivers/firmware/psci.c +++ b/drivers/firmware/psci.c @@ -54,7 +54,9 @@ bool psci_tos_resident_on(int cpu) return cpu == resident_cpu; } -struct psci_operations psci_ops; +struct psci_operations psci_ops = { + .conduit = PSCI_CONDUIT_NONE, +}; typedef unsigned long (psci_fn)(unsigned long, unsigned long, unsigned long, unsigned long); @@ -187,6 +189,22 @@ static unsigned long psci_migrate_info_up_cpu(void) 0, 0, 0); } +static void set_conduit(enum psci_conduit conduit) +{ + switch (conduit) { + case PSCI_CONDUIT_HVC: + invoke_psci_fn = __invoke_psci_fn_hvc; + break; + case PSCI_CONDUIT_SMC: + invoke_psci_fn = __invoke_psci_fn_smc; + break; + default: + WARN(1, "Unexpected PSCI conduit %d\n", conduit); + } + + psci_ops.conduit = conduit; +} + static int get_set_conduit_method(struct device_node *np) { const char *method; @@ -199,9 +217,9 @@ static int get_set_conduit_method(struct device_node *np) } if (!strcmp("hvc", method)) { - invoke_psci_fn = __invoke_psci_fn_hvc; + set_conduit(PSCI_CONDUIT_HVC); } else if (!strcmp("smc", method)) { - invoke_psci_fn = __invoke_psci_fn_smc; + set_conduit(PSCI_CONDUIT_SMC); } else { pr_warn("invalid \"method\" property: %s\n", method); return -EINVAL; @@ -463,9 +481,9 @@ int __init psci_acpi_init(void) pr_info("probing for conduit method from ACPI.\n"); if (acpi_psci_use_hvc()) - invoke_psci_fn = __invoke_psci_fn_hvc; + set_conduit(PSCI_CONDUIT_HVC); else - invoke_psci_fn = __invoke_psci_fn_smc; + set_conduit(PSCI_CONDUIT_SMC); return psci_probe(); } diff --git a/include/linux/psci.h b/include/linux/psci.h index 04b4d92c7791..e071a1b8ddb5 100644 --- a/include/linux/psci.h +++ b/include/linux/psci.h @@ -24,6 +24,12 @@ bool psci_tos_resident_on(int cpu); bool psci_power_state_loses_context(u32 state); bool psci_power_state_is_valid(u32 state); +enum psci_conduit { + PSCI_CONDUIT_NONE, + PSCI_CONDUIT_SMC, + PSCI_CONDUIT_HVC, +}; + struct psci_operations { u32 (*get_version)(void); int (*cpu_suspend)(u32 state, unsigned long entry_point); @@ -33,6 +39,7 @@ struct psci_operations { int (*affinity_info)(unsigned long target_affinity, unsigned long lowest_affinity_level); int (*migrate_info_type)(void); + enum psci_conduit conduit; }; extern struct psci_operations psci_ops; From patchwork Fri Jun 14 03:08:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166778 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1506454ilk; Thu, 13 Jun 2019 20:13:41 -0700 (PDT) X-Google-Smtp-Source: APXvYqyBzeVGNLymwH17e2HeFNyp5R9uk1VTZQIukoWioFAQjkFdVIEMWAQWJFCFxXBEkrlDD6rM X-Received: by 2002:a65:56c5:: with SMTP id w5mr33156694pgs.434.1560482020680; Thu, 13 Jun 2019 20:13:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560482020; cv=none; d=google.com; s=arc-20160816; b=cwRHe6YbbJ5DSXorQAn19+/PIaHZ7VEvgud2h7a7Wxe17xFO9SGq3nTLtZzF96DMAT EXY7aiVpUMVGTlXm2W6gUCPHEceRjkJS9XginEpr50MPPZ1MVeaSIkymGAUO+PbDCgPE 7wNDeq1rwgz+fq9A2aAJbRVKw1y/l1RK5CUKxM86YzrRx1z0u884VLaIX+eKf7YDhVTy 3iCd7bNnU0ebNqqJeTAojrxOHIQ5t9ZqHMGZck+lFO6+3t2Mh/fvpfyLoE0uEZv/j9tb nGU44ZXeUDcJpH0GQRQw0PT3uKi+vEpUHLfTS01QbboU5r6lsSXuxiUf3iFvw301cpgs ZuzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=8FgYZ0lVoh76yEFRGdkiTuXxRHgDjc15a9Db0UAG0RM=; b=kw+GDNX5gyLdr9iCuDaeoRgVnpxXw+e1L/lWewMm2YeT1erSNZAd2yDE4hSv5EWQ0A qQ+y5Mm5T6Jk/uB8fqOOXNf2F0kg5PBBXIvD75bj8WDW5d5X2zxuED9464QZSghqDvmD 6SHHt2ahx64pnyBlnUnfWw3MZuUGXOuxt3yYwXvYJHMVxryt9cltLBCQZ2JYIry3LPho UmVblbVmrBS3YMxod/L6yt3tL900gnxRNldm+I8yxWp+YTjLockeWdqqzKJ2M7SJmh+T 7+lLfQ+ycMeI6FaPkyLhMmGzSKp6JbqzEHPjikAZ67aJ51AOGLUQjxNMt1sX90PfrlZU Mvyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lv7ALkok; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e8si1073936plb.420.2019.06.13.20.13.40; Thu, 13 Jun 2019 20:13:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lv7ALkok; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726757AbfFNDNk (ORCPT + 14 others); Thu, 13 Jun 2019 23:13:40 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:45459 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726705AbfFNDNj (ORCPT ); Thu, 13 Jun 2019 23:13:39 -0400 Received: by mail-pg1-f195.google.com with SMTP id s21so656762pga.12 for ; Thu, 13 Jun 2019 20:13:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8FgYZ0lVoh76yEFRGdkiTuXxRHgDjc15a9Db0UAG0RM=; b=lv7ALkokBtCxuF0Pb2QGAynH5EmP6+hWl8YTf/8htRpD/JOpxkK1Xua6Q32p3zAcJG MlKJcqsbz1BZt1tqo8tVvOPin1iNWGS1K6vb4+S5DL/w8JwY69CkxhmvsPgybtMSUt2y dX4adwqML14qOFeBbRhLQVBoxwaKNGrAXPQWW/CSQmHOJAznIPzo/P9umTzO4khHXPEd /ElLjLUlWaRKbTTbi6i8H6WoRILdTuSgwWQy5f5rY2018+96HoUsMaCWeV6KsfoEu/uG 6NciLkwwDCxmVny3AZfHRF7pM7QkTQpPdnKJQW9w4ut5rsTLsv63X3Z0VD/EfTN1ypud hTVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8FgYZ0lVoh76yEFRGdkiTuXxRHgDjc15a9Db0UAG0RM=; b=nHSM7GYLTQc7bmuv66xFCLCbSqprHOrljpu/NYUeeCchWBf3/FuBkIG6IG17oFQxpA O8Qiq37k9j1KZ/WM3z6qZm8hB3pBF1GMDMzC4S5EeOUf9aSYq3VDLPt7koi+kPuqsV/W 0uYZCukBLzk4e8ij2bEE5vQORV4S3YSY+DeNwHVjf04IK/GIl8wJyHQZdsURJk2znC1+ Q8VbByylUcz4aXIiOGfdf7Gj4OWr5ryu2i/sefj3KTfPGq+UtWXRLxzwJOFgxIf79kWq MYkkTKypnOjrLSHQAAbhe7FAXdrCCiPIDzcoQAFxKheplND3uCLzEMh5GgXCi/3tMsrF 9i6g== X-Gm-Message-State: APjAAAUDjf9SlNkuIPTYxHvXIIhuF86Qa6A2ceBXQtucE6+niI1JH8qS NLiZDaCZQWHDcmXaQwfOrxBwSA== X-Received: by 2002:a17:90a:5d0a:: with SMTP id s10mr8696027pji.94.1560482019108; Thu, 13 Jun 2019 20:13:39 -0700 (PDT) Received: from localhost ([122.172.66.84]) by smtp.gmail.com with ESMTPSA id s15sm1080007pfd.183.2019.06.13.20.13.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jun 2019 20:13:38 -0700 (PDT) From: Viresh Kumar To: linux-arm-kernel@lists.infradead.org, Julien Thierry Cc: Viresh Kumar , stable@vger.kernel.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 40/45] firmware/psci: Expose SMCCC version through psci_ops Date: Fri, 14 Jun 2019 08:38:23 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit e78eef554a912ef6c1e0bbf97619dafbeae3339f upstream. Since PSCI 1.0 allows the SMCCC version to be (indirectly) probed, let's do that at boot time, and expose the version of the calling convention as part of the psci_ops structure. Acked-by: Lorenzo Pieralisi Reviewed-by: Robin Murphy Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas [ v4.4: Included arm-smccc.h ] Signed-off-by: Viresh Kumar --- drivers/firmware/psci.c | 28 ++++++++++++++++++++++++++++ include/linux/psci.h | 6 ++++++ 2 files changed, 34 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c index 7b2665f6b38d..0809a48e8089 100644 --- a/drivers/firmware/psci.c +++ b/drivers/firmware/psci.c @@ -13,6 +13,7 @@ #define pr_fmt(fmt) "psci: " fmt +#include #include #include #include @@ -56,6 +57,7 @@ bool psci_tos_resident_on(int cpu) struct psci_operations psci_ops = { .conduit = PSCI_CONDUIT_NONE, + .smccc_version = SMCCC_VERSION_1_0, }; typedef unsigned long (psci_fn)(unsigned long, unsigned long, @@ -320,6 +322,31 @@ static void __init psci_init_migrate(void) pr_info("Trusted OS resident on physical CPU 0x%lx\n", cpuid); } +static void __init psci_init_smccc(void) +{ + u32 ver = ARM_SMCCC_VERSION_1_0; + int feature; + + feature = psci_features(ARM_SMCCC_VERSION_FUNC_ID); + + if (feature != PSCI_RET_NOT_SUPPORTED) { + u32 ret; + ret = invoke_psci_fn(ARM_SMCCC_VERSION_FUNC_ID, 0, 0, 0); + if (ret == ARM_SMCCC_VERSION_1_1) { + psci_ops.smccc_version = SMCCC_VERSION_1_1; + ver = ret; + } + } + + /* + * Conveniently, the SMCCC and PSCI versions are encoded the + * same way. No, this isn't accidental. + */ + pr_info("SMC Calling Convention v%d.%d\n", + PSCI_VERSION_MAJOR(ver), PSCI_VERSION_MINOR(ver)); + +} + static void __init psci_0_2_set_functions(void) { pr_info("Using standard PSCI v0.2 function IDs\n"); @@ -368,6 +395,7 @@ static int __init psci_probe(void) psci_init_migrate(); if (PSCI_VERSION_MAJOR(ver) >= 1) { + psci_init_smccc(); psci_init_cpu_suspend(); psci_init_system_suspend(); } diff --git a/include/linux/psci.h b/include/linux/psci.h index e071a1b8ddb5..e5c3277bfd78 100644 --- a/include/linux/psci.h +++ b/include/linux/psci.h @@ -30,6 +30,11 @@ enum psci_conduit { PSCI_CONDUIT_HVC, }; +enum smccc_version { + SMCCC_VERSION_1_0, + SMCCC_VERSION_1_1, +}; + struct psci_operations { u32 (*get_version)(void); int (*cpu_suspend)(u32 state, unsigned long entry_point); @@ -40,6 +45,7 @@ struct psci_operations { unsigned long lowest_affinity_level); int (*migrate_info_type)(void); enum psci_conduit conduit; + enum smccc_version smccc_version; }; extern struct psci_operations psci_ops; From patchwork Fri Jun 14 03:08:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166779 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1506493ilk; Thu, 13 Jun 2019 20:13:44 -0700 (PDT) X-Google-Smtp-Source: APXvYqz6YkKT10iJPQERoEI6Bc9U+ZxeobF+u4V6synvHyddLvVCq9h0667jd4uoSIquRmqTH6gf X-Received: by 2002:a63:6c87:: with SMTP id h129mr34440753pgc.427.1560482024086; Thu, 13 Jun 2019 20:13:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560482024; cv=none; d=google.com; s=arc-20160816; b=mTttHI516IlHZhmzrs0J/i+0b7uDVhFsQzZozuCAITcN0xTrI9EksWS5gQI3f+emhH ceNRjP3Hd1ImmPy+csWlcnxdselu7YaUn5yeqew/ZZGK15i8hzlPqforx12vPmlaNCKg g5slHFCbhUGaydW1s+I1j8Xy5cwJuMtiBTZPFtkWNU09ndbMCBVlRUKj4zaYov8d/fjs X7tGgp60UC23hal8jVixVLzZIBa5TTBrqPiuZQDDyrCUMiaqsLbjlrJ4kezugTA4kh4V m/vVCz+HnmmtAZILPWY0s4wSqCTd09Z2qx7XphB89R4+oj2eM4SVkETVw5JcB9QB+Ctv ns9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=QAkAWOSid7lK0+CYFipQ6VxUVVXehQyD0WFI7UyGT+o=; b=IA5Fyg9oQqx8/YIbLDV1zdCZ45YtFL8khXN4yZkIxN8t8dz4NEXTne6J3vrDUwssIL wEwUcgBbumPi1pSvis49Gn8IJT+IlhrES2FMyOFCNkUmRn1nNeYFG58wmd7y8HOM5cDx 4tVLv50ytUa/7tsUWNE+BhPjJyqBYKvI+Knq/SnfCRApiAi3Hzcd2Pd0pwLNifaRkNtX eiHiN3ZKt1P7M6dJqKaCJ+3HPOKCQPQm/zO1Pmqk9PIplehHzOa1Nmd2b9kVOSwHZEkT wdI1V02gmJxMjlogaUCUqyo9akNNsK1y5rP493xXj217CjezlcJjWvOfFkoZoJu0xgRh 8U5A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dmFfqE3R; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e8si1073936plb.420.2019.06.13.20.13.43; Thu, 13 Jun 2019 20:13:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dmFfqE3R; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725819AbfFNDNn (ORCPT + 14 others); Thu, 13 Jun 2019 23:13:43 -0400 Received: from mail-pl1-f196.google.com ([209.85.214.196]:33573 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726705AbfFNDNn (ORCPT ); Thu, 13 Jun 2019 23:13:43 -0400 Received: by mail-pl1-f196.google.com with SMTP id c14so386651plo.0 for ; Thu, 13 Jun 2019 20:13:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QAkAWOSid7lK0+CYFipQ6VxUVVXehQyD0WFI7UyGT+o=; b=dmFfqE3RSIU4Ho6hkmSADd23EX+tld4u3806oEUalpRrZVS1cmqp5pzecti/qkD7MZ 9Q3F2qViabRLb87OzNLEHUqavrai4vT1AePqeLFjnkK9PoK0AfUNYJH2+KI7xJBPS6r7 pCpMcHoGyhyHHrUyjEX+zzBhOGuN+rle9DTQ5CMxtawV8Ggri+/OhRLNOYiPgc1txdxD 283Mtizasgg7BvjljAVyKErkf04q+T1Mg7+g9U5s1atYL96TtGRaJL5dYuqOaa3CE2St bygSaCJMOu8636e0BsJZ7m6fYlBUCXIEHTfkTcduBKpFjhZM03cCN79RPuIq2AqaekHK M8BQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QAkAWOSid7lK0+CYFipQ6VxUVVXehQyD0WFI7UyGT+o=; b=o7rsh0Zd9Aa7VezmIRPj7we+oUn8cdqEOllpGy3w2ohotwQZCnuUtmG040rYUmDFnI HksHtr1oWIL2oBaT4XHq1OOPikq85kzVN2YHODPUQTO4X4RdmOogOvTkAutMjh+cBXaG r9IBp/mzj51WDPnoZYfM5q6q25syhMiDvI/WNaHt55JMukf2WV5J2UHDtPAMiMd9+GxG JUkp97GbKE1C/huP+7HnNiB8AbihXmLOL8STQ+YgMJ5T0uE1z8CqRaHJlSlGPkDAVxj1 Nesq568b9q/qVNT5CYHHXBsMnFtoj4LBAPsZIFv6guvCADzUNl5X9lcgW+vLcSOlmUjn JRtA== X-Gm-Message-State: APjAAAUR2NdIz9CXGYfBRytabAtQ4x8JvB/am5Ew3DdIfJbohkOUH+6q NxsVHACrxHQNuBxhF9NXCz6Zj1X80BM= X-Received: by 2002:a17:902:7c04:: with SMTP id x4mr31949468pll.70.1560482021795; Thu, 13 Jun 2019 20:13:41 -0700 (PDT) Received: from localhost ([122.172.66.84]) by smtp.gmail.com with ESMTPSA id w187sm1079648pfb.4.2019.06.13.20.13.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jun 2019 20:13:41 -0700 (PDT) From: Viresh Kumar To: linux-arm-kernel@lists.infradead.org, Julien Thierry Cc: Viresh Kumar , stable@vger.kernel.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 41/45] arm/arm64: smccc: Make function identifiers an unsigned quantity Date: Fri, 14 Jun 2019 08:38:24 +0530 Message-Id: <5aeb3eee8907e3b49c19614c5c104f8a598faa95.1560480942.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit ded4c39e93f3b72968fdb79baba27f3b83dad34c upstream. Function identifiers are a 32bit, unsigned quantity. But we never tell so to the compiler, resulting in the following: 4ac: b26187e0 mov x0, #0xffffffff80000001 We thus rely on the firmware narrowing it for us, which is not always a reasonable expectation. Cc: stable@vger.kernel.org Reported-by: Ard Biesheuvel Acked-by: Ard Biesheuvel Reviewed-by: Robin Murphy Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- include/linux/arm-smccc.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index 1f02e4045a9e..4c45fd75db5d 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -16,6 +16,7 @@ #include #include +#include /* * This file provides common defines for ARM SMC Calling Convention as @@ -23,8 +24,8 @@ * http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html */ -#define ARM_SMCCC_STD_CALL 0 -#define ARM_SMCCC_FAST_CALL 1 +#define ARM_SMCCC_STD_CALL _AC(0,U) +#define ARM_SMCCC_FAST_CALL _AC(1,U) #define ARM_SMCCC_TYPE_SHIFT 31 #define ARM_SMCCC_SMC_32 0 From patchwork Fri Jun 14 03:08:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166780 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1506518ilk; Thu, 13 Jun 2019 20:13:45 -0700 (PDT) X-Google-Smtp-Source: APXvYqxZB5Aza3b3NkpEfVyMl/r0gxgJ7ZCTPgiPqhpCe9xAKRY2SkgUSdgHEBX5P6vVo3/TeBCJ X-Received: by 2002:aa7:8e54:: with SMTP id d20mr7536589pfr.16.1560482025870; Thu, 13 Jun 2019 20:13:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560482025; cv=none; d=google.com; s=arc-20160816; b=guG7QfbV2IpaOEiIPIA+xT1p1nou0UJOgnUleNUaRFeFOjpa1qHAb0yokWFsdPC4Zq i8W6tYoKo9CQaVSri/LUmFvsm0BjUtC6Hiay2Bx8T46KtWRNv+P9qmAdOzhnnJHNsELE Kh90HOOmhK+bmBAaGUNylgC5n3cpeuL2Var2xj1r7qRW5KdcrTXTGWgCk0k0+6jf+gpe U1nZ/5CFLjyZL6EfxqixVsMNct92n1KKkbetg3WEa3u7TqsCcQLgvYiJ8cyjKJRCxTS4 qQBh5ak8T9/pK5rk4pFEDyVwKHtgymk4vosuYvNt7HEoOIuWB6RwgTj3nqJpzIUuny3p mx8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kulBovnYLz4YjgSJ0sOniJhX8Qcc8ljUXoag6+mJQMI=; b=OeX6IAttptlBz2V9ctPt6NDZiq8imECUf8Axeb2t4dyiX7oz7WyYa1E1rTaibFbfBL /SwPb6vpSfdn/ccQRGcwDtUEwRkztp+TBe9gSXM0I6AE+O+Hv8C+TWfF9XSaDX5yFckZ RJLA6gqrb96fkxqJT2VvvnfCtA/27zIEztNMRnfUbB2YNA2NJU+fiJ93+54WBSX67xPS 2+CZ795W0Djzcrft/pcRFyR7N+dbnwDFr/qlNP3bTm0jht+c/8ob559YEQaJYVYxNzkI VDfk/chq+PeVEKAra/MtRK1yV41xdoACJC3pzDx0YQMB8HGWh64XaLFyDYo/CldGvioE ZcyA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZuPth7El; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e8si1073936plb.420.2019.06.13.20.13.45; Thu, 13 Jun 2019 20:13:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZuPth7El; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726765AbfFNDNp (ORCPT + 14 others); Thu, 13 Jun 2019 23:13:45 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:39769 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726705AbfFNDNp (ORCPT ); Thu, 13 Jun 2019 23:13:45 -0400 Received: by mail-pf1-f196.google.com with SMTP id j2so494706pfe.6 for ; Thu, 13 Jun 2019 20:13:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kulBovnYLz4YjgSJ0sOniJhX8Qcc8ljUXoag6+mJQMI=; b=ZuPth7El82cfeoWv8qXI0kULOoymbsqUIM1ht3vdgKpkGkPrBhXQjROt8Y46oqOOZN NW0wSdYyeYqZbWOn8EkbIGVulRgHXgcl8gWsNQFY5Ho5YsDuostC4jlQrdPSLMXql821 uIPnibCnCusSMq9GlFaiDZs7zRIL5CXUIWhDrasfXcSXkC/b5kIdkIu3IJXUoBJI5D9m 72+PNQK90lICef7SjkbVshOMWasZqTLV07YKmMK9uetNJrv+ZQGx4PZmsbyGy5FJyYxH nN5PgAknmx1xcU9tLut4myAh+yT9NN1ZatTB4RArnw5pHuc+UhsIfPdarUdobDXL18LY HfcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kulBovnYLz4YjgSJ0sOniJhX8Qcc8ljUXoag6+mJQMI=; b=Li6blahh0b4kYoWtV1lQ1k65hki3c4GWhT8g1OK53hvwBACA/vD6N+JrMOVwbvOp2y xkeBxjMrB6M83FLlWrpP/mieDEECIBy98lcbpWe33FAAwclIUpAOokbxaux44PrGuKLj 6us9rMzG3fTWBjdJDPcJaSNt8sVAkHn1mL5Svatmzi652wfki2qC4Nx3bkT4xBeWatkZ cgPIYT//hrcPuqBbFG3EvKA/Z0n6LkSLxIxasCKAlPn5CpjJKNdnDOe21MLO0d1+CEVy Z1zrSATtn4swANRjGiLDETi1iJx255Yxzc2UzKjbmofNtcKzpZDITeBfKl7UzTgg6Tto 8bwQ== X-Gm-Message-State: APjAAAVuyzyMdpBNPsZnUCyUSa93IKXZqLc8MmsmET/o2YMTmcs4l5kE EU65XCR/fHhWz1IJgj2WSZ3hmQ== X-Received: by 2002:a63:6ecf:: with SMTP id j198mr20165303pgc.437.1560482024157; Thu, 13 Jun 2019 20:13:44 -0700 (PDT) Received: from localhost ([122.172.66.84]) by smtp.gmail.com with ESMTPSA id l44sm1270624pje.29.2019.06.13.20.13.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jun 2019 20:13:43 -0700 (PDT) From: Viresh Kumar To: linux-arm-kernel@lists.infradead.org, Julien Thierry Cc: Viresh Kumar , stable@vger.kernel.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 42/45] arm/arm64: smccc: Implement SMCCC v1.1 inline primitive Date: Fri, 14 Jun 2019 08:38:25 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit f2d3b2e8759a5833df6f022e42df2d581e6d843c upstream. One of the major improvement of SMCCC v1.1 is that it only clobbers the first 4 registers, both on 32 and 64bit. This means that it becomes very easy to provide an inline version of the SMC call primitive, and avoid performing a function call to stash the registers that would otherwise be clobbered by SMCCC v1.0. Reviewed-by: Robin Murphy Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- include/linux/arm-smccc.h | 141 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 141 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index 4c45fd75db5d..60c2ad6316d8 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -122,5 +122,146 @@ asmlinkage void arm_smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a5, unsigned long a6, unsigned long a7, struct arm_smccc_res *res); +/* SMCCC v1.1 implementation madness follows */ +#ifdef CONFIG_ARM64 + +#define SMCCC_SMC_INST "smc #0" +#define SMCCC_HVC_INST "hvc #0" + +#elif defined(CONFIG_ARM) +#include +#include + +#define SMCCC_SMC_INST __SMC(0) +#define SMCCC_HVC_INST __HVC(0) + +#endif + +#define ___count_args(_0, _1, _2, _3, _4, _5, _6, _7, _8, x, ...) x + +#define __count_args(...) \ + ___count_args(__VA_ARGS__, 7, 6, 5, 4, 3, 2, 1, 0) + +#define __constraint_write_0 \ + "+r" (r0), "=&r" (r1), "=&r" (r2), "=&r" (r3) +#define __constraint_write_1 \ + "+r" (r0), "+r" (r1), "=&r" (r2), "=&r" (r3) +#define __constraint_write_2 \ + "+r" (r0), "+r" (r1), "+r" (r2), "=&r" (r3) +#define __constraint_write_3 \ + "+r" (r0), "+r" (r1), "+r" (r2), "+r" (r3) +#define __constraint_write_4 __constraint_write_3 +#define __constraint_write_5 __constraint_write_4 +#define __constraint_write_6 __constraint_write_5 +#define __constraint_write_7 __constraint_write_6 + +#define __constraint_read_0 +#define __constraint_read_1 +#define __constraint_read_2 +#define __constraint_read_3 +#define __constraint_read_4 "r" (r4) +#define __constraint_read_5 __constraint_read_4, "r" (r5) +#define __constraint_read_6 __constraint_read_5, "r" (r6) +#define __constraint_read_7 __constraint_read_6, "r" (r7) + +#define __declare_arg_0(a0, res) \ + struct arm_smccc_res *___res = res; \ + register u32 r0 asm("r0") = a0; \ + register unsigned long r1 asm("r1"); \ + register unsigned long r2 asm("r2"); \ + register unsigned long r3 asm("r3") + +#define __declare_arg_1(a0, a1, res) \ + struct arm_smccc_res *___res = res; \ + register u32 r0 asm("r0") = a0; \ + register typeof(a1) r1 asm("r1") = a1; \ + register unsigned long r2 asm("r2"); \ + register unsigned long r3 asm("r3") + +#define __declare_arg_2(a0, a1, a2, res) \ + struct arm_smccc_res *___res = res; \ + register u32 r0 asm("r0") = a0; \ + register typeof(a1) r1 asm("r1") = a1; \ + register typeof(a2) r2 asm("r2") = a2; \ + register unsigned long r3 asm("r3") + +#define __declare_arg_3(a0, a1, a2, a3, res) \ + struct arm_smccc_res *___res = res; \ + register u32 r0 asm("r0") = a0; \ + register typeof(a1) r1 asm("r1") = a1; \ + register typeof(a2) r2 asm("r2") = a2; \ + register typeof(a3) r3 asm("r3") = a3 + +#define __declare_arg_4(a0, a1, a2, a3, a4, res) \ + __declare_arg_3(a0, a1, a2, a3, res); \ + register typeof(a4) r4 asm("r4") = a4 + +#define __declare_arg_5(a0, a1, a2, a3, a4, a5, res) \ + __declare_arg_4(a0, a1, a2, a3, a4, res); \ + register typeof(a5) r5 asm("r5") = a5 + +#define __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res) \ + __declare_arg_5(a0, a1, a2, a3, a4, a5, res); \ + register typeof(a6) r6 asm("r6") = a6 + +#define __declare_arg_7(a0, a1, a2, a3, a4, a5, a6, a7, res) \ + __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res); \ + register typeof(a7) r7 asm("r7") = a7 + +#define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__) +#define __declare_args(count, ...) ___declare_args(count, __VA_ARGS__) + +#define ___constraints(count) \ + : __constraint_write_ ## count \ + : __constraint_read_ ## count \ + : "memory" +#define __constraints(count) ___constraints(count) + +/* + * We have an output list that is not necessarily used, and GCC feels + * entitled to optimise the whole sequence away. "volatile" is what + * makes it stick. + */ +#define __arm_smccc_1_1(inst, ...) \ + do { \ + __declare_args(__count_args(__VA_ARGS__), __VA_ARGS__); \ + asm volatile(inst "\n" \ + __constraints(__count_args(__VA_ARGS__))); \ + if (___res) \ + *___res = (typeof(*___res)){r0, r1, r2, r3}; \ + } while (0) + +/* + * arm_smccc_1_1_smc() - make an SMCCC v1.1 compliant SMC call + * + * This is a variadic macro taking one to eight source arguments, and + * an optional return structure. + * + * @a0-a7: arguments passed in registers 0 to 7 + * @res: result values from registers 0 to 3 + * + * This macro is used to make SMC calls following SMC Calling Convention v1.1. + * The content of the supplied param are copied to registers 0 to 7 prior + * to the SMC instruction. The return values are updated with the content + * from register 0 to 3 on return from the SMC instruction if not NULL. + */ +#define arm_smccc_1_1_smc(...) __arm_smccc_1_1(SMCCC_SMC_INST, __VA_ARGS__) + +/* + * arm_smccc_1_1_hvc() - make an SMCCC v1.1 compliant HVC call + * + * This is a variadic macro taking one to eight source arguments, and + * an optional return structure. + * + * @a0-a7: arguments passed in registers 0 to 7 + * @res: result values from registers 0 to 3 + * + * This macro is used to make HVC calls following SMC Calling Convention v1.1. + * The content of the supplied param are copied to registers 0 to 7 prior + * to the HVC instruction. The return values are updated with the content + * from register 0 to 3 on return from the HVC instruction if not NULL. + */ +#define arm_smccc_1_1_hvc(...) __arm_smccc_1_1(SMCCC_HVC_INST, __VA_ARGS__) + #endif /*__ASSEMBLY__*/ #endif /*__LINUX_ARM_SMCCC_H*/ From patchwork Fri Jun 14 03:08:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166781 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1506556ilk; Thu, 13 Jun 2019 20:13:48 -0700 (PDT) X-Google-Smtp-Source: APXvYqwV7tch7p/mzK4elMRZidrUJ8xrCXTXs7ZwFWcVa0iDTBdr6SIW5yfv2dijoNG/5n7zvb+r X-Received: by 2002:a62:b503:: with SMTP id y3mr94613327pfe.4.1560482028639; Thu, 13 Jun 2019 20:13:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560482028; cv=none; d=google.com; s=arc-20160816; b=rI2p5SUy7ZhDdksCKcqtO7dfTN8IHVb68clcOB2akQsWXu+Fim0eg0vbAoN4CfD9Ek qrDURRiLTVg7GFDiOij2IiDiIjUEfRhb9IIFAArqDGgOCLDDl80Jy0WnlRV+zdwyJ5+d D42tsnFzkSTVX/mZCD6Y+hFfkooIKiY4IoZ2vuX53or6Nhr2OFYstsUTcciY3WOU1Hid ZXTjZdWI2nRzZiWgYZcK+zrosEXjXufwkI3y1vgH4hWa2Xq7xzGkW9fzaBDBf3KfIPsD MXFs5KKSE6qe2QH2rx9EI/kLPY17lQp5suCAn/hMz1idrJJsmNk0nbMaQWkQNRwe1Hv6 f1AQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=wEbgFQxZMC6fJD33Waf3N1W37Y6IiBDcFwhvI4lbj2Y=; b=CXSYkQfiKU2tq/JHwjfAOCRKKxtUxr8SwxSauk/MT7PeKW/SeK/TxEp0u6/0k3dIHH bltQsOMkeCm+cnDtZ5plllcBmLmTDt/RslYdMlVJscVfF0c57FJBWcre76JlgJc0zS8b L9J2Li2OQlbjvm89JhTFKfsHw8zSH7euDFbQ4uD+odsOVc1EjH+n+Gl4+bkO2l1O+nxl iAse925joKotWZ3QIllL/j+5tKrgj8Tj/txWmNWo4LiT8s+UCXGe2X+1qiZmXjvTUyzT REunegOwTD0NS2m+Txx6zgjuDavl0wS69JQb/BSMvECqxVKWkOiGbIr4fDqRazgXBhi5 u/Xw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=va81nY0f; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e8si1073936plb.420.2019.06.13.20.13.48; Thu, 13 Jun 2019 20:13:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=va81nY0f; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726766AbfFNDNs (ORCPT + 14 others); Thu, 13 Jun 2019 23:13:48 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:36321 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726705AbfFNDNr (ORCPT ); Thu, 13 Jun 2019 23:13:47 -0400 Received: by mail-pg1-f194.google.com with SMTP id f21so684046pgi.3 for ; Thu, 13 Jun 2019 20:13:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wEbgFQxZMC6fJD33Waf3N1W37Y6IiBDcFwhvI4lbj2Y=; b=va81nY0feP5sEouud+fj3TpaKzUjL4h3DIk3Y1b7M7OpENMdls4SqZdkdcWM/bFwol cxLfuDhb8rkZnov7C4WnONY4NIS2iZUBmdJzyIrOrMeA8QXLsS/GNl/dISGjNzpzu0hr 8Xed6r894iT+aS9xp9BCfqgPhVD1T7k2rfUpWPmiPaash2i7Met8Cq76UosREyYjEd6R HHdrf8pcUZTbcAAWlUUZMbroQmy4mG2l8UQL1tgi0ueNXZIEclvhTKHT6Qx4knFveG2z KvhvLxkLMx7Fj5bYA1GNt/z9CvXFc2HOZ2mmqgFacovro8YrIE3TS5VD1JMmuLw7tlo+ fHxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wEbgFQxZMC6fJD33Waf3N1W37Y6IiBDcFwhvI4lbj2Y=; b=YMmP06tP5aNU4809MKENBXQ37Z8Yn6Is98TQ/UquwD09vL3/mXoJrm+y2uVW9e0wkP ye+3QPZCBbMIiaFe1AXsYDBHFkWAAAQfc0qRqlbT1tEf/4qQP6lXidKEHybvp1Ji3vhn GEsjuX+9Tyf1iPA2NzRPYGmAOxKyZmmMp0qo+nW9dEGTKC+mS0VwxGeTlbznN4iO4RlV vEuzLnkFEXrGJdtsqoUV3/PSKI29Jbfs8eRHKwFCUxcYPaLhUNENkGIOlDtMNBL36pZL UB/CELeoKtlRG4Vz+e16+PXxEhzQ6i1pqOfSMAH0Asx2VjpTvKZuMFmiyVwCIoB2XIW4 FxPA== X-Gm-Message-State: APjAAAWXQZksFMl/60t8TbL4YeE2W6Zxb5m508y7F7sm0evkuZrTQlQr IE13q9gk8HiCoMl/Khie3JumqA== X-Received: by 2002:a65:4209:: with SMTP id c9mr34466210pgq.111.1560482026653; Thu, 13 Jun 2019 20:13:46 -0700 (PDT) Received: from localhost ([122.172.66.84]) by smtp.gmail.com with ESMTPSA id 188sm1042980pfg.11.2019.06.13.20.13.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jun 2019 20:13:46 -0700 (PDT) From: Viresh Kumar To: linux-arm-kernel@lists.infradead.org, Julien Thierry Cc: Viresh Kumar , stable@vger.kernel.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 43/45] arm64: Add ARM_SMCCC_ARCH_WORKAROUND_1 BP hardening support Date: Fri, 14 Jun 2019 08:38:26 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit b092201e0020614127f495c092e0a12d26a2116e upstream. Add the detection and runtime code for ARM_SMCCC_ARCH_WORKAROUND_1. It is lovely. Really. Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/kernel/bpi.S | 20 ++++++++++ arch/arm64/kernel/cpu_errata.c | 68 +++++++++++++++++++++++++++++++++- 2 files changed, 87 insertions(+), 1 deletion(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/bpi.S b/arch/arm64/kernel/bpi.S index dec95bd82e31..c72f261f4b64 100644 --- a/arch/arm64/kernel/bpi.S +++ b/arch/arm64/kernel/bpi.S @@ -17,6 +17,7 @@ */ #include +#include .macro ventry target .rept 31 @@ -77,3 +78,22 @@ ENTRY(__psci_hyp_bp_inval_start) ldp x0, x1, [sp, #(16 * 8)] add sp, sp, #(8 * 18) ENTRY(__psci_hyp_bp_inval_end) + +.macro smccc_workaround_1 inst + sub sp, sp, #(8 * 4) + stp x2, x3, [sp, #(8 * 0)] + stp x0, x1, [sp, #(8 * 2)] + mov w0, #ARM_SMCCC_ARCH_WORKAROUND_1 + \inst #0 + ldp x2, x3, [sp, #(8 * 0)] + ldp x0, x1, [sp, #(8 * 2)] + add sp, sp, #(8 * 4) +.endm + +ENTRY(__smccc_workaround_1_smc_start) + smccc_workaround_1 smc +ENTRY(__smccc_workaround_1_smc_end) + +ENTRY(__smccc_workaround_1_hvc_start) + smccc_workaround_1 hvc +ENTRY(__smccc_workaround_1_hvc_end) diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index da861bf24780..506b339b91bb 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -51,6 +51,10 @@ DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data); #ifdef CONFIG_KVM extern char __psci_hyp_bp_inval_start[], __psci_hyp_bp_inval_end[]; +extern char __smccc_workaround_1_smc_start[]; +extern char __smccc_workaround_1_smc_end[]; +extern char __smccc_workaround_1_hvc_start[]; +extern char __smccc_workaround_1_hvc_end[]; static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start, const char *hyp_vecs_end) @@ -95,6 +99,10 @@ static void __install_bp_hardening_cb(bp_hardening_cb_t fn, #else #define __psci_hyp_bp_inval_start NULL #define __psci_hyp_bp_inval_end NULL +#define __smccc_workaround_1_smc_start NULL +#define __smccc_workaround_1_smc_end NULL +#define __smccc_workaround_1_hvc_start NULL +#define __smccc_workaround_1_hvc_end NULL static void __install_bp_hardening_cb(bp_hardening_cb_t fn, const char *hyp_vecs_start, @@ -121,17 +129,75 @@ static void install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry, __install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end); } +#include +#include #include +static void call_smc_arch_workaround_1(void) +{ + arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL); +} + +static void call_hvc_arch_workaround_1(void) +{ + arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL); +} + +static bool check_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry) +{ + bp_hardening_cb_t cb; + void *smccc_start, *smccc_end; + struct arm_smccc_res res; + + if (!entry->matches(entry, SCOPE_LOCAL_CPU)) + return false; + + if (psci_ops.smccc_version == SMCCC_VERSION_1_0) + return false; + + switch (psci_ops.conduit) { + case PSCI_CONDUIT_HVC: + arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, + ARM_SMCCC_ARCH_WORKAROUND_1, &res); + if (res.a0) + return false; + cb = call_hvc_arch_workaround_1; + smccc_start = __smccc_workaround_1_hvc_start; + smccc_end = __smccc_workaround_1_hvc_end; + break; + + case PSCI_CONDUIT_SMC: + arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, + ARM_SMCCC_ARCH_WORKAROUND_1, &res); + if (res.a0) + return false; + cb = call_smc_arch_workaround_1; + smccc_start = __smccc_workaround_1_smc_start; + smccc_end = __smccc_workaround_1_smc_end; + break; + + default: + return false; + } + + install_bp_hardening_cb(entry, cb, smccc_start, smccc_end); + + return true; +} + static int enable_psci_bp_hardening(void *data) { const struct arm64_cpu_capabilities *entry = data; - if (psci_ops.get_version) + if (psci_ops.get_version) { + if (check_smccc_arch_workaround_1(entry)) + return 0; + install_bp_hardening_cb(entry, (bp_hardening_cb_t)psci_ops.get_version, __psci_hyp_bp_inval_start, __psci_hyp_bp_inval_end); + } return 0; } From patchwork Fri Jun 14 03:08:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 166782 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1506585ilk; Thu, 13 Jun 2019 20:13:51 -0700 (PDT) X-Google-Smtp-Source: APXvYqxLnTGfDSCEu+UxgXXVONMKBe0mb9pEpRuia2O7xXF3xWpLANXz8/3wlW5/1Wfn1kJEQucA X-Received: by 2002:aa7:9a92:: with SMTP id w18mr66719819pfi.167.1560482031746; Thu, 13 Jun 2019 20:13:51 -0700 (PDT) ARC-Seal: i=1; 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Now that we've standardised on SMCCC v1.1 to perform the branch prediction invalidation, let's drop the previous band-aid. If vendors haven't updated their firmware to do SMCCC 1.1, they haven't updated PSCI either, so we don't loose anything. Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas [ v4.4: Dropped switch.c changes ] Signed-off-by: Viresh Kumar --- arch/arm64/kernel/bpi.S | 24 ------------------ arch/arm64/kernel/cpu_errata.c | 45 ++++++++++------------------------ 2 files changed, 13 insertions(+), 56 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/bpi.S b/arch/arm64/kernel/bpi.S index c72f261f4b64..dc4eb154e33b 100644 --- a/arch/arm64/kernel/bpi.S +++ b/arch/arm64/kernel/bpi.S @@ -54,30 +54,6 @@ ENTRY(__bp_harden_hyp_vecs_start) vectors __kvm_hyp_vector .endr ENTRY(__bp_harden_hyp_vecs_end) -ENTRY(__psci_hyp_bp_inval_start) - sub sp, sp, #(8 * 18) - stp x16, x17, [sp, #(16 * 0)] - stp x14, x15, [sp, #(16 * 1)] - stp x12, x13, [sp, #(16 * 2)] - stp x10, x11, [sp, #(16 * 3)] - stp x8, x9, [sp, #(16 * 4)] - stp x6, x7, [sp, #(16 * 5)] - stp x4, x5, [sp, #(16 * 6)] - stp x2, x3, [sp, #(16 * 7)] - stp x0, x1, [sp, #(16 * 8)] - mov x0, #0x84000000 - smc #0 - ldp x16, x17, [sp, #(16 * 0)] - ldp x14, x15, [sp, #(16 * 1)] - ldp x12, x13, [sp, #(16 * 2)] - ldp x10, x11, [sp, #(16 * 3)] - ldp x8, x9, [sp, #(16 * 4)] - ldp x6, x7, [sp, #(16 * 5)] - ldp x4, x5, [sp, #(16 * 6)] - ldp x2, x3, [sp, #(16 * 7)] - ldp x0, x1, [sp, #(16 * 8)] - add sp, sp, #(8 * 18) -ENTRY(__psci_hyp_bp_inval_end) .macro smccc_workaround_1 inst sub sp, sp, #(8 * 4) diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 506b339b91bb..c9a2c5a1e0aa 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -50,7 +50,6 @@ is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope) DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data); #ifdef CONFIG_KVM -extern char __psci_hyp_bp_inval_start[], __psci_hyp_bp_inval_end[]; extern char __smccc_workaround_1_smc_start[]; extern char __smccc_workaround_1_smc_end[]; extern char __smccc_workaround_1_hvc_start[]; @@ -97,8 +96,6 @@ static void __install_bp_hardening_cb(bp_hardening_cb_t fn, spin_unlock(&bp_lock); } #else -#define __psci_hyp_bp_inval_start NULL -#define __psci_hyp_bp_inval_end NULL #define __smccc_workaround_1_smc_start NULL #define __smccc_workaround_1_smc_end NULL #define __smccc_workaround_1_hvc_start NULL @@ -143,24 +140,25 @@ static void call_hvc_arch_workaround_1(void) arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL); } -static bool check_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry) +static int enable_smccc_arch_workaround_1(void *data) { + const struct arm64_cpu_capabilities *entry = data; bp_hardening_cb_t cb; void *smccc_start, *smccc_end; struct arm_smccc_res res; if (!entry->matches(entry, SCOPE_LOCAL_CPU)) - return false; + return 0; if (psci_ops.smccc_version == SMCCC_VERSION_1_0) - return false; + return 0; switch (psci_ops.conduit) { case PSCI_CONDUIT_HVC: arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, ARM_SMCCC_ARCH_WORKAROUND_1, &res); if (res.a0) - return false; + return 0; cb = call_hvc_arch_workaround_1; smccc_start = __smccc_workaround_1_hvc_start; smccc_end = __smccc_workaround_1_hvc_end; @@ -170,35 +168,18 @@ static bool check_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *e arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, ARM_SMCCC_ARCH_WORKAROUND_1, &res); if (res.a0) - return false; + return 0; cb = call_smc_arch_workaround_1; smccc_start = __smccc_workaround_1_smc_start; smccc_end = __smccc_workaround_1_smc_end; break; default: - return false; + return 0; } install_bp_hardening_cb(entry, cb, smccc_start, smccc_end); - return true; -} - -static int enable_psci_bp_hardening(void *data) -{ - const struct arm64_cpu_capabilities *entry = data; - - if (psci_ops.get_version) { - if (check_smccc_arch_workaround_1(entry)) - return 0; - - install_bp_hardening_cb(entry, - (bp_hardening_cb_t)psci_ops.get_version, - __psci_hyp_bp_inval_start, - __psci_hyp_bp_inval_end); - } - return 0; } #endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */ @@ -283,32 +264,32 @@ const struct arm64_cpu_capabilities arm64_errata[] = { { .capability = ARM64_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM64_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM64_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM64_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM64_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM64_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, #endif { From patchwork Fri Jun 14 03:08:28 2019 Content-Type: text/plain; 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The arm64 futex code has some explicit dereferencing of user pointers where performing atomic operations in response to a futex command. This patch uses masking to limit any speculative futex operations to within the user address space. Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/futex.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/futex.h b/arch/arm64/include/asm/futex.h index 34d4d2e2f561..8ab6e83cb629 100644 --- a/arch/arm64/include/asm/futex.h +++ b/arch/arm64/include/asm/futex.h @@ -53,9 +53,10 @@ : "memory") static inline int -arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr) +arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *_uaddr) { int oldval = 0, ret, tmp; + u32 __user *uaddr = __uaccess_mask_ptr(_uaddr); pagefault_disable(); @@ -93,15 +94,17 @@ arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr) } static inline int -futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, +futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *_uaddr, u32 oldval, u32 newval) { int ret = 0; u32 val, tmp; + u32 __user *uaddr; - if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) + if (!access_ok(VERIFY_WRITE, _uaddr, sizeof(u32))) return -EFAULT; + uaddr = __uaccess_mask_ptr(_uaddr); asm volatile("// futex_atomic_cmpxchg_inatomic\n" ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN, CONFIG_ARM64_PAN) " prfm pstl1strm, %2\n"