From patchwork Tue May 30 16:24:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 687410 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 191B6C77B7A for ; Tue, 30 May 2023 16:25:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230131AbjE3QZn (ORCPT ); Tue, 30 May 2023 12:25:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41678 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232468AbjE3QZg (ORCPT ); Tue, 30 May 2023 12:25:36 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E049AF7; Tue, 30 May 2023 09:25:19 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 7593562CAE; Tue, 30 May 2023 16:25:19 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7E44EC433A7; Tue, 30 May 2023 16:25:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1685463918; bh=D5LdQuy2U1gKYvQKSrKbDYGL1yk23EzjPBPT+ECI098=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bWjfsnxvaB+RfXzxYDiyXGeWMTqCxvrahj4YaFI8fmAw77BlSOrbefOWeHFXavAe1 hkK9lGYQ0RJxL4lyP8tLavc0vQ89zVc7fRdklYycUeOHOmtL8wsjz2UvlOLFHYV07y fGOShoT4pNuWZaHUrZN62WOjdZ32pgCLzJYAdMa1mwb1i29iQ3s7TUqnUNvGXJkyW9 Ly3Y3nRcKXFM5T9vVACm/ByrL+rrOfuIT6Mj0NieqaLI7Nw0utwDnAur+l0hmlN1IJ /LkWW/P2zMF6iURvdYxawYU9dTfKGurfX4upoiPajRIabpiYDnSVVzbhEFLt7/t5fN 3Tkgt9gOCXalg== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Konrad Dybcio , Avri Altman , Manivannan Sadhasivam , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vinod Koul Subject: [PATCH v3 04/15] scsi: ufs: dt-bindings: Add SC8180x binding Date: Tue, 30 May 2023 21:54:43 +0530 Message-Id: <20230530162454.51708-5-vkoul@kernel.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230530162454.51708-1-vkoul@kernel.org> References: <20230530162454.51708-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document the UFS HC for SC8180x SoC Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml index c5a06c048389..a3db34f35f4f 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -26,6 +26,7 @@ properties: - qcom,msm8994-ufshc - qcom,msm8996-ufshc - qcom,msm8998-ufshc + - qcom,sc8180x-ufshc - qcom,sc8280xp-ufshc - qcom,sdm845-ufshc - qcom,sm6350-ufshc @@ -105,6 +106,7 @@ allOf: contains: enum: - qcom,msm8998-ufshc + - qcom,sc8280x-ufshc - qcom,sc8280xp-ufshc - qcom,sm8250-ufshc - qcom,sm8350-ufshc From patchwork Tue May 30 16:24:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 687409 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DBE1C7EE31 for ; Tue, 30 May 2023 16:26:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232812AbjE3Q0S (ORCPT ); Tue, 30 May 2023 12:26:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42266 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232611AbjE3Q0E (ORCPT ); Tue, 30 May 2023 12:26:04 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CA934116; Tue, 30 May 2023 09:25:31 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id EC9B162CB9; Tue, 30 May 2023 16:25:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 70DABC433A1; Tue, 30 May 2023 16:25:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1685463922; bh=wAHJlb8lYNyT1QOpxqJtmj6hMsX6F/ImtjxHDEegDEs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=n6wS7xB3wV8wHza/+EHAOo3RJG214r/zbD6xlSY2KXV3UbA/UmkscwD3fgTK1AOIO QPf78LE3zdx3TLniryNFY1vcEdjAM2MfvR1OItcQmFEyqbR2FevXI6Ml8DhaE+AYB1 A4BDvqWV1qQmVm/c6WRSKZLid4Jc8f6vaDrGuGfc6lqQpRRNDvxoHiibieCO/lxQaO dB+KC3XxfmQ5C4Hsrlrd96G+RC9EOQx9RQVhphPi+FUZ/Ne7ALKm4Vx7PN2YDSk9LT Odggk9a2p0GFRrh5Gh/zdQm/hoRBAOMX5UPuao+6aNMcZN+x1wm+zH5OXTm1wGBQyE 12TWY1wkhyqvA== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Konrad Dybcio , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Vinod Koul Subject: [PATCH v3 05/15] dt-bindings: qcom,pdc: Add SC8180x compatible Date: Tue, 30 May 2023 21:54:44 +0530 Message-Id: <20230530162454.51708-6-vkoul@kernel.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230530162454.51708-1-vkoul@kernel.org> References: <20230530162454.51708-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document the compatible for pdc in SC8180X SoC Signed-off-by: Vinod Koul Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml index a106ba6e810b..bed79a0ceac5 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml @@ -30,6 +30,7 @@ properties: - qcom,sa8775p-pdc - qcom,sc7180-pdc - qcom,sc7280-pdc + - qcom,sc8180x-pdc - qcom,sc8280xp-pdc - qcom,sdm845-pdc - qcom,sdx55-pdc From patchwork Tue May 30 16:24:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 687408 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6A1AC7EE39 for ; Tue, 30 May 2023 16:26:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233333AbjE3Q0U (ORCPT ); Tue, 30 May 2023 12:26:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42366 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232876AbjE3Q0L (ORCPT ); Tue, 30 May 2023 12:26:11 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3E2A11A; Tue, 30 May 2023 09:25:35 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 405DB62CEC; Tue, 30 May 2023 16:25:29 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 30C33C433A0; Tue, 30 May 2023 16:25:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1685463928; bh=6hF4nw0YEHTiUKBONURNmKrG4nrmtQLrIeSFVCgSOpM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nCpAKsU0305mi30B5dNcwKgbqgbygqR5hfbn5Co7cBs9PFyHv3WSd/q2TY9P0B9b2 ZhSY8r6wgQV4a2hFdan5DZF09t5q9bFFjHGlHMcg6D51HCamXOJxyl7IfPwq3SOK9Y rDlYmorK9rCQ69+U11gozu9ORSeSEWOTLwqNFj3bhbf2HVnNH0jXENU3pado6Dieag PA4O5gSL0HKYWTbdzae+zg8ybPJF/o/X6hvYkRufQugSyleZl2SYhM/ZhF+fX7H+ms 9LB7x0AW6kw4nelT7WsSzZocfFU/IOvq4i3NbGs1fQyGcRSi8dImGA9Aulwa8CHNT9 XAUpJddwssPqQ== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vinod Koul Subject: [PATCH v3 07/15] arm64: dts: qcom: sc8180x: Add interconnects and lmh Date: Tue, 30 May 2023 21:54:46 +0530 Message-Id: <20230530162454.51708-8-vkoul@kernel.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230530162454.51708-1-vkoul@kernel.org> References: <20230530162454.51708-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This add interconnect nodes and add LMH to sc8180x SoC dtsi Co-developed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 126 ++++++++++++++++++++++++++ 1 file changed, 126 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index e38ea2545654..08f5ad65efd5 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -6,6 +6,8 @@ #include #include +#include +#include #include #include #include @@ -44,6 +46,8 @@ CPU0: cpu@0 { next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -70,6 +74,8 @@ CPU1: cpu@100 { next-level-cache = <&L2_100>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD1>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -93,6 +99,8 @@ CPU2: cpu@200 { next-level-cache = <&L2_200>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD2>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -115,6 +123,8 @@ CPU3: cpu@300 { next-level-cache = <&L2_300>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD3>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -137,6 +147,8 @@ CPU4: cpu@400 { next-level-cache = <&L2_400>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD4>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -159,6 +171,8 @@ CPU5: cpu@500 { next-level-cache = <&L2_500>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD5>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -181,6 +195,8 @@ CPU6: cpu@600 { next-level-cache = <&L2_600>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD6>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -203,6 +219,8 @@ CPU7: cpu@700 { next-level-cache = <&L2_700>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD7>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -476,6 +494,24 @@ scm: scm { }; }; + camnoc_virt: interconnect-camnoc-virt { + compatible = "qcom,sc8180x-camnoc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect-mc-virt { + compatible = "qcom,sc8180x-mc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + qup_virt: interconnect-qup-virt { + compatible = "qcom,sc8180x-qup-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ @@ -743,6 +779,48 @@ gcc: clock-controller@100000 { "sleep_clk"; }; + config_noc: interconnect@1500000 { + compatible = "qcom,sc8180x-config-noc"; + reg = <0 0x01500000 0 0x7400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1620000 { + compatible = "qcom,sc8180x-system-noc"; + reg = <0 0x01620000 0 0x19400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,sc8180x-aggre1-noc"; + reg = <0 0x016e0000 0 0xd080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,sc8180x-aggre2-noc"; + reg = <0 0x01700000 0 0x20000>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + compute_noc: interconnect@1720000 { + compatible = "qcom,sc8180x-compute-noc"; + reg = <0 0x01720000 0 0x7000>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1740000 { + compatible = "qcom,sc8180x-mmss-noc"; + reg = <0 0x01740000 0 0x1c100>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sc8180x-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; @@ -810,6 +888,13 @@ ufs_mem_phy_lanes: phy@1d87400 { }; }; + ipa_virt: interconnect@1e00000 { + compatible = "qcom,sc8180x-ipa-virt"; + reg = <0 0x01e00000 0 0x1000>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; @@ -860,6 +945,13 @@ system-cache-controller@9200000 { interrupts = ; }; + gem_noc: interconnect@9680000 { + compatible = "qcom,sc8180x-gem-noc"; + reg = <0 0x09680000 0 0x58200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sc8180x-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>; @@ -1166,6 +1258,40 @@ rpmhpd_opp_turbo_l1: opp10 { }; }; + osm_l3: interconnect@18321000 { + compatible = "qcom,sc8180x-osm-l3"; + reg = <0 0x18321000 0 0x1400>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; + + lmh@18350800 { + compatible = "qcom,sc8180x-lmh"; + reg = <0 0x18350800 0 0x400>; + interrupts = ; + cpus = <&CPU4>; + qcom,lmh-temp-arm-millicelsius = <65000>; + qcom,lmh-temp-low-millicelsius = <94500>; + qcom,lmh-temp-high-millicelsius = <95000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + lmh@18358800 { + compatible = "qcom,sc8180x-lmh"; + reg = <0 0x18358800 0 0x400>; + interrupts = ; + cpus = <&CPU0>; + qcom,lmh-temp-arm-millicelsius = <65000>; + qcom,lmh-temp-low-millicelsius = <94500>; + qcom,lmh-temp-high-millicelsius = <95000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + cpufreq_hw: cpufreq@18323000 { compatible = "qcom,cpufreq-hw"; reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; From patchwork Tue May 30 16:24:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 687407 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53B6AC7EE2E for ; Tue, 30 May 2023 16:26:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232774AbjE3Q0W (ORCPT ); Tue, 30 May 2023 12:26:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41984 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229668AbjE3Q0O (ORCPT ); Tue, 30 May 2023 12:26:14 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 32514188; Tue, 30 May 2023 09:25:39 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 8180C62CA4; Tue, 30 May 2023 16:25:38 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7510AC433D2; Tue, 30 May 2023 16:25:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1685463937; bh=6XrkPYV5OD0SOPv2HSGcre2+E9eNQqCuaZRz6/NOtlc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=p4USfzS/8osYxoE2XqBhzoRshBfOTgU4KDPAj9PeIxE4845AyhMqHXwZpRXAkGtvY tE/W4q2UKAf+bSPezxs+sWRoYZGQyiStFSGOEGqgOUjn/TaMqynZJSox4X+JG+NGNh z8ja5za7m1u1K1xXu5d5yw60amSe2xezoEsFR2Gvc1eAFJLahuAqpNEeO0LypeBbiV Ob3i0A53urvWcwGSmOgfPgPsJ+9LXzVGVqkZfavaMQ8BJ6KDNyBJb6YBmDWcJd+dWk qQ/a6GfkbdrK8fjS7tUhsEO3cxjhAI/H34uEDQBhLzBbRMlkxoM3ipZLL7uQqaxO5C e3dufb0HC6yXw== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vinod Koul Subject: [PATCH v3 10/15] arm64: dts: qcom: sc8180x: Add PCIe instances Date: Tue, 30 May 2023 21:54:49 +0530 Message-Id: <20230530162454.51708-11-vkoul@kernel.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230530162454.51708-1-vkoul@kernel.org> References: <20230530162454.51708-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This patch adds PCIe instances found on this SoC Co-developed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 429 ++++++++++++++++++++++++++ 1 file changed, 429 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index b50673b7c147..2639f5fb6e39 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -1681,6 +1681,435 @@ mmss_noc: interconnect@1740000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + pcie0: pci@1c00000 { + compatible = "qcom,pcie-sc8180x"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ref", + "tbu"; + + assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; + assigned-clock-rates = <19200000>; + + iommus = <&apps_smmu 0x1d80 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, + <0x100 &apps_smmu 0x1d81 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_0_GDSC>; + + interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + phys = <&pcie0_lane>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie0_phy: phy-wrapper@1c06000 { + compatible = "qcom,sc8180x-qmp-pcie-phy"; + reg = <0 0x1c06000 0 0x1c0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie0_lane: phy@1c06200 { + reg = <0 0x1c06200 0 0x170>, /* tx0 */ + <0 0x1c06400 0 0x200>, /* rx0 */ + <0 0x1c06a00 0 0x1f0>, /* pcs */ + <0 0x1c06600 0 0x170>, /* tx1 */ + <0 0x1c06800 0 0x200>, /* rx1 */ + <0 0x1c06e00 0 0xf4>; /* pcs_com */ + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "pipe0"; + + #clock-cells = <0>; + clock-output-names = "pcie_0_pipe_clk"; + #phy-cells = <0>; + }; + }; + + pcie3: pci@1c08000 { + compatible = "qcom,pcie-sc8180x"; + reg = <0 0x01c08000 0 0x3000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40001000 0 0x1000>, + <0 0x40100000 0 0x100000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config"; + device_type = "pci"; + linux,pci-domain = <3>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_3_PIPE_CLK>, + <&gcc GCC_PCIE_3_AUX_CLK>, + <&gcc GCC_PCIE_3_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_3_SLV_AXI_CLK>, + <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_3_CLKREF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ref", + "tbu"; + + assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>; + assigned-clock-rates = <19200000>; + + iommus = <&apps_smmu 0x1e00 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, + <0x100 &apps_smmu 0x1e01 0x1>; + + resets = <&gcc GCC_PCIE_3_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_3_GDSC>; + + interconnects = <&aggre2_noc MASTER_PCIE_3 0 &mc_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + phys = <&pcie3_lane>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie3_phy: phy-wrapper@1c0c000 { + compatible = "qcom,sc8180x-qmp-pcie-phy"; + reg = <0 0x1c0c000 0 0x1c0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_3_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3_CLKREF_CLK>, + <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_3_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE3_PHY_REFGEN_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie3_lane: phy@1c0c200 { + reg = <0 0x1c0c200 0 0x170>, /* tx0 */ + <0 0x1c0c400 0 0x200>, /* rx0 */ + <0 0x1c0ca00 0 0x1f0>, /* pcs */ + <0 0x1c0c600 0 0x170>, /* tx1 */ + <0 0x1c0c800 0 0x200>, /* rx1 */ + <0 0x1c0ce00 0 0xf4>; /* pcs_com */ + clocks = <&gcc GCC_PCIE_3_PIPE_CLK>; + clock-names = "pipe0"; + + #clock-cells = <0>; + clock-output-names = "pcie_3_pipe_clk"; + #phy-cells = <0>; + }; + }; + + pcie1: pci@1c10000 { + compatible = "qcom,pcie-sc8180x"; + reg = <0 0x01c10000 0 0x3000>, + <0 0x68000000 0 0xf1d>, + <0 0x68000f20 0 0xa8>, + <0 0x68001000 0 0x1000>, + <0 0x68100000 0 0x100000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x68200000 0x0 0x68200000 0x0 0x100000>, + <0x02000000 0x0 0x68300000 0x0 0x68300000 0x0 0x3d00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_1_CLKREF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ref", + "tbu"; + + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates = <19200000>; + + iommus = <&apps_smmu 0x1c80 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>; + + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_1_GDSC>; + + interconnects = <&aggre2_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + phys = <&pcie1_lane>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie1_phy: phy-wrapper@1c16000 { + compatible = "qcom,sc8180x-qmp-pcie-phy"; + reg = <0 0x1c16000 0 0x1c0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_CLKREF_CLK>, + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie1_lane: phy@1c0e200 { + reg = <0 0x1c16200 0 0x170>, /* tx0 */ + <0 0x1c16400 0 0x200>, /* rx0 */ + <0 0x1c16a00 0 0x1f0>, /* pcs */ + <0 0x1c16600 0 0x170>, /* tx1 */ + <0 0x1c16800 0 0x200>, /* rx1 */ + <0 0x1c16e00 0 0xf4>; /* pcs_com */ + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "pipe0"; + #clock-cells = <0>; + clock-output-names = "pcie_1_pipe_clk"; + + #phy-cells = <0>; + }; + }; + + pcie2: pci@1c18000 { + compatible = "qcom,pcie-sc8180x"; + reg = <0 0x01c18000 0 0x3000>, + <0 0x70000000 0 0xf1d>, + <0 0x70000f20 0 0xa8>, + <0 0x70001000 0 0x1000>, + <0 0x70100000 0 0x100000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config"; + device_type = "pci"; + linux,pci-domain = <2>; + bus-range = <0x00 0xff>; + num-lanes = <4>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x70200000 0x0 0x70200000 0x0 0x100000>, + <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, + <&gcc GCC_PCIE_2_AUX_CLK>, + <&gcc GCC_PCIE_2_CFG_AHB_CLK>, + <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_2_SLV_AXI_CLK>, + <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_2_CLKREF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ref", + "tbu"; + + assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; + assigned-clock-rates = <19200000>; + + iommus = <&apps_smmu 0x1d00 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, + <0x100 &apps_smmu 0x1d01 0x1>; + + resets = <&gcc GCC_PCIE_2_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_2_GDSC>; + + interconnects = <&aggre2_noc MASTER_PCIE_2 0 &mc_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + phys = <&pcie2_lane>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie2_phy: phy-wrapper@1c1c000 { + compatible = "qcom,sc8180x-qmp-pcie-phy"; + reg = <0 0x1c1c000 0 0x1c0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_2_CFG_AHB_CLK>, + <&gcc GCC_PCIE_2_CLKREF_CLK>, + <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_2_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie2_lane: phy@1c0e200 { + reg = <0 0x1c1c200 0 0x170>, /* tx0 */ + <0 0x1c1c400 0 0x200>, /* rx0 */ + <0 0x1c1ca00 0 0x1f0>, /* pcs */ + <0 0x1c1c600 0 0x170>, /* tx1 */ + <0 0x1c1c800 0 0x200>, /* rx1 */ + <0 0x1c1ce00 0 0xf4>; /* pcs_com */ + clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; + clock-names = "pipe0"; + + #clock-cells = <0>; + clock-output-names = "pcie_2_pipe_clk"; + + #phy-cells = <0>; + }; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sc8180x-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; From patchwork Tue May 30 16:24:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 687406 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0163EC7EE2E for ; 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d=kernel.org; s=k20201202; t=1685463940; bh=UrnI2ovCkLMUGir6nEl9xb5A7zdP0flUTLe0/qoyl/M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lnY4CQwROOsmn7jqV9BYqCj6JFekyt/y4U20/bPKhPk1wQQeM4xPj8ZCbVuJEqf5B qrRZMmUCL6iIhAVye2DQs4myXN3dljihx9O8GaT7cWrKv1ZpCNl0QvHFIqCm/ZSrjJ bAHJn/fo7/+HfOKBskRp35GEx+DzlE16/z3aDFBWx9knCKplJdLdjW09Zay2mW7Zev f+y3gobmGtWSx7DdSbKG5LEc3fkOCkp1O6dABtQ7YKq+0fgv1aQu7A3nGjQWe784cg iJGtFZzy+RCEPHcwN5YhdtH8IDIGs8V1O6NmLWB6rf7BhLe7h86W2DYrY3yZ2aKaSB 0N1oFE7y1JLRg== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vinod Koul Subject: [PATCH v3 11/15] arm64: dts: qcom: sc8180x: Add remoteprocs, wifi and usb nodes Date: Tue, 30 May 2023 21:54:50 +0530 Message-Id: <20230530162454.51708-12-vkoul@kernel.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230530162454.51708-1-vkoul@kernel.org> References: <20230530162454.51708-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This patch adds remoteprocs, wifi and usb and usb phy nodes for this SoC Co-developed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 355 ++++++++++++++++++++++++++ 1 file changed, 355 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 2639f5fb6e39..c73fb25f5af0 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -2227,6 +2227,198 @@ tlmm: pinctrl@3100000 { wakeup-parent = <&pdc>; }; + remoteproc_mpss: remoteproc@4080000 { + compatible = "qcom,sc8180x-mpss-pas"; + reg = <0x0 0x04080000 0x0 0x4040>; + + interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SC8180X_CX>, + <&rpmhpd SC8180X_MSS>; + power-domain-names = "cx", "mss"; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts = ; + label = "modem"; + qcom,remote-pid = <1>; + mboxes = <&apss_shared 12>; + }; + }; + + remoteproc_cdsp: remoteproc@8300000 { + compatible = "qcom,sc8180x-cdsp-pas"; + reg = <0x0 0x08300000 0x0 0x4040>; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SC8180X_CX>; + power-domain-names = "cx"; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + label = "cdsp"; + qcom,remote-pid = <5>; + mboxes = <&apss_shared 4>; + }; + }; + + usb_prim_hsphy: phy@88e2000 { + compatible = "qcom,sc8180x-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0 0x088e2000 0 0x400>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_sec_hsphy: phy@88e3000 { + compatible = "qcom,sc8180x-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0 0x088e3000 0 0x400>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_prim_qmpphy: phy@88e9000 { + compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; + reg = <0 0x088e9000 0 0x18c>, + <0 0x088e8000 0 0x38>, + <0 0x088ea000 0 0x40>; + reg-names = "reg-base", "dp_com"; + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux", + "ref_clk_src", + "ref", + "com_aux"; + resets = <&gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>, + <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>; + reset-names = "phy", "common"; + + #clock-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + usb_prim_ssphy: usb3-phy@88e9200 { + reg = <0 0x088e9200 0 0x200>, + <0 0x088e9400 0 0x200>, + <0 0x088e9c00 0 0x218>, + <0 0x088e9600 0 0x200>, + <0 0x088e9800 0 0x200>, + <0 0x088e9a00 0 0x100>; + #phy-cells = <0>; + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_prim_phy_pipe_clk_src"; + }; + + usb_prim_dpphy: dp-phy@88ea200 { + reg = <0 0x088ea200 0 0x200>, + <0 0x088ea400 0 0x200>, + <0 0x088eaa00 0 0x200>, + <0 0x088ea600 0 0x200>, + <0 0x088ea800 0 0x200>; + #clock-cells = <1>; + #phy-cells = <0>; + }; + }; + + usb_sec_qmpphy: phy@88ee000 { + compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; + reg = <0 0x088ee000 0 0x18c>, + <0 0x088ed000 0 0x10>, + <0 0x088ef000 0 0x40>; + reg-names = "reg-base", "dp_com"; + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; + clock-names = "aux", + "ref_clk_src", + "ref", + "com_aux"; + resets = <&gcc GCC_USB3_DP_PHY_SEC_BCR>, + <&gcc GCC_USB3_PHY_SEC_BCR>; + reset-names = "phy", "common"; + + #clock-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + usb_sec_ssphy: usb3-phy@88e9200 { + reg = <0 0x088ee200 0 0x200>, + <0 0x088ee400 0 0x200>, + <0 0x088eec00 0 0x218>, + <0 0x088ee600 0 0x200>, + <0 0x088ee800 0 0x200>, + <0 0x088eea00 0 0x100>; + #phy-cells = <0>; + clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_sec_phy_pipe_clk_src"; + }; + + usb_sec_dpphy: dp-phy@88ef200 { + reg = <0 0x088ef200 0 0x200>, + <0 0x088ef400 0 0x200>, + <0 0x088efa00 0 0x200>, + <0 0x088ef600 0 0x200>, + <0 0x088ef800 0 0x200>; + #clock-cells = <1>; + #phy-cells = <0>; + clock-output-names = "qmp_dptx1_phy_pll_link_clk", + "qmp_dptx1_phy_pll_vco_div_clk"; + }; + }; + system-cache-controller@9200000 { compatible = "qcom,sc8180x-llcc"; reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; @@ -2241,6 +2433,112 @@ gem_noc: interconnect@9680000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + usb_prim: usb@a6f8800 { + compatible = "qcom,sc8180x-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "mock_utmi", + "sleep", + "xo"; + resets = <&gcc GCC_USB30_PRIM_BCR>; + power-domains = <&gcc USB30_PRIM_GDSC>; + + interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; + interconnect-names = "usb-ddr", "apps-usb"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + status = "disabled"; + + usb_prim_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xcd00>; + interrupts = ; + iommus = <&apps_smmu 0x140 0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_prim_hsphy>, <&usb_prim_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + usb_sec: usb@a8f8800 { + compatible = "qcom,sc8180x-dwc3", "qcom,dwc3"; + reg = <0 0x0a8f8800 0 0x400>; + + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "mock_utmi", + "sleep", + "xo"; + resets = <&gcc GCC_USB30_SEC_BCR>; + power-domains = <&gcc USB30_SEC_GDSC>; + interrupts = , + , + , + ; + interrupt-names = "hs_phy_irq", "ss_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq"; + + assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; + interconnect-names = "usb-ddr", "apps-usb"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + status = "disabled"; + + usb_sec_dwc3: usb@a800000 { + compatible = "snps,dwc3"; + reg = <0 0x0a800000 0 0xcd00>; + interrupts = ; + iommus = <&apps_smmu 0x160 0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_sec_hsphy>, <&usb_sec_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sc8180x-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>; @@ -2416,6 +2714,39 @@ apps_smmu: iommu@15000000 { }; + remoteproc_adsp: remoteproc@17300000 { + compatible = "qcom,sc8180x-adsp-pas"; + reg = <0x0 0x17300000 0x0 0x4040>; + + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SC8180X_CX>; + power-domain-names = "cx"; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + remoteproc_adsp_glink: glink-edge { + interrupts = ; + label = "lpass"; + qcom,remote-pid = <2>; + mboxes = <&apss_shared 8>; + }; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; interrupt-controller; @@ -2615,6 +2946,30 @@ cpufreq_hw: cpufreq@18323000 { #clock-cells = <1>; }; + wifi: wifi@18800000 { + compatible = "qcom,wcn3990-wifi"; + reg = <0 0x18800000 0 0x800000>; + reg-names = "membase"; + clock-names = "cxo_ref_clk_pin"; + clocks = <&rpmhcc RPMH_RF_CLK2>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + iommus = <&apps_smmu 0x0640 0x1>; + qcom,msa-fixed-perm; + status = "disabled"; + }; + }; + thermal-zones { cpu0-thermal { polling-delay-passive = <250>; From patchwork Tue May 30 16:24:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 687405 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A86AEC7EE2E for ; Tue, 30 May 2023 16:27:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233236AbjE3Q1H (ORCPT ); Tue, 30 May 2023 12:27:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42484 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229722AbjE3Q0S (ORCPT ); Tue, 30 May 2023 12:26:18 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C65A8E5F; Tue, 30 May 2023 09:25:47 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 98C1B62D0D; Tue, 30 May 2023 16:25:47 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8A160C433D2; Tue, 30 May 2023 16:25:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1685463947; bh=rqx3qNTChWEWTS+p87/Ih8VMmHD5EkDjfcHn6CUYSLA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Cbx0mlVxKIDRa3E9GEAO6Ga/LAR/p/cWAxCMYyu9+Ddf8asLbZ/hyoAcDeItgs7Sf HoxQJ+Scjw1Rj/i6bp6su0ri6dffmPZmqBM26L380QquuFHtHMVeMdYqOuUSHqg7Pp u/sELmtlIlUyn2m0d6gSnkJAsTZG3tpI8BQF7yQ1NFvyHAEAynG9zjnenCzsVhHV0/ 551o00yXCvpaFVdjuLzdl1fFyYiV30pCFXDYqXi3H4btS3WCHVLNjgAWM0Iru7L9ts qwIZFopGsHuAbUm/d3Eno5xcApydNPD52792LfwcmIgBpiE62upJ4u++3ReN3bMVvw KIymjj0sZDPfw== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vinod Koul Subject: [PATCH v3 13/15] arm64: dts: qcom: sc8180x: Add pmics Date: Tue, 30 May 2023 21:54:52 +0530 Message-Id: <20230530162454.51708-14-vkoul@kernel.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230530162454.51708-1-vkoul@kernel.org> References: <20230530162454.51708-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org SC8180X based platforms have PM8150, PM8150C, PMC8180 and SMB2351 PMICs, so add these as well Co-developed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul --- arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi | 326 ++++++++++++++++++++ 1 file changed, 326 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi diff --git a/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi new file mode 100644 index 000000000000..8247af01c84a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi @@ -0,0 +1,326 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2023, Linaro Limited + */ + +#include +#include +#include +#include + +/ { + thermal-zones { + pmc8180-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pmc8180_temp>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmc8180c-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pmc8180c_temp>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + pmc8180_0: pmic@0 { + compatible = "qcom,pm8150", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pon: power-on@800 { + compatible = "qcom,pm8916-pon"; + reg = <0x0800>; + pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = ; + + status = "disabled"; + }; + }; + + pmc8180_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pmc8180_adc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pmc8180_adc: adc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + + ref-gnd@0 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "ref_gnd"; + }; + + vref-1p25@1 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "vref_1p25"; + }; + + die-temp@6 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "die_temp"; + }; + }; + + pmc8180_adc_tm: adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + + pmc8180_gpios: gpio@c000 { + compatible = "qcom,pmc8180-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmic@1 { + compatible = "qcom,pmc8180", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; + + pmic@2 { + compatible = "qcom,smb2351", "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + adc@3100 { + compatible = "qcom,spmi-adc-rev2"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + + ref-gnd@0 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "ref_gnd"; + }; + + vref-1p25@1 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "vref_1p25"; + }; + + vcoin@85 { + reg = <0x85>; + qcom,pre-scaling = <1 1>; + label = "vcoin2"; + }; + }; + }; + + pmic@6 { + compatible = "qcom,pm8150c", "qcom,spmi-pmic"; + reg = <0x6 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; + + pmic@8 { + compatible = "qcom,pm8150", "qcom,spmi-pmic"; + reg = <0x8 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; + + pmic@a { + compatible = "qcom,smb2351", "qcom,spmi-pmic"; + reg = <0xa SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + adc@3100 { + compatible = "qcom,spmi-adc-rev2"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + interrupts = <0xa 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + + ref-gnd@0 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "ref_gnd"; + }; + + vref-1p25@1 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "vref_1p25"; + }; + + vcoin@85 { + reg = <0x85>; + qcom,pre-scaling = <1 1>; + label = "vcoin"; + }; + }; + }; + + pmic@4 { + compatible = "qcom,pm8150c", "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + power-on@800 { + compatible = "qcom,pm8916-pon"; + reg = <0x0800>; + + status = "disabled"; + }; + + pmc8180c_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pmc8180c_adc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pmc8180c_adc: adc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + + ref-gnd@0 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "ref_gnd"; + }; + + vref-1p25@1 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "vref_1p25"; + }; + + die-temp@6 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "die_temp"; + }; + }; + + pmc8180c_adc_tm: adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x4 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pmc8180c_gpios: gpio@c000 { + compatible = "qcom,pmc8180c-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmic@5 { + compatible = "qcom,pmc8180c", "qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + + pmc8180c_lpg: lpg { + compatible = "qcom,pmc8180c-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + + status = "disabled"; + }; + }; +}; From patchwork Tue May 30 16:24:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 687404 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AA5FC7EE2E for ; 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d=kernel.org; s=k20201202; t=1685463953; bh=DQJlbIaRxUzhLoeiwqosedaH1XHXalJoWDyse+of4CI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cydra5ADxT90xRPEsVe5EL4qA7nsqeF8RuBi2WAlTq5RHwPC7da3oDlHtzK0mZLwB Ls8lLGORTXyGJJd4NqH5i3F38v3Ld1wP775fstP2PII9KrimkIcubA9Ma11NpzzePv gkheXQ8aNdRiu5GFt+HoJBsSzekyR9pOn/mLFdPAuGmjrEdrfGJVGBR6WTiCtTYYOr VaTA960VAGX7SEA48A0lbOM+f83rzkWrhfdGFAfa0H513fDyogKMXQxbhV2G8vcdd6 qNRrZJKVKHtouuERarqOCk+w2T3HPbN9OH8eRM4Mh8uEnTPg+B1z0NUamNvHjrYlkC 3slkUnq8sZC9g== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vinod Koul Subject: [PATCH v3 15/15] arm64: dts: qcom: sc8180x: Introduce Lenovo Flex 5G Date: Tue, 30 May 2023 21:54:54 +0530 Message-Id: <20230530162454.51708-16-vkoul@kernel.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230530162454.51708-1-vkoul@kernel.org> References: <20230530162454.51708-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Bjorn Andersson Introduce support for the Lenovo Flex 5G laptop, built on the Qualcomm SC8180X platform. Supported peripherals includes keyboard, touchpad, UFS storage, external USB and WiFi. Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 583 ++++++++++++++++++ 2 files changed, 584 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 29bfc13d3425..89faec765eff 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -140,6 +140,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-zombie-nvme-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd-r3.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc8180x-lenovo-flex-5g.dtb dtb-$(CONFIG_ARCH_QCOM) += sc8180x-primus.dtb dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-lenovo-thinkpad-x13s.dtb diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts new file mode 100644 index 000000000000..fe3b366e1435 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -0,0 +1,583 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020-2023, Linaro Limited + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "sc8180x.dtsi" +#include "sc8180x-pmics.dtsi" + +/ { + model = "Lenovo Flex 5G"; + compatible = "lenovo,flex-5g", "qcom,sc8180x"; + + aliases { + serial0 = &uart13; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pmc8180c_lpg 4 1000000>; + enable-gpios = <&pmc8180c_gpios 8 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&bl_pwm_default>; + pinctrl-names = "default"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&hall_int_active_state>; + pinctrl-names = "default"; + + lid { + gpios = <&tlmm 121 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-source; + wakeup-event-action = ; + }; + }; + + reserved-memory { + rmtfs_mem: rmtfs-region@85500000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0x85500000 0x0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; + }; + + wlan_mem: wlan-region@8bc00000 { + reg = <0x0 0x8bc00000 0x0 0x180000>; + no-map; + }; + + mpss_mem: mpss-region@8d800000 { + reg = <0x0 0x8d800000 0x0 0x3000000>; + no-map; + }; + + adsp_mem: adsp-region@90800000 { + reg = <0x0 0x90800000 0x0 0x1c00000>; + no-map; + }; + + gpu_mem: gpu-region@98715000 { + reg = <0x0 0x98715000 0x0 0x2000>; + no-map; + }; + + cdsp_mem: cdsp-region@98900000 { + reg = <0x0 0x98900000 0x0 0x1400000>; + no-map; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_s4a_1p8: pm8150-s4-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmc8180-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s5-supply = <&vph_pwr>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p0>; + + vreg_s5a_2p0: smps5 { + regulator-min-microvolt = <2040000>; + regulator-max-microvolt = <2100000>; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9a_1p3: ldo9 { + regulator-min-microvolt = <1296000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pmc8180c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s6-supply = <&vph_pwr>; + vdd-l2-l3-supply = <&vreg_s6c_1p35>; + vdd-bob-supply = <&vph_pwr>; + + vreg_s6c_1p35: smps6 { + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1372000>; + regulator-initial-mode = ; + }; + + vreg_l3c_1p2: ldo3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l10c_3p3: ldo10 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l11c_3p3: ldo11 { + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3350000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8180-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-l2-l10-supply = <&vreg_bob>; + vdd-l3-l4-l5-l18-supply = <&vreg_s4e_0p98>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5e_2p05>; + vdd-l13-l16-l17-supply = <&vreg_bob>; + + vreg_s4e_0p98: smps4 { + regulator-min-microvolt = <992000>; + regulator-max-microvolt = <992000>; + regulator-initial-mode = ; + }; + + vreg_s5e_2p05: smps5 { + regulator-min-microvolt = <2040000>; + regulator-max-microvolt = <2040000>; + regulator-initial-mode = ; + }; + + vreg_l1e_0p75: ldo1 { + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + regulator-initial-mode = ; + }; + + vreg_l5e_0p88: ldo5 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l7e_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l10e_2p9: ldo10 { + regulator-min-microvolt = <2904000>; + regulator-max-microvolt = <2904000>; + regulator-initial-mode = ; + }; + + vreg_l16e_3p0: ldo16 { + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + }; +}; + +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sc8180x/qcdxkmsuc8180.mbn"; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + + pinctrl-0 = <&i2c1_active>, <&i2c1_hid_active>; + pinctrl-names = "default"; + + status = "okay"; + + hid@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + hid-descr-addr = <0x1>; + + interrupts-extended = <&tlmm 122 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c7 { + clock-frequency = <100000>; + + pinctrl-0 = <&i2c7_active>, <&i2c7_hid_active>; + pinctrl-names = "default"; + + status = "okay"; + + hid@5 { + compatible = "hid-over-i2c"; + reg = <0x5>; + hid-descr-addr = <0x20>; + + interrupts-extended = <&tlmm 37 IRQ_TYPE_LEVEL_LOW>; + }; + + hid@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + hid-descr-addr = <0x20>; + + interrupts-extended = <&tlmm 24 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_edp { + data-lanes = <0 1 2 3>; + + pinctrl-0 = <&edp_hpd_active>; + pinctrl-names = "default"; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + no-hpd; + + backlight = <&backlight>; + + ports { + port { + auo_b140han06_in: endpoint { + remote-endpoint = <&mdss_edp_out>; + }; + }; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + mdss_edp_out: endpoint { + remote-endpoint = <&auo_b140han06_in>; + }; + }; + }; +}; + +&pcie3 { + perst-gpio = <&tlmm 178 GPIO_ACTIVE_LOW>; + wake-gpio = <&tlmm 180 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pcie3_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie3_phy { + vdda-phy-supply = <&vreg_l5e_0p88>; + vdda-pll-supply = <&vreg_l3c_1p2>; + + status = "okay"; +}; + +&pmc8180c_lpg { + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&qupv3_id_2 { + status = "okay"; +}; + +&remoteproc_adsp { + memory-region = <&adsp_mem>; + firmware-name = "qcom/sc8180x/LENOVO/82AK/qcadsp8180.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + memory-region = <&cdsp_mem>; + firmware-name = "qcom/sc8180x/LENOVO/82AK/qccdsp8180.mbn"; + + status = "okay"; +}; + +&remoteproc_mpss { + memory-region = <&mpss_mem>; + firmware-name = "qcom/sc8180x/LENOVO/82AK/qcmpss8180_nm.mbn"; + + status = "okay"; +}; + +&uart13 { + pinctrl-0 = <&uart13_state>; + pinctrl-names = "default"; + + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3998-bt"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l9a_1p3>; + vddch0-supply = <&vreg_l11c_3p3>; + max-speed = <3200000>; + }; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 190 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l10e_2p9>; + vcc-max-microamp = <155000>; + + vccq2-supply = <&vreg_l7e_1p8>; + vccq2-max-microamp = <425000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l5e_0p88>; + vdda-pll-supply = <&vreg_l3c_1p2>; + + status = "okay"; +}; + +&usb_prim_hsphy { + vdda-pll-supply = <&vreg_l5e_0p88>; + vdda18-supply = <&vreg_l12a_1p8>; + vdda33-supply = <&vreg_l16e_3p0>; + + status = "okay"; +}; + +&usb_prim_qmpphy { + vdda-phy-supply = <&vreg_l3c_1p2>; + vdda-pll-supply = <&vreg_l5e_0p88>; + + status = "okay"; +}; + +&usb_prim { + status = "okay"; +}; + +&usb_prim_dwc3 { + dr_mode = "host"; +}; + +&usb_sec_hsphy { + vdda-pll-supply = <&vreg_l5e_0p88>; + vdda18-supply = <&vreg_l12a_1p8>; + vdda33-supply = <&vreg_l16e_3p0>; + + status = "okay"; +}; + +&usb_sec_qmpphy { + vdda-phy-supply = <&vreg_l3c_1p2>; + vdda-pll-supply = <&vreg_l5e_0p88>; + + status = "okay"; +}; + +&usb_sec { + status = "okay"; +}; + +&usb_sec_dwc3 { + dr_mode = "host"; +}; + +&wifi { + memory-region = <&wlan_mem>; + + vdd-0.8-cx-mx-supply = <&vreg_l1e_0p75>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l9a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l11c_3p3>; + vdd-3.3-ch1-supply = <&vreg_l10c_3p3>; + + status = "okay"; +}; + +&xo_board_clk { + clock-frequency = <38400000>; +}; + +/* PINCTRL */ + +&pmc8180c_gpios { + bl_pwm_default: bl-pwm-default-state { + en-pins { + pins = "gpio8"; + function = "normal"; + }; + + pwm-pins { + pins = "gpio10"; + function = "func1"; + }; + }; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <47 4>, <126 4>; + + edp_hpd_active: epd-hpd-active-state { + pins = "gpio10"; + function = "edp_hot"; + }; + + hall_int_active_state: hall-int-active-state { + pins = "gpio121"; + function = "gpio"; + + input-enable; + bias-disable; + }; + + i2c1_active: i2c1-active-state { + pins = "gpio114", "gpio115"; + function = "qup1"; + + bias-pull-up = <1>; + drive-strength = <2>; + }; + + i2c1_hid_active: i2c1-hid-active-state { + pins = "gpio122"; + function = "gpio"; + + input-enable; + bias-pull-up; + drive-strength = <2>; + }; + + i2c7_active: i2c7-active-state { + pins = "gpio98", "gpio99"; + function = "qup7"; + + bias-pull-up; + drive-strength = <2>; + }; + + i2c7_hid_active: i2c7-hid-active-state { + pins = "gpio37", "gpio24"; + function = "gpio"; + + input-enable; + bias-pull-up; + drive-strength = <2>; + }; + + pcie3_default_state: pcie3-default-state { + clkreq-pins { + pins = "gpio179"; + function = "pci_e3"; + bias-pull-up; + }; + + reset-n-pins { + pins = "gpio178"; + function = "gpio"; + + drive-strength = <2>; + output-low; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio180"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; + }; + + uart13_state: uart13-state { + cts-pins { + pins = "gpio43"; + function = "qup13"; + bias-pull-down; + }; + + rts-tx-pins { + pins = "gpio44", "gpio45"; + function = "qup13"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio46"; + function = "qup13"; + bias-pull-up; + }; + }; +};