From patchwork Thu Jun 1 16:38:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 689413 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74DB3C7EE2F for ; Thu, 1 Jun 2023 16:39:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231815AbjFAQjV (ORCPT ); Thu, 1 Jun 2023 12:39:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231761AbjFAQjU (ORCPT ); Thu, 1 Jun 2023 12:39:20 -0400 Received: from mail-pf1-x432.google.com (mail-pf1-x432.google.com [IPv6:2607:f8b0:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED7C3197 for ; Thu, 1 Jun 2023 09:39:18 -0700 (PDT) Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-64fd7723836so754637b3a.1 for ; Thu, 01 Jun 2023 09:39:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685637558; x=1688229558; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0Jhi/SGtXf0zcdn3PGnK3djwXYahz8JQorb98x1QvGk=; b=Xn/NRwPDI6HpANyrkks5fzFEE67qAj4af2lWBD1rDIyt1Ney3dCiXRymzDS+XvX4BL H8LoIHenyRU7nik0zxODlsldTuCR4YC1LEUlt3OF5m2I3kuDj4Ck8rUgfdD2JZ+wld0w OhElSzjGv5SjqZ9zi7OBN3ATZaovvPW2ciW5TIGM0Yez9TIUiU1t2AI0VuZ5oQSOGZpW 4WJcNqhFb4C1PHmxBq/dGXNfA+MJ+/T6rcczqUHeyXhPXOXSLAviFY5ryesSFB5JOoJ8 XHNLGQ8uIqLGDE5tRp/i/tJdbo9VpaGLi+oTDDQUwInTG+sGy1Ab0QQy2VCo0gTH+WPd hU2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685637558; x=1688229558; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0Jhi/SGtXf0zcdn3PGnK3djwXYahz8JQorb98x1QvGk=; b=SioN0OP5nLhhaLA77XbdfVNdADKh0GxYPlLLyAeHHUXr+T5zp8R75Ee2r6ILKcEb81 p8FFmgkeIOrNbqpzU8qgD67gwoQXLoJHQmXerBV3C36ebMkxO4uNQ6HMa508RMw5grVy w0eA9QqnhJMnq7NCSSa2wQHejRMSmURVVLuntFgz/J3GmkdpLluVY9TwGsIJExEJtW6F ZAF5mXZNTJx3ytZyu1EGc04taq0dtwObrArROREX5F0ySr2x8VE7/Th5jGLFmnTP13Zs wgcN+kJoh1hUKoN+cnK/YUGJBqW/FIxHej+ruomweu14RUnOW8o436yCFrwGsw1fVRSU z+Xg== X-Gm-Message-State: AC+VfDyVYktDl3PeGifK9NAo0JndpD0QjVd5/4J5j0DMyJJxvdUIP7b/ RADHkaA5/KEMTZWLEkjcPTcf X-Google-Smtp-Source: ACHHUZ4c81XxdaW+VFcaYDhF2yAW5EiYmmmxUGAvQerboA7m2X50pNmd0SYbpzZj6NcB4i02zQs2rg== X-Received: by 2002:a05:6a00:15ca:b0:64f:e997:50fc with SMTP id o10-20020a056a0015ca00b0064fe99750fcmr8711274pfu.2.1685637558349; Thu, 01 Jun 2023 09:39:18 -0700 (PDT) Received: from localhost.localdomain ([117.217.186.123]) by smtp.gmail.com with ESMTPSA id a9-20020aa78649000000b0064f83595bbcsm5273630pfo.58.2023.06.01.09.39.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Jun 2023 09:39:17 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com, Manivannan Sadhasivam , Dmitry Baryshkov Subject: [PATCH v3 1/8] PCI: qcom: Use DWC helpers for modifying the read-only DBI registers Date: Thu, 1 Jun 2023 22:08:53 +0530 Message-Id: <20230601163900.15500-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230601163900.15500-1-manivannan.sadhasivam@linaro.org> References: <20230601163900.15500-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org DWC core already exposes dw_pcie_dbi_ro_wr_{en/dis} helper APIs for enabling and disabling the write access to read only DBI registers. So let's use them instead of doing it manually. Also, the existing code doesn't disable the write access when it's done. This is also fixed now. Fixes: 5d76117f070d ("PCI: qcom: Add support for IPQ8074 PCIe controller") Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 4ab30892f6ef..01795ee7ce45 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -61,7 +61,6 @@ /* DBI registers */ #define AXI_MSTR_RESP_COMP_CTRL0 0x818 #define AXI_MSTR_RESP_COMP_CTRL1 0x81c -#define MISC_CONTROL_1_REG 0x8bc /* MHI registers */ #define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04 @@ -132,9 +131,6 @@ /* AXI_MSTR_RESP_COMP_CTRL1 register fields */ #define CFG_BRIDGE_SB_INIT BIT(0) -/* MISC_CONTROL_1_REG register fields */ -#define DBI_RO_WR_EN 1 - /* PCI_EXP_SLTCAP register fields */ #define PCIE_CAP_SLOT_POWER_LIMIT_VAL FIELD_PREP(PCI_EXP_SLTCAP_SPLV, 250) #define PCIE_CAP_SLOT_POWER_LIMIT_SCALE FIELD_PREP(PCI_EXP_SLTCAP_SPLS, 1) @@ -826,7 +822,9 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) writel(0, pcie->parf + PARF_Q2A_FLUSH); writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND); - writel(DBI_RO_WR_EN, pci->dbi_base + MISC_CONTROL_1_REG); + + dw_pcie_dbi_ro_wr_en(pci); + writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); @@ -836,6 +834,8 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + PCI_EXP_DEVCTL2); + dw_pcie_dbi_ro_wr_dis(pci); + return 0; } From patchwork Thu Jun 1 16:38:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 687792 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 570C8C77B7E for ; Thu, 1 Jun 2023 16:39:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231844AbjFAQjb (ORCPT ); Thu, 1 Jun 2023 12:39:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54414 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231213AbjFAQj3 (ORCPT ); Thu, 1 Jun 2023 12:39:29 -0400 Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F49C19A for ; Thu, 1 Jun 2023 09:39:23 -0700 (PDT) Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-65242634690so249058b3a.0 for ; Thu, 01 Jun 2023 09:39:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685637562; x=1688229562; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KnYTPbLQMWkMCSqucReygW86UFXzEWRo6n6RYpHSl6Q=; b=wBzO85j2VUs9YE2cSVZyHuuo6cJgjcFFmWfUvTqI0j03fYivOlmMQ0LUG54ux43OkI YX2IM7GvQoBOyrdcJ6+WLeCNU92B5P7+zTZfu3T84UNy15g3EQeqYr6n7NrPSrpjEWI7 uc5Cg/Ropok7Dzj/CSBJva9AnzFYzsIcvVPQiUN5cAf8mK5G8o05Q31BLPO0bA0rgJRz Ez62Tzxe/0uXDbeJ+noflCx5tH47XEOQLu7jE9Mm2tXBqbxX4Gb8mCe/mwPhwa3uKDLG gCqA6/sFEgneY2tp8vT29T5h5tb7A+/7o+1PEKeHuPFy+6WHQHaJjaGk5/hze40aI4xQ n21w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685637562; x=1688229562; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KnYTPbLQMWkMCSqucReygW86UFXzEWRo6n6RYpHSl6Q=; b=eilzaWO4Khl4beN8iSCoXEsioOBaY9Pj4O2ex+QmN3ImhH990XQSeKKF2huRDeVSvL wQUdY1YdAmYrZQPua73uHSN4agXzPhBtAC8mAcU+a9O5ZRB+tE0FUIA6bfIC5iOTpjiJ 60HPvu6QQgppdWxjSgnFWrQzQuqLDwDqYBCX7IlZYJQoeER21AFodAUuxQ8MNoeS20N4 eq6XK5mapnXh65TLrZltuIcf5zVMjVB8o2HaZt2LrQfitAfkkYq77s9TJ6KMPqbp95bz Dy7MWKqnFVPH1NfgqLrBCGJax4DtxP1zsNXFSuadboks07KLhFTEQc6Zxoeg5jDo+mhg Ws2w== X-Gm-Message-State: AC+VfDzwKvlVtabG1kEzEhjL3yLQ3VySdB8+m992veMmnjxyioOJ5h/t FBxSKzWpspCNNUVaxh3RafT5 X-Google-Smtp-Source: ACHHUZ7GGUssnqY3zrsliP+PpnBqOwj5ZWl9h6filq5WyYsAf+Pa3qWRDc/MTA7S3oORNC1o9xF9MQ== X-Received: by 2002:a05:6a00:1594:b0:64f:daa6:3e3f with SMTP id u20-20020a056a00159400b0064fdaa63e3fmr9799969pfk.5.1685637562607; Thu, 01 Jun 2023 09:39:22 -0700 (PDT) Received: from localhost.localdomain ([117.217.186.123]) by smtp.gmail.com with ESMTPSA id a9-20020aa78649000000b0064f83595bbcsm5273630pfo.58.2023.06.01.09.39.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Jun 2023 09:39:22 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com, Manivannan Sadhasivam , Dmitry Baryshkov Subject: [PATCH v3 2/8] PCI: qcom: Disable write access to read only registers for IP v2.9.0 Date: Thu, 1 Jun 2023 22:08:54 +0530 Message-Id: <20230601163900.15500-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230601163900.15500-1-manivannan.sadhasivam@linaro.org> References: <20230601163900.15500-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In the post init sequence of v2.9.0, write access to read only registers are not disabled after updating the registers. Fix it by disabling the access after register update. While at it, let's also add a newline after existing dw_pcie_dbi_ro_wr_en() guard function to align with rest of the driver. Fixes: 0cf7c2efe8ac ("PCI: qcom: Add IPQ60xx support") Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 01795ee7ce45..391a45d1e70a 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1136,6 +1136,7 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) writel(0, pcie->parf + PARF_Q2A_FLUSH); dw_pcie_dbi_ro_wr_en(pci); + writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); @@ -1145,6 +1146,8 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + PCI_EXP_DEVCTL2); + dw_pcie_dbi_ro_wr_dis(pci); + for (i = 0; i < 256; i++) writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i)); From patchwork Thu Jun 1 16:38:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 689412 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8ED66C7EE2A for ; Thu, 1 Jun 2023 16:39:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231890AbjFAQjf (ORCPT ); Thu, 1 Jun 2023 12:39:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231817AbjFAQjb (ORCPT ); Thu, 1 Jun 2023 12:39:31 -0400 Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 324B71B6 for ; Thu, 1 Jun 2023 09:39:27 -0700 (PDT) Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-651e298be3fso412773b3a.2 for ; Thu, 01 Jun 2023 09:39:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685637566; x=1688229566; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=A98UhrwZrGyc1cxKVoW5P/FDL2aF5ZgMxYnhHsr36+Y=; b=E7xVyLHQEdy1sSoqFHt0HUgu8+COuY0AzCKFK6QQr62Nd6kEIzEpLYdGCiMj004Xr5 Tczl3YZWm+mq8crwTMdQeCOXZXe8mgwJZMTnX6t4kROowySzF4JUZBdKlix1+ZBxbie7 S+TLh/1nfdEmtHeG1he8XJtpCnf/ioZtHhj+OV5eWnEUMXIHpOjPx6nLhg0sNrgJi3iB tOnCEcimDhG5GDUz4Id2tDsT0I2as79N5RurfCNVK1Cn7kg42C2UCN2wVU1UMTQmknfA fogPEnz3//Wdtkrh1LdmBJ5iv3OHuSYdd2rbo7YNkc5+Ae+QoSjzrkwS9DCHZU+I35j6 MFeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685637566; x=1688229566; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=A98UhrwZrGyc1cxKVoW5P/FDL2aF5ZgMxYnhHsr36+Y=; b=l4P5BTSgJGNqUcE/btX5js61P4GeTKt7Nfm2HxbzE01IJwISOzjIS5TDw0LJsWuH3S USwUdnN0EVwbnEv1m/wrHCRx5YdzwbyPlYHPoPhkGkaGkiOHAbqRmfiZcPouQescSJYg WcPKC3uyJW5bU41sKWfpWWf8ue9fd10ieO7oT2J+9txdbPRn+YOKTEER+Q9cfsIRkREX G3C835HRMAuYIyVTh/x0FK7LK+lzjILei/edNyXAFnHGAH4zSJCh8zuCU2nxizea65Wx NH29knTfvTbfCN/2ROYnMQ6MCiET0ORB43u5L/i1z31wcYFp9AYylh40fxt/Bm73gUZg GHgA== X-Gm-Message-State: AC+VfDzcLwU+N0JTWuYmmhhImUxPYhv75XFJgX0vp/b7uwYbmvClht4x VimSr9Q2z8AqBTaoo7zPB/WQ X-Google-Smtp-Source: ACHHUZ4RassK4Ui4fNJvOZn3BsQzHnJQVBSvkoJ1ZtUxOJq4w0salBur1zhX6ibq6ExfpN48LKBmCA== X-Received: by 2002:a05:6a00:1502:b0:63e:6b8a:7975 with SMTP id q2-20020a056a00150200b0063e6b8a7975mr12102776pfu.9.1685637566626; Thu, 01 Jun 2023 09:39:26 -0700 (PDT) Received: from localhost.localdomain ([117.217.186.123]) by smtp.gmail.com with ESMTPSA id a9-20020aa78649000000b0064f83595bbcsm5273630pfo.58.2023.06.01.09.39.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Jun 2023 09:39:26 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com, Manivannan Sadhasivam , Dmitry Baryshkov Subject: [PATCH v3 3/8] PCI: qcom: Do not advertise hotplug capability for IPs v2.7.0 and v1.9.0 Date: Thu, 1 Jun 2023 22:08:55 +0530 Message-Id: <20230601163900.15500-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230601163900.15500-1-manivannan.sadhasivam@linaro.org> References: <20230601163900.15500-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org SoCs making use of Qcom PCIe controller IPs v2.7.0 and v1.9.0 do not support hotplug functionality. But the hotplug capability bit is set by default in the hardware. This causes the kernel PCI core to register hotplug service for the controller and send hotplug commands to it. But those commands will timeout generating messages as below during boot and suspend/resume. [ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2020 msec ago) [ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2048 msec ago) [ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2020 msec ago) [ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2052 msec ago) This not only spams the console output but also induces a delay of a couple of seconds. To fix this issue, let's clear the HPC bit in PCI_EXP_SLTCAP register as a part of the post init sequence to not advertise the hotplug capability for the controller. Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 391a45d1e70a..8f448156eccc 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -270,6 +270,20 @@ static int qcom_pcie_start_link(struct dw_pcie *pci) return 0; } +static void qcom_pcie_clear_hpc(struct dw_pcie *pci) +{ + u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u32 val; + + dw_pcie_dbi_ro_wr_en(pci); + + val = readl(pci->dbi_base + offset + PCI_EXP_SLTCAP); + val &= ~PCI_EXP_SLTCAP_HPC; + writel(val, pci->dbi_base + offset + PCI_EXP_SLTCAP); + + dw_pcie_dbi_ro_wr_dis(pci); +} + static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie) { u32 val; @@ -966,6 +980,13 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) return ret; } +static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) +{ + qcom_pcie_clear_hpc(pcie->pci); + + return 0; +} + static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; @@ -1272,6 +1293,7 @@ static const struct qcom_pcie_ops ops_2_3_3 = { static const struct qcom_pcie_ops ops_2_7_0 = { .get_resources = qcom_pcie_get_resources_2_7_0, .init = qcom_pcie_init_2_7_0, + .post_init = qcom_pcie_post_init_2_7_0, .deinit = qcom_pcie_deinit_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, }; @@ -1280,6 +1302,7 @@ static const struct qcom_pcie_ops ops_2_7_0 = { static const struct qcom_pcie_ops ops_1_9_0 = { .get_resources = qcom_pcie_get_resources_2_7_0, .init = qcom_pcie_init_2_7_0, + .post_init = qcom_pcie_post_init_2_7_0, .deinit = qcom_pcie_deinit_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, .config_sid = qcom_pcie_config_sid_1_9_0, From patchwork Thu Jun 1 16:38:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 687791 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09E6AC77B7A for ; Thu, 1 Jun 2023 16:39:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231166AbjFAQjp (ORCPT ); Thu, 1 Jun 2023 12:39:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54414 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231831AbjFAQjh (ORCPT ); Thu, 1 Jun 2023 12:39:37 -0400 Received: from mail-pg1-x536.google.com (mail-pg1-x536.google.com [IPv6:2607:f8b0:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C761184 for ; Thu, 1 Jun 2023 09:39:31 -0700 (PDT) Received: by mail-pg1-x536.google.com with SMTP id 41be03b00d2f7-53fb64b3368so564366a12.0 for ; Thu, 01 Jun 2023 09:39:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685637571; x=1688229571; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yzV1ZtX30jIpTNOGlDajFE+kq9Q8oevaq3YwpxK0i1A=; b=D+wcQzBeTbYTHWlZSm0qieGBvVgH+9eec35aDr7jm1X+DPUNgAodL/jJQRfmH14w1G 5IKKjNbSifFMI2aN9uz4ncyxUkmF54jbIhlPGn8Vz0BDlLrh4OV4J5z/DSgEabWLDb+m kPyOvvnDZ+oW3yC8Obc+QPfrq7D7txM4gYEpZ0Ol6oS+PvsDBUZuz6bUhrDd20x7RzyE K+eKl6SGOwhdbr+MXvviHpTCi5QdWskCsqBSoY7fChNVHFmhxfeXsI4BVUVRUloyaz+p qYcCQ6Ieowk0rhvQ4AI4uyQVaoqRelhm3UhFTNQh3d0hkic5c2udq/FKN4dHggR4Hwyj MBBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685637571; x=1688229571; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yzV1ZtX30jIpTNOGlDajFE+kq9Q8oevaq3YwpxK0i1A=; b=ckbzBjlWj50K9IipBQNyIQ+nxnMKBpdFW/9dVQT2HwDZyu3cnq2Gh9BtbCzT12pXiw ZjjvPjfCsJ22rnD1pzoZZFYkUTA9IAJgXVIMeHvrt21AAqRLjs9+A353+P6KEW1LQYOi dnOGdrY8tApyiezEFHQDxmU9XTUN2+yxe77RMakmjzDWLTDAkoJVNtSuqlgKBI5m8rHT 7MY9bgybzt6zr5IKhyPD4/Ma5oRmVXlS1h9ioo8xkcXLtiv3MdUgLYUQvOQ5XqW0ePgF Vt+mcnnzuzFzIcmc2/lCgZ7mjJrFRI0X6FWcK+Bi+mP+jMBV7V1fmOdQwPkCRWHneEcB JQkw== X-Gm-Message-State: AC+VfDxq6bnFOk6yl3uz9414o95lvtmNdBsBNPxp+InsRVAvcQUO2jq+ 5kfNvHKLjdkzxqzCr8/1lstR X-Google-Smtp-Source: ACHHUZ4Jx8wtnSM84R9/MxZJSKPCYzukItjK/PIpjZjyIfvlM7fUGSVPHnGzfLuRrzq47Y9srH93/Q== X-Received: by 2002:a05:6a20:7345:b0:10c:1076:ff69 with SMTP id v5-20020a056a20734500b0010c1076ff69mr8049876pzc.48.1685637570874; Thu, 01 Jun 2023 09:39:30 -0700 (PDT) Received: from localhost.localdomain ([117.217.186.123]) by smtp.gmail.com with ESMTPSA id a9-20020aa78649000000b0064f83595bbcsm5273630pfo.58.2023.06.01.09.39.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Jun 2023 09:39:30 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com, Manivannan Sadhasivam , Dmitry Baryshkov Subject: [PATCH v3 4/8] PCI: qcom: Do not advertise hotplug capability for IPs v2.3.3 and v2.9.0 Date: Thu, 1 Jun 2023 22:08:56 +0530 Message-Id: <20230601163900.15500-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230601163900.15500-1-manivannan.sadhasivam@linaro.org> References: <20230601163900.15500-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org SoCs making use of Qcom PCIe controller IPs v2.3.3 and v2.9.0 do not support hotplug functionality. But the hotplug capability bit is set by default in the hardware. This causes the kernel PCI core to register hotplug service for the controller and send hotplug commands to it. But those commands will timeout generating messages as below during boot and suspend/resume. [ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2020 msec ago) [ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2048 msec ago) [ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2020 msec ago) [ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2052 msec ago) This not only spams the console output but also induces a delay of a couple of seconds. To fix this issue, let's not set the HPC bit in PCI_EXP_SLTCAP register as a part of the post init sequence to not advertise the hotplug capability for the controller. Tested-by: Sricharan Ramabadhran Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 8f448156eccc..64b6a8c6a99d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -140,7 +140,6 @@ PCI_EXP_SLTCAP_AIP | \ PCI_EXP_SLTCAP_PIP | \ PCI_EXP_SLTCAP_HPS | \ - PCI_EXP_SLTCAP_HPC | \ PCI_EXP_SLTCAP_EIP | \ PCIE_CAP_SLOT_POWER_LIMIT_VAL | \ PCIE_CAP_SLOT_POWER_LIMIT_SCALE) From patchwork Thu Jun 1 16:38:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 687789 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D45FC77B7A for ; Thu, 1 Jun 2023 16:40:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232009AbjFAQk2 (ORCPT ); Thu, 1 Jun 2023 12:40:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55306 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232005AbjFAQkU (ORCPT ); Thu, 1 Jun 2023 12:40:20 -0400 Received: from mail-pf1-x42c.google.com (mail-pf1-x42c.google.com [IPv6:2607:f8b0:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DC7CAE5D for ; Thu, 1 Jun 2023 09:39:51 -0700 (PDT) Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-652a6cf1918so4b3a.1 for ; Thu, 01 Jun 2023 09:39:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685637574; x=1688229574; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ltCiTsDOD5ydUGLVe1beQMJS2WLXn803YOi09x8rHPs=; b=xxRQyB0umoYR4doJKWn2bRmQyS1b/dVaSXq9Fsga/Zdsnu0iSl1xFY1ixF0mHFVQhW ePRGU+WfpqNtH47KurdQ5NZIjjkpd8N3Ucgx9eDcqb1ClOW58wVqEM6tzWUahYJr0RkR XCxdivA7ir9XpmxhiCSxbIfGnelC0Ul974hGVQN7lo3Q+XaIPTr84eYixV1Bd+oim4eJ pxys22UBlDsjBTArd03E2bpDjVPrI+arhL72P+tj8Mx5mI8thcFLmiAGkHyhGAbR7pjB qkcFIo9RlDfUaNjBleY59vfj8BbcGiYxkiW7nJEGfgJpLa0v01Oe1MzS+zvAQg2LqRbg d4IQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685637574; x=1688229574; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ltCiTsDOD5ydUGLVe1beQMJS2WLXn803YOi09x8rHPs=; b=ZYGURkr7Wadp7+kJyBfynm2m3ZfC2mvc8IaXBZyKAkN181UZd4/Hz4DwHwvutuxCjt MzC6T8rvjUI/2NSEs70OYWpDtg1uqT+5+oECzvWndrhNb63JDFTxMxQY2A2eNEExynUC o3B7p4bnsfUni/TxmpBhs3eAh9hvoWRZswWnYTnpV39g1Hp0a2lcdfiPIo7Nb89Y2W12 u8v079c1yBAKCsXIxa1S+7l7NgjwaXMALaNtOukE6Z4dmYhJcX0U//KYprUSoq01a5Fg duOOp4C727gDxWb2TfPa93nt5C97uD/yMgU8z0/Sb4xhDdsfY1hU995s190qMeP/wsGN 0KZA== X-Gm-Message-State: AC+VfDyMdjcgSRgs7y04NMOc+0LxSdcxfZyav/8qlOPiys9FSNpIeU4w lsJYVHW9UmH7XMoyafOoyvFn X-Google-Smtp-Source: ACHHUZ7byDbzjNm8+urxPBG4an1LcDKnIV7vixubuE2mGJxqEjQYKFlNo+gcyvoJE0uxn4ylXwgA5Q== X-Received: by 2002:a05:6a20:3d0f:b0:10f:9317:153a with SMTP id y15-20020a056a203d0f00b0010f9317153amr7926215pzi.62.1685637574709; Thu, 01 Jun 2023 09:39:34 -0700 (PDT) Received: from localhost.localdomain ([117.217.186.123]) by smtp.gmail.com with ESMTPSA id a9-20020aa78649000000b0064f83595bbcsm5273630pfo.58.2023.06.01.09.39.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Jun 2023 09:39:34 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v3 5/8] PCI: qcom: Do not advertise hotplug capability for IP v2.3.2 Date: Thu, 1 Jun 2023 22:08:57 +0530 Message-Id: <20230601163900.15500-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230601163900.15500-1-manivannan.sadhasivam@linaro.org> References: <20230601163900.15500-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org SoCs making use of Qcom PCIe controller IP v2.3.2 do not support hotplug functionality. But the hotplug capability bit is set by default in the hardware. This causes the kernel PCI core to register hotplug service for the controller and send hotplug commands to it. But those commands will timeout generating messages as below during boot and suspend/resume. [ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2020 msec ago) [ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2048 msec ago) [ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2020 msec ago) [ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2052 msec ago) This not only spams the console output but also induces a delay of a couple of seconds. To fix this issue, let's clear the HPC bit in PCI_EXP_SLTCAP register as a part of the post init sequence to not advertise the hotplug capability for the controller. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 64b6a8c6a99d..9c8dfd224e6e 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -616,6 +616,8 @@ static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie) val |= EN; writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); + qcom_pcie_clear_hpc(pcie->pci); + return 0; } From patchwork Thu Jun 1 16:38:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 687790 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C1C2C7EE33 for ; Thu, 1 Jun 2023 16:40:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231947AbjFAQkP (ORCPT ); Thu, 1 Jun 2023 12:40:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54504 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232058AbjFAQjw (ORCPT ); Thu, 1 Jun 2023 12:39:52 -0400 Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB4C1E66 for ; Thu, 1 Jun 2023 09:39:39 -0700 (PDT) Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-65242634690so249442b3a.0 for ; Thu, 01 Jun 2023 09:39:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685637579; x=1688229579; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Y/GAaoCJDXRESh8SzkgobGj/lkVGqp4sgMGqg7raF+w=; b=MFrl8aIwFyl9P9P6sQ88C+Ns1uk7i9NttFfh4NLy1N9jaQa7cCPU682EWWRUPqAfvv YaTtDdCRy7k2Bz1OxAgYtFlubz/QRWbOVsL7pPRgyjaUa55D8E49PFa3a2Q07ND5qrtm R6uR5kLSzDSQotQ9X0PBZOyR+pyl23p131nDHMIwS/dn4RW5f1Sqc8qUShZ/Yfef9dw2 +qno9y2PcU0FyzhJYlgy/uTS4Ta7e5nZUwCrvw5YMF0SQuZ7t4HtmNOkbX3FMEA1o+09 f4WtJrlrQYUpsZEJm17PmqB3y+Lvzd2E88Ou/0nu2UfYKdZMMayjdkUHnfmritKNW1Ir bDOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685637579; x=1688229579; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Y/GAaoCJDXRESh8SzkgobGj/lkVGqp4sgMGqg7raF+w=; b=J5eQDd9Hr6c4Gvv3s8T3V7sYrQ7ot31Fp2tHYXvHkcA4KVBztdejVhrH6YX6JML+7t qabbQoSFcOmLhTNHHfoOG72s6CKWwHUOEcVUQUmmf0EdhXqXBgo9xvGNfYzjgbZYhB6T OD+nO07GZSFv5oc4BRQuncnf3+ka+pmMQ100M7Q55RlnQkiRhqcv3cShP9nsIwJhoKjS 1JkDQcQLUxTGAQbLjlDWmrzpWnvhbgGrw74q8eFlSa2KOPhEDQDoSRrHMsTwJmHFjqyx GmlxU8NRIqGgdoprTFbxhTtGGOfwfN/o/OoqWgCxJh0Pqw6fHzppinDdTVA1F2kX4udB TnEg== X-Gm-Message-State: AC+VfDzfJg/5JyGcyylTEDJc5ODG4SdreGGdcnaNUTRurcACDsW53xOi w9t3wRFNFiuqGb4WD5O/wHcG X-Google-Smtp-Source: ACHHUZ75Ddp4Do2qUl/1QIKzYGkkVYKYzywKj2vM5yteB3nk0lRQk+Mx2HxVJNWL99DBCyPPcP9jfA== X-Received: by 2002:a05:6a20:2451:b0:106:c9b7:c92f with SMTP id t17-20020a056a20245100b00106c9b7c92fmr8172553pzc.49.1685637578994; Thu, 01 Jun 2023 09:39:38 -0700 (PDT) Received: from localhost.localdomain ([117.217.186.123]) by smtp.gmail.com with ESMTPSA id a9-20020aa78649000000b0064f83595bbcsm5273630pfo.58.2023.06.01.09.39.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Jun 2023 09:39:38 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com, Manivannan Sadhasivam , Dmitry Baryshkov Subject: [PATCH v3 6/8] PCI: qcom: Use post init sequence of IP v2.3.2 for v2.4.0 Date: Thu, 1 Jun 2023 22:08:58 +0530 Message-Id: <20230601163900.15500-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230601163900.15500-1-manivannan.sadhasivam@linaro.org> References: <20230601163900.15500-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The post init sequence of IP v2.4.0 is same as v2.3.2. So let's reuse the v2.3.2 sequence which now also disables hotplug capability of the controller as it is not at all supported on any SoCs making use of this IP. Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 30 +------------------------- 1 file changed, 1 insertion(+), 29 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 9c8dfd224e6e..e6db9e551752 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -703,34 +703,6 @@ static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie) return 0; } -static int qcom_pcie_post_init_2_4_0(struct qcom_pcie *pcie) -{ - u32 val; - - /* enable PCIe clocks and resets */ - val = readl(pcie->parf + PARF_PHY_CTRL); - val &= ~PHY_TEST_PWR_DOWN; - writel(val, pcie->parf + PARF_PHY_CTRL); - - /* change DBI base address */ - writel(0, pcie->parf + PARF_DBI_BASE_ADDR); - - /* MAC PHY_POWERDOWN MUX DISABLE */ - val = readl(pcie->parf + PARF_SYS_CTRL); - val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN; - writel(val, pcie->parf + PARF_SYS_CTRL); - - val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); - val |= BYPASS; - writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); - - val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); - val |= EN; - writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); - - return 0; -} - static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; @@ -1276,7 +1248,7 @@ static const struct qcom_pcie_ops ops_2_3_2 = { static const struct qcom_pcie_ops ops_2_4_0 = { .get_resources = qcom_pcie_get_resources_2_4_0, .init = qcom_pcie_init_2_4_0, - .post_init = qcom_pcie_post_init_2_4_0, + .post_init = qcom_pcie_post_init_2_3_2, .deinit = qcom_pcie_deinit_2_4_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, }; From patchwork Thu Jun 1 16:38:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 689410 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EAA89C7EE31 for ; Thu, 1 Jun 2023 16:40:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231879AbjFAQkN (ORCPT ); Thu, 1 Jun 2023 12:40:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55058 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232161AbjFAQkA (ORCPT ); Thu, 1 Jun 2023 12:40:00 -0400 Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B67ADE51 for ; Thu, 1 Jun 2023 09:39:43 -0700 (PDT) Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-64f47448aeaso776582b3a.0 for ; Thu, 01 Jun 2023 09:39:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685637583; x=1688229583; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bkQkFXSrqR5MDMbqBcH7Nxin9P2rGGa9soJkqC/yxfY=; b=B341daAOj2uN3XSIUlP1VcnuxzKjCIfk1SWh8pVAtepYMfhkydQ5wmsSXtxJ4mJ8Lf lvBF1ARTk4lwamQZXgAdcZ/Jd7HD4kseHqPognfcSnPBTufXm2GJaN3Rx7NWvPHviPW2 cWEfldgLVniflYncZdFarISJodJymcbJwES66t0ZUWO8nk9HR1bV5ryFVMspTIHQ4UI9 d5+M1huNAlHbh1mOQXTiRRBQY+S6qXmIm0gL3ob0kT+r9tZja4A+6+PUAAWq8BFuEDpt fysNlcxESgrNOSr9YCxNvAa15+3C48zgHETr5q/zYA0F8geyUmEfOeemyEApTuAMg6E5 KDKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685637583; x=1688229583; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bkQkFXSrqR5MDMbqBcH7Nxin9P2rGGa9soJkqC/yxfY=; b=h8sAP+e0LJhu29ujDLzLfPHN488s67tJafS+OcHqthl7UMw8hca0cy8ocTKCxhR13M nkfTS1ssxELo6zAMs88T1DbZM8GCPAo/TAwD0Q3KQIWRGZ0X4oZeJqL05XYSInA6bEj9 PJmnfPv9WSjojaYf4piaXmmoQ6Sv/bxV7AEkon4y/eyrLn2WIiCM9U7FNNpBtuhUum2F rDQZPaaZyGAhAimx4uZGZvgb6qJDToYtmm9XIA7Mlk2efQboR1CEDy2cGxkeY2lG76ic SgJrDqumGcBsPDJ+lwBZwaEHAd17GXNrj8QjkA38dqEB19gOUWMVQsH0naiaBcddTMB3 b0Vw== X-Gm-Message-State: AC+VfDzySuyCGpBhbZ1Fx1leBPBfe54b+jzkWcVUY75kzyZpC6SjkUQK 2/mQoIJCPfqfF/0DpsXuUOlT X-Google-Smtp-Source: ACHHUZ7Pvb3CcXxxu+Wa3w24gX++w34Ip6NVCoreX56/MrrIXw8gaZkOS9sqBqM54jlhghRwgYwhGg== X-Received: by 2002:a05:6a00:986:b0:63b:19e5:a9ec with SMTP id u6-20020a056a00098600b0063b19e5a9ecmr9215482pfg.33.1685637582956; Thu, 01 Jun 2023 09:39:42 -0700 (PDT) Received: from localhost.localdomain ([117.217.186.123]) by smtp.gmail.com with ESMTPSA id a9-20020aa78649000000b0064f83595bbcsm5273630pfo.58.2023.06.01.09.39.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Jun 2023 09:39:42 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v3 7/8] PCI: qcom: Do not advertise hotplug capability for IP v1.0.0 Date: Thu, 1 Jun 2023 22:08:59 +0530 Message-Id: <20230601163900.15500-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230601163900.15500-1-manivannan.sadhasivam@linaro.org> References: <20230601163900.15500-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org SoCs making use of Qcom PCIe controller IP v1.0.0 do not support hotplug functionality. But the hotplug capability bit is set by default in the hardware. This causes the kernel PCI core to register hotplug service for the controller and send hotplug commands to it. But those commands will timeout generating messages as below during boot and suspend/resume. [ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2020 msec ago) [ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2048 msec ago) [ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2020 msec ago) [ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2052 msec ago) This not only spams the console output but also induces a delay of a couple of seconds. To fix this issue, let's clear the HPC bit in PCI_EXP_SLTCAP register as a part of the post init sequence to not advertise the hotplug capability for the controller. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index e6db9e551752..612266fb849a 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -521,6 +521,8 @@ static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie) writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); } + qcom_pcie_clear_hpc(pcie->pci); + return 0; } From patchwork Thu Jun 1 16:39:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 689411 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B85C0C77B7A for ; Thu, 1 Jun 2023 16:40:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231831AbjFAQkM (ORCPT ); Thu, 1 Jun 2023 12:40:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55148 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232319AbjFAQkI (ORCPT ); Thu, 1 Jun 2023 12:40:08 -0400 Received: from mail-pf1-x434.google.com (mail-pf1-x434.google.com [IPv6:2607:f8b0:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D0D451AE for ; Thu, 1 Jun 2023 09:39:47 -0700 (PDT) Received: by mail-pf1-x434.google.com with SMTP id d2e1a72fcca58-65292f79456so107430b3a.2 for ; Thu, 01 Jun 2023 09:39:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685637587; x=1688229587; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BAHgbKUGLDFGyzp+XWYZ2sseIunYBsYQIO/Xldf05CU=; b=ryx0q2tgrm1ZKWtwvRMJ9C4j+popyHn3lXSPJE9WeKkQ8kOC7HrJjfKFRmCDgLK4jz G+xHfxxcaoeujui+lcZ6sPSDA/hrnRZY37AoAlRfbMdJ0mKBg9o1d/Ht6SWrWKvI+/Ob 3AqIkXmgLW7Ow0C11PK9HJ73XCF3XNb3nZKClbX6cAkDj7N8NY4UfuQ1+r1widBM4GBD nlCUvtrR1tVC/L+3NG4elw/3ZxlvASHGYNmD9LVnt2zDOWfuvYnoinrYnEBboea7Stsb AmdQgtgKGiCeC/Ov1oHeEioCI7ba3+dxWO6sZhmjzpca5UywJn/3+LNXabcEui4aSGPM tpOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685637587; x=1688229587; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BAHgbKUGLDFGyzp+XWYZ2sseIunYBsYQIO/Xldf05CU=; b=WsDtJ6385JJ0ptrGQ12CrYqfHVOFuygdkAhTPMI122JlKEGk09Jv37+j2mIFMKsqqq s85XgvJqTprQ34ZHQAawzkaefy1nHYDaM6b/1bTUC8dwgYHLxs8f9+ATyj+hqQSsVbBG BhLj8i19q0beqcHRWk1Ba4K1cIaFsoNkWWsHfzNpnOKD96GtIPkeTjT7lW3qHcRKOaXt Xtdww929PTjuPP4C/TsZWg1hiOLQf75R5L+uV+dXUezc5zDnXZXHvzhf/4mlHqlF2dT9 ilH1C1eMCWymPb6y+oqAyw7Ye43QSngw5MjBYGnPZarNAoqOEBGb6zBvvilejpFVnQkh 24kA== X-Gm-Message-State: AC+VfDyEHsjSiNzsdLu3vlW6TtsDxBD3ooT9dQfsRmxv16EoF0lUxkCO CK2XVKjXIGE6rUVG0pt/V9gb X-Google-Smtp-Source: ACHHUZ77Hvcyy/LhNWPZBGSZ2qUN6+7BPRkk03iorDwp2wOt2Mtg1w9NrwyWpOHSK+Sam8bl4ZhCTw== X-Received: by 2002:a05:6a00:2184:b0:64a:2dd6:4f18 with SMTP id h4-20020a056a00218400b0064a2dd64f18mr7536124pfi.13.1685637586895; Thu, 01 Jun 2023 09:39:46 -0700 (PDT) Received: from localhost.localdomain ([117.217.186.123]) by smtp.gmail.com with ESMTPSA id a9-20020aa78649000000b0064f83595bbcsm5273630pfo.58.2023.06.01.09.39.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Jun 2023 09:39:46 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v3 8/8] PCI: qcom: Do not advertise hotplug capability for IP v2.1.0 Date: Thu, 1 Jun 2023 22:09:00 +0530 Message-Id: <20230601163900.15500-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230601163900.15500-1-manivannan.sadhasivam@linaro.org> References: <20230601163900.15500-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org SoCs making use of Qcom PCIe controller IP v2.1.0 do not support hotplug functionality. But the hotplug capability bit is set by default in the hardware. This causes the kernel PCI core to register hotplug service for the controller and send hotplug commands to it. But those commands will timeout generating messages as below during boot and suspend/resume. [ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2020 msec ago) [ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2048 msec ago) [ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2020 msec ago) [ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2052 msec ago) This not only spams the console output but also induces a delay of a couple of seconds. To fix this issue, let's clear the HPC bit in PCI_EXP_SLTCAP register as a part of the post init sequence to not advertise the hotplug capability for the controller. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 612266fb849a..7a87a47eb7ed 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -438,6 +438,8 @@ static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie) writel(CFG_BRIDGE_SB_INIT, pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL1); + qcom_pcie_clear_hpc(pcie->pci); + return 0; }