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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y17-20020a1c4b11000000b003f7298a32ccsm12195508wma.41.2023.06.06.03.46.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Jun 2023 03:46:10 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Beniamino Galvani , Strahinja Jankovic , Guenter Roeck , qemu-stable@nongnu.org, Michael Tokarev Subject: [PATCH 1/2] hw/intc/allwinner-a10-pic: Handle IRQ levels other than 0 or 1 Date: Tue, 6 Jun 2023 11:46:08 +0100 Message-Id: <20230606104609.3692557-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230606104609.3692557-1-peter.maydell@linaro.org> References: <20230606104609.3692557-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In commit 2c5fa0778c3b430 we fixed an endianness bug in the Allwinner A10 PIC model; however in the process we introduced a regression. This is because the old code was robust against the incoming 'level' argument being something other than 0 or 1, whereas the new code was not. In particular, the allwinner-sdhost code treats its IRQ line as 0-vs-non-0 rather than 0-vs-1, so when the SD controller set its IRQ line for any reason other than transmit the interrupt controller would ignore it. The observed effect was a guest timeout when rebooting the guest kernel. Handle level values other than 0 or 1, to restore the old behaviour. Fixes: 2c5fa0778c3b430 ("hw/intc/allwinner-a10-pic: Don't use set_bit()/clear_bit()") Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Tested-by: Guenter Roeck --- hw/intc/allwinner-a10-pic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c index 4875e68ba6a..d0bf8d545ba 100644 --- a/hw/intc/allwinner-a10-pic.c +++ b/hw/intc/allwinner-a10-pic.c @@ -51,7 +51,7 @@ static void aw_a10_pic_set_irq(void *opaque, int irq, int level) AwA10PICState *s = opaque; uint32_t *pending_reg = &s->irq_pending[irq / 32]; - *pending_reg = deposit32(*pending_reg, irq % 32, 1, level); + *pending_reg = deposit32(*pending_reg, irq % 32, 1, !!level); aw_a10_pic_update(s); } From patchwork Tue Jun 6 10:46:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 689738 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2561778wru; Tue, 6 Jun 2023 03:47:01 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4aVD/FaWop+EXvACZsKZisy3uA21AnY+H333L7i3RdxfTHAzMEz5lGmsaC4k5T9uLt9X72 X-Received: by 2002:a05:6214:19c6:b0:625:b962:30b6 with SMTP id j6-20020a05621419c600b00625b96230b6mr1986591qvc.22.1686048420898; Tue, 06 Jun 2023 03:47:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686048420; cv=none; d=google.com; s=arc-20160816; b=pcKRmxPUNObCBfP4N2pUEFu4mnBpatdM+dHu1+RvBRHHq+mjsIbnPSGLXVprfX0yj7 CXFpMwfCnD1cN/jU+ml6BZoi4LBA2x4N0McYHvoN1jxySxnL1ieUJbQKQtCTC2WZYlyr PCIcsN4DQ8c+glL7OtcPanVbGJZy/euo5LKoCEojsGWce+2/Jcn2jk/hkcWNtQzgpEc2 TKqyy8vj7Zs2ljzGu23hM2WGmPapV/wFtdE5MwZ8NQ91bcBxrYbVOfZvPqlNKuTGhVBG ImGO3GmUY7NnGjbaHUoDdYGhNr3gYBPvlKRR7i2vv0WwUYasRaT9sQiHVSyb58tTV1gs YDwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=wQ8xvQXIw/NPA5OUrBvDh1xgwx3zEtlyU2wqK/K1jn0=; b=J7OsWw1dOGD0uJ1S8SAPUCe2ZoylZcACPqmCi+xQPPGzn+wTn5iUezXjNOjE3DZfUb YB8mE6n+NTdDFvhP1H3zhgZUpLwEPY24y7oVUYuI0wQPuBXO8COExW2npfpC/ywbVaNa 42ZzoNRR6qJLaJZNowv0G//PKaU291M5kZ0fQw12aYt0JAi1XA6JDZ0fN5DdXm0ZwATE eWgqDUfM3PEv0F+Bg0DiK9W9ukUFVixgmzvrLqKUoeaQJCT1OE2ZWZ6UDblEQmmlxDG6 3i+ZlTR3SrQgpUyxvZ10m/tXzq1r85eFogsL1gE5b9S+UgOascG2ilhXrOR+V9jh+NQN M4fQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SDIqZkpm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y17-20020a1c4b11000000b003f7298a32ccsm12195508wma.41.2023.06.06.03.46.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Jun 2023 03:46:11 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Beniamino Galvani , Strahinja Jankovic , Guenter Roeck , qemu-stable@nongnu.org, Michael Tokarev Subject: [PATCH 2/2] hw/sd/allwinner-sdhost: Don't send non-boolean IRQ line levels Date: Tue, 6 Jun 2023 11:46:09 +0100 Message-Id: <20230606104609.3692557-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230606104609.3692557-1-peter.maydell@linaro.org> References: <20230606104609.3692557-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org QEMU allows qemu_irq lines to transfer arbitrary integers. However the convention is that for a simple IRQ line the values transferred are always 0 and 1. The A10 SD controller device instead assumes a 0-vs-non-0 convention, which happens to work with the interrupt controller it is wired up to. Coerce the value to boolean to follow our usual convention. Signed-off-by: Peter Maydell Tested-by: Guenter Roeck --- hw/sd/allwinner-sdhost.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c index 92a0f42708d..62df8f3d396 100644 --- a/hw/sd/allwinner-sdhost.c +++ b/hw/sd/allwinner-sdhost.c @@ -191,7 +191,7 @@ static void allwinner_sdhost_update_irq(AwSdHostState *s) } trace_allwinner_sdhost_update_irq(irq); - qemu_set_irq(s->irq, irq); + qemu_set_irq(s->irq, !!irq); } static void allwinner_sdhost_update_transfer_cnt(AwSdHostState *s,