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[83.9.31.150]) by smtp.gmail.com with ESMTPSA id e25-20020a2e8199000000b002adbf24212esm2052384ljg.49.2023.06.06.16.04.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Jun 2023 16:04:22 -0700 (PDT) From: Konrad Dybcio Date: Wed, 07 Jun 2023 01:04:19 +0200 Subject: [PATCH v2] arm64: dts: qcom: qcm2290: Add CPU idle states MIME-Version: 1.0 Message-Id: <20230606-topic-qcm2290_idlestates-v2-1-580a5a2d28c9@linaro.org> X-B4-Tracking: v=1; b=H4sIAHK7f2QC/42NWw6CMBREt0L6bU2pWpQv92GI6eMCN6kttpVoC Hv3ygr8PDOZOQvLkBAya6uFJZgxYwwEclcxO+owAEdHzKSQB6GE4iVOaPnTPqS8iDs6D7noApm fDNXSiP5oFaO50Rm4STrYkQ7Cy3sKpwQ9vjffrSMeMZeYPpt+rn/pH6a55jV3rmkAeiHOCq4eg 05xH9PAunVdv9GMJLDWAAAA To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686092661; l=3464; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=9nKmu31YD8GcSD2/6NbQ7qO/EwtCV6fy082gMFHlK5U=; b=wKP8/iEbDbsH4/RtM8CoEhKALhodBs3ASHW8Wx+4US6dv653eMVIW2uhT3l2wZEtVWr5DKFBj 8+pjviD33GgBUtazu7ddpyt1V0JBRi2tfLEFGmo/K0d7KVS3qYYBEsA X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the (scarce) idle states for the individual CPUs, as well as the whole cluster. This enables deeper-than-WFI cpuidle Signed-off-by: Konrad Dybcio --- Changes in v2: - Add missing BIT(24) ("last in power level") - Use the correct CPU low-power state (0x3 instead of 0x4) - Link to v1: https://lore.kernel.org/r/20230606-topic-qcm2290_idlestates-v1-1-dd77eef0086e@linaro.org --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 61 +++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) --- base-commit: 6db29e14f4fb7bce9eb5290288e71b05c2b0d118 change-id: 20230606-topic-qcm2290_idlestates-5b6062b0f4c6 Best regards, diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index b29bc4e4b837..0ed11e80e5e2 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -48,6 +48,8 @@ CPU0: cpu@0 { enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; L2_0: l2-cache { compatible = "cache"; cache-level = <2>; @@ -65,6 +67,8 @@ CPU1: cpu@1 { enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; }; CPU2: cpu@2 { @@ -77,6 +81,8 @@ CPU2: cpu@2 { enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; }; CPU3: cpu@3 { @@ -89,6 +95,8 @@ CPU3: cpu@3 { enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; }; cpu-map { @@ -110,6 +118,30 @@ core3 { }; }; }; + + domain-idle-states { + CLUSTER_SLEEP: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000043>; + entry-latency-us = <800>; + exit-latency-us = <2118>; + min-residency-us = <7376>; + }; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep-0 { + compatible = "arm,idle-state"; + idle-state-name = "power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <290>; + exit-latency-us = <376>; + min-residency-us = <1182>; + local-timer-stop; + }; + }; }; firmware { @@ -135,6 +167,35 @@ pmu { psci { compatible = "arm,psci-1.0"; method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CLUSTER_PD: power-domain-cpu-cluster { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP>; + }; }; reserved_memory: reserved-memory {