From patchwork Tue Jun 6 14:55:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Nyekjaer X-Patchwork-Id: 689899 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BCC1C7EE29 for ; Tue, 6 Jun 2023 14:57:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236749AbjFFO5J (ORCPT ); Tue, 6 Jun 2023 10:57:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60006 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238488AbjFFO4w (ORCPT ); Tue, 6 Jun 2023 10:56:52 -0400 Received: from www530.your-server.de (www530.your-server.de [188.40.30.78]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DAF0A1705; Tue, 6 Jun 2023 07:56:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=geanix.com; s=default2211; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID; bh=ZNcuLhScoFLTrYmEtBLsGb9AliqwkZhWEKZ79KXaSYo=; b=Zi6nOzii95u8pkZlnSFAvSVpKA m2pf8FvNLjVKUSgYbJbnKEoZPkHLMaZT+8Jfrvvg7Y0gUrsMyMy1zyeE/Cv9kJ7OQvTl8BhUQx/0U K5o0t7zvnt+y3BsPvtXTtkL3zH0Alto5foD8s+KN9Vskg+X841b/CeT4ohgITSF41CR0ZHJWKusu3 3pXdo0nOli/FJ571Iy7QAkWdUXkcUh6Uj7g2cAAHi/ZN4QxSgIW2lLvA+RKFSv5t1/cOt1tasmcpp 9q1Od2bYx0P3tfSq+kZmevI5cZg7ft0PEkdUmTnkhv58030WpBMmFKP4FlEi0l+rLFAG5ZGy8lK9o 1oj1q5NA==; Received: from sslproxy05.your-server.de ([78.46.172.2]) by www530.your-server.de with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1q6Y6i-000Pn1-Nl; Tue, 06 Jun 2023 16:56:24 +0200 Received: from [185.17.218.86] (helo=zen..) by sslproxy05.your-server.de with esmtpsa (TLSv1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1q6Y6i-0006D0-7R; Tue, 06 Jun 2023 16:56:24 +0200 From: Sean Nyekjaer To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue Cc: Sean Nyekjaer , dantuguf14105@gmail.com, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 2/5] ARM: dts: stm32: Add alternate pinmux for ldtc pins Date: Tue, 6 Jun 2023 16:55:51 +0200 Message-Id: <20230606145555.2155664-2-sean@geanix.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230606145555.2155664-1-sean@geanix.com> References: <20230606145555.2155664-1-sean@geanix.com> MIME-Version: 1.0 X-Authenticated-Sender: sean@geanix.com X-Virus-Scanned: Clear (ClamAV 0.103.8/26930/Tue Jun 6 09:25:07 2023) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add another mux option for ltdc pins, this is used on Octavo OSD32MP1-RED board. Signed-off-by: Sean Nyekjaer --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 75 ++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index d79f89f37bc7..422db6dd466c 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -979,6 +979,81 @@ pins { }; }; + ltdc_pins_e: ltdc-4 { + pins1 { + pinmux = , /* LTDC_R0 */ + , /* LTDC_R1 */ + , /* LTDC_R2 */ + , /* LTDC_R3 */ + , /* LTDC_R4 */ + , /* LTDC_R5 */ + , /* LTDC_R6 */ + , /* LTDC_R7 */ + , /* LTDC_G0 */ + , /* LTDC_G1 */ + , /* LTDC_G2 */ + , /* LTDC_G3 */ + , /* LTDC_G4 */ + , /* LTDC_G5 */ + , /* LTDC_G6 */ + , /* LTDC_G7 */ + , /* LTDC_B0 */ + , /* LTDC_B1 */ + , /* LTDC_B2 */ + , /* LTDC_B3 */ + , /* LTDC_B4 */ + , /* LTDC_B5 */ + , /* LTDC_B6 */ + , /* LTDC_B7 */ + , /* LTDC_DE */ + , /* LTDC_VSYNC */ + ; /* LTDC_HSYNC */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + + pins2 { + pinmux = ; /* LTDC_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + ltdc_sleep_pins_e: ltdc-sleep-4 { + pins { + pinmux = , /* LTDC_R0 */ + , /* LTDC_R1 */ + , /* LTDC_R2 */ + , /* LTDC_R3 */ + , /* LTDC_R4 */ + , /* LTDC_R5 */ + , /* LTDC_R6 */ + , /* LTDC_R7 */ + , /* LTDC_B0 */ + , /* LTDC_B1 */ + , /* LTDC_B2 */ + , /* LTDC_B3 */ + , /* LTDC_B4 */ + , /* LTDC_B5 */ + , /* LTDC_B6 */ + , /* LTDC_B7 */ + , /* LTDC_G0 */ + , /* LTDC_G1 */ + , /* LTDC_G2 */ + , /* LTDC_G3 */ + , /* LTDC_G4 */ + , /* LTDC_G5 */ + , /* LTDC_G6 */ + , /* LTDC_G7 */ + , /* LTDC_DE */ + , /* LTDC_VSYNC */ + , /* LTDC_HSYNC */ + ; /* LTDC_CLK */ + }; + }; + mco1_pins_a: mco1-0 { pins { pinmux = ; /* MCO1 */ From patchwork Tue Jun 6 14:55:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Nyekjaer X-Patchwork-Id: 689898 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D54EEC7EE32 for ; Tue, 6 Jun 2023 14:57:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238513AbjFFO5K (ORCPT ); Tue, 6 Jun 2023 10:57:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60628 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238509AbjFFO4y (ORCPT ); Tue, 6 Jun 2023 10:56:54 -0400 Received: from www530.your-server.de (www530.your-server.de [188.40.30.78]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F1EC170B; Tue, 6 Jun 2023 07:56:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=geanix.com; s=default2211; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID; bh=4YI6I5iTDhxkNikcxTDT1ukR79k9QBY5V2RRnmcdeQA=; b=NuYBuduwA4GGlMIJqBo/jjCaXi UmJIG5rdfR+nZplgoeFk+81fSU9DpTYmg9lgmctroCZSnurkHqKeCuZ+FRMU62He0xJXuM9dhQUAn KpRhX6iLZqGvZnlY8PyHJMGKLa8buRpXsGs0Jrkdu8LDwUbTzDnmY3Ym8Y5jeG2BfRYqkOedk1AMF YBaOrRbqrQpTC39HJxDYgq+t1uOLmX/brRc174ll7nxHmKmpHlTzc0sc7MY1JRH3J8UM+/uDDHA71 rWNpgeucK5fRT3zPnJ0HdRY6T6apKXLOamsTjKYlqj93ZDKA/vewdwBaVu3G5MhC+UB4y4Qn4wwA3 pnC7rFVw==; Received: from sslproxy05.your-server.de ([78.46.172.2]) by www530.your-server.de with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1q6Y6k-000PnT-8E; Tue, 06 Jun 2023 16:56:26 +0200 Received: from [185.17.218.86] (helo=zen..) by sslproxy05.your-server.de with esmtpsa (TLSv1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1q6Y6j-0006D0-O4; Tue, 06 Jun 2023 16:56:25 +0200 From: Sean Nyekjaer To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue Cc: Sean Nyekjaer , dantuguf14105@gmail.com, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 4/5] ARM: dts: stm32: Add Octavo STM32MP15x SiP Date: Tue, 6 Jun 2023 16:55:53 +0200 Message-Id: <20230606145555.2155664-4-sean@geanix.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230606145555.2155664-1-sean@geanix.com> References: <20230606145555.2155664-1-sean@geanix.com> MIME-Version: 1.0 X-Authenticated-Sender: sean@geanix.com X-Virus-Scanned: Clear (ClamAV 0.103.8/26930/Tue Jun 6 09:25:07 2023) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Octavo STM32MP15x is a System-in-Package based on STM32MP15xx SoC from ST. This SiP module integrates the SoC, DDR Memory, PMIC, EEPROM etc. https://octavosystems.com/octavo_products/osd32mp15x/ Signed-off-by: Sean Nyekjaer --- This is made with great inspiration from Neeraj Dantu's work: https://raw.githubusercontent.com/octavosystems/OSD32MP1-RED-Device-tree/main/linux-v5.10-r0/stm32mp157c-osd32mp1-red.dts So what copyright is needed here? And author? Still need to test ethernet and HDMI, thats why I have done this a RFC. Is it good pratice to add labels to all regulator's on the PMIC so boards can add regulator options? arch/arm/boot/dts/stm32mp15xx-osd32mp1.dtsi | 308 ++++++++++++++++++++ 1 file changed, 308 insertions(+) create mode 100644 arch/arm/boot/dts/stm32mp15xx-osd32mp1.dtsi diff --git a/arch/arm/boot/dts/stm32mp15xx-osd32mp1.dtsi b/arch/arm/boot/dts/stm32mp15xx-osd32mp1.dtsi new file mode 100644 index 000000000000..4de9213f6d43 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15xx-osd32mp1.dtsi @@ -0,0 +1,308 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) ?? - All Rights Reserved + * Author: ??? + */ + +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include +#include +#include + +/ { + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + + gpu_reserved: gpu@d4000000 { + reg = <0xd4000000 0x4000000>; + no-map; + }; + }; + + vin: vin { + compatible = "regulator-fixed"; + regulator-name = "vin"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&m4_rproc { + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>; + mbox-names = "vq0", "vq1", "shutdown", "detach"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + status = "okay"; +}; + +&gpu { + contiguous-area = <&gpu_reserved>; +}; + +&hash1 { + status = "okay"; +}; + +&cryp1 { + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c4_pins_a>; + pinctrl-1 = <&i2c4_sleep_pins_a>; + status = "okay"; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + clock-frequency = <400000>; + /delete-property/ dmas; + /delete-property/ dma-names; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; + buck1-supply = <&vin>; + buck2-supply = <&vin>; + buck3-supply = <&vin>; + buck4-supply = <&vin>; + ldo1-supply = <&v3v3>; + ldo2-supply = <&vin>; + ldo3-supply = <&vdd_ddr>; + ldo4-supply = <&vin>; + ldo5-supply = <&vin>; + ldo6-supply = <&v3v3>; + vref_ddr-supply = <&vin>; + boost-supply = <&vin>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + ldo1: ldo1 { + regulator-name = "v1v8_audio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + interrupts = ; + }; + + v2v8: ldo2 { + regulator-name = "v2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + interrupts = ; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + interrupts = ; + }; + + vdda: ldo5 { + regulator-name = "vdda"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = ; + }; + + v1v8: ldo6 { + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + interrupts = ; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = ; + regulator-active-discharge = <1>; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = , ; + interrupt-names = "onkey-falling", "onkey-rising"; + power-off-time-sec = <10>; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&cpu0 { + cpu-supply = <&vddcore>; +}; + +&cpu1 { + cpu-supply = <&vddcore>; +}; + +&ipcc { + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&crc1 { + status = "okay"; +}; + +&dts { + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbh_ohci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + vbus-supply = <&vbus_otg>; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +};