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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id j2sm16457065pfn.135.2019.06.17.22.23.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 22:23:49 -0700 (PDT) From: Bjorn Andersson To: Andy Gross Cc: David Brown , Rob Herring , Mark Rutland , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH] arm64: dts: qcom: msm8996: Enable SMMUs Date: Mon, 17 Jun 2019 22:23:46 -0700 Message-Id: <20190618052346.32239-1-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable SMMUs on 8996 now that the WRZ workaround in the arm-smmu driver has landed. Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 6 ------ 1 file changed, 6 deletions(-) -- 2.18.0 diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 1e3143c4fe8f..2ecd9d775d61 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1177,7 +1177,6 @@ clock-names = "iface", "bus"; #iommu-cells = <1>; - status = "disabled"; }; camss: camss@a00000 { @@ -1330,8 +1329,6 @@ clock-names = "iface", "bus"; power-domains = <&mmcc GPU_GDSC>; - - status = "disabled"; }; mdp_smmu: arm,smmu@d00000 { @@ -1348,8 +1345,6 @@ clock-names = "iface", "bus"; power-domains = <&mmcc MDSS_GDSC>; - - status = "disabled"; }; lpass_q6_smmu: arm,smmu-lpass_q6@1600000 { @@ -1376,7 +1371,6 @@ clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>, <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; clock-names = "iface", "bus"; - status = "disabled"; }; agnoc@0 {