From patchwork Fri Jun 23 14:18:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Komal Bajaj X-Patchwork-Id: 695960 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87D74EB64DD for ; Fri, 23 Jun 2023 14:19:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231582AbjFWOTS (ORCPT ); Fri, 23 Jun 2023 10:19:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50354 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231817AbjFWOTE (ORCPT ); Fri, 23 Jun 2023 10:19:04 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FDA32697; Fri, 23 Jun 2023 07:19:00 -0700 (PDT) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35NDPCCc021458; Fri, 23 Jun 2023 14:18:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=m2OLOh/h0xBAY0ICfbHaYott8PupJP3Ngk6gfvOLizM=; b=LtmBO2qS+8XWTcnkF8veUr0DFScj+/qp057CFFc7WOTfM7PhscMPq677yEm34Vzu2Us9 RSpYnYabt6tcjoHDXfKXxeexNm2cSsgTX8XJbsrLGpmYDLS5HcDCKdlFONCJb3KAGMEE D8OdLMjuo+vsclqIdoUJpVDijbjh9VQMWYJksKKwv8w+i9lNWgfpGoWnxOGr5nmbMp2j aHZV1odlLVV4CYuVZ20hLpm1AH0xe17Z/z99hOdjJnjgsa8irHKBDYSmID6Pp9xwubVT bXPHDTIIlJB6qGele0/xFpxZc9j3zj0CnA2bJSGh6UmSRx9/iWyVD0PVdvp6QMJEcCzE Kw== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rc0sk5s8d-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 23 Jun 2023 14:18:56 +0000 Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 35NEIXee013472 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 23 Jun 2023 14:18:33 GMT Received: from hu-kbajaj-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Fri, 23 Jun 2023 07:18:29 -0700 From: Komal Bajaj To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Srinivas Kandagatla , Conor Dooley CC: , , , Komal Bajaj Subject: [PATCH v4 1/6] dt-bindings: nvmem: sec-qfprom: Add bindings for secure qfprom Date: Fri, 23 Jun 2023 19:48:01 +0530 Message-ID: <20230623141806.13388-2-quic_kbajaj@quicinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230623141806.13388-1-quic_kbajaj@quicinc.com> References: <20230623141806.13388-1-quic_kbajaj@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: J1NqZjY0UUmaXALb09Au2ktyJvM0octL X-Proofpoint-ORIG-GUID: J1NqZjY0UUmaXALb09Au2ktyJvM0octL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-23_07,2023-06-22_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxscore=0 phishscore=0 impostorscore=0 mlxlogscore=756 priorityscore=1501 malwarescore=0 adultscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306230130 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds bindings for secure qfprom found in QCOM SOCs. SECURE QFPROM driver is based on simple nvmem framework. Signed-off-by: Komal Bajaj --- .../bindings/nvmem/qcom,sec-qfprom.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/qcom,sec-qfprom.yaml diff --git a/Documentation/devicetree/bindings/nvmem/qcom,sec-qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,sec-qfprom.yaml new file mode 100644 index 000000000000..675e27918c7b --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/qcom,sec-qfprom.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/qcom,sec-qfprom.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies Inc, SECURE QFPROM Efuse + +maintainers: + - Komal Bajaj + +allOf: + - $ref: nvmem.yaml# + +properties: + compatible: + items: + - enum: + - qcom,qdu1000-sec-qfprom + - const: qcom,sec-qfprom + + reg: + items: + - description: The secure qfprom corrected region. + + # Needed if any child nodes are present. + "#address-cells": + const: 1 + "#size-cells": + const: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + efuse@221c8000 { + compatible = "qcom,qdu1000-sec-qfprom", "qcom,sec-qfprom"; + reg = <0 0x221c8000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + multi_chan_ddr: multi_chan_ddr@12b { + reg = <0x12b 0x1>; + bits = <0 2>; + }; + }; + }; + From patchwork Fri Jun 23 14:18:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Komal Bajaj X-Patchwork-Id: 695962 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBBD7C001B0 for ; Fri, 23 Jun 2023 14:18:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232019AbjFWOSv (ORCPT ); Fri, 23 Jun 2023 10:18:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232057AbjFWOSs (ORCPT ); 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Fri, 23 Jun 2023 14:18:39 +0000 Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 35NEIc0Y031441 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 23 Jun 2023 14:18:38 GMT Received: from hu-kbajaj-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Fri, 23 Jun 2023 07:18:35 -0700 From: Komal Bajaj To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Srinivas Kandagatla , Conor Dooley CC: , , , Komal Bajaj Subject: [PATCH v4 2/6] dt-bindings: cache: qcom, llcc: Add LLCC compatible for QDU1000/QRU1000 Date: Fri, 23 Jun 2023 19:48:02 +0530 Message-ID: <20230623141806.13388-3-quic_kbajaj@quicinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230623141806.13388-1-quic_kbajaj@quicinc.com> References: <20230623141806.13388-1-quic_kbajaj@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: KlrsUU0lni41IrAiQtAKD-Ecf7GIElUh X-Proofpoint-ORIG-GUID: KlrsUU0lni41IrAiQtAKD-Ecf7GIElUh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-23_08,2023-06-22_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 malwarescore=0 mlxlogscore=820 suspectscore=0 spamscore=0 adultscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 bulkscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306230130 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add LLCC compatible for QDU1000/QRU1000 SoCs and add optional nvmem-cells and nvmem-cell-names property. Signed-off-by: Komal Bajaj --- Documentation/devicetree/bindings/cache/qcom,llcc.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml index 44892aa589fd..580f9a97ddf7 100644 --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml @@ -20,6 +20,7 @@ description: | properties: compatible: enum: + - qcom,qdu1000-llcc - qcom,sc7180-llcc - qcom,sc7280-llcc - qcom,sc8180x-llcc @@ -44,6 +45,14 @@ properties: interrupts: maxItems: 1 + nvmem-cells: + items: + - description: Reference to an nvmem node for multi channel DDR + + nvmem-cell-names: + items: + - const: multi-chan-ddr + required: - compatible - reg @@ -92,6 +101,7 @@ allOf: compatible: contains: enum: + - qcom,qdu1000-llcc - qcom,sc8180x-llcc - qcom,sc8280xp-llcc then: From patchwork Fri Jun 23 14:18:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Komal Bajaj X-Patchwork-Id: 695961 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED0C2EB64DD for ; Fri, 23 Jun 2023 14:19:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232036AbjFWOTB (ORCPT ); Fri, 23 Jun 2023 10:19:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50230 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232081AbjFWOSu (ORCPT ); Fri, 23 Jun 2023 10:18:50 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B4282126; Fri, 23 Jun 2023 07:18:48 -0700 (PDT) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35NDoeMi004763; Fri, 23 Jun 2023 14:18:45 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=JPQbAF/VQPtjKprLEiJlkztDthG5+7eJbxAGAtrZUu0=; b=CFAWR2Qr5YIW6eTYIWsrogxAZl9iZ4EyFlkEM1TqOWDhiRA+3uWgGqHm455r5C2XBdqE +ar5OqLRjBycIs9C8Px3UrQpMDBFOIte27nYUgUO1rp4fXqKwolgedcWd/mCwY4EHYCu lbZEdONbwK4moLI/DsZYkbsRrtNSGBeVXqzVwAjETBUjkZ2TVEKGmOce/GFJYlq8DlOX RNVQaIHDjTyII+Nn+E9Du8IQNzV/HfJBMapBE8gihTTl2NAbunxtSlHFG8UnwlDR5k2E GoVkmWc+Zl4ZUSrzLpOws3FeIRsabOHMCCj+srjEwcsc167Hq+URDIQWfNbX6nh/x4SC wA== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rc2rcndqc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 23 Jun 2023 14:18:45 +0000 Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 35NEIiFK031459 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 23 Jun 2023 14:18:44 GMT Received: from hu-kbajaj-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Fri, 23 Jun 2023 07:18:40 -0700 From: Komal Bajaj To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Srinivas Kandagatla , Conor Dooley CC: , , , Komal Bajaj Subject: [PATCH v4 3/6] nvmem: sec-qfprom: Add Qualcomm secure QFPROM support. Date: Fri, 23 Jun 2023 19:48:03 +0530 Message-ID: <20230623141806.13388-4-quic_kbajaj@quicinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230623141806.13388-1-quic_kbajaj@quicinc.com> References: <20230623141806.13388-1-quic_kbajaj@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: hDBMhK6pzcB-4TdSLQZmDBTcDXkVP-K6 X-Proofpoint-GUID: hDBMhK6pzcB-4TdSLQZmDBTcDXkVP-K6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-23_08,2023-06-22_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 priorityscore=1501 mlxscore=0 spamscore=0 impostorscore=0 adultscore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=999 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306230130 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org For some of the Qualcomm SoC's, it is possible that some of the fuse regions or entire qfprom region is protected from non-secure access. In such situations, linux will have to use secure calls to read the region. With that motivation, add secure qfprom driver. Ensuring the address to read is word aligned since our secure I/O only supports word size I/O. Signed-off-by: Komal Bajaj --- drivers/nvmem/Kconfig | 12 ++++ drivers/nvmem/Makefile | 2 + drivers/nvmem/sec-qfprom.c | 116 +++++++++++++++++++++++++++++++++++++ 3 files changed, 130 insertions(+) create mode 100644 drivers/nvmem/sec-qfprom.c diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index b291b27048c7..2b0dd73d899e 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -216,6 +216,18 @@ config NVMEM_QCOM_QFPROM This driver can also be built as a module. If so, the module will be called nvmem_qfprom. +config NVMEM_QCOM_SEC_QFPROM + tristate "QCOM SECURE QFPROM Support" + depends on ARCH_QCOM || COMPILE_TEST + depends on HAS_IOMEM + select QCOM_SCM + help + Say y here to enable secure QFPROM support. The secure QFPROM provides access + functions for QFPROM data to rest of the drivers via nvmem interface. + + This driver can also be built as a module. If so, the module will be called + nvmem_sec_qfprom. + config NVMEM_RAVE_SP_EEPROM tristate "Rave SP EEPROM Support" depends on RAVE_SP_CORE diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index f82431ec8aef..4b4bf5880488 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -44,6 +44,8 @@ obj-$(CONFIG_NVMEM_NINTENDO_OTP) += nvmem-nintendo-otp.o nvmem-nintendo-otp-y := nintendo-otp.o obj-$(CONFIG_NVMEM_QCOM_QFPROM) += nvmem_qfprom.o nvmem_qfprom-y := qfprom.o +obj-$(CONFIG_NVMEM_QCOM_SEC_QFPROM) += nvmem_sec_qfprom.o +nvmem_sec_qfprom-y := sec-qfprom.o obj-$(CONFIG_NVMEM_RAVE_SP_EEPROM) += nvmem-rave-sp-eeprom.o nvmem-rave-sp-eeprom-y := rave-sp-eeprom.o obj-$(CONFIG_NVMEM_RMEM) += nvmem-rmem.o diff --git a/drivers/nvmem/sec-qfprom.c b/drivers/nvmem/sec-qfprom.c new file mode 100644 index 000000000000..47b2c71593dd --- /dev/null +++ b/drivers/nvmem/sec-qfprom.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +/** + * struct sec_sec_qfprom_priv - structure holding secure qfprom attributes + * + * @qfpseccorrected: iomapped memory space for secure qfprom corrected address space. + * @dev: qfprom device structure. + */ +struct sec_qfprom_priv { + phys_addr_t qfpseccorrected; + struct device *dev; +}; + +static int sec_qfprom_reg_read(void *context, unsigned int reg, void *_val, size_t bytes) +{ + struct sec_qfprom_priv *priv = context; + u8 *val = _val; + u8 *tmp; + u32 read_val; + unsigned int i; + + for (i = 0; i < bytes; i++, reg++) { + if (i == 0 || reg % 4 == 0) { + if (qcom_scm_io_readl(priv->qfpseccorrected + (reg & ~3), &read_val)) { + dev_err(priv->dev, "Couldn't access fuse register\n"); + return -EINVAL; + } + tmp = (u8 *)&read_val; + } + + val[i] = tmp[reg & 3]; + } + + return 0; +} + +static void sec_qfprom_runtime_disable(void *data) +{ + pm_runtime_disable(data); +} + +static int sec_qfprom_probe(struct platform_device *pdev) +{ + struct nvmem_config econfig = { + .name = "sec-qfprom", + .stride = 1, + .word_size = 1, + .id = NVMEM_DEVID_AUTO, + .reg_read = sec_qfprom_reg_read, + }; + struct device *dev = &pdev->dev; + struct resource *res; + struct nvmem_device *nvmem; + struct sec_qfprom_priv *priv; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->qfpseccorrected = res->start; + if (!priv->qfpseccorrected) + return -ENOMEM; + + econfig.size = resource_size(res); + econfig.dev = dev; + econfig.priv = priv; + + priv->dev = dev; + + pm_runtime_enable(dev); + ret = devm_add_action_or_reset(dev, sec_qfprom_runtime_disable, dev); + if (ret) + return ret; + + nvmem = devm_nvmem_register(dev, &econfig); + + return PTR_ERR_OR_ZERO(nvmem); +} + +static const struct of_device_id sec_qfprom_of_match[] = { + { .compatible = "qcom,sec-qfprom",}, + {/* sentinel */}, +}; +MODULE_DEVICE_TABLE(of, sec_qfprom_of_match); + +static struct platform_driver qfprom_driver = { + .probe = sec_qfprom_probe, + .driver = { + .name = "qcom,sec_qfprom", + .of_match_table = sec_qfprom_of_match, + }, +}; +module_platform_driver(qfprom_driver); +MODULE_DESCRIPTION("Qualcomm Secure QFPROM driver"); +MODULE_LICENSE("GPL v2"); From patchwork Fri Jun 23 14:18:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Komal Bajaj X-Patchwork-Id: 695387 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA6AEEB64D7 for ; Fri, 23 Jun 2023 14:18:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232083AbjFWOS4 (ORCPT ); Fri, 23 Jun 2023 10:18:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50302 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232080AbjFWOSz (ORCPT ); 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Fri, 23 Jun 2023 14:18:50 +0000 Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 35NEInoe013754 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 23 Jun 2023 14:18:49 GMT Received: from hu-kbajaj-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Fri, 23 Jun 2023 07:18:45 -0700 From: Komal Bajaj To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Srinivas Kandagatla , Conor Dooley CC: , , , Komal Bajaj , "Abel Vesa" Subject: [PATCH v4 4/6] soc: qcom: llcc: Refactor llcc driver to support multiple configuration Date: Fri, 23 Jun 2023 19:48:04 +0530 Message-ID: <20230623141806.13388-5-quic_kbajaj@quicinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230623141806.13388-1-quic_kbajaj@quicinc.com> References: <20230623141806.13388-1-quic_kbajaj@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: TwvvbLe_64GVFb8lMcajjc1Ms8dnziHH X-Proofpoint-ORIG-GUID: TwvvbLe_64GVFb8lMcajjc1Ms8dnziHH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-23_08,2023-06-22_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 malwarescore=0 mlxlogscore=999 suspectscore=0 spamscore=0 adultscore=0 clxscore=1011 lowpriorityscore=0 phishscore=0 bulkscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306230130 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Refactor driver to support multiple configuration for llcc on a target. Reviewed-by: Abel Vesa Signed-off-by: Komal Bajaj --- drivers/soc/qcom/llcc-qcom.c | 210 ++++++++++++++++++++--------------- 1 file changed, 123 insertions(+), 87 deletions(-) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 67c19ed2219a..6cf373da5df9 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -423,101 +423,137 @@ static const u32 llcc_v2_1_reg_offset[] = { [LLCC_COMMON_STATUS0] = 0x0003400c, }; -static const struct qcom_llcc_config sc7180_cfg = { - .sct_data = sc7180_data, - .size = ARRAY_SIZE(sc7180_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sc7180_cfg[] = { + { + .sct_data = sc7180_data, + .size = ARRAY_SIZE(sc7180_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sc7280_cfg = { - .sct_data = sc7280_data, - .size = ARRAY_SIZE(sc7280_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sc7280_cfg[] = { + { + .sct_data = sc7280_data, + .size = ARRAY_SIZE(sc7280_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sc8180x_cfg = { - .sct_data = sc8180x_data, - .size = ARRAY_SIZE(sc8180x_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sc8180x_cfg[] = { + { + .sct_data = sc8180x_data, + .size = ARRAY_SIZE(sc8180x_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sc8280xp_cfg = { - .sct_data = sc8280xp_data, - .size = ARRAY_SIZE(sc8280xp_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sc8280xp_cfg[] = { + { + .sct_data = sc8280xp_data, + .size = ARRAY_SIZE(sc8280xp_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sdm845_cfg = { - .sct_data = sdm845_data, - .size = ARRAY_SIZE(sdm845_data), - .need_llcc_cfg = false, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, - .no_edac = true, +static const struct qcom_llcc_config sdm845_cfg[] = { + { + .sct_data = sdm845_data, + .size = ARRAY_SIZE(sdm845_data), + .need_llcc_cfg = false, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + .no_edac = true, + }, + { }, }; -static const struct qcom_llcc_config sm6350_cfg = { - .sct_data = sm6350_data, - .size = ARRAY_SIZE(sm6350_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sm6350_cfg[] = { + { + .sct_data = sm6350_data, + .size = ARRAY_SIZE(sm6350_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sm7150_cfg = { - .sct_data = sm7150_data, - .size = ARRAY_SIZE(sm7150_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sm7150_cfg[] = { + { + .sct_data = sm7150_data, + .size = ARRAY_SIZE(sm7150_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sm8150_cfg = { - .sct_data = sm8150_data, - .size = ARRAY_SIZE(sm8150_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sm8150_cfg[] = { + { + .sct_data = sm8150_data, + .size = ARRAY_SIZE(sm8150_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sm8250_cfg = { - .sct_data = sm8250_data, - .size = ARRAY_SIZE(sm8250_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sm8250_cfg[] = { + { + .sct_data = sm8250_data, + .size = ARRAY_SIZE(sm8250_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sm8350_cfg = { - .sct_data = sm8350_data, - .size = ARRAY_SIZE(sm8350_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sm8350_cfg[] = { + { + .sct_data = sm8350_data, + .size = ARRAY_SIZE(sm8350_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sm8450_cfg = { - .sct_data = sm8450_data, - .size = ARRAY_SIZE(sm8450_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v2_1_reg_offset, - .edac_reg_offset = &llcc_v2_1_edac_reg_offset, +static const struct qcom_llcc_config sm8450_cfg[] = { + { + .sct_data = sm8450_data, + .size = ARRAY_SIZE(sm8450_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v2_1_reg_offset, + .edac_reg_offset = &llcc_v2_1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sm8550_cfg = { - .sct_data = sm8550_data, - .size = ARRAY_SIZE(sm8550_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v2_1_reg_offset, - .edac_reg_offset = &llcc_v2_1_edac_reg_offset, +static const struct qcom_llcc_config sm8550_cfg[] = { + { + .sct_data = sm8550_data, + .size = ARRAY_SIZE(sm8550_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v2_1_reg_offset, + .edac_reg_offset = &llcc_v2_1_edac_reg_offset, + }, + { }, }; static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER; @@ -1004,8 +1040,8 @@ static int qcom_llcc_probe(struct platform_device *pdev) drv_data->version = version; - llcc_cfg = cfg->sct_data; - sz = cfg->size; + llcc_cfg = cfg[0]->sct_data; + sz = cfg[0]->size; for (i = 0; i < sz; i++) if (llcc_cfg[i].slice_id > drv_data->max_slices) @@ -1051,18 +1087,18 @@ static int qcom_llcc_probe(struct platform_device *pdev) } static const struct of_device_id qcom_llcc_of_match[] = { - { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg }, - { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfg }, - { .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfg }, - { .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfg }, - { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg }, - { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfg }, - { .compatible = "qcom,sm7150-llcc", .data = &sm7150_cfg }, - { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg }, - { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg }, - { .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfg }, - { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfg }, - { .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfg }, + { .compatible = "qcom,sc7180-llcc", .data = sc7180_cfg }, + { .compatible = "qcom,sc7280-llcc", .data = sc7280_cfg }, + { .compatible = "qcom,sc8180x-llcc", .data = sc8180x_cfg }, + { .compatible = "qcom,sc8280xp-llcc", .data = sc8280xp_cfg }, + { .compatible = "qcom,sdm845-llcc", .data = sdm845_cfg }, + { .compatible = "qcom,sm6350-llcc", .data = sm6350_cfg }, + { .compatible = "qcom,sm7150-llcc", .data = sm7150_cfg }, + { .compatible = "qcom,sm8150-llcc", .data = sm8150_cfg }, + { .compatible = "qcom,sm8250-llcc", .data = sm8250_cfg }, + { .compatible = "qcom,sm8350-llcc", .data = sm8350_cfg }, + { .compatible = "qcom,sm8450-llcc", .data = sm8450_cfg }, + { .compatible = "qcom,sm8550-llcc", .data = sm8550_cfg }, { } }; MODULE_DEVICE_TABLE(of, qcom_llcc_of_match); From patchwork Fri Jun 23 14:18:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Komal Bajaj X-Patchwork-Id: 695386 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3676C001B0 for ; Fri, 23 Jun 2023 14:19:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232068AbjFWOTQ (ORCPT ); Fri, 23 Jun 2023 10:19:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50380 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232017AbjFWOTA (ORCPT ); Fri, 23 Jun 2023 10:19:00 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 816ED2693; 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Fri, 23 Jun 2023 14:18:55 +0000 Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 35NEIsDd013593 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 23 Jun 2023 14:18:54 GMT Received: from hu-kbajaj-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Fri, 23 Jun 2023 07:18:50 -0700 From: Komal Bajaj To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Srinivas Kandagatla , Conor Dooley CC: , , , Komal Bajaj Subject: [PATCH v4 5/6] soc: qcom: Add LLCC support for multi channel DDR Date: Fri, 23 Jun 2023 19:48:05 +0530 Message-ID: <20230623141806.13388-6-quic_kbajaj@quicinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230623141806.13388-1-quic_kbajaj@quicinc.com> References: <20230623141806.13388-1-quic_kbajaj@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: VGSDNmTnx1G88uooTdPkL3WjWYZiBPg7 X-Proofpoint-ORIG-GUID: VGSDNmTnx1G88uooTdPkL3WjWYZiBPg7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-23_08,2023-06-22_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 spamscore=0 phishscore=0 mlxscore=0 adultscore=0 mlxlogscore=833 clxscore=1015 priorityscore=1501 suspectscore=0 bulkscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306230130 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add LLCC support for multi channel DDR configuration based on a feature register. Reading DDR channel confiuration uses nvmem framework, so select the dependency in Kconfig. Without this, there will be errors while building the driver with COMPILE_TEST only. Signed-off-by: Komal Bajaj --- drivers/soc/qcom/Kconfig | 2 ++ drivers/soc/qcom/llcc-qcom.c | 33 ++++++++++++++++++++++++++++++--- 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index a491718f8064..cc9ad41c63aa 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -64,6 +64,8 @@ config QCOM_LLCC tristate "Qualcomm Technologies, Inc. LLCC driver" depends on ARCH_QCOM || COMPILE_TEST select REGMAP_MMIO + select NVMEM + select QCOM_SCM help Qualcomm Technologies, Inc. platform specific Last Level Cache Controller(LLCC) driver for platforms such as, diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 6cf373da5df9..3c29612da1c5 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -943,6 +944,19 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev, return ret; } +static int qcom_llcc_get_cfg_index(struct platform_device *pdev, u8 *cfg_index) +{ + int ret; + + ret = nvmem_cell_read_u8(&pdev->dev, "multi-chan-ddr", cfg_index); + if (ret == -ENOENT) { + *cfg_index = 0; + return 0; + } + + return ret; +} + static int qcom_llcc_remove(struct platform_device *pdev) { /* Set the global pointer to a error code to avoid referencing it */ @@ -975,11 +989,13 @@ static int qcom_llcc_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; int ret, i; struct platform_device *llcc_edac; - const struct qcom_llcc_config *cfg; + const struct qcom_llcc_config *cfg, *entry; const struct llcc_slice_config *llcc_cfg; u32 sz; + u8 cfg_index; u32 version; struct regmap *regmap; + u32 num_entries = 0; drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); if (!drv_data) { @@ -1040,8 +1056,19 @@ static int qcom_llcc_probe(struct platform_device *pdev) drv_data->version = version; - llcc_cfg = cfg[0]->sct_data; - sz = cfg[0]->size; + ret = qcom_llcc_get_cfg_index(pdev, &cfg_index); + if (ret) + goto err; + + for (entry = cfg; entry->sct_data; entry++, num_entries++) + ; + if (cfg_index >= num_entries || cfg_index < 0) { + ret = -EINVAL; + goto err; + } + + llcc_cfg = cfg[cfg_index].sct_data; + sz = cfg[cfg_index].size; for (i = 0; i < sz; i++) if (llcc_cfg[i].slice_id > drv_data->max_slices) From patchwork Fri Jun 23 14:18:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Komal Bajaj X-Patchwork-Id: 695385 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A349EB64DD for ; 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Fri, 23 Jun 2023 07:18:55 -0700 From: Komal Bajaj To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Srinivas Kandagatla , Conor Dooley CC: , , , Komal Bajaj Subject: [PATCH v4 6/6] soc: qcom: llcc: Add QDU1000 and QRU1000 LLCC support Date: Fri, 23 Jun 2023 19:48:06 +0530 Message-ID: <20230623141806.13388-7-quic_kbajaj@quicinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230623141806.13388-1-quic_kbajaj@quicinc.com> References: <20230623141806.13388-1-quic_kbajaj@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: u3BqsjCk60-Dl6U2nWYyfqKeMKpZgBtI X-Proofpoint-ORIG-GUID: u3BqsjCk60-Dl6U2nWYyfqKeMKpZgBtI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-23_07,2023-06-22_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 bulkscore=0 suspectscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 clxscore=1015 spamscore=0 phishscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306230130 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add LLCC configuration data for QDU1000 and QRU1000 SoCs and updating macro name for LLCC_DRE to LLCC_ECC as per the latest specification. Signed-off-by: Komal Bajaj --- drivers/soc/qcom/llcc-qcom.c | 65 +++++++++++++++++++++++++++++- include/linux/soc/qcom/llcc-qcom.h | 2 +- 2 files changed, 65 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 3c29612da1c5..d2826158ae60 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -187,7 +187,7 @@ static const struct llcc_slice_config sc8280xp_data[] = { { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, { LLCC_DISP, 16, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, { LLCC_AUDHW, 22, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, - { LLCC_DRE, 26, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_ECC, 26, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, { LLCC_CVP, 28, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0, 0 }, { LLCC_WRCACHE, 31, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, @@ -358,6 +358,36 @@ static const struct llcc_slice_config sm8550_data[] = { {LLCC_VIDVSP, 28, 256, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, }; +static const struct llcc_slice_config qdu1000_data_2ch[] = { + {LLCC_MDMHPGRW, 7, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_MODHW, 9, 256, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_MDMPNG, 21, 256, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_ECC, 26, 512, 3, 1, 0xFFC, 0x0, 0, 0, 0, 0, 1, 0, 0 }, + {LLCC_MODPE, 29, 256, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_APTCM, 30, 256, 3, 1, 0x0, 0xC, 1, 0, 0, 1, 0, 0, 0 }, + {LLCC_WRCACHE, 31, 128, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 }, +}; + +static const struct llcc_slice_config qdu1000_data_4ch[] = { + {LLCC_MDMHPGRW, 7, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_MODHW, 9, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_MDMPNG, 21, 512, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_ECC, 26, 1024, 3, 1, 0xFFC, 0x0, 0, 0, 0, 0, 1, 0, 0 }, + {LLCC_MODPE, 29, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_APTCM, 30, 512, 3, 1, 0x0, 0xC, 1, 0, 0, 1, 0, 0, 0 }, + {LLCC_WRCACHE, 31, 256, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 }, +}; + +static const struct llcc_slice_config qdu1000_data_8ch[] = { + {LLCC_MDMHPGRW, 7, 2048, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_MODHW, 9, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_MDMPNG, 21, 1024, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_ECC, 26, 2048, 3, 1, 0xFFC, 0x0, 0, 0, 0, 0, 1, 0, 0 }, + {LLCC_MODPE, 29, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0xC, 1, 0, 0, 1, 0, 0, 0 }, + {LLCC_WRCACHE, 31, 512, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 }, +}; + static const struct llcc_edac_reg_offset llcc_v1_edac_reg_offset = { .trp_ecc_error_status0 = 0x20344, .trp_ecc_error_status1 = 0x20348, @@ -557,6 +587,38 @@ static const struct qcom_llcc_config sm8550_cfg[] = { { }, }; +static const struct qcom_llcc_config qdu1000_cfg[] = { + { + .sct_data = qdu1000_data_8ch, + .size = ARRAY_SIZE(qdu1000_data_8ch), + .need_llcc_cfg = true, + .reg_offset = llcc_v2_1_reg_offset, + .edac_reg_offset = &llcc_v2_1_edac_reg_offset, + }, + { + .sct_data = qdu1000_data_4ch, + .size = ARRAY_SIZE(qdu1000_data_4ch), + .need_llcc_cfg = true, + .reg_offset = llcc_v2_1_reg_offset, + .edac_reg_offset = &llcc_v2_1_edac_reg_offset, + }, + { + .sct_data = qdu1000_data_4ch, + .size = ARRAY_SIZE(qdu1000_data_4ch), + .need_llcc_cfg = true, + .reg_offset = llcc_v2_1_reg_offset, + .edac_reg_offset = &llcc_v2_1_edac_reg_offset, + }, + { + .sct_data = qdu1000_data_2ch, + .size = ARRAY_SIZE(qdu1000_data_2ch), + .need_llcc_cfg = true, + .reg_offset = llcc_v2_1_reg_offset, + .edac_reg_offset = &llcc_v2_1_edac_reg_offset, + }, + { }, +}; + static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER; /** @@ -1114,6 +1176,7 @@ static int qcom_llcc_probe(struct platform_device *pdev) } static const struct of_device_id qcom_llcc_of_match[] = { + { .compatible = "qcom,qdu1000-llcc", .data = qdu1000_cfg}, { .compatible = "qcom,sc7180-llcc", .data = sc7180_cfg }, { .compatible = "qcom,sc7280-llcc", .data = sc7280_cfg }, { .compatible = "qcom,sc8180x-llcc", .data = sc8180x_cfg }, diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index 93417ba1ead4..1a886666bbb6 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -30,7 +30,7 @@ #define LLCC_NPU 23 #define LLCC_WLHW 24 #define LLCC_PIMEM 25 -#define LLCC_DRE 26 +#define LLCC_ECC 26 #define LLCC_CVP 28 #define LLCC_MODPE 29 #define LLCC_APTCM 30