From patchwork Sun Jun 25 20:25:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 696303 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6AD7C001DD for ; Sun, 25 Jun 2023 20:25:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230111AbjFYUZz (ORCPT ); Sun, 25 Jun 2023 16:25:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60188 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230088AbjFYUZy (ORCPT ); Sun, 25 Jun 2023 16:25:54 -0400 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB137E4C for ; Sun, 25 Jun 2023 13:25:51 -0700 (PDT) Received: by mail-lf1-x12e.google.com with SMTP id 2adb3069b0e04-4fafe87c6fbso856291e87.3 for ; Sun, 25 Jun 2023 13:25:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687724750; x=1690316750; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=z1S1is2cOz63gQMr+iNsqA7cGkmzXDgvApekIDI21n4=; b=IPkhDeBtv1Tnpg8MFffJbkZe8Qw0dogWowNIkFifoqYVxDORKYIYYPlyb6F6IfHPeP tr3QK9AaGNI+LbULrFXO6N0Cp2To2JnkHWl3XvalPdZMTmCCn7Qo8L5wlMMQxF6TZ7lD j5qI3nZbEw/Q+xu3PrAyFsMTF252S7iA3kodH+Cu+LCw0muhGCaYyCTlronFEDokJA58 taQCRPi+jMxeSZO7qcOOlfl1zatPcatOwzdKQz94qZPMkJSRYVkvbnO7lnv3mK2yxe1F zINrIda5b29EP0ktnx+TnmUc+USWclm6G+iC2SHiLSjXvE3cDedNFUv/Zn4hIq25L26O edqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687724750; x=1690316750; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=z1S1is2cOz63gQMr+iNsqA7cGkmzXDgvApekIDI21n4=; b=S2ogrFtaYtKKihhWR/lS82c5mwi4e7fPdU+iQ+Vtazx+e3lrab/02EmDAIHmakzW1A S+24s1Yf6+ywNJiP7dI1BJ9aybOSWN6o/si08P1oa+pS49cefzhcgJwgaSCnr1mvhRgi mu1otYJnGeVPkrXvB50WIuCURV5lUaBVLCWF55rRJ5xXAl38SDtsXTsoyxKpa4kSB02y UZ1L8iEkSW+jrLoBqDkjsUfldOA/bI4ZuwXpxj/rqdIwSfSYlcWnMXGX06BHs5VngwuO n0b9AbszDm2TbVLFYseU11EqEhgL3mbllvktjPWT/TW7qup+MN5HV041SjCzx5k919VJ JnwA== X-Gm-Message-State: AC+VfDzR7S5qja4CfwpBE3Prv7iG+PemPuUwptyEvkUJUyA1S0kGPBLc bxuGMU6ZOWX9xeIvEAvgiWNGAQ== X-Google-Smtp-Source: ACHHUZ5CC8puO7GbHdrVgRG7ffiHWCvaGNAWdqGja/m0zKO+WEDCYC8YY0TOxxarPk33O5HZVXHo5Q== X-Received: by 2002:a19:ca50:0:b0:4f8:578f:ace1 with SMTP id h16-20020a19ca50000000b004f8578face1mr13971019lfj.21.1687724749873; Sun, 25 Jun 2023 13:25:49 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id m21-20020a195215000000b004f8427f8716sm787537lfb.262.2023.06.25.13.25.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jun 2023 13:25:49 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v2 01/26] dt-bindings: opp: opp-v2-kryo-cpu: support Qualcomm Krait SoCs Date: Sun, 25 Jun 2023 23:25:22 +0300 Message-Id: <20230625202547.174647-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> References: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Exted the opp-v2-kryo-cpu.yaml to support defining OPP tables for the previous generation of Qualcomm CPUs, 32-bit Krait-based platforms. It makes no sense to use 'operating-points-v2-kryo-cpu' compatibility node for the Krait cores. Add support for the Krait-specific 'operating-points-v2-krait-cpu' compatibility string and the relevant opp-microvolt subclasses properties. The listed opp-supported-hw values are applicable only to msm8996 / msm8996pro platforms. Remove the enum as other platforms will use other bit values. It makes little sense to list all possible values for all the platforms here. Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/opp/opp-v2-kryo-cpu.yaml | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml index bbbad31ae4ca..4e84d06d5ff9 100644 --- a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml +++ b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml @@ -26,7 +26,9 @@ description: | properties: compatible: - const: operating-points-v2-kryo-cpu + enum: + - operating-points-v2-krait-cpu + - operating-points-v2-kryo-cpu nvmem-cells: description: | @@ -63,14 +65,16 @@ patternProperties: 5: MSM8996SG, speedbin 1 6: MSM8996SG, speedbin 2 7-31: unused - enum: [0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, - 0x9, 0xd, 0xe, 0xf, - 0x10, 0x20, 0x30, 0x70] + + Other platforms use bits directly corresponding to speedbin index. clock-latency-ns: true required-opps: true + patternProperties: + '^opp-microvolt-speed[0-9]+-pvs[0-9]+$': true + required: - opp-hz From patchwork Sun Jun 25 20:25:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 696302 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 607D0C001E0 for ; Sun, 25 Jun 2023 20:26:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229683AbjFYUZ7 (ORCPT ); Sun, 25 Jun 2023 16:25:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230029AbjFYUZz (ORCPT ); Sun, 25 Jun 2023 16:25:55 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A911E51 for ; Sun, 25 Jun 2023 13:25:52 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id 2adb3069b0e04-4fb761efa7aso148176e87.0 for ; Sun, 25 Jun 2023 13:25:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687724751; x=1690316751; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=k2Nz0ILPn3EOKaQkWVWab6M25ZwY+ZxoTLvBh9FKz8o=; b=iHoYbuvZhuPZTnglBCNcuLHF79uhlqOvP7dE81aDEKrCplUjQC9DEw223eqOOZmfjL xWUwpB8FiJoARTkuofkj1DhMRqnMTXmntJuwlOBtNgR8g4J6CDSX/dwX0F4WUKDJOlYC diXD1lVDI5c72kzm8srv0/5aIzCwQsdMh0Auh039Zcw97ldndgE7YhsNj6cYRO09tqwS 5vbBzndYhN0+EocERdet702eydlvA7WGcbN4iJ5tc7x5xwI9s7ObwjEa54BNJdGjbISX nepMXPsELwjzjoTf10LwcXW7WorBZN4Qy+q1oRLosRnryY+uSxLPg30DSIdrpSIQ3cIP GE6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687724751; x=1690316751; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=k2Nz0ILPn3EOKaQkWVWab6M25ZwY+ZxoTLvBh9FKz8o=; b=hPh6VITBC+s4MioO0hlA24sA2eG6Fguu2WEivH5+D7adyy3Ughxwg694MbUXeO5mYu txZnqfM2BDBaS0GrpW684nteIFHyTQubJePY8q95QgSjUzXxYeZmM8DXxyV4b1lvQDXQ zAjp9JtNH5T018Ton1WNWbU+DEa/e/opcjDkdeXsiSG7SRDw8B5SfCjcd9OHKGuofv9S gaKu33E7Q8psAoXFNCjIQYQX5YpJlva9vcSChzLzYYXeVuhi5oIeD0oImRIrSY0XltsO K1RA0KZkhkm/g1pmasZ9eLXibHZ4umjZ5CSK0wn6gV3KNPLYcYBic2WvPmTvxcxx8U1y RxCA== X-Gm-Message-State: AC+VfDxYj9vUMmNfcx0dBzjBt5iKR9odKz/3sNucVByoL6mxK9i9MMU7 p4AW5BN6qpbZlAIB5tKviD7hbw== X-Google-Smtp-Source: ACHHUZ6Mgbq0WTTe1FZF23x/VuJ9Cvbn9txxpD+uM9o8/8VD9zcT+uWuAd/VHmrMifKmSNOM293P3g== X-Received: by 2002:a19:5e01:0:b0:4f6:45af:70b8 with SMTP id s1-20020a195e01000000b004f645af70b8mr14700353lfb.58.1687724750738; Sun, 25 Jun 2023 13:25:50 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id m21-20020a195215000000b004f8427f8716sm787537lfb.262.2023.06.25.13.25.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jun 2023 13:25:50 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v2 02/26] dt-bindings: soc: qcom: merge qcom,saw2.txt into qcom,spm.yaml Date: Sun, 25 Jun 2023 23:25:23 +0300 Message-Id: <20230625202547.174647-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> References: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Qualcomm SPM / SAW2 device is described in two bindigns files: arm/msm/qcom,saw2.txt and soc/qcom/qcom,spm.yaml. Merge the former into the latter, adding detailed device node description. While we are at it, also rename qcom,spm.yaml to qcom,saw2.yaml to follow the actual compatible used for these devices. The regulator property is retained as is. It will be changed in the later patches. Signed-off-by: Dmitry Baryshkov Reviewed-by: Rob Herring --- .../devicetree/bindings/arm/msm/qcom,saw2.txt | 58 ------------------- .../qcom/{qcom,spm.yaml => qcom,saw2.yaml} | 26 +++++++-- 2 files changed, 20 insertions(+), 64 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt rename Documentation/devicetree/bindings/soc/qcom/{qcom,spm.yaml => qcom,saw2.yaml} (64%) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt deleted file mode 100644 index c0e3c3a42bea..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt +++ /dev/null @@ -1,58 +0,0 @@ -SPM AVS Wrapper 2 (SAW2) - -The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the -Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable -power-controller that transitions a piece of hardware (like a processor or -subsystem) into and out of low power modes via a direct connection to -the PMIC. It can also be wired up to interact with other processors in the -system, notifying them when a low power state is entered or exited. - -Multiple revisions of the SAW hardware are supported using these Device Nodes. -SAW2 revisions differ in the register offset and configuration data. Also, the -same revision of the SAW in different SoCs may have different configuration -data due the differences in hardware capabilities. Hence the SoC name, the -version of the SAW hardware in that SoC and the distinction between cpu (big -or Little) or cache, may be needed to uniquely identify the SAW register -configuration and initialization data. The compatible string is used to -indicate this parameter. - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: Must have - "qcom,saw2" - A more specific value could be one of: - "qcom,apq8064-saw2-v1.1-cpu" - "qcom,msm8226-saw2-v2.1-cpu" - "qcom,msm8974-saw2-v2.1-cpu" - "qcom,apq8084-saw2-v2.1-cpu" - -- reg: - Usage: required - Value type: - Definition: the first element specifies the base address and size of - the register region. An optional second element specifies - the base address and size of the alias register region. - -- regulator: - Usage: optional - Value type: boolean - Definition: Indicates that this SPM device acts as a regulator device - device for the core (CPU or Cache) the SPM is attached - to. - -Example 1: - - power-controller@2099000 { - compatible = "qcom,saw2"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - -Example 2: - saw0: power-controller@f9089000 { - compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml similarity index 64% rename from Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml rename to Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml index 20c8cd38ff0d..84b3f01d590c 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml @@ -1,18 +1,25 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/soc/qcom/qcom,spm.yaml# +$id: http://devicetree.org/schemas/soc/qcom/qcom,saw2.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Subsystem Power Manager +title: Qualcomm Subsystem Power Manager / SPM AVS Wrapper 2 (SAW2) maintainers: - Andy Gross - Bjorn Andersson description: | - This binding describes the Qualcomm Subsystem Power Manager, used to control - the peripheral logic surrounding the application cores in Qualcomm platforms. + The Qualcomm Subsystem Power Manager is used to control the peripheral logic + surrounding the application cores in Qualcomm platforms. + + The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the + Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable + power-controller that transitions a piece of hardware (like a processor or + subsystem) into and out of low power modes via a direct connection to + the PMIC. It can also be wired up to interact with other processors in the + system, notifying them when a low power state is entered or exited. properties: compatible: @@ -34,8 +41,15 @@ properties: - const: qcom,saw2 reg: - description: Base address and size of the SPM register region - maxItems: 1 + items: + - description: Base address and size of the SPM register region + - description: Base address and size of the alias register region + minItems: 1 + + regulator: + type: boolean + description: Indicates that this SPM device acts as a regulator device + device for the core (CPU or Cache) the SPM is attached to. required: - compatible From patchwork Sun Jun 25 20:25:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 696660 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81B95C001DE for ; Sun, 25 Jun 2023 20:25:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230058AbjFYUZ6 (ORCPT ); Sun, 25 Jun 2023 16:25:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60174 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229980AbjFYUZy (ORCPT ); Sun, 25 Jun 2023 16:25:54 -0400 Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 40CF8E53 for ; Sun, 25 Jun 2023 13:25:53 -0700 (PDT) Received: by mail-lj1-x22e.google.com with SMTP id 38308e7fff4ca-2b5c231c23aso16249671fa.0 for ; Sun, 25 Jun 2023 13:25:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687724751; x=1690316751; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YRhN5z1vU2RAXK0BYSOU9fT7Q2zkxmGWrbBmOJPqu/c=; b=QEq0MlSoDhCAgK7Ad/4bzzhE7sVEzWwEGM+g/ud1teYXtHZlgjUh/JmMpA609z5TEw d94US60qBZgOszxy+uxxiqG8UaVd27VGAnO1nQV2K19y8CGdG5iPjdsVuMYwYzoAw7Om UJdgMxtGqpCpnUUFaPHPQ6Ww5Y46enCG6KG5cptLoZl7c+nbAjja2cu9/DJtOPZGzeEg jw8cU3WwG/7O7QwomowSDBINedRaKhmo21cnr6EpwWu6tEruTZxKB3YxEevtDy7IpHHr n872IDfNr4Z5gWmilph7BrWvewu6bEqXApZG3MY7G3U79bxOuU9mGNBpNAsVcqBK2gu/ zoGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687724751; x=1690316751; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YRhN5z1vU2RAXK0BYSOU9fT7Q2zkxmGWrbBmOJPqu/c=; b=Yjwn6ZdhkiYbuBzCJ4VGL6B0IA40863BZOD27E/bI48yzowFBMvjM9jtNKcpmpX8HW LZMJlG2vfsJTASFmo9WCoFQ4aaogoe5DvAt+04vdpFOdVB9Q9vGG0ztHPgN62WAp40ud QL/qaf2qjMUQDGLn5ipDA+QhLbF5QGQwkM8X6T3I/nl/ottKuJH76/fKH1RWGlOGBnXF gCD/m9i1r4vS1UZoj54l1tS2Tp33XrlHNB6ydwxxLZpMdWvmHR5YaK8S0P2TSjo3fdDc Rde9BquwnH5LmmWSWpok1GJ7b/OQAISbYBIiEFwqhJdq1LMpFrz3QMwr6PM39IPYWx4w WOUQ== X-Gm-Message-State: AC+VfDxoUMgvQ9Ww4Klf8CNMNh/cjhb3liouSVNztCJ8+p2MPnCOSI9j iK3DhLwgIwfsLkPnrso4k0o55A== X-Google-Smtp-Source: ACHHUZ40qDwP1FylA6mHXt3RFgKjl1b/4Rndo841EDArO8bFNBKhDIw0wD1jFUK6fR/KiD7L7c4Sxg== X-Received: by 2002:ac2:5b83:0:b0:4f8:75af:e917 with SMTP id o3-20020ac25b83000000b004f875afe917mr10801640lfn.41.1687724751573; Sun, 25 Jun 2023 13:25:51 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id m21-20020a195215000000b004f8427f8716sm787537lfb.262.2023.06.25.13.25.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jun 2023 13:25:51 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v2 03/26] dt-bindings: soc: qcom: qcom,saw2: define optional regulator node Date: Sun, 25 Jun 2023 23:25:24 +0300 Message-Id: <20230625202547.174647-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> References: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SAW2 device can optionally provide a voltage regulator supplying the CPU core, cluster or L2 cache. Change the boolean 'regulator' property into a proper regulator description. This breaks schema compatibility for the sake of properly describing the regulator. Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/soc/qcom/qcom,saw2.yaml | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml index 84b3f01d590c..a2d871ba8c45 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml @@ -47,7 +47,7 @@ properties: minItems: 1 regulator: - type: boolean + $ref: /schemas/regulator/regulator.yaml# description: Indicates that this SPM device acts as a regulator device device for the core (CPU or Cache) the SPM is attached to. @@ -96,4 +96,17 @@ examples: reg = <0x17912000 0x1000>; }; + - | + /* + * Example 3: SAW2 with the bundled regulator definition. + */ + power-manager@2089000 { + compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; + + regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; + }; ... 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Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v2 04/26] dt-bindings: clock: qcom, krait-cc: Krait core clock controller Date: Sun, 25 Jun 2023 23:25:25 +0300 Message-Id: <20230625202547.174647-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> References: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Define bindings for the Qualcomm Krait CPU and L2 clock controller. This device is used on old Qualcomm SoCs (APQ8064, MSM8960) and supports up to 4 core clocks and a separate L2 clock. Furthermore, L2 clock is represented as the interconnect to facilitate L2 frequency scaling together with scaling the CPU frequencies. Signed-off-by: Dmitry Baryshkov Acked-by: Rob Herring --- include/dt-bindings/clock/qcom,krait-cc.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,krait-cc.h diff --git a/include/dt-bindings/clock/qcom,krait-cc.h b/include/dt-bindings/clock/qcom,krait-cc.h new file mode 100644 index 000000000000..ff69a0a968d8 --- /dev/null +++ b/include/dt-bindings/clock/qcom,krait-cc.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Linaro Ltd. All rights reserved. + */ + +#ifndef __DT_BINDINGS_CLOCK_QCOM_KRAIT_CC_H +#define __DT_BINDINGS_CLOCK_QCOM_KRAIT_CC_H + +#define KRAIT_CPU_0 0 +#define KRAIT_CPU_1 1 +#define KRAIT_CPU_2 2 +#define KRAIT_CPU_3 3 +#define KRAIT_L2 4 + +#define KRAIT_NUM_CLOCKS 5 + +#endif From patchwork Sun Jun 25 20:25:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 696658 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7251C05051 for ; Sun, 25 Jun 2023 20:26:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230003AbjFYU0B (ORCPT ); Sun, 25 Jun 2023 16:26:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230160AbjFYUZ6 (ORCPT ); Sun, 25 Jun 2023 16:25:58 -0400 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5D84BE4A for ; Sun, 25 Jun 2023 13:25:55 -0700 (PDT) Received: by mail-lf1-x129.google.com with SMTP id 2adb3069b0e04-4f86fbe5e4fso2965801e87.2 for ; Sun, 25 Jun 2023 13:25:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687724753; x=1690316753; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=P6IQl2jydqEVzMHgyvXGKi5dP1nmhqYFToeW0usGn04=; b=cCnMP6hgg80Wv1iohEYrspwKCL/eAfWkw4IHVVj4IbDRWAwtE4drLYNKdJyMNqtKen C90le5J112H8WfyG7Ej5c6n5+SaVfltC3Kn0heIh5PNwI/NAcr0Qnhwh2xSnshbpjz4A pChJxPAKHNiFs/DX48jFnLQhpHDjtZTrIDVvRGVPnk+ZFekdo9op3Ec19OYXJ+MQCl3h 3LnQ78ymAU9vRQxfId8yeg/eQtVMYT1QKiyxjNppSxceADNil98RxR9GkOPDH20g1lmk IAutLklX6PPG012cyZERYCQTb2CZg0q+5eHfxZFgKRbjaoepVtc/pSfDL3cFhtaD9n6D /naQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687724753; x=1690316753; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=P6IQl2jydqEVzMHgyvXGKi5dP1nmhqYFToeW0usGn04=; b=LFF7WeMpUCXSBOhCEiWhOsji7ZmN5yL9nQBIajo94CyW213wbm9O9KhxUFjcenFMwb yMibygx7BbSxz9XF5S8ks9WR9sgkXqp/L7KB2WlwdkY008DDR/UzASv99rer3Mf19djN yX8V3xZlVf3cdSD35YFzicbTP/PztTNJf13uX8dRm3HwBucZU2Sc4FysmGjDV7Cy6bsh ck1jaC/cv03a55M4iG5YdaT7uTHe6fVCLIas6oiK4biodwaMN91ZuHEHQWpnjj2YeKg5 vlTR+0Q24F0w12vAlbOVA/hK9/RvTkHvIGC36bqocdGgBpQ3Sr+jKmWaEid6c3jlbMqj qAKQ== X-Gm-Message-State: AC+VfDx8JqKTOZirWLk3Rfa0p1br5Ba4T/ZWzULVCPdk90ToQLkdHrXh jkKxbkThx9XCPBvuMHgGV75ZnA== X-Google-Smtp-Source: ACHHUZ7sdpONkCT0uFv1glG3RaUylMcRYeZ1VbX8RY+p/4zKS2XBEMJP4IeGiit/8MnyK9a4R4EpxQ== X-Received: by 2002:ac2:4db7:0:b0:4f8:5f19:4b49 with SMTP id h23-20020ac24db7000000b004f85f194b49mr13400874lfe.64.1687724753721; Sun, 25 Jun 2023 13:25:53 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id m21-20020a195215000000b004f8427f8716sm787537lfb.262.2023.06.25.13.25.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jun 2023 13:25:53 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v2 05/26] dt-bindings: cache: describe L2 cache on Qualcomm Krait platforms Date: Sun, 25 Jun 2023 23:25:26 +0300 Message-Id: <20230625202547.174647-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> References: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The L2 cache device on Qualcomm Krait platforms controls the supplying voltages and the cache frequency. Add corresponding bindings for this device. Signed-off-by: Dmitry Baryshkov --- .../bindings/cache/qcom,krait-l2-cache.yaml | 75 +++++++++++++++++++ include/dt-bindings/soc/qcom,krait-l2-cache.h | 12 +++ 2 files changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/cache/qcom,krait-l2-cache.yaml create mode 100644 include/dt-bindings/soc/qcom,krait-l2-cache.h diff --git a/Documentation/devicetree/bindings/cache/qcom,krait-l2-cache.yaml b/Documentation/devicetree/bindings/cache/qcom,krait-l2-cache.yaml new file mode 100644 index 000000000000..1dcf8165135b --- /dev/null +++ b/Documentation/devicetree/bindings/cache/qcom,krait-l2-cache.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Krait L2 Cache + +maintainers: + - Bjorn Andersson + +description: + L2 cache on Qualcomm Krait platforms is shared between all CPU cores. L2 + cache frequency and voltages should be scaled according to the needs of the + cores. + +allOf: + - $ref: ../cache-controller.yaml# + +properties: + compatible: + items: + - const: qcom,krait-l2-cache + - const: cache + + clocks: + maxItems: 1 + + '#interconnect-cells': + const: 1 + + vdd-mem-supply: + description: suppling regulator for the memory cells of the cache + + vdd-dig-supply: + description: suppling regulator for the digital logic of the cache + + operating-points-v2: true + opp-table-l2: true + +required: + - compatible + - cache-level + - cache-unified + - clocks + - '#interconnect-cells' + +unevaluatedProperties: false + +examples: + - | + #include + + l2-cache { + compatible = "qcom,krait-l2-cache", "cache"; + cache-level = <2>; + cache-unified; + vdd-mem-supply = <&pm8921_l24>; + vdd-dig-supply = <&pm8921_s3>; + clocks = <&kraitcc 4>; + #interconnect-cells = <1>; + operating-points-v2 = <&l2_opp_table>; + + l2_opp_table: opp-table-l2 { + compatible = "operating-points-v2"; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + opp-microvolt = <1050000 1050000 1150000>, + <950000 950000 1150000>; + }; + }; + }; +... + diff --git a/include/dt-bindings/soc/qcom,krait-l2-cache.h b/include/dt-bindings/soc/qcom,krait-l2-cache.h new file mode 100644 index 000000000000..c9a38d368111 --- /dev/null +++ b/include/dt-bindings/soc/qcom,krait-l2-cache.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Linaro Ltd. All rights reserved. + */ + +#ifndef __DT_BINDINGS_SOC_QCOM_KRAIT_L2_CACHE_H +#define __DT_BINDINGS_SOC_QCOM_KRAIT_L2_CACHE_H + +#define MASTER_KRAIT_L2 0 +#define SLAVE_KRAIT_L2 1 + +#endif From patchwork Sun Jun 25 20:25:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 696301 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1EB16C001B3 for ; Sun, 25 Jun 2023 20:26:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230088AbjFYU0C (ORCPT ); Sun, 25 Jun 2023 16:26:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60224 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230179AbjFYUZ7 (ORCPT ); Sun, 25 Jun 2023 16:25:59 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E9BBE5D for ; Sun, 25 Jun 2023 13:25:56 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id 2adb3069b0e04-4f96d680399so3180152e87.0 for ; Sun, 25 Jun 2023 13:25:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687724754; x=1690316754; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=39CekJt2bg+dTnou8ZXeVeRak2YiAVNMpxW8X6GTBtU=; b=pZePDbwLmTp5CLqETeMXeQZ8LeNEEJAsCxNROc/8NWe5DHz5jrO7Z92KfK//jBW3a/ TjgDvOCcJhph+mMXV0l/PBl9bFZey+1nUlCQCQT92KAOvsabPfWkqO3hi6E4/+fhBVM0 5M4TJC4hcA3Kr0TWaTWicZ6Tt5KCsJin005WvtdqLkGk6hctZRG0nuyJBiLKHy4E2M0A lxx61jJ7guior9/wseqgDaVHmmG00Ynx+qNT3BBAOg0ONKAhKVIOmS3dzgQF8tb6KjAB JP2Ey1OKM0hqzBeDKG5RU8hmaBCbE5TCwvsOAhrE0mlyItf6fBSpd+lC+G9wCjWPwmdP Wk+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687724754; x=1690316754; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=39CekJt2bg+dTnou8ZXeVeRak2YiAVNMpxW8X6GTBtU=; b=R67RXNgy03UoaupDRcoCF8MSQwuipUTBFlBdB9hO/yZH9lsFV/yNW2FS5JUAPNY8fr amHjaBGhBxamqjRZBjlg+r4uw6oc5IlvZMdjlJJ8FMu0S/xEy1YS+eLkhhE+eSfJu+r8 b4cJgpIguSEDLJFfrsBKxTe7xmu33cLjXOvJG+2+8kBJjr8ch739BK6BbWIBMNxrxZEK Q2TavWBRCmPDZoO+cxV6YzQe9JJGTKHLNX7K0H9/izZP80uuZV/LxeoJrRNetaASrMqF zqerOO5gmsSxNoNlV5zpdvSRzYTFvXkPthx6GfOKy7ejT7skkCa8pydEGB7hJHvY2x5p 3Eaw== X-Gm-Message-State: AC+VfDxvpOmkYidCzBy8XmcEWdzKehoKbwB6BX6lQNUp/L5S26pHK6YN jqbBY1xbgFX6EuvGCFOf9zu05JlKCx3HJ5ER8Ls= X-Google-Smtp-Source: ACHHUZ4eAaXE156DRPniC1J54MyG1vDnEpIan5OGQXdQv/iBAIM+CPW+jig6lpFAADo8yZAUq0tkeQ== X-Received: by 2002:a05:6512:3c88:b0:4f9:6a7b:b8de with SMTP id h8-20020a0565123c8800b004f96a7bb8demr6876714lfv.3.1687724754516; Sun, 25 Jun 2023 13:25:54 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id m21-20020a195215000000b004f8427f8716sm787537lfb.262.2023.06.25.13.25.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jun 2023 13:25:54 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v2 06/26] interconnect: icc-clk: add support for scaling using OPP Date: Sun, 25 Jun 2023 23:25:27 +0300 Message-Id: <20230625202547.174647-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> References: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Sometimes it might be required to scale the clock using the OPP framework (e.g. to scale regulators following the required clock rate). Extend the interconnec-clk framework to handle OPP case in addition to scaling the clock. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/icc-clk.c | 13 +++++++++++-- include/linux/interconnect-clk.h | 1 + 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/interconnect/icc-clk.c b/drivers/interconnect/icc-clk.c index 4d43ebff4257..c7962acdcee7 100644 --- a/drivers/interconnect/icc-clk.c +++ b/drivers/interconnect/icc-clk.c @@ -7,10 +7,13 @@ #include #include #include +#include struct icc_clk_node { + struct device *dev; struct clk *clk; bool enabled; + bool opp; }; struct icc_clk_provider { @@ -25,12 +28,16 @@ struct icc_clk_provider { static int icc_clk_set(struct icc_node *src, struct icc_node *dst) { struct icc_clk_node *qn = src->data; + unsigned long rate = icc_units_to_bps(src->peak_bw); int ret; if (!qn || !qn->clk) return 0; - if (!src->peak_bw) { + if (qn->opp) + return dev_pm_opp_set_rate(qn->dev, rate); + + if (!rate) { if (qn->enabled) clk_disable_unprepare(qn->clk); qn->enabled = false; @@ -45,7 +52,7 @@ static int icc_clk_set(struct icc_node *src, struct icc_node *dst) qn->enabled = true; } - return clk_set_rate(qn->clk, icc_units_to_bps(src->peak_bw)); + return clk_set_rate(qn->clk, rate); } static int icc_clk_get_bw(struct icc_node *node, u32 *avg, u32 *peak) @@ -106,7 +113,9 @@ struct icc_provider *icc_clk_register(struct device *dev, icc_provider_init(provider); for (i = 0, j = 0; i < num_clocks; i++) { + qp->clocks[i].dev = dev; qp->clocks[i].clk = data[i].clk; + qp->clocks[i].opp = data[i].opp; node = icc_node_create(first_id + j); if (IS_ERR(node)) { diff --git a/include/linux/interconnect-clk.h b/include/linux/interconnect-clk.h index 0cd80112bea5..c695e5099901 100644 --- a/include/linux/interconnect-clk.h +++ b/include/linux/interconnect-clk.h @@ -11,6 +11,7 @@ struct device; struct icc_clk_data { struct clk *clk; const char *name; + bool opp; }; struct icc_provider *icc_clk_register(struct device *dev, From patchwork Sun Jun 25 20:25:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 696299 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29E64C00528 for ; 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Sun, 25 Jun 2023 13:25:55 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id m21-20020a195215000000b004f8427f8716sm787537lfb.262.2023.06.25.13.25.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jun 2023 13:25:55 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v2 07/26] clk: qcom: krait-cc: rewrite driver to use clk_hw instead of clk Date: Sun, 25 Jun 2023 23:25:28 +0300 Message-Id: <20230625202547.174647-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> References: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The krait-cc driver still uses struct clk internally. Rewrite it to allocate and register struct clk_hw instead. Reviewed-by: Stephen Boyd Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/krait-cc.c | 141 ++++++++++++++++-------------------- 1 file changed, 63 insertions(+), 78 deletions(-) diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c index 410ae8390f1c..a37abbd31f50 100644 --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c @@ -13,17 +13,9 @@ #include #include -#include "clk-krait.h" - -enum { - cpu0_mux = 0, - cpu1_mux, - cpu2_mux, - cpu3_mux, - l2_mux, +#include - clks_max, -}; +#include "clk-krait.h" static unsigned int sec_mux_map[] = { 2, @@ -235,7 +227,7 @@ krait_add_pri_mux(struct device *dev, struct clk_hw *hfpll_div, struct clk_hw *s .parent_data = p_data, .num_parents = ARRAY_SIZE(p_data), .ops = &krait_mux_clk_ops, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, }; struct clk_hw *clk; char *hfpll_name; @@ -324,19 +316,6 @@ static struct clk_hw *krait_add_clks(struct device *dev, int id, bool unique_aux return pri_mux; } -static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data) -{ - unsigned int idx = clkspec->args[0]; - struct clk **clks = data; - - if (idx >= clks_max) { - pr_err("%s: invalid clock index %d\n", __func__, idx); - return ERR_PTR(-EINVAL); - } - - return clks[idx] ? : ERR_PTR(-ENODEV); -} - static const struct of_device_id krait_cc_match_table[] = { { .compatible = "qcom,krait-cc-v1", (void *)1UL }, { .compatible = "qcom,krait-cc-v2" }, @@ -344,60 +323,84 @@ static const struct of_device_id krait_cc_match_table[] = { }; MODULE_DEVICE_TABLE(of, krait_cc_match_table); +static int krait_clk_reinit(struct clk_hw *hw, int cpu) +{ + struct clk *clk; + unsigned long cur_rate, aux_rate; + char name[5]; /* CPUn */ + + if (cpu == -1) + strcpy(name, "L2"); + else + snprintf(name, sizeof(name), "CPU%d", cpu); + + clk = clk_hw_get_clk(hw, clk_hw_get_name(hw)); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + aux_rate = 384000000; + + cur_rate = clk_get_rate(clk); + if (cur_rate < aux_rate) { + pr_info("%s @ Undefined rate %lu. Forcing new rate.\n", + name, cur_rate / 1000); + cur_rate = aux_rate; + } + + clk_set_rate(clk, aux_rate); + clk_set_rate(clk, 2); + clk_set_rate(clk, cur_rate); + pr_info("%s @ %lu KHz\n", name, clk_get_rate(clk) / 1000); + + clk_put(clk); + + return 0; +} + +/* Krait configurations have at most 4 CPUs and one L2 */ +#define KRAIT_NUM_CLOCKS 5 + static int krait_cc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; const struct of_device_id *id; - unsigned long cur_rate, aux_rate; - int cpu; - struct clk_hw *mux, *l2_pri_mux; - struct clk *clk, **clks; + int cpu, ret; + struct clk_hw *clk; + struct clk_hw_onecell_data *clks; id = of_match_device(krait_cc_match_table, dev); if (!id) return -ENODEV; /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */ - clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); + clk = clk_hw_register_fixed_rate(dev, "qsb", NULL, 0, 1); if (IS_ERR(clk)) return PTR_ERR(clk); if (!id->data) { - clk = clk_register_fixed_factor(dev, "acpu_aux", - "gpll0_vote", 0, 1, 2); + clk = clk_hw_register_fixed_factor(dev, "acpu_aux", "gpll0_vote", 0, 1, 2); if (IS_ERR(clk)) return PTR_ERR(clk); } - /* Krait configurations have at most 4 CPUs and one L2 */ - clks = devm_kcalloc(dev, clks_max, sizeof(*clks), GFP_KERNEL); + clks = devm_kzalloc(dev, struct_size(clks, hws, KRAIT_NUM_CLOCKS), GFP_KERNEL); if (!clks) return -ENOMEM; + clks->num = KRAIT_NUM_CLOCKS; + BUILD_BUG_ON(KRAIT_L2 >= KRAIT_NUM_CLOCKS); + for_each_possible_cpu(cpu) { - mux = krait_add_clks(dev, cpu, id->data); - if (IS_ERR(mux)) - return PTR_ERR(mux); - clks[cpu] = mux->clk; + clk = krait_add_clks(dev, cpu, id->data); + if (IS_ERR(clk)) + return PTR_ERR(clk); + clks->hws[cpu] = clk; } - l2_pri_mux = krait_add_clks(dev, -1, id->data); - if (IS_ERR(l2_pri_mux)) - return PTR_ERR(l2_pri_mux); - clks[l2_mux] = l2_pri_mux->clk; - - /* - * We don't want the CPU or L2 clocks to be turned off at late init - * if CPUFREQ or HOTPLUG configs are disabled. So, bump up the - * refcount of these clocks. Any cpufreq/hotplug manager can assume - * that the clocks have already been prepared and enabled by the time - * they take over. - */ - for_each_online_cpu(cpu) { - clk_prepare_enable(clks[l2_mux]); - WARN(clk_prepare_enable(clks[cpu]), - "Unable to turn on CPU%d clock", cpu); - } + clk = krait_add_clks(dev, -1, id->data); + if (IS_ERR(clk)) + return PTR_ERR(clk); + clks->hws[KRAIT_L2] = clk; /* * Force reinit of HFPLLs and muxes to overwrite any potential @@ -410,31 +413,13 @@ static int krait_cc_probe(struct platform_device *pdev) * two different rates to force a HFPLL reinit under all * circumstances. */ - cur_rate = clk_get_rate(clks[l2_mux]); - aux_rate = 384000000; - if (cur_rate < aux_rate) { - pr_info("L2 @ Undefined rate. Forcing new rate.\n"); - cur_rate = aux_rate; - } - clk_set_rate(clks[l2_mux], aux_rate); - clk_set_rate(clks[l2_mux], 2); - clk_set_rate(clks[l2_mux], cur_rate); - pr_info("L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000); - for_each_possible_cpu(cpu) { - clk = clks[cpu]; - cur_rate = clk_get_rate(clk); - if (cur_rate < aux_rate) { - pr_info("CPU%d @ Undefined rate. Forcing new rate.\n", cpu); - cur_rate = aux_rate; - } + krait_clk_reinit(clks->hws[KRAIT_L2], -1); + for_each_possible_cpu(cpu) + krait_clk_reinit(clks->hws[cpu], cpu); - clk_set_rate(clk, aux_rate); - clk_set_rate(clk, 2); - clk_set_rate(clk, cur_rate); - pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000); - } - - of_clk_add_provider(dev->of_node, krait_of_get, clks); + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clks); + if (ret) + return ret; return 0; } From patchwork Sun Jun 25 20:25:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 696300 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A773CC10F1A for ; Sun, 25 Jun 2023 20:26:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230318AbjFYU0F (ORCPT ); Sun, 25 Jun 2023 16:26:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229835AbjFYU0A (ORCPT ); Sun, 25 Jun 2023 16:26:00 -0400 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3DBFAE6E for ; Sun, 25 Jun 2023 13:25:58 -0700 (PDT) Received: by mail-lf1-x12b.google.com with SMTP id 2adb3069b0e04-4f870247d6aso3107166e87.0 for ; Sun, 25 Jun 2023 13:25:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687724756; x=1690316756; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bK8WPsZQis5KBu/8sVzWIZ3oMBJ8zoaGC76tJyGSV0I=; b=LP6w4Lv5HH3pb/vol/VtoG0N1JyWKP/0XOvzkBVccwE+Arn9xHIfc/RUWq94Hw3RJh 5XcARLuBPz1+b3/S3X8CR2K//P+hKLQYepOoDrLJebq8/NxnQE8BbOyhwSsMyfJ/gyFO CtTLIDbnnX4NgCwVKa+mDeA81kK+a0PI7zjBw7sGX2/Hyw2inSoeWWBvcIw790chsLjT 04X9CXc/zvcc3OGgAqGBPF1XpkLpDuCRWc9NkfJIjWjo+yX+t5AlKMmHXvutr0Vd4gkE 3dy0qmEYNGxJucLn0eB4Coql2aajkCztp3eWilQOnzo/Tm57K4uTO7fvX5nml7EcPI5q 2owQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687724756; x=1690316756; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bK8WPsZQis5KBu/8sVzWIZ3oMBJ8zoaGC76tJyGSV0I=; b=dI1DuH1B0JSW0G/5aYiIA6TyL6NbAcROQ9dbQ2WEQWkOAYUdp/zjdcMSb9qSR/fFAF L/Wu/0IS7wkoPrLFvelHbxtVjK6kY3Rph/nytxJGxNzmOnhgsGNz4Q0FDpRpcXgXFEMo x89/Ba2HL/z/cJBh6lqXGYF+dxDjrTOZbngZbtw0pd22Fm1B+j2B61aLSCQaVLwKK+K/ 6LRp/4FNdMPh9Hc9A6Op13zL81cUcrvdly/cVqoiTQyrhP2uRmZPnkbFc2HYNuMaqtsN U5X6zha1Z2z0R/0WC1pdoZsp5VbJifnYb60159rT5mYOvjRrpHBXx6+k3xagudgCJFyc 0dlg== X-Gm-Message-State: AC+VfDztSWws9AVUTr116prkK6HByUNGeZVz/nZm4k6D6kz6t9zQfzYE 2g3BGol9vWqSRhEsIPnJ96hRvrH8hjiE+xAocag= X-Google-Smtp-Source: ACHHUZ644gw+qYgSvXbdbp5GGpaNIpOBqxqHPsuw928MfGb1WK6UwNqfAE8CitvGuXLsLwSGaAVnxQ== X-Received: by 2002:a05:6512:60e:b0:4f8:67d7:8712 with SMTP id b14-20020a056512060e00b004f867d78712mr13530971lfe.54.1687724756536; Sun, 25 Jun 2023 13:25:56 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id m21-20020a195215000000b004f8427f8716sm787537lfb.262.2023.06.25.13.25.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jun 2023 13:25:55 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v2 08/26] soc: qcom: spm: add support for voltage regulator Date: Sun, 25 Jun 2023 23:25:29 +0300 Message-Id: <20230625202547.174647-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> References: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SPM / SAW2 device also provides a voltage regulator functionality with optional AVS (Adaptive Voltage Scaling) support. The exact register sequence and voltage ranges differs from device to device. Signed-off-by: Dmitry Baryshkov --- drivers/soc/qcom/spm.c | 205 ++++++++++++++++++++++++++++++++++++++++- include/soc/qcom/spm.h | 9 ++ 2 files changed, 212 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c index a6cbeb40831b..3c16a7e1710c 100644 --- a/drivers/soc/qcom/spm.c +++ b/drivers/soc/qcom/spm.c @@ -9,19 +9,31 @@ #include #include #include +#include +#include #include #include #include #include #include +#include #include #include +#include +#include #include +#define FIELD_SET(current, mask, val) \ + (((current) & ~(mask)) | FIELD_PREP((mask), (val))) + #define SPM_CTL_INDEX 0x7f #define SPM_CTL_INDEX_SHIFT 4 #define SPM_CTL_EN BIT(0) +#define SPM_1_1_AVS_CTL_AVS_ENABLED BIT(27) +#define SPM_AVS_CTL_MIN_VLVL (0x3f << 10) +#define SPM_AVS_CTL_MAX_VLVL (0x3f << 17) + enum spm_reg { SPM_REG_CFG, SPM_REG_SPM_CTL, @@ -31,10 +43,12 @@ enum spm_reg { SPM_REG_PMIC_DATA_1, SPM_REG_VCTL, SPM_REG_SEQ_ENTRY, - SPM_REG_SPM_STS, + SPM_REG_STS0, + SPM_REG_STS1, SPM_REG_PMIC_STS, SPM_REG_AVS_CTL, SPM_REG_AVS_LIMIT, + SPM_REG_RST, SPM_REG_NR, }; @@ -171,6 +185,10 @@ static const struct spm_reg_data spm_reg_8226_cpu = { static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = { [SPM_REG_CFG] = 0x08, + [SPM_REG_STS0] = 0x0c, + [SPM_REG_STS1] = 0x10, + [SPM_REG_VCTL] = 0x14, + [SPM_REG_AVS_CTL] = 0x18, [SPM_REG_SPM_CTL] = 0x20, [SPM_REG_PMIC_DLY] = 0x24, [SPM_REG_PMIC_DATA_0] = 0x28, @@ -178,7 +196,12 @@ static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = { [SPM_REG_SEQ_ENTRY] = 0x80, }; +static void smp_set_vdd_v1_1(void *data); + /* SPM register data for 8064 */ +static struct linear_range spm_v1_1_regulator_range = + REGULATOR_LINEAR_RANGE(700000, 0, 56, 12500); + static const struct spm_reg_data spm_reg_8064_cpu = { .reg_offset = spm_reg_offset_v1_1, .spm_cfg = 0x1F, @@ -189,6 +212,10 @@ static const struct spm_reg_data spm_reg_8064_cpu = { 0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F }, .start_index[PM_SLEEP_MODE_STBY] = 0, .start_index[PM_SLEEP_MODE_SPC] = 2, + .set_vdd = smp_set_vdd_v1_1, + .range = &spm_v1_1_regulator_range, + .init_uV = 1300000, + .ramp_delay = 1250, }; static inline void spm_register_write(struct spm_driver_data *drv, @@ -240,6 +267,179 @@ void spm_set_low_power_mode(struct spm_driver_data *drv, spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val); } +static int spm_set_voltage_sel(struct regulator_dev *rdev, unsigned int selector) +{ + struct spm_driver_data *drv = rdev_get_drvdata(rdev); + + drv->volt_sel = selector; + + /* Always do the SAW register writes on the corresponding CPU */ + return smp_call_function_single(drv->reg_cpu, drv->reg_data->set_vdd, drv, true); +} + +static int spm_get_voltage_sel(struct regulator_dev *rdev) +{ + struct spm_driver_data *drv = rdev_get_drvdata(rdev); + + return drv->volt_sel; +} + +static const struct regulator_ops spm_reg_ops = { + .set_voltage_sel = spm_set_voltage_sel, + .get_voltage_sel = spm_get_voltage_sel, + .list_voltage = regulator_list_voltage_linear_range, + .set_voltage_time_sel = regulator_set_voltage_time_sel, +}; + +static void smp_set_vdd_v1_1(void *data) +{ + struct spm_driver_data *drv = data; + unsigned int vlevel = drv->volt_sel; + unsigned int vctl, data0, data1, avs_ctl, sts; + bool avs_enabled; + + vlevel |= 0x80; /* band */ + + avs_ctl = spm_register_read(drv, SPM_REG_AVS_CTL); + vctl = spm_register_read(drv, SPM_REG_VCTL); + data0 = spm_register_read(drv, SPM_REG_PMIC_DATA_0); + data1 = spm_register_read(drv, SPM_REG_PMIC_DATA_1); + + avs_enabled = avs_ctl & SPM_1_1_AVS_CTL_AVS_ENABLED; + + /* If AVS is enabled, switch it off during the voltage change */ + if (avs_enabled) { + avs_ctl &= ~SPM_1_1_AVS_CTL_AVS_ENABLED; + spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl); + } + + /* Kick the state machine back to idle */ + spm_register_write(drv, SPM_REG_RST, 1); + + vctl = FIELD_SET(vctl, 0xff, vlevel); + data0 = FIELD_SET(data0, 0xff, vlevel); + data1 = FIELD_SET(data1, 0x3f, vlevel); + data1 = FIELD_SET(data1, 0x3f << 16, vlevel); + + spm_register_write(drv, SPM_REG_VCTL, vctl); + spm_register_write(drv, SPM_REG_PMIC_DATA_0, data0); + spm_register_write(drv, SPM_REG_PMIC_DATA_1, data1); + + if (read_poll_timeout_atomic(spm_register_read, + sts, sts == vlevel, + 1, 200, false, + drv, SPM_REG_STS1)) { + dev_err_ratelimited(drv->dev, "timeout setting the voltage (%x %x)!\n", sts, vlevel); + goto enable_avs; + } + + if (avs_enabled) { + unsigned int max_avs = vlevel & 0x3f; + unsigned int min_avs = max(max_avs, 4U) - 4; + avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MIN_VLVL, min_avs); + avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MAX_VLVL, max_avs); + spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl); + } + +enable_avs: + if (avs_enabled) { + avs_ctl |= SPM_1_1_AVS_CTL_AVS_ENABLED; + spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl); + } +} + +static int spm_get_cpu(struct device *dev) +{ + int cpu; + bool found; + + for_each_possible_cpu(cpu) { + struct device_node *cpu_node, *saw_node; + + cpu_node = of_cpu_device_node_get(cpu); + if (!cpu_node) + continue; + + saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0); + found = (saw_node == dev->of_node); + of_node_put(saw_node); + of_node_put(cpu_node); + + if (found) + return cpu; + } + + /* L2 SPM is not bound to any CPU, tie it to CPU0 */ + + return 0; +} + +#ifdef CONFIG_REGULATOR +static int spm_register_regulator(struct device *dev, struct spm_driver_data *drv) +{ + struct regulator_config config = { + .dev = dev, + .driver_data = drv, + }; + struct regulator_desc *rdesc; + struct regulator_dev *rdev; + int ret; + bool found; + + if (!drv->reg_data->set_vdd) + return 0; + + rdesc = devm_kzalloc(dev, sizeof(*rdesc), GFP_KERNEL); + if (!rdesc) + return -ENOMEM; + + rdesc->name = "spm"; + rdesc->of_match = of_match_ptr("regulator"); + rdesc->type = REGULATOR_VOLTAGE; + rdesc->owner = THIS_MODULE; + rdesc->ops = &spm_reg_ops; + + rdesc->linear_ranges = drv->reg_data->range; + rdesc->n_linear_ranges = 1; + rdesc->n_voltages = rdesc->linear_ranges[rdesc->n_linear_ranges - 1].max_sel + 1; + rdesc->ramp_delay = drv->reg_data->ramp_delay; + + drv->reg_cpu = spm_get_cpu(dev); + dev_dbg(dev, "SAW2 bound to CPU %d\n", drv->reg_cpu); + + /* + * Program initial voltage, otherwise registration will also try + * setting the voltage, which might result in undervolting the CPU. + */ + drv->volt_sel = DIV_ROUND_UP(drv->reg_data->init_uV - rdesc->min_uV, + rdesc->uV_step); + ret = linear_range_get_selector_high(drv->reg_data->range, + drv->reg_data->init_uV, + &drv->volt_sel, + &found); + if (ret) { + dev_err(dev, "Initial uV value out of bounds\n"); + return ret; + } + + /* Always do the SAW register writes on the corresponding CPU */ + smp_call_function_single(drv->reg_cpu, drv->reg_data->set_vdd, drv, true); + + rdev = devm_regulator_register(dev, rdesc, &config); + if (IS_ERR(rdev)) { + dev_err(dev, "failed to register regulator\n"); + return PTR_ERR(rdev); + } + + return 0; +} +#else +static int spm_register_regulator(struct device *dev, struct spm_driver_data *drv) +{ + return 0; +} +#endif + static const struct of_device_id spm_match_table[] = { { .compatible = "qcom,sdm660-gold-saw2-v4.1-l2", .data = &spm_reg_660_gold_l2 }, @@ -292,6 +492,7 @@ static int spm_dev_probe(struct platform_device *pdev) return -ENODEV; drv->reg_data = match_id->data; + drv->dev = &pdev->dev; platform_set_drvdata(pdev, drv); /* Write the SPM sequences first.. */ @@ -319,7 +520,7 @@ static int spm_dev_probe(struct platform_device *pdev) if (drv->reg_data->reg_offset[SPM_REG_SPM_CTL]) spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY); - return 0; + return spm_register_regulator(&pdev->dev, drv); } static struct platform_driver spm_driver = { diff --git a/include/soc/qcom/spm.h b/include/soc/qcom/spm.h index 4951f9d8b0bd..9859ebe42003 100644 --- a/include/soc/qcom/spm.h +++ b/include/soc/qcom/spm.h @@ -30,11 +30,20 @@ struct spm_reg_data { u32 avs_limit; u8 seq[MAX_SEQ_DATA]; u8 start_index[PM_SLEEP_MODE_NR]; + + smp_call_func_t set_vdd; + /* for now we support only a single range */ + struct linear_range *range; + unsigned int ramp_delay; + unsigned int init_uV; }; struct spm_driver_data { void __iomem *reg_base; const struct spm_reg_data *reg_data; + struct device *dev; + unsigned int volt_sel; + int reg_cpu; }; void spm_set_low_power_mode(struct spm_driver_data *drv, From patchwork Sun Jun 25 20:25:30 2023 Content-Type: text/plain; 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Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v2 09/26] cpufreq: qcom-nvmem: create L2 cache device Date: Sun, 25 Jun 2023 23:25:30 +0300 Message-Id: <20230625202547.174647-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> References: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Scaling the frequencies on some of Qualcomm Krait platforms (e.g. APQ8064) also requires scaling of the L2 cache frequency. As the l2-cache device node is places under /cpus/ path, it is not created by default by the OF code. Create corresponding device here. Signed-off-by: Dmitry Baryshkov --- drivers/cpufreq/qcom-cpufreq-nvmem.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index a88b6fe5db50..ab78ef1531d0 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -380,6 +380,7 @@ static int __init qcom_cpufreq_init(void) { struct device_node *np = of_find_node_by_path("/"); const struct of_device_id *match; + unsigned int cpu; int ret; if (!np) @@ -390,6 +391,25 @@ static int __init qcom_cpufreq_init(void) if (!match) return -ENODEV; + for_each_possible_cpu(cpu) { + struct device *dev = get_cpu_device(cpu); + struct device_node *cache; + struct platform_device *pdev; + + cache = of_find_next_cache_node(dev->of_node); + if (!cache) + continue; + + if (of_device_is_compatible(cache, "qcom,krait-l2-cache")) { + pdev = of_platform_device_create(cache, NULL, NULL); + if (IS_ERR(pdev)) + pr_err("%s: %pe, failed to create L2 cache node\n", __func__, pdev); + /* the error is not fatal */ + } + + of_node_put(cache); + } + ret = platform_driver_register(&qcom_cpufreq_driver); if (unlikely(ret < 0)) return ret; From patchwork Sun Jun 25 20:25:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 696656 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D96B5C0015E for ; Sun, 25 Jun 2023 20:26:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230127AbjFYU0G (ORCPT ); Sun, 25 Jun 2023 16:26:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60232 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230161AbjFYU0C (ORCPT ); Sun, 25 Jun 2023 16:26:02 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 503EB1BB for ; Sun, 25 Jun 2023 13:26:00 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id 2adb3069b0e04-4fb7589b187so206752e87.1 for ; Sun, 25 Jun 2023 13:26:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687724758; x=1690316758; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=c1nKcaVfPItdNnd084tpWE4cy/erttO67WFc7s18El8=; b=riCQEjNydzQwD+qTxa7CaKEn+baUASyGj+qU2/kP2Qd5pyp0XQCVASg7oCW2Zefdsz tp1twjmhi1BZGDMpKDRbRY8Yj9eg6d5BRjB5FzMqaZNxf7y56KZHc/g/iAOSwkg2ZJ+H cqGjgwZOVOnbre/U/nfwe5t4X7DNMeAVnMSZ5vCtmF6Bzx4QVFcyK1fTalaWJKdW2goA RlzZJnWHYeOlRlO71s77CuM7+REmm+tOjZwAiSUJlsWxWG2l8bWVOb9Hp657/DSqf6bv Ogm2hDCD5aJXNYXkM3uUu9EHfP9nqWCc64Gj43AVb9hExtzOWkeZ5afX/YxJMoFFVOZw vrvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687724758; x=1690316758; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c1nKcaVfPItdNnd084tpWE4cy/erttO67WFc7s18El8=; b=BkRBsXsjUHY7t8Tld3whLrLgIUk2HmSeJ72U7irzTn639S8mOeQAR7xafNPKNR84kh /K6TWdme63nJ12O7wiCLFXlukHQ0MJD//GGoCDX7ZwEKs+qzDF5pq7RBlw3sBGbbPk5h Yw9FrgyPAQImin/PyNr9Ze0UaSnPYhGBA8Tf3zyaFOdYC1LjRgFz+YBOnTkc57GxSCIs klZLMN7FSvWzfUoDttcLFTW61S3XfPe0u4O2xqncbmZqvcKOpM7yZltFI2BKDVMCq0at RLoygMEpCM+YU5n+V2Vz41NP1ehNtXZ4tv8QE3BRT9gUl+s3bQwEGjZ9Y8dUEpiRxcTS s0vA== X-Gm-Message-State: AC+VfDwAjG1s5TMiTLGaUv1h+ONFIWueKf9zRGALkrHt3LbO/+xRXNgR Cfl2GP6mQlAlyVFE9OY2/A3Y8Q== X-Google-Smtp-Source: ACHHUZ7yAvIsFKBxHC7sl8caX8317B5sQI87G5FhbotJEhsvBrXKjimmTAeipHRKpBfBqSkMSxabsQ== X-Received: by 2002:a05:6512:1d1:b0:4f8:6534:c6fa with SMTP id f17-20020a05651201d100b004f86534c6famr14210147lfp.63.1687724758643; Sun, 25 Jun 2023 13:25:58 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id m21-20020a195215000000b004f8427f8716sm787537lfb.262.2023.06.25.13.25.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jun 2023 13:25:57 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v2 10/26] cpufreq: qcom-nvmem: also accept operating-points-v2-krait-cpu Date: Sun, 25 Jun 2023 23:25:31 +0300 Message-Id: <20230625202547.174647-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> References: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org the qcom-cpufreq-nvmem driver attempts to support both Qualcomm Kryo (newer 64-bit ARMv8 cores) and Krait (older 32-bit ARMv7 cores). It makes no sense to use 'operating-points-v2-kryo-cpu' compatibility node for the Krait cores. Add support for 'operating-points-v2-krait-cpu' compatibility string. Signed-off-by: Dmitry Baryshkov --- drivers/cpufreq/qcom-cpufreq-nvmem.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index ab78ef1531d0..3bb552f498da 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -238,7 +238,8 @@ static int qcom_cpufreq_probe(struct platform_device *pdev) if (!np) return -ENOENT; - ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu"); + ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu") || + of_device_is_compatible(np, "operating-points-v2-krait-cpu"); if (!ret) { of_node_put(np); return -ENOENT; From patchwork Sun Jun 25 20:25:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 696298 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1A29C16B13 for ; Sun, 25 Jun 2023 20:26:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230161AbjFYU0H (ORCPT ); Sun, 25 Jun 2023 16:26:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60410 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230254AbjFYU0C (ORCPT ); Sun, 25 Jun 2023 16:26:02 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 266E1E54 for ; Sun, 25 Jun 2023 13:26:01 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id 2adb3069b0e04-4f6283d0d84so3311619e87.1 for ; Sun, 25 Jun 2023 13:26:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687724759; x=1690316759; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BPFo4vKtlliqmSpWNYdoeOen7rdyhvMtSIlE/C3NlFc=; b=l7Iixw7bug4ZuSJSq92NLEKBeeOCDFLRM9fUqVow4EFu3DB144HUL/du2+0+zCmw38 vEy76L7n9elywaxnpowMvUVRVjF4ikybsg3NBhGLVqoB+h68vzbzh/YARwIzsNWZBT7y jprdiGgckq8OsIgKeJ2cMjh6kX85s1yTwlsg3wtI+Z3MoInyi0Vmw9wcDwNE0yvFJpBy dlppI+O2/yjZH/Hce2hXZTbGyvGKBBFTJw/jetVNJDhZ3a4VchL6iMbY39+B0yOl2Vzr BJ7/rviOWoFTUkgOg3DYdbnGovehUPgBqTvM5Qtgg4CtCf9ml6WS+LeleUzXiDiJMfkT 3ndw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687724759; x=1690316759; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BPFo4vKtlliqmSpWNYdoeOen7rdyhvMtSIlE/C3NlFc=; b=M0IXrLSQ66a5Vd41m/Hh9mCvjSErcqCCrOpzlxad46VGxq4LFWYD5BG7LL6m29rv9M 7cesbn4CCoezKuBOja46pENmkMBA6e1Y90YUTxhuYdxwFkRKNnVjiLSEhkbMGXNG22kI XtCcrritHE0MpYLw+SEYjy+N/YNogSkp8lJylB1K13nLKgElx0+DK+/s4qpEC9DLm2d2 3ZKhPk0MVuS0pFvs66qVTIUnUT+IseLIAl383f+MTq7WTNsmEcifbjCgZC8jeQ6j5PpW mMsX9MugTO6VHbHIN6amASarTeSMXh44DAMIEc/a8kGlNzVo+ptsV86x3P8mrV1+sX65 u0BQ== X-Gm-Message-State: AC+VfDzDVaBFWMQ7NyA35thUegBMX3PREf3JpTKSx9vs7zrlMNPR+ziX 0xci0t5dYawSIB4xgcpaQRXP8w== X-Google-Smtp-Source: ACHHUZ67qlVEM58Z7E3cNlLy9cCNX4saDLR1Z/Yn3BJTJjlnM0dntiGhCZ22xsM/PzVWdXYYb767cw== X-Received: by 2002:a19:e346:0:b0:4f8:3b17:e0c7 with SMTP id c6-20020a19e346000000b004f83b17e0c7mr15294424lfk.7.1687724759483; Sun, 25 Jun 2023 13:25:59 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id m21-20020a195215000000b004f8427f8716sm787537lfb.262.2023.06.25.13.25.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jun 2023 13:25:58 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v2 11/26] cpufreq: qcom-nvmem: drop pvs_ver for format a fuses Date: Sun, 25 Jun 2023 23:25:32 +0300 Message-Id: <20230625202547.174647-12-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> References: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The fuses used on msm8960 / apq8064 / ipq806x families of devices do not have the pvs version. Drop this argument from parsing function. Signed-off-by: Dmitry Baryshkov --- drivers/cpufreq/qcom-cpufreq-nvmem.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index 3bb552f498da..2a591fafc090 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -50,7 +50,7 @@ struct qcom_cpufreq_drv { static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev; static void get_krait_bin_format_a(struct device *cpu_dev, - int *speed, int *pvs, int *pvs_ver, + int *speed, int *pvs, u8 *buf) { u32 pte_efuse; @@ -181,7 +181,7 @@ static int qcom_cpufreq_krait_name_version(struct device *cpu_dev, switch (len) { case 4: - get_krait_bin_format_a(cpu_dev, &speed, &pvs, &pvs_ver, + get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin); break; case 8: From patchwork Sun Jun 25 20:25:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 696655 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 802D4C19F4F for ; Sun, 25 Jun 2023 20:26:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230358AbjFYU0I (ORCPT ); Sun, 25 Jun 2023 16:26:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229566AbjFYU0E (ORCPT ); Sun, 25 Jun 2023 16:26:04 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 34B96E6B for ; Sun, 25 Jun 2023 13:26:02 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id 2adb3069b0e04-4f95bf5c493so2953670e87.3 for ; Sun, 25 Jun 2023 13:26:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687724760; x=1690316760; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6jaBkKadUWtDPt8dHILR5FATfH/ynS29hE6HSGf3w28=; b=III+FM6TGR05oyymoH1LKGFmfljglFSvDwH+Y2ibmh1pMegZumIsAay0iIym03uxPF vCHbT1y7/FgQfnN2HErxAflP21OJuS7ZTq0n2n0j+hu5nSDCiisYwXW2av9J1c1WWw8x 7q1XXUTkKcYqbgWKH+v1WEDwIRVs2KqFN8SkLzPTafBaphuVUBzNLsRrGE17BBJD87E6 iUO5u/Len+aiMP+TiFjkMU3c6AdnSC5QYKu/59mf/9mkuqv9uR5MioWPrD9YUkQ0FD+z er/bUArXoU+zpplZLLOO58E29lOVXfzCEtK0N0IAT3jE25q3wUEtqTBxS0Y070wVRoIa EKiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687724760; x=1690316760; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6jaBkKadUWtDPt8dHILR5FATfH/ynS29hE6HSGf3w28=; b=P9QiEVcBylgG7HbrcfHaPA3pKxa2QJIs58luyjKa1pzb8Xse/xB0xptM25wTjaoH8d 9M7kGRDmx1oWNCUZt+b1lU9jSpAwuRqfSOVBWot/XuUf+ktfc6v6rz1GVDLN/zBLc+gG iY5P0qXowaHwN+hXInKvVNwzi7enHEQggcbPuZtD9PxE0iwXb1wkNrOqobHuIyBQOYKn MzOa6tY52ZY9gX+A1HdSTqZu5PKCmThHy5z6CGcmkIOa1y9y1gsdwWauP29tDKLtIIf6 f+H9gGpNth5gdmsS000XATllA6uH8UBTZ1G3mblxubmZi4p4g+rriOFamGvnk35ojhSc 0aKw== X-Gm-Message-State: AC+VfDx/ItIjE69pA7/8vE3ehjEDRGJv0L+Q6CJvGvadw6rVzy1fV40/ 3Onjt/7ayUIehyPJeIzmmus4kg== X-Google-Smtp-Source: ACHHUZ5+tEEkhinGLyR8nEY1Y99x7FKrJLFxvUHnVTekjen88gHvbXLirp5ZmcmInitLAlctgSsf7w== X-Received: by 2002:a05:6512:2314:b0:4fa:21d4:b3ca with SMTP id o20-20020a056512231400b004fa21d4b3camr1465859lfu.2.1687724760466; Sun, 25 Jun 2023 13:26:00 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id m21-20020a195215000000b004f8427f8716sm787537lfb.262.2023.06.25.13.25.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jun 2023 13:25:59 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v2 12/26] cpufreq: qcom-nvmem: provide separate configuration data for apq8064 Date: Sun, 25 Jun 2023 23:25:33 +0300 Message-Id: <20230625202547.174647-13-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> References: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org APQ8064 can scale core voltage according to the frequency needs. Rather than reusing the A/B format multiplexer, use a simple fuse parsing function and configure required regulator. Signed-off-by: Dmitry Baryshkov --- drivers/cpufreq/qcom-cpufreq-nvmem.c | 49 ++++++++++++++++++++++++++-- 1 file changed, 47 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index 2a591fafc090..9cbc37ce91a8 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include @@ -39,6 +40,7 @@ struct qcom_cpufreq_match_data { char **pvs_name, struct qcom_cpufreq_drv *drv); const char **genpd_names; + const char * const *regulator_names; }; struct qcom_cpufreq_drv { @@ -204,6 +206,34 @@ static int qcom_cpufreq_krait_name_version(struct device *cpu_dev, return ret; } +static int qcom_cpufreq_apq8064_name_version(struct device *cpu_dev, + struct nvmem_cell *speedbin_nvmem, + char **pvs_name, + struct qcom_cpufreq_drv *drv) +{ + int speed = 0, pvs = 0; + u8 *speedbin; + size_t len; + int ret = 0; + + speedbin = nvmem_cell_read(speedbin_nvmem, &len); + if (IS_ERR(speedbin)) + return PTR_ERR(speedbin); + + if (len != 4) + return -EINVAL; + + get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin); + + snprintf(*pvs_name, sizeof("speedXX-pvsXX"), "speed%d-pvs%d", + speed, pvs); + + drv->versions = (1 << speed); + + kfree(speedbin); + return ret; +} + static const struct qcom_cpufreq_match_data match_data_kryo = { .get_version = qcom_cpufreq_kryo_name_version, }; @@ -218,6 +248,16 @@ static const struct qcom_cpufreq_match_data match_data_qcs404 = { .genpd_names = qcs404_genpd_names, }; +static const char * apq8064_regulator_names[] = { + "vdd-core", + NULL +}; + +static const struct qcom_cpufreq_match_data match_data_apq8064 = { + .get_version = qcom_cpufreq_apq8064_name_version, + .regulator_names = apq8064_regulator_names, +}; + static int qcom_cpufreq_probe(struct platform_device *pdev) { struct qcom_cpufreq_drv *drv; @@ -305,7 +345,12 @@ static int qcom_cpufreq_probe(struct platform_device *pdev) config.virt_devs = NULL; } - if (config.supported_hw || config.genpd_names) { + if (drv->data->regulator_names) + config.regulator_names = drv->data->regulator_names; + + if (config.supported_hw || + config.genpd_names || + config.regulator_names) { drv->opp_tokens[cpu] = dev_pm_opp_set_config(cpu_dev, &config); if (drv->opp_tokens[cpu] < 0) { ret = drv->opp_tokens[cpu]; @@ -364,7 +409,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = { { .compatible = "qcom,msm8996", .data = &match_data_kryo }, { .compatible = "qcom,qcs404", .data = &match_data_qcs404 }, { .compatible = "qcom,ipq8064", .data = &match_data_krait }, - { .compatible = "qcom,apq8064", .data = &match_data_krait }, + { .compatible = "qcom,apq8064", .data = &match_data_apq8064 }, { .compatible = "qcom,msm8974", .data = &match_data_krait }, { .compatible = "qcom,msm8960", .data = &match_data_krait }, {}, From patchwork Sun Jun 25 20:25:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 696654 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2155DC04FE0 for ; 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Sun, 25 Jun 2023 13:26:01 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id m21-20020a195215000000b004f8427f8716sm787537lfb.262.2023.06.25.13.26.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jun 2023 13:26:00 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v2 13/26] soc: qcom: Add driver for Qualcomm Krait L2 cache scaling Date: Sun, 25 Jun 2023 23:25:34 +0300 Message-Id: <20230625202547.174647-14-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> References: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a simple driver that handles scaling of L2 frequency and voltages. Signed-off-by: Dmitry Baryshkov --- drivers/soc/qcom/Kconfig | 9 ++ drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/krait-l2-cache.c | 190 ++++++++++++++++++++++++++++++ 3 files changed, 200 insertions(+) create mode 100644 drivers/soc/qcom/krait-l2-cache.c diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index e597799e8121..01090b7a3c06 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -70,6 +70,15 @@ config QCOM_LLCC SDM845. This provides interfaces to clients that use the LLCC. Say yes here to enable LLCC slice driver. +config QCOM_KRAIT_L2_CACHE + tristate "Qualcomm Krait L2 cache scaling" + depends on ARCH_QCOM && ARM || COMPILE_TEST + select INTERCONNECT + select INTERCONNECT_CLK + default ARM_QCOM_CPUFREQ_NVMEM + help + The driver for scaling the L2 cache frequency on Qualcomm Krait platforms. + config QCOM_KRYO_L2_ACCESSORS bool depends on (ARCH_QCOM || COMPILE_TEST) && ARM64 diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index 99114c71092b..cdd1cc96e9f9 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_QCOM_APR) += apr.o obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o +obj-$(CONFIG_QCOM_KRAIT_L2_CACHE) += krait-l2-cache.o obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) += kryo-l2-accessors.o obj-$(CONFIG_QCOM_ICC_BWMON) += icc-bwmon.o qcom_ice-objs += ice.o diff --git a/drivers/soc/qcom/krait-l2-cache.c b/drivers/soc/qcom/krait-l2-cache.c new file mode 100644 index 000000000000..af9e7b955daf --- /dev/null +++ b/drivers/soc/qcom/krait-l2-cache.c @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023, Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +/* Random ID that doesn't clash with main qnoc and OSM */ +#define L2_MASTER_NODE 2000 + +/* vdd-mem and vdd-dig */ +#define NUM_SUPPLIES 2 +static int krait_l2_config_regulators(struct device *dev, + struct dev_pm_opp *old_opp, + struct dev_pm_opp *new_opp, + struct regulator **regulators, + unsigned int count) +{ + struct dev_pm_opp_supply supplies[NUM_SUPPLIES]; + unsigned long old_freq, freq; + unsigned int i; + int ret; + + if (WARN_ON_ONCE(count != NUM_SUPPLIES)) + return -EINVAL; + + ret = dev_pm_opp_get_supplies(new_opp, supplies); + if (WARN_ON(ret)) + return ret; + + old_freq = dev_pm_opp_get_freq(old_opp); + freq = dev_pm_opp_get_freq(new_opp); + + WARN_ON(!old_freq || !freq); + if (freq > old_freq) { + for (i = 0; i < count; i++) { + struct regulator *reg = regulators[i]; + struct dev_pm_opp_supply *supply = &supplies[i]; + + dev_dbg(dev, "%s: voltages (mV): %lu %lu %lu\n", __func__, + supply->u_volt_min, supply->u_volt, supply->u_volt_max); + + ret = regulator_set_voltage_triplet(reg, + supply->u_volt_min, + supply->u_volt, + supply->u_volt_max); + if (ret) { + dev_err(dev, "%s: failed to set voltage (%lu %lu %lu mV): %d\n", + __func__, supply->u_volt_min, supply->u_volt, + supply->u_volt_max, ret); + goto restore_backwards; + } + } + } else { + for (i = count; i > 0; i--) { + struct regulator *reg = regulators[i - 1]; + struct dev_pm_opp_supply *supply = &supplies[i - 1]; + + dev_dbg(dev, "%s: voltages (mV): %lu %lu %lu\n", __func__, + supply->u_volt_min, supply->u_volt, supply->u_volt_max); + + ret = regulator_set_voltage_triplet(reg, + supply->u_volt_min, + supply->u_volt, + supply->u_volt_max); + if (ret) { + dev_err(dev, "%s: failed to set voltage (%lu %lu %lu mV): %d\n", + __func__, supply->u_volt_min, supply->u_volt, + supply->u_volt_max, ret); + goto restore_forward; + } + } + } + + return 0; + +restore_backwards: + + dev_pm_opp_get_supplies(old_opp, supplies); + + for (; i > 0; i--) { + struct regulator *reg = regulators[i - 1]; + struct dev_pm_opp_supply *supply = &supplies[i - 1]; + + dev_dbg(dev, "%s: voltages (mV): %lu %lu %lu\n", __func__, + supply->u_volt_min, supply->u_volt, supply->u_volt_max); + + regulator_set_voltage_triplet(reg, + supply->u_volt_min, + supply->u_volt, + supply->u_volt_max); + } + + return ret; + +restore_forward: + + dev_pm_opp_get_supplies(old_opp, supplies); + + for ( ; i < count; i++) { + struct regulator *reg = regulators[i]; + struct dev_pm_opp_supply *supply = &supplies[i]; + + dev_dbg(dev, "%s: voltages (mV): %lu %lu %lu\n", __func__, + supply->u_volt_min, supply->u_volt, supply->u_volt_max); + + regulator_set_voltage_triplet(reg, + supply->u_volt_min, + supply->u_volt, + supply->u_volt_max); + } + + return ret; +} + +static int krait_l2_probe(struct platform_device *pdev) +{ + struct dev_pm_opp_config krait_l2_cfg = { + .clk_names = (const char * const[]) { NULL, NULL }, + .config_regulators = krait_l2_config_regulators, + .regulator_names = (const char * const[]) { "vdd-mem", "vdd-dig", NULL }, + }; + struct icc_clk_data data[] = { + { .name = "l2", .opp = true}, + }; + + struct device *dev = &pdev->dev; + struct icc_provider *provider; + struct clk *clk; + int ret; + + clk = devm_clk_get(dev, NULL); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + ret = devm_pm_opp_set_config(dev, &krait_l2_cfg); + if (ret) + return ret; + + ret = devm_pm_opp_of_add_table(dev); + if (ret) + return ret; + + data[0].clk = clk; + provider = icc_clk_register(dev, L2_MASTER_NODE, ARRAY_SIZE(data), data); + if (IS_ERR(provider)) + return PTR_ERR(provider); + + platform_set_drvdata(pdev, provider); + + return 0; +} + +static int krait_l2_remove(struct platform_device *pdev) +{ + struct icc_provider *provider = platform_get_drvdata(pdev); + + icc_clk_unregister(provider); + + return 0; +} + +static const struct of_device_id krait_l2_match_table[] = { + { .compatible = "qcom,krait-l2-cache" }, + {} +}; +MODULE_DEVICE_TABLE(of, krait_l2_match_table); + +static struct platform_driver krait_l2_driver = { + .probe = krait_l2_probe, + .remove = krait_l2_remove, + .driver = { + .name = "qcom-krait-l2", + .of_match_table = krait_l2_match_table, + .sync_state = icc_sync_state, + }, +}; + +module_platform_driver(krait_l2_driver); + +MODULE_DESCRIPTION("Qualcomm Krait L2 scaling driver"); +MODULE_LICENSE("GPL v2"); From patchwork Sun Jun 25 20:25:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 696297 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05117C25B74 for ; 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Sun, 25 Jun 2023 13:26:02 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id m21-20020a195215000000b004f8427f8716sm787537lfb.262.2023.06.25.13.26.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jun 2023 13:26:01 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v2 14/26] ARM: dts: qcom: apq8064: rename SAW nodes to power-manager Date: Sun, 25 Jun 2023 23:25:35 +0300 Message-Id: <20230625202547.174647-15-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> References: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Per the power-domain.yaml, the power-controller node name is reserved for power-domain providers. Rename SAW2 nodes to 'power-manager', the name which is suggested by qcom,spm.yaml Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index d2289205ff81..471eeca6a589 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -422,25 +422,25 @@ acc3: clock-controller@20b8000 { #clock-cells = <0>; }; - saw0: power-controller@2089000 { + saw0: power-manager@2089000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw1: power-controller@2099000 { + saw1: power-manager@2099000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw2: power-controller@20a9000 { + saw2: power-manager@20a9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw3: power-controller@20b9000 { + saw3: power-manager@20b9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; regulator; From patchwork Sun Jun 25 20:25:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 696653 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B81CCEB64DC for ; Sun, 25 Jun 2023 20:26:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230224AbjFYU0N (ORCPT ); Sun, 25 Jun 2023 16:26:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60224 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230169AbjFYU0H (ORCPT ); Sun, 25 Jun 2023 16:26:07 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B3F0EE65 for ; Sun, 25 Jun 2023 13:26:04 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id 2adb3069b0e04-4f954d7309fso3146112e87.1 for ; Sun, 25 Jun 2023 13:26:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687724763; x=1690316763; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gqYfKELW1+wrqPsZqRcnDYBPEPnkcviMkJ4jXzmrQAY=; b=WB7c8ob6gjoKG2Y0dUtc9a/UKvDIXuy4Acx7sOxoEidLA46Qdr2q0OL1He+tLcclLE H9FAxVcQbaVKhZ/k48N+c5VqM3qInnxzG+tWCvI8B7EaJ3CDLgCi8KEJOWJUjbpOL8w+ oPl25pRcQPZnZiOwZ60CPsKSbxxFfZF3Xj4FAJS03BykVfF+88QsOOCb1QLyssXMphV/ VqrUiECrnDParhb+VEHtAqrW7rebfdbcFJrpHlUDNBGVs+0o9TOBlTdHgstKGTJ9HV9l sTGEyzh4Mt2H/fHKHjLH9ME/V2Fa690xDD+SRKkPLXGuHjXDWraVhYO+wo7LuchSrZCb ZXwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687724763; x=1690316763; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gqYfKELW1+wrqPsZqRcnDYBPEPnkcviMkJ4jXzmrQAY=; b=BFxPTsJWKFK9VkCG/YzbjKlnuNoOKKON0VLjA4HA6tYi7AWlDs0SaNqdou85pKcbg5 eE6akNleT+XOe4uazVfXdonxQJTIY8dK0S7I+k2qI4yqbcxGi5Q3/o41+VLdEgN2Mipo 89nYjMbF7Q53aVi+1PC3ezWe1Qa3NjrFaaHTlIGn2m0OQD8LPrcuqKjChY/AZh0cxtrl 5py4+Ex67qmGa/zVc6j1sKHXrQAAzUOFBWa4p0fvNOT+RJvSH4Z+nScBFTiJaX46IsDf lrZUT9LBOB3sDMxNSwQBr7eGI/ScO0RHMGpYQAMsA9R/mR8qBCkFjJrWMl0CHS4LIS6j fm5g== X-Gm-Message-State: AC+VfDwyrAFFKASY08AkCkqbE/GiONJfRU8dVguQUBSUbS0SM41qUOda 9ohMp5s4RJnDLWR8lCZ8lR1y4w== X-Google-Smtp-Source: ACHHUZ66sG2YdOyyWQNbNN2f5oMRfBf+HALD5+I6vSStwtWpPZoO7gqk6SSw9Tijyo1NrGhfmNFjjw== X-Received: by 2002:a19:7115:0:b0:4f3:b242:aa98 with SMTP id m21-20020a197115000000b004f3b242aa98mr9732949lfc.30.1687724762965; Sun, 25 Jun 2023 13:26:02 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id m21-20020a195215000000b004f8427f8716sm787537lfb.262.2023.06.25.13.26.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jun 2023 13:26:02 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v2 15/26] ARM: dts: qcom: apq8064: declare SAW2 regulators Date: Sun, 25 Jun 2023 23:25:36 +0300 Message-Id: <20230625202547.174647-16-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> References: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SAW2 (SPM and AVS Wrapper) among other things is yet another way to handle CPU-related PMIC regulators. Provide a way to control voltage of these regulators. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 471eeca6a589..1eb6d752ebae 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -425,25 +425,41 @@ acc3: clock-controller@20b8000 { saw0: power-manager@2089000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw0_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; saw1: power-manager@2099000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw1_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; saw2: power-manager@20a9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw2_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; saw3: power-manager@20b9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw3_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; sps_sic_non_secure: sps-sic-non-secure@12100000 { From patchwork Sun Jun 25 20:25:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 696296 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC02BC25B7A for ; Sun, 25 Jun 2023 20:26:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230223AbjFYU0M (ORCPT ); Sun, 25 Jun 2023 16:26:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229566AbjFYU0L (ORCPT ); Sun, 25 Jun 2023 16:26:11 -0400 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E617EE5A for ; Sun, 25 Jun 2023 13:26:05 -0700 (PDT) Received: by mail-lf1-x129.google.com with SMTP id 2adb3069b0e04-4f973035d60so2938341e87.3 for ; Sun, 25 Jun 2023 13:26:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687724764; x=1690316764; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7H4gfmiVKhRklk1FA6KTDQbQYJQQYujXQM62+zAj3hY=; b=MDC/ONeIcfezrE/OusI5lHeb8A/X2/wJJZoZdQmgfHH6pAqJNm6q8ZAxsPrUmgyQzU Yh+cpkW+uDYA1EHKx6ZQgo8Mq/Yb+9hjOL9PlXZo5BBubl4VuA1w9GDg28AFRNSCJfys YTYrOMNhVhOsamDMAKkknjl2pVni55jEP0lV1f6RHIpOd8LjV7DZ4NeJ2By0SOQP+3Y0 1M0GBzUSN0utfTY3AT/N3ZgO8M6Z7EGlpY/+17+HTH9O+IQVpQXBdUiaEXCzh8kQKjjt G/V3omEa1o2YmkIjgaertKzybqCR+AxezGXrN3OdEDzXCsAEDuRnHYynkqvn/siQwh1s tNiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687724764; x=1690316764; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7H4gfmiVKhRklk1FA6KTDQbQYJQQYujXQM62+zAj3hY=; b=P3SGB2ICov4aAGbIHNvL+ipdCtwwOfx/Fc9H2GuxxDVvCBTzlg0yz5QxdJqOUkjTYf HSi3boDxKmRV1DF3aSjDanHUo/ytr4d8h7iwt+cuS1cgUyj3d+4JptnKFCi2J5rBhAhR frcZqE85be5uK4I0w/34BD7aUJFPVDW73QCyzGO/svHFKveiuEIXoW7DSoul7dayZzK0 tbCHR2JoMoMO15Y6UlKWmvVwAvGzEkvaGAEJ+PiuFVC8Y/RjLADJpiFF7S5TXGiI764v oZvzcwAmAEme4CDEfeGC9a67T0JfuTkyMcDvUbqOMpDuZxqLemLEVcYP1D0FUNAiF2M4 qA2A== X-Gm-Message-State: AC+VfDyS8GO9swr+XFjON1YhhdXSZ4Tr3scU5IR007RszYNNH4rlrFUY cwDxZgaLhD5VNy3/LLNz9719iA== X-Google-Smtp-Source: ACHHUZ5xt3r2nB5CFen5CIj6Off17gXUBLeLX32uJ8VPJvJGExuqqUXKOAZFTkMV7XHmwWp/MzY+aA== X-Received: by 2002:a05:6512:3d8e:b0:4fb:73d1:58e5 with SMTP id k14-20020a0565123d8e00b004fb73d158e5mr557018lfv.53.1687724764006; Sun, 25 Jun 2023 13:26:04 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id m21-20020a195215000000b004f8427f8716sm787537lfb.262.2023.06.25.13.26.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jun 2023 13:26:03 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v2 16/26] ARM: dts: qcom: apq8064: add L2 cache scaling Date: Sun, 25 Jun 2023 23:25:37 +0300 Message-Id: <20230625202547.174647-17-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> References: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Populate L2 cache node with clock, supplies and OPP information to facilitate scaling L2 frequency. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 101 ++++++++++++++++++++++- 1 file changed, 100 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 1eb6d752ebae..ac07170c702f 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -81,9 +81,108 @@ CPU3: cpu@3 { }; L2: l2-cache { - compatible = "cache"; + compatible = "qcom,krait-l2-cache", "cache"; cache-level = <2>; cache-unified; + vdd-mem-supply = <&pm8921_l24>; + vdd-dig-supply = <&pm8921_s3>; + clocks = <&kraitcc KRAIT_L2>; + #interconnect-cells = <1>; + operating-points-v2 = <&l2_opp_table>; + + l2_opp_table: opp-table-l2 { + compatible = "operating-points-v2"; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + opp-microvolt = <1050000 1050000 1150000>, + <950000 950000 1150000>; + }; + + opp-432000000 { + opp-hz = /bits/ 64 <432000000>; + opp-microvolt = <1050000 1050000 1150000>, + <1050000 1050000 1150000>; + }; + + opp-486000000 { + opp-hz = /bits/ 64 <486000000>; + opp-microvolt = <1050000 1050000 1150000>, + <1050000 1050000 1150000>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + opp-microvolt = <1050000 1050000 1150000>, + <1050000 1050000 1150000>; + }; + + opp-594000000 { + opp-hz = /bits/ 64 <594000000>; + opp-microvolt = <1050000 1050000 1150000>, + <1050000 1050000 1150000>; + }; + + opp-648000000 { + opp-hz = /bits/ 64 <648000000>; + opp-microvolt = <1050000 1050000 1150000>, + <1050000 1050000 1150000>; + }; + + opp-702000000 { + opp-hz = /bits/ 64 <702000000>; + opp-microvolt = <1150000 1150000 1150000>, + <1150000 1150000 1150000>; + }; + + opp-756000000 { + opp-hz = /bits/ 64 <756000000>; + opp-microvolt = <1150000 1150000 1150000>, + <1150000 1150000 1150000>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + opp-microvolt = <1150000 1150000 1150000>, + <1150000 1150000 1150000>; + }; + + opp-864000000 { + opp-hz = /bits/ 64 <864000000>; + opp-microvolt = <1150000 1150000 1150000>, + <1150000 1150000 1150000>; + }; + + opp-918000000 { + opp-hz = /bits/ 64 <918000000>; + opp-microvolt = <1150000 1150000 1150000>, + <1150000 1150000 1150000>; + }; + + opp-972000000 { + opp-hz = /bits/ 64 <972000000>; + opp-microvolt = <1150000 1150000 1150000>, + <1150000 1150000 1150000>; + }; + + opp-1026000000 { + opp-hz = /bits/ 64 <1026000000>; + opp-microvolt = <1150000 1150000 1150000>, + <1150000 1150000 1150000>; + }; + + opp-1080000000 { + opp-hz = /bits/ 64 <1080000000>; + opp-microvolt = <1150000 1150000 1150000>, + <1150000 1150000 1150000>; + }; + + opp-1134000000 { + opp-hz = /bits/ 64 <1134000000>; + opp-microvolt = <1150000 1150000 1150000>, + <1150000 1150000 1150000>; + }; + }; }; idle-states { From patchwork Sun Jun 25 20:25:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 696295 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8208EB64DD for ; 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Sun, 25 Jun 2023 13:26:04 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id m21-20020a195215000000b004f8427f8716sm787537lfb.262.2023.06.25.13.26.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jun 2023 13:26:04 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v2 17/26] ARM: dts: qcom: apq8064: add simple CPUFreq support Date: Sun, 25 Jun 2023 23:25:38 +0300 Message-Id: <20230625202547.174647-18-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> References: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Declare CPU frequency-scaling properties. Each CPU has its own clock, how all CPUs have the same OPP table. Voltage scaling is not (yet) enabled with this patch. It will be enabled later. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 170 +++++++++++++++++++++++ 1 file changed, 170 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index ac07170c702f..e4d2fd48d843 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -2,11 +2,13 @@ /dts-v1/; #include +#include #include #include #include #include #include +#include #include #include / { @@ -45,6 +47,12 @@ CPU0: cpu@0 { qcom,acc = <&acc0>; qcom,saw = <&saw0>; cpu-idle-states = <&CPU_SPC>; + clocks = <&kraitcc KRAIT_CPU_0>; + clock-names = "cpu"; + clock-latency = <100000>; + interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; }; CPU1: cpu@1 { @@ -56,6 +64,12 @@ CPU1: cpu@1 { qcom,acc = <&acc1>; qcom,saw = <&saw1>; cpu-idle-states = <&CPU_SPC>; + clocks = <&kraitcc KRAIT_CPU_1>; + clock-names = "cpu"; + clock-latency = <100000>; + interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; }; CPU2: cpu@2 { @@ -67,6 +81,12 @@ CPU2: cpu@2 { qcom,acc = <&acc2>; qcom,saw = <&saw2>; cpu-idle-states = <&CPU_SPC>; + clocks = <&kraitcc KRAIT_CPU_2>; + clock-names = "cpu"; + clock-latency = <100000>; + interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; }; CPU3: cpu@3 { @@ -78,6 +98,12 @@ CPU3: cpu@3 { qcom,acc = <&acc3>; qcom,saw = <&saw3>; cpu-idle-states = <&CPU_SPC>; + clocks = <&kraitcc KRAIT_CPU_3>; + clock-names = "cpu"; + clock-latency = <100000>; + interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; }; L2: l2-cache { @@ -196,6 +222,121 @@ CPU_SPC: spc { }; }; + cpu_opp_table: opp-table-cpu { + compatible = "operating-points-v2-krait-cpu"; + nvmem-cells = <&speedbin_efuse>; + + /* + * Voltage thresholds are + */ + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + opp-peak-kBps = <384000>; + opp-supported-hw = <0x4007>; + /* + * higher latency as it requires switching between + * clock sources + */ + clock-latency-ns = <244144>; + }; + + opp-486000000 { + opp-hz = /bits/ 64 <486000000>; + opp-peak-kBps = <648000>; + opp-supported-hw = <0x4007>; + }; + + opp-594000000 { + opp-hz = /bits/ 64 <594000000>; + opp-peak-kBps = <648000>; + opp-supported-hw = <0x4007>; + }; + + opp-702000000 { + opp-hz = /bits/ 64 <702000000>; + opp-peak-kBps = <648000>; + opp-supported-hw = <0x4007>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + opp-peak-kBps = <648000>; + opp-supported-hw = <0x4007>; + }; + + opp-918000000 { + opp-hz = /bits/ 64 <918000000>; + opp-peak-kBps = <648000>; + opp-supported-hw = <0x4007>; + }; + + opp-1026000000 { + opp-hz = /bits/ 64 <1026000000>; + opp-peak-kBps = <648000>; + opp-supported-hw = <0x4007>; + }; + + opp-1134000000 { + opp-hz = /bits/ 64 <1134000000>; + opp-peak-kBps = <1134000>; + opp-supported-hw = <0x4007>; + }; + + opp-1242000000 { + opp-hz = /bits/ 64 <1242000000>; + opp-peak-kBps = <1134000>; + opp-supported-hw = <0x4007>; + }; + + opp-1350000000 { + opp-hz = /bits/ 64 <1350000000>; + opp-peak-kBps = <1134000>; + opp-supported-hw = <0x4007>; + }; + + opp-1458000000 { + opp-hz = /bits/ 64 <1458000000>; + opp-peak-kBps = <1134000>; + opp-supported-hw = <0x4007>; + }; + + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-peak-kBps = <1134000>; + opp-supported-hw = <0x4001>; + }; + + opp-1566000000 { + opp-hz = /bits/ 64 <1566000000>; + opp-peak-kBps = <1134000>; + opp-supported-hw = <0x06>; + }; + + opp-1674000000 { + opp-hz = /bits/ 64 <1674000000>; + opp-peak-kBps = <1134000>; + opp-supported-hw = <0x06>; + }; + + opp-1728000000 { + opp-hz = /bits/ 64 <1728000000>; + opp-peak-kBps = <1134000>; + opp-supported-hw = <0x02>; + }; + + opp-1782000000 { + opp-hz = /bits/ 64 <1782000000>; + opp-peak-kBps = <1134000>; + opp-supported-hw = <0x04>; + }; + + opp-1890000000 { + opp-hz = /bits/ 64 <1890000000>; + opp-peak-kBps = <1134000>; + opp-supported-hw = <0x04>; + }; + }; + memory@0 { device_type = "memory"; reg = <0x0 0x0>; @@ -312,6 +453,32 @@ sleep_clk: sleep_clk { }; }; + kraitcc: clock-controller { + compatible = "qcom,krait-cc-v1"; + clocks = <&gcc PLL9>, /* hfpll0 */ + <&gcc PLL10>, /* hfpll1 */ + <&gcc PLL16>, /* hfpll2 */ + <&gcc PLL17>, /* hfpll3 */ + <&gcc PLL12>, /* hfpll_l2 */ + <&acc0>, + <&acc1>, + <&acc2>, + <&acc3>, + <&l2cc>; + clock-names = "hfpll0", + "hfpll1", + "hfpll2", + "hfpll3", + "hfpll_l2", + "acpu0_aux", + "acpu1_aux", + "acpu2_aux", + "acpu3_aux", + "acpu_l2_aux"; + #clock-cells = <1>; + #interconnect-cells = <1>; + }; + sfpb_mutex: hwmutex { compatible = "qcom,sfpb-mutex"; syscon = <&sfpb_wrapper_mutex 0x604 0x4>; @@ -933,6 +1100,9 @@ qfprom: qfprom@700000 { #address-cells = <1>; #size-cells = <1>; ranges; + speedbin_efuse: speedbin@c0 { + reg = <0x0c0 0x4>; + }; tsens_calib: calib@404 { reg = <0x404 0x10>; }; From patchwork Sun Jun 25 20:25:39 2023 Content-Type: text/plain; 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Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v2 18/26] ARM: dts: qcom: apq8064: provide voltage scaling tables Date: Sun, 25 Jun 2023 23:25:39 +0300 Message-Id: <20230625202547.174647-19-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> References: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org APQ8064 has 4 speed bins, each of them having from 4 to 6 categorization kinds. Provide tables necessary to handle voltage scaling on this SoC. Signed-off-by: Dmitry Baryshkov Acked-by: Konrad Dybcio --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 339 +++++++++++++++++++++++ 1 file changed, 339 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index e4d2fd48d843..b97d88517805 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -50,6 +50,7 @@ CPU0: cpu@0 { clocks = <&kraitcc KRAIT_CPU_0>; clock-names = "cpu"; clock-latency = <100000>; + vdd-core-supply = <&saw0_vreg>; interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; @@ -67,6 +68,7 @@ CPU1: cpu@1 { clocks = <&kraitcc KRAIT_CPU_1>; clock-names = "cpu"; clock-latency = <100000>; + vdd-core-supply = <&saw1_vreg>; interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; @@ -84,6 +86,7 @@ CPU2: cpu@2 { clocks = <&kraitcc KRAIT_CPU_2>; clock-names = "cpu"; clock-latency = <100000>; + vdd-core-supply = <&saw2_vreg>; interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; @@ -101,6 +104,7 @@ CPU3: cpu@3 { clocks = <&kraitcc KRAIT_CPU_3>; clock-names = "cpu"; clock-latency = <100000>; + vdd-core-supply = <&saw3_vreg>; interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; @@ -232,6 +236,31 @@ cpu_opp_table: opp-table-cpu { opp-384000000 { opp-hz = /bits/ 64 <384000000>; opp-peak-kBps = <384000>; + opp-microvolt-speed0-pvs0 = <950000 950000 975000>; + opp-microvolt-speed0-pvs1 = <925000 900000 950000>; + opp-microvolt-speed0-pvs3 = <875000 850000 900000>; + opp-microvolt-speed0-pvs4 = <875000 850000 900000>; + opp-microvolt-speed1-pvs0 = <950000 950000 975000>; + opp-microvolt-speed1-pvs1 = <975000 950000 1000000>; + opp-microvolt-speed1-pvs2 = <950000 925000 975000>; + opp-microvolt-speed1-pvs3 = <925000 900000 950000>; + opp-microvolt-speed1-pvs4 = <900000 875000 925000>; + opp-microvolt-speed1-pvs5 = <900000 875000 925000>; + opp-microvolt-speed1-pvs6 = <900000 875000 925000>; + opp-microvolt-speed2-pvs0 = <950000 950000 975000>; + opp-microvolt-speed2-pvs1 = <925000 925000 925000>; + opp-microvolt-speed2-pvs2 = <925000 900000 950000>; + opp-microvolt-speed2-pvs3 = <925000 900000 950000>; + opp-microvolt-speed2-pvs4 = <900000 875000 925000>; + opp-microvolt-speed2-pvs5 = <900000 875000 925000>; + opp-microvolt-speed2-pvs6 = <900000 875000 925000>; + opp-microvolt-speed14-pvs0 = <950000 950000 975000>; + opp-microvolt-speed14-pvs1 = <975000 950000 1000000>; + opp-microvolt-speed14-pvs2 = <950000 925000 975000>; + opp-microvolt-speed14-pvs3 = <925000 900000 950000>; + opp-microvolt-speed14-pvs4 = <900000 875000 925000>; + opp-microvolt-speed14-pvs5 = <875000 875000 875000>; + opp-microvolt-speed14-pvs6 = <900000 875000 925000>; opp-supported-hw = <0x4007>; /* * higher latency as it requires switching between @@ -243,96 +272,406 @@ opp-384000000 { opp-486000000 { opp-hz = /bits/ 64 <486000000>; opp-peak-kBps = <648000>; + opp-microvolt-speed0-pvs0 = <975000 975000 1000000>; + opp-microvolt-speed0-pvs1 = <950000 925000 975000>; + opp-microvolt-speed0-pvs3 = <900000 875000 925000>; + opp-microvolt-speed0-pvs4 = <900000 875000 925000>; + opp-microvolt-speed1-pvs0 = <950000 950000 975000>; + opp-microvolt-speed1-pvs1 = <975000 950000 1000000>; + opp-microvolt-speed1-pvs2 = <950000 925000 975000>; + opp-microvolt-speed1-pvs3 = <925000 900000 950000>; + opp-microvolt-speed1-pvs4 = <900000 875000 925000>; + opp-microvolt-speed1-pvs5 = <900000 875000 925000>; + opp-microvolt-speed1-pvs6 = <900000 875000 925000>; + opp-microvolt-speed2-pvs0 = <950000 950000 975000>; + opp-microvolt-speed2-pvs1 = <925000 925000 925000>; + opp-microvolt-speed2-pvs2 = <925000 900000 950000>; + opp-microvolt-speed2-pvs3 = <925000 900000 950000>; + opp-microvolt-speed2-pvs4 = <900000 875000 925000>; + opp-microvolt-speed2-pvs5 = <900000 875000 925000>; + opp-microvolt-speed2-pvs6 = <900000 875000 925000>; + opp-microvolt-speed14-pvs0 = <950000 950000 975000>; + opp-microvolt-speed14-pvs1 = <975000 950000 1000000>; + opp-microvolt-speed14-pvs2 = <950000 925000 975000>; + opp-microvolt-speed14-pvs3 = <925000 900000 950000>; + opp-microvolt-speed14-pvs4 = <900000 875000 925000>; + opp-microvolt-speed14-pvs5 = <875000 875000 875000>; + opp-microvolt-speed14-pvs6 = <875000 875000 875000>; opp-supported-hw = <0x4007>; }; opp-594000000 { opp-hz = /bits/ 64 <594000000>; opp-peak-kBps = <648000>; + opp-microvolt-speed0-pvs0 = <1000000 1000000 1025000>; + opp-microvolt-speed0-pvs1 = <975000 950000 1000000>; + opp-microvolt-speed0-pvs3 = <925000 900000 950000>; + opp-microvolt-speed0-pvs4 = <925000 900000 950000>; + opp-microvolt-speed1-pvs0 = <950000 950000 975000>; + opp-microvolt-speed1-pvs1 = <975000 950000 1000000>; + opp-microvolt-speed1-pvs2 = <950000 925000 975000>; + opp-microvolt-speed1-pvs3 = <925000 900000 950000>; + opp-microvolt-speed1-pvs4 = <900000 875000 925000>; + opp-microvolt-speed1-pvs5 = <900000 875000 925000>; + opp-microvolt-speed1-pvs6 = <900000 875000 925000>; + opp-microvolt-speed2-pvs0 = <950000 950000 975000>; + opp-microvolt-speed2-pvs1 = <925000 925000 925000>; + opp-microvolt-speed2-pvs2 = <925000 900000 950000>; + opp-microvolt-speed2-pvs3 = <925000 900000 950000>; + opp-microvolt-speed2-pvs4 = <900000 875000 925000>; + opp-microvolt-speed2-pvs5 = <900000 875000 925000>; + opp-microvolt-speed2-pvs6 = <900000 875000 925000>; + opp-microvolt-speed14-pvs0 = <950000 950000 975000>; + opp-microvolt-speed14-pvs1 = <975000 950000 1000000>; + opp-microvolt-speed14-pvs2 = <950000 925000 975000>; + opp-microvolt-speed14-pvs3 = <925000 900000 950000>; + opp-microvolt-speed14-pvs4 = <900000 875000 925000>; + opp-microvolt-speed14-pvs5 = <875000 875000 875000>; + opp-microvolt-speed14-pvs6 = <900000 875000 925000>; opp-supported-hw = <0x4007>; }; opp-702000000 { opp-hz = /bits/ 64 <702000000>; opp-peak-kBps = <648000>; + opp-microvolt-speed0-pvs0 = <1025000 1025000 1050000>; + opp-microvolt-speed0-pvs1 = <1000000 975000 1025000>; + opp-microvolt-speed0-pvs3 = <950000 925000 975000>; + opp-microvolt-speed0-pvs4 = <950000 925000 975000>; + opp-microvolt-speed1-pvs0 = <962500 962500 987500>; + opp-microvolt-speed1-pvs1 = <987500 962500 1012500>; + opp-microvolt-speed1-pvs2 = <950000 925000 975000>; + opp-microvolt-speed1-pvs3 = <925000 900000 950000>; + opp-microvolt-speed1-pvs4 = <900000 875000 925000>; + opp-microvolt-speed1-pvs5 = <900000 875000 925000>; + opp-microvolt-speed1-pvs6 = <900000 875000 925000>; + opp-microvolt-speed2-pvs0 = <950000 950000 975000>; + opp-microvolt-speed2-pvs1 = <925000 925000 925000>; + opp-microvolt-speed2-pvs2 = <925000 900000 950000>; + opp-microvolt-speed2-pvs3 = <925000 900000 950000>; + opp-microvolt-speed2-pvs4 = <900000 875000 925000>; + opp-microvolt-speed2-pvs5 = <900000 875000 925000>; + opp-microvolt-speed2-pvs6 = <900000 875000 925000>; + opp-microvolt-speed14-pvs0 = <962500 962500 987500>; + opp-microvolt-speed14-pvs1 = <987500 962500 1012500>; + opp-microvolt-speed14-pvs2 = <950000 925000 975000>; + opp-microvolt-speed14-pvs3 = <925000 900000 950000>; + opp-microvolt-speed14-pvs4 = <900000 875000 925000>; + opp-microvolt-speed14-pvs5 = <875000 875000 875000>; + opp-microvolt-speed14-pvs6 = <900000 875000 925000>; opp-supported-hw = <0x4007>; }; opp-810000000 { opp-hz = /bits/ 64 <810000000>; opp-peak-kBps = <648000>; + opp-microvolt-speed0-pvs0 = <1075000 1075000 1100000>; + opp-microvolt-speed0-pvs1 = <1050000 1025000 1075000>; + opp-microvolt-speed0-pvs3 = <1000000 975000 1025000>; + opp-microvolt-speed0-pvs4 = <987500 962500 1012500>; + opp-microvolt-speed1-pvs0 = <1000000 1000000 1025000>; + opp-microvolt-speed1-pvs1 = <1000000 975000 1025000>; + opp-microvolt-speed1-pvs2 = <962500 937500 987500>; + opp-microvolt-speed1-pvs3 = <925000 900000 950000>; + opp-microvolt-speed1-pvs4 = <912500 887500 937500>; + opp-microvolt-speed1-pvs5 = <912500 887500 937500>; + opp-microvolt-speed1-pvs6 = <912500 887500 937500>; + opp-microvolt-speed2-pvs0 = <962500 962500 987500>; + opp-microvolt-speed2-pvs1 = <937500 937500 937500>; + opp-microvolt-speed2-pvs2 = <937500 912500 962500>; + opp-microvolt-speed2-pvs3 = <925000 900000 950000>; + opp-microvolt-speed2-pvs4 = <912500 887500 937500>; + opp-microvolt-speed2-pvs5 = <912500 887500 937500>; + opp-microvolt-speed2-pvs6 = <912500 887500 937500>; + opp-microvolt-speed14-pvs0 = <1000000 1000000 1025000>; + opp-microvolt-speed14-pvs1 = <1000000 975000 1025000>; + opp-microvolt-speed14-pvs2 = <962500 937500 987500>; + opp-microvolt-speed14-pvs3 = <925000 900000 950000>; + opp-microvolt-speed14-pvs4 = <912500 887500 937500>; + opp-microvolt-speed14-pvs5 = <887500 887500 887500>; + opp-microvolt-speed14-pvs6 = <912500 887500 937500>; opp-supported-hw = <0x4007>; }; opp-918000000 { opp-hz = /bits/ 64 <918000000>; opp-peak-kBps = <648000>; + opp-microvolt-speed0-pvs0 = <1100000 1100000 1125000>; + opp-microvolt-speed0-pvs1 = <1075000 1050000 1100000>; + opp-microvolt-speed0-pvs3 = <1025000 1000000 1050000>; + opp-microvolt-speed0-pvs4 = <1000000 975000 1025000>; + opp-microvolt-speed1-pvs0 = <1025000 1025000 1050000>; + opp-microvolt-speed1-pvs1 = <1025000 1000000 1050000>; + opp-microvolt-speed1-pvs2 = <975000 950000 1000000>; + opp-microvolt-speed1-pvs3 = <950000 925000 975000>; + opp-microvolt-speed1-pvs4 = <925000 900000 950000>; + opp-microvolt-speed1-pvs5 = <925000 900000 950000>; + opp-microvolt-speed1-pvs6 = <925000 900000 950000>; + opp-microvolt-speed2-pvs0 = <975000 975000 1000000>; + opp-microvolt-speed2-pvs1 = <950000 950000 950000>; + opp-microvolt-speed2-pvs2 = <950000 925000 975000>; + opp-microvolt-speed2-pvs3 = <937500 912500 962500>; + opp-microvolt-speed3-pvs4 = <925000 900000 950000>; + opp-microvolt-speed2-pvs5 = <925000 900000 950000>; + opp-microvolt-speed2-pvs6 = <925000 900000 950000>; + opp-microvolt-speed14-pvs0 = <1025000 1025000 1050000>; + opp-microvolt-speed14-pvs1 = <1025000 1000000 1050000>; + opp-microvolt-speed14-pvs2 = <975000 950000 1000000>; + opp-microvolt-speed14-pvs3 = <950000 925000 975000>; + opp-microvolt-speed14-pvs4 = <925000 900000 950000>; + opp-microvolt-speed14-pvs5 = <900000 900000 900000>; + opp-microvolt-speed14-pvs6 = <925000 900000 950000>; opp-supported-hw = <0x4007>; }; opp-1026000000 { opp-hz = /bits/ 64 <1026000000>; opp-peak-kBps = <648000>; + opp-microvolt-speed0-pvs0 = <1125000 1125000 1150000>; + opp-microvolt-speed0-pvs1 = <1100000 1075000 1125000>; + opp-microvolt-speed0-pvs3 = <1050000 1025000 1075000>; + opp-microvolt-speed0-pvs4 = <1025000 1000000 1050000>; + opp-microvolt-speed1-pvs0 = <1037500 1037500 1062500>; + opp-microvolt-speed1-pvs1 = <1037500 1012500 1062500>; + opp-microvolt-speed1-pvs2 = <1000000 975000 1025000>; + opp-microvolt-speed1-pvs3 = <975000 950000 1000000>; + opp-microvolt-speed1-pvs4 = <950000 925000 975000>; + opp-microvolt-speed1-pvs5 = <950000 925000 975000>; + opp-microvolt-speed1-pvs6 = <950000 925000 975000>; + opp-microvolt-speed2-pvs0 = <1000000 1000000 1025000>; + opp-microvolt-speed2-pvs1 = <975000 975000 975000>; + opp-microvolt-speed2-pvs2 = <975000 950000 1000000>; + opp-microvolt-speed2-pvs3 = <962500 937500 987500>; + opp-microvolt-speed2-pvs4 = <950000 925000 975000>; + opp-microvolt-speed2-pvs5 = <950000 925000 975000>; + opp-microvolt-speed2-pvs6 = <950000 925000 975000>; + opp-microvolt-speed14-pvs0 = <1037500 1037500 1062500>; + opp-microvolt-speed14-pvs1 = <1037500 1012500 1062500>; + opp-microvolt-speed14-pvs2 = <1000000 975000 1025000>; + opp-microvolt-speed14-pvs3 = <975000 950000 1000000>; + opp-microvolt-speed14-pvs4 = <950000 925000 975000>; + opp-microvolt-speed14-pvs5 = <925000 925000 925000>; + opp-microvolt-speed14-pvs6 = <950000 925000 975000>; opp-supported-hw = <0x4007>; }; opp-1134000000 { opp-hz = /bits/ 64 <1134000000>; opp-peak-kBps = <1134000>; + opp-microvolt-speed0-pvs0 = <1175000 1175000 1200000>; + opp-microvolt-speed0-pvs1 = <1150000 1125000 1175000>; + opp-microvolt-speed0-pvs3 = <1100000 1075000 1125000>; + opp-microvolt-speed0-pvs4 = <1075000 1050000 1100000>; + opp-microvolt-speed1-pvs0 = <1075000 1075000 1100000>; + opp-microvolt-speed1-pvs1 = <1062500 1037500 1087500>; + opp-microvolt-speed1-pvs2 = <1025000 1000000 1050000>; + opp-microvolt-speed1-pvs3 = <1000000 975000 1025000>; + opp-microvolt-speed1-pvs4 = <975000 950000 1000000>; + opp-microvolt-speed1-pvs5 = <962500 937500 987500>; + opp-microvolt-speed1-pvs6 = <962500 937500 987500>; + opp-microvolt-speed2-pvs0 = <1025000 1025000 1050000>; + opp-microvolt-speed2-pvs1 = <1000000 1000000 1000000>; + opp-microvolt-speed2-pvs2 = <1000000 975000 1025000>; + opp-microvolt-speed2-pvs3 = <987500 962500 1012500>; + opp-microvolt-speed2-pvs4 = <975000 950000 1000000>; + opp-microvolt-speed2-pvs5 = <962500 937500 987500>; + opp-microvolt-speed2-pvs6 = <962500 937500 987500>; + opp-microvolt-speed14-pvs0 = <1075000 1075000 1100000>; + opp-microvolt-speed14-pvs1 = <1062500 1037500 1087500>; + opp-microvolt-speed14-pvs2 = <1025000 1000000 1050000>; + opp-microvolt-speed14-pvs3 = <1000000 975000 1025000>; + opp-microvolt-speed14-pvs4 = <975000 950000 1000000>; + opp-microvolt-speed14-pvs5 = <937500 937500 937500>; + opp-microvolt-speed14-pvs6 = <962500 937500 987500>; opp-supported-hw = <0x4007>; }; opp-1242000000 { opp-hz = /bits/ 64 <1242000000>; opp-peak-kBps = <1134000>; + opp-microvolt-speed0-pvs0 = <1200000 1200000 1225000>; + opp-microvolt-speed0-pvs1 = <1175000 1150000 1200000>; + opp-microvolt-speed0-pvs3 = <1125000 1100000 1150000>; + opp-microvolt-speed0-pvs4 = <1100000 1075000 1125000>; + opp-microvolt-speed1-pvs0 = <1087500 1087500 1112500>; + opp-microvolt-speed1-pvs1 = <1075000 1050000 1100000>; + opp-microvolt-speed1-pvs2 = <1037500 1012500 1062500>; + opp-microvolt-speed1-pvs3 = <1012500 987500 1037500>; + opp-microvolt-speed1-pvs4 = <987500 962500 1012500>; + opp-microvolt-speed1-pvs5 = <975000 950000 1000000>; + opp-microvolt-speed1-pvs6 = <975000 950000 1000000>; + opp-microvolt-speed2-pvs0 = <1037500 1037500 1062500>; + opp-microvolt-speed2-pvs1 = <1012500 1012500 1012500>; + opp-microvolt-speed2-pvs2 = <1012500 987500 1037500>; + opp-microvolt-speed2-pvs3 = <1000000 975000 1025000>; + opp-microvolt-speed2-pvs4 = <987500 962500 1012500>; + opp-microvolt-speed2-pvs5 = <975000 950000 1000000>; + opp-microvolt-speed2-pvs6 = <975000 950000 1000000>; + opp-microvolt-speed14-pvs0 = <1087500 1087500 1112500>; + opp-microvolt-speed14-pvs1 = <1075000 1050000 1100000>; + opp-microvolt-speed14-pvs2 = <1037500 1012500 1062500>; + opp-microvolt-speed14-pvs3 = <1012500 987500 1037500>; + opp-microvolt-speed14-pvs4 = <987500 962500 1012500>; + opp-microvolt-speed14-pvs5 = <950000 950000 950000>; + opp-microvolt-speed14-pvs6 = <975000 950000 1000000>; opp-supported-hw = <0x4007>; }; opp-1350000000 { opp-hz = /bits/ 64 <1350000000>; opp-peak-kBps = <1134000>; + opp-microvolt-speed0-pvs0 = <1225000 1225000 1250000>; + opp-microvolt-speed0-pvs1 = <1200000 1175000 1225000>; + opp-microvolt-speed0-pvs3 = <1150000 1125000 1175000>; + opp-microvolt-speed0-pvs4 = <1125000 1100000 1150000>; + opp-microvolt-speed1-pvs0 = <1125000 1125000 1150000>; + opp-microvolt-speed1-pvs1 = <1112500 1087500 1137500>; + opp-microvolt-speed1-pvs2 = <1062500 1037500 1087500>; + opp-microvolt-speed1-pvs3 = <1025000 1000000 1050000>; + opp-microvolt-speed1-pvs4 = <1000000 975000 1025000>; + opp-microvolt-speed1-pvs5 = <987500 962500 1012500>; + opp-microvolt-speed1-pvs6 = <987500 962500 1012500>; + opp-microvolt-speed2-pvs0 = <1062500 1062500 1087500>; + opp-microvolt-speed2-pvs1 = <1037500 1037500 1037500>; + opp-microvolt-speed2-pvs2 = <1037500 1012500 1062500>; + opp-microvolt-speed2-pvs3 = <1025000 1000000 1050000>; + opp-microvolt-speed2-pvs4 = <1000000 975000 1025000>; + opp-microvolt-speed2-pvs5 = <987500 962500 1012500>; + opp-microvolt-speed2-pvs6 = <987500 962500 1012500>; + opp-microvolt-speed14-pvs0 = <1125000 1125000 1150000>; + opp-microvolt-speed14-pvs1 = <1112500 1087500 1137500>; + opp-microvolt-speed14-pvs2 = <1062500 1037500 1087500>; + opp-microvolt-speed14-pvs3 = <1025000 1000000 1050000>; + opp-microvolt-speed14-pvs4 = <1000000 975000 1025000>; + opp-microvolt-speed14-pvs5 = <962500 962500 962500>; + opp-microvolt-speed14-pvs6 = <987500 962500 1012500>; opp-supported-hw = <0x4007>; }; opp-1458000000 { opp-hz = /bits/ 64 <1458000000>; opp-peak-kBps = <1134000>; + opp-microvolt-speed0-pvs0 = <1237500 1237500 1262500>; + opp-microvolt-speed0-pvs1 = <1212500 1187500 1237500>; + opp-microvolt-speed0-pvs3 = <1162500 1137500 1187500>; + opp-microvolt-speed0-pvs4 = <1137500 1112500 1162500>; + opp-microvolt-speed1-pvs0 = <1150000 1150000 1175000>; + opp-microvolt-speed1-pvs1 = <1137500 1112500 1162500>; + opp-microvolt-speed1-pvs2 = <1100000 1075000 1125000>; + opp-microvolt-speed1-pvs3 = <1062500 1037500 1087500>; + opp-microvolt-speed1-pvs4 = <1025000 1000000 1050000>; + opp-microvolt-speed1-pvs5 = <1012500 987500 1037500>; + opp-microvolt-speed1-pvs6 = <1000000 975000 1025000>; + opp-microvolt-speed2-pvs0 = <1100000 1100000 1125000>; + opp-microvolt-speed2-pvs1 = <1075000 1075000 1075000>; + opp-microvolt-speed2-pvs2 = <1075000 1050000 1100000>; + opp-microvolt-speed2-pvs3 = <1050000 1025000 1075000>; + opp-microvolt-speed2-pvs4 = <1025000 1000000 1050000>; + opp-microvolt-speed2-pvs5 = <1012500 987500 1037500>; + opp-microvolt-speed2-pvs6 = <1000000 975000 1025000>; + opp-microvolt-speed14-pvs0 = <1150000 1150000 1175000>; + opp-microvolt-speed14-pvs1 = <1137500 1112500 1162500>; + opp-microvolt-speed14-pvs2 = <1100000 1075000 1125000>; + opp-microvolt-speed14-pvs3 = <1062500 1037500 1087500>; + opp-microvolt-speed14-pvs4 = <1025000 1000000 1050000>; + opp-microvolt-speed14-pvs5 = <987500 987500 987500>; + opp-microvolt-speed14-pvs6 = <1000000 975000 1025000>; opp-supported-hw = <0x4007>; }; opp-1512000000 { opp-hz = /bits/ 64 <1512000000>; opp-peak-kBps = <1134000>; + opp-microvolt-speed0-pvs0 = <1250000 1250000 1275000>; + opp-microvolt-speed0-pvs1 = <1225000 1200000 1250000>; + opp-microvolt-speed0-pvs3 = <1175000 1150000 1200000>; + opp-microvolt-speed0-pvs4 = <1150000 1125000 1175000>; + opp-microvolt-speed14-pvs0 = <1162500 1162500 1187500>; + opp-microvolt-speed14-pvs1 = <1150000 1125000 1175000>; + opp-microvolt-speed14-pvs2 = <1112500 1087500 1137500>; + opp-microvolt-speed14-pvs3 = <1075000 1050000 1100000>; + opp-microvolt-speed14-pvs4 = <1037500 1012500 1062500>; + opp-microvolt-speed14-pvs5 = <1000000 1000000 1000000>; + opp-microvolt-speed14-pvs6 = <1012500 987500 1037500>; opp-supported-hw = <0x4001>; }; opp-1566000000 { opp-hz = /bits/ 64 <1566000000>; opp-peak-kBps = <1134000>; + opp-microvolt-speed1-pvs0 = <1175000 1175000 1200000>; + opp-microvolt-speed1-pvs1 = <1175000 1150000 1200000>; + opp-microvolt-speed1-pvs2 = <1125000 1100000 1150000>; + opp-microvolt-speed1-pvs3 = <1087500 1062500 1112500>; + opp-microvolt-speed1-pvs4 = <1062500 1037500 1087500>; + opp-microvolt-speed1-pvs5 = <1037500 1012500 1062500>; + opp-microvolt-speed1-pvs6 = <1025000 1000000 1050000>; + opp-microvolt-speed2-pvs0 = <1125000 1125000 1150000>; + opp-microvolt-speed2-pvs1 = <1100000 1100000 1100000>; + opp-microvolt-speed2-pvs2 = <1100000 1075000 1125000>; + opp-microvolt-speed2-pvs3 = <1075000 1050000 1100000>; + opp-microvolt-speed2-pvs4 = <1062500 1037500 1087500>; + opp-microvolt-speed2-pvs5 = <1037500 1012500 1062500>; + opp-microvolt-speed2-pvs6 = <1025000 1000000 1050000>; opp-supported-hw = <0x06>; }; opp-1674000000 { opp-hz = /bits/ 64 <1674000000>; opp-peak-kBps = <1134000>; + opp-microvolt-speed1-pvs0 = <1225000 1225000 1250000>; + opp-microvolt-speed1-pvs1 = <1212500 1187500 1237500>; + opp-microvolt-speed1-pvs2 = <1162500 1137500 1187500>; + opp-microvolt-speed1-pvs3 = <1125000 1100000 1150000>; + opp-microvolt-speed1-pvs4 = <1100000 1075000 1125000>; + opp-microvolt-speed1-pvs5 = <1075000 1050000 1100000>; + opp-microvolt-speed1-pvs6 = <1050000 1025000 1075000>; + opp-microvolt-speed2-pvs0 = <1175000 1175000 1200000>; + opp-microvolt-speed2-pvs1 = <1137500 1137500 1137500>; + opp-microvolt-speed2-pvs2 = <1137500 1112500 1162500>; + opp-microvolt-speed2-pvs3 = <1112500 1087500 1137500>; + opp-microvolt-speed2-pvs4 = <1100000 1075000 1125000>; + opp-microvolt-speed2-pvs5 = <1075000 1050000 1100000>; + opp-microvolt-speed2-pvs6 = <1050000 1025000 1075000>; opp-supported-hw = <0x06>; }; opp-1728000000 { opp-hz = /bits/ 64 <1728000000>; opp-peak-kBps = <1134000>; + opp-microvolt-speed1-pvs0 = <1250000 1250000 1275000>; + opp-microvolt-speed1-pvs1 = <1225000 1200000 1250000>; + opp-microvolt-speed1-pvs2 = <1187500 1162500 1212500>; + opp-microvolt-speed1-pvs3 = <1150000 1125000 1175000>; + opp-microvolt-speed1-pvs4 = <1125000 1100000 1150000>; + opp-microvolt-speed1-pvs5 = <1100000 1075000 1125000>; + opp-microvolt-speed1-pvs6 = <1075000 1050000 1100000>; opp-supported-hw = <0x02>; }; opp-1782000000 { opp-hz = /bits/ 64 <1782000000>; opp-peak-kBps = <1134000>; + opp-microvolt-speed2-pvs0 = <1225000 1225000 1250000>; + opp-microvolt-speed2-pvs1 = <1187500 1187500 1187500>; + opp-microvolt-speed2-pvs2 = <1187500 1162500 1212500>; + opp-microvolt-speed2-pvs3 = <1162500 1137500 1187500>; + opp-microvolt-speed2-pvs4 = <1137500 1112500 1162500>; + opp-microvolt-speed2-pvs5 = <1112500 1087500 1137500>; + opp-microvolt-speed2-pvs6 = <1087500 1062500 1112500>; opp-supported-hw = <0x04>; }; opp-1890000000 { opp-hz = /bits/ 64 <1890000000>; opp-peak-kBps = <1134000>; + opp-microvolt-speed2-pvs0 = <1287500 1287500 1312500>; + opp-microvolt-speed2-pvs1 = <1250000 1250000 1250000>; + opp-microvolt-speed2-pvs2 = <1237500 1212500 1262500>; + opp-microvolt-speed2-pvs3 = <1200000 1175000 1225000>; + opp-microvolt-speed2-pvs4 = <1175000 1150000 1200000>; + opp-microvolt-speed2-pvs5 = <1150000 1125000 1175000>; + opp-microvolt-speed2-pvs6 = <1125000 1100000 1150000>; opp-supported-hw = <0x04>; }; }; From patchwork Sun Jun 25 20:25:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 696652 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8173BC04FDF for ; Sun, 25 Jun 2023 20:26:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230362AbjFYU0S (ORCPT ); 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Sun, 25 Jun 2023 13:26:06 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v2 19/26] ARM: dts: qcom: apq8064: enable passive CPU cooling Date: Sun, 25 Jun 2023 23:25:40 +0300 Message-Id: <20230625202547.174647-20-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> References: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Wire up CPUs and thermal trip points to save the SoC from overheating by lowering the CPU frequency. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 29 ++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index b97d88517805..f38e3394b422 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include / { #address-cells = <1>; #size-cells = <1>; @@ -701,6 +702,13 @@ cpu_crit0: trip1 { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu1-thermal { @@ -722,6 +730,13 @@ cpu_crit1: trip1 { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu_alert1>; + cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu2-thermal { @@ -743,6 +758,13 @@ cpu_crit2: trip1 { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu_alert2>; + cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu3-thermal { @@ -764,6 +786,13 @@ cpu_crit3: trip1 { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu_alert3>; + cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; }; From patchwork Sun Jun 25 20:25:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 696294 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B11E2C05051 for ; Sun, 25 Jun 2023 20:26:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230397AbjFYU0U (ORCPT ); Sun, 25 Jun 2023 16:26:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60810 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230411AbjFYU0R (ORCPT ); Sun, 25 Jun 2023 16:26:17 -0400 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2D4F310C6 for ; Sun, 25 Jun 2023 13:26:09 -0700 (PDT) Received: by mail-lj1-x235.google.com with SMTP id 38308e7fff4ca-2b466744368so36507191fa.0 for ; Sun, 25 Jun 2023 13:26:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687724767; x=1690316767; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=77d+d36KDkZJ6tRGLwEY2Ux3Xp+jyLxcEE3RlyjNnBw=; b=MJGUwU4csWft8gwY9EJC4GHGrYyX/vKLSqxL3D927k67Pwk3efZvimrtJgIoXQYd8M vBtGc6DejbION5Nl/fKaRox3bZ+Hop0MolxyeyerNtTS5aEGwh9VSklf9uvl1QV4exQn Q2W3i0EfINlMMMNrUJ5HMtfg+/Zossia5RowRM+Zrl/S/jCmVQIuLgjLmr6Bn4c+yo6Q bk0yoOTZtOyfzK8MDnARqlNdZHrO+UJukQbrIRneJ26h2tyY50L2/l4tVNGmV/5cjfc+ D1lQDtHRMTKh5/X/OB6OBYKxyy5J0hyw1n3LD2PC3Z8IAYaQDj5pUJoBQIdEA7nsjMa6 It3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687724767; x=1690316767; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=77d+d36KDkZJ6tRGLwEY2Ux3Xp+jyLxcEE3RlyjNnBw=; b=YMXJvE23DFsBOkj7k/sK6tRB8vY5MI6Rlo5xnLQJ9c2ZAttztNd1BhDoS3o0GCofsf edFuxq9STSJchDivGO5GLTBWWTyZF2hjBuM969aVgebixD4rvanHkMKepsDLfya1Wym6 Hwo7rZqCGxI8mnBXZy6bbT2Sxd7CqvT2nd7Tu7EJ6CL6E6J1s3D2jQuMi71wGjGmmn2h JNOYt6FBTPCrmGIw/Yw4nVfd8QGF01pr6CWSSbAUR2gi1EYKQD3Zgs+c2KErCOr2l44e N5/Ug8Zf0TFd1R8je/iZtulRV1H+Wnx8MCPVslEid9Cw129MVQbB4c2yFVeXy7j1aTsw Cpng== X-Gm-Message-State: AC+VfDxrMFc9LoYm2mb0WBEmWeDffiYw6CsyuQYwk9+8uhvLOWEfslUl q3+YMRFEJAEhigRToaq00dINXg== X-Google-Smtp-Source: ACHHUZ6UOX37vIQM2BQ6tIOcTtFsFUySwM68LzB8NeMFXoHNq8Fk5PRtssY25xmAChM3kT5Sdujpfg== X-Received: by 2002:a2e:740e:0:b0:2b5:86e4:558e with SMTP id p14-20020a2e740e000000b002b586e4558emr8355931ljc.38.1687724767234; Sun, 25 Jun 2023 13:26:07 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id m21-20020a195215000000b004f8427f8716sm787537lfb.262.2023.06.25.13.26.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jun 2023 13:26:06 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v2 20/26] ARM: dts: qcom: apq8064-asus-nexus7-flo: constraint cpufreq regulators Date: Sun, 25 Jun 2023 23:25:41 +0300 Message-Id: <20230625202547.174647-21-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> References: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add additional constraints to the CPUfreq-related regulators, it is better be safe than sorry there. Signed-off-by: Dmitry Baryshkov Acked-by: Konrad Dybcio --- .../boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts index c57c27cd8a20..9f5d72727356 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts @@ -218,9 +218,9 @@ s1 { bias-pull-down; }; - /* msm otg HSUSB_VDDCX */ + /* msm otg HSUSB_VDDCX and VDD_DIG */ s3 { - regulator-min-microvolt = <500000>; + regulator-min-microvolt = <950000>; regulator-max-microvolt = <1150000>; qcom,switch-mode-frequency = <4800000>; }; @@ -301,6 +301,12 @@ l23 { bias-pull-down; }; + /* VDD_MEM */ + l24 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + }; + /* * tabla2x-slim-CDC_VDDA_A_1P2V * tabla2x-slim-VDDD_CDC_D @@ -329,8 +335,12 @@ lvs6 { /* * mipi_dsi.1-dsi1_vddio * pil_riva-pll_vdd + * HFPLL regulator */ lvs7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; bias-pull-down; }; }; From patchwork Sun Jun 25 20:25:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 696651 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61642C04E69 for ; Sun, 25 Jun 2023 20:26:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230434AbjFYU0X (ORCPT ); Sun, 25 Jun 2023 16:26:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60880 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230459AbjFYU0V (ORCPT ); Sun, 25 Jun 2023 16:26:21 -0400 Received: from mail-lj1-x22b.google.com (mail-lj1-x22b.google.com [IPv6:2a00:1450:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0632AE75 for ; Sun, 25 Jun 2023 13:26:09 -0700 (PDT) Received: by mail-lj1-x22b.google.com with SMTP id 38308e7fff4ca-2b699284ff4so12189011fa.2 for ; Sun, 25 Jun 2023 13:26:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687724768; x=1690316768; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rsB0kVQqX4mQM7Q3aDO7WkdZMCIaYUHODUHDaiQmm24=; b=rm7Pg0KmuGexdBAp36B8Gl2KIiLw78VIsMS5mILTXlIzw+V9xIZwQMkj+/7tcGJ2sZ znYdWyLd4iJBljNtWoSFrgHf8/rqIkLzs6pFDMbmS9lDCeWbzJ9poAq7sJUX3iobGPpJ JBjU772CnwXiz4jnwNjtauYqwekpxSp25TIs2OX//RQz7LRwfXdH7Zd5et9v68OAyUeT dHqVAzvgYHUCcV8oS2CYPli1Va9P8QNJ+AiySIu2L3Iy9qHLtF/rkVxNXLYF4ByIPoVg TsvCdzXGiyOH1o4lrb+JEIvHfDOlxd3pg8wIW3kZrq0O6y8iYo9Z/oJOD1Y4gpTMXVGe 2Dcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687724768; x=1690316768; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rsB0kVQqX4mQM7Q3aDO7WkdZMCIaYUHODUHDaiQmm24=; b=GgHJT8KTaM5Jg1a816LnZzJWZk2XxvLctBx+95NCi4p9UPJ3Gk2TmI8+oQEyBcLHxE t/Hdj6XsHPmY8etyYslGlCIlePGtTkPmLVkyrni3A6QHINe8gt07rXd45RyhHTNwWKS9 TpnXZk66rZ6SFHl9JuR616DLmDcCLAtynhYynbLlQ3BcYqwS4/wZbW/LO53ns1RaX4XD 2h0gWp5W1iFJdYyk79pHtebmRQwqGZCX0PvkFHmevOEKPJiaZcuIFSovaqpYr9+wV9Rp E8gABnqBkTMBo19L5anOLPYBoDSY3ndBkSq6YjjjyuI4OTj323U7RFkFY0KxIEROF/qN E9Mw== X-Gm-Message-State: AC+VfDzr1nKUgxz7AJjyTc8WwkiYgsOmQbqKZzgjcpWr84IrQ60yIEKZ valS1hJQLRp6DMrmbyKsB3uXmQ== X-Google-Smtp-Source: ACHHUZ7CHkogDyv44MiRPQkIPF8Zv0B5eSz5A9zcFea+knBkfFw+iSG6+3HjDMVst2VMERATa7MKcw== X-Received: by 2002:a2e:9650:0:b0:2b6:9d4a:d67b with SMTP id z16-20020a2e9650000000b002b69d4ad67bmr857533ljh.44.1687724768085; Sun, 25 Jun 2023 13:26:08 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id m21-20020a195215000000b004f8427f8716sm787537lfb.262.2023.06.25.13.26.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jun 2023 13:26:07 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v2 21/26] ARM: dts: qcom: apq8064-ifc6410: constraint cpufreq regulators Date: Sun, 25 Jun 2023 23:25:42 +0300 Message-Id: <20230625202547.174647-22-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> References: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add additional constraints to the CPUfreq-related regulators, it is better be safe than sorry there. Signed-off-by: Dmitry Baryshkov Acked-by: Konrad Dybcio --- .../arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts index 96307550523a..ad3cd45362df 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts @@ -215,8 +215,8 @@ s1 { }; s3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; qcom,switch-mode-frequency = <4800000>; }; @@ -262,6 +262,12 @@ l23 { bias-pull-down; }; + l24 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + bias-pull-down; + }; + lvs1 { bias-pull-down; }; @@ -269,6 +275,14 @@ lvs1 { lvs6 { bias-pull-down; }; + + /* HFPLL regulator */ + lvs7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; }; }; From patchwork Sun Jun 25 20:25:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 696650 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA13DC18E1B for ; Sun, 25 Jun 2023 20:26:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230506AbjFYU0Z (ORCPT ); Sun, 25 Jun 2023 16:26:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230484AbjFYU0V (ORCPT ); Sun, 25 Jun 2023 16:26:21 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB870E4C for ; Sun, 25 Jun 2023 13:26:10 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id 2adb3069b0e04-4f8775126d3so3176520e87.1 for ; Sun, 25 Jun 2023 13:26:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687724769; x=1690316769; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7x8ZUoWpxa9r1cAw/Urm1Fq8ospvaA77mmKnj58hx+A=; b=lkhqRRhaId1+fbUnNm8uMIjIIeodv/0pwGqmfPIll+FGFZPjIPD4zB3v/ZkkRNHxrL ut8mxWqb8nwiMJ52OWmyXx9p0opqy/I0cj7g02zq0i60qmruBvk2V2DAS1G62rJg0Mt9 Cfa/juZPY/drDVUEkNHVjG4GOPb47bYWOpqNiqwxzIFKpGhXvglBA0kBy+INLzmsOvJV OAnJWJCyxHk0xtbckgVdPRxXr2qz3Au6yja5K67p3IZ0zvzoDe1lFfjuqm0j2nk1ZcUu PqOFnAV4LWTW9mhD+e3+/9VoTRScOqZ9nc1KA7Vzk2iMXeUdAX5unLvc/6yAFaCrRh9p /A+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687724769; x=1690316769; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7x8ZUoWpxa9r1cAw/Urm1Fq8ospvaA77mmKnj58hx+A=; b=GGWUmyl++lzYkLRSZxPmcYG5KwaTRjHx/zPa8Bjxbewl0sNClBw8Zls8OwLrIYuvv4 F31jd3rB6LuyQJiJ8jYyX4zspJbDvh0wL5fcIZjgeJ7Ucb1urLtYQRuPzYRMbZ5ODCoc jCiSEpmjp5oY4HGwo+qp6eSB1appA4KAUhbMxMBa87qttAPwCIFpNE5c4zbOerXhuCwi 3Vjuv8mAxbZYeCVXpLGDydZM7696LuWW0W+R0V95A6/Kk0oIf7Cdq2TRH8CUkCZjLsbp Meo5LRkYprMOq+NmKUhRtSWkozQQCHoCxEXMWhRHBWnz/N0PRxYiak7Kxrbd4RNU9rO2 FyeA== X-Gm-Message-State: AC+VfDyuv1/D6lKGVZGyfVzZvnbWmzINORoOUp+Dn2SHrNTNbsBSJT7B biWMVJpzfTk6/Fbkex+7NQQzhg== X-Google-Smtp-Source: ACHHUZ5XjeASG5nUB0DbX/IzMVaJHVKgs5sHkFrYuBE2nlr+YdkMA9u4/K8F3fEDH+ZGO0xR/zNH1A== X-Received: by 2002:a05:6512:32d3:b0:4f9:6528:fb1e with SMTP id f19-20020a05651232d300b004f96528fb1emr8150780lfg.51.1687724768852; Sun, 25 Jun 2023 13:26:08 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id m21-20020a195215000000b004f8427f8716sm787537lfb.262.2023.06.25.13.26.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jun 2023 13:26:08 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v2 22/26] ARM: dts: qcom: msm8960: declare SAW2 regulators Date: Sun, 25 Jun 2023 23:25:43 +0300 Message-Id: <20230625202547.174647-23-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> References: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SAW2 (SPM and AVS Wrapper) among other things is yet another way to handle CPU-related PMIC regulators. Provide a way to control voltage of these regulators. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index fa2013388d99..50a5d87e9851 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -227,13 +227,21 @@ acc1: clock-controller@2098000 { saw0: regulator@2089000 { compatible = "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw0_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; saw1: regulator@2099000 { compatible = "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw1_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; gsbi5: gsbi@16400000 { From patchwork Sun Jun 25 20:25:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 696292 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6338C001DB for ; Sun, 25 Jun 2023 20:26:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230507AbjFYU00 (ORCPT ); Sun, 25 Jun 2023 16:26:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229689AbjFYU0X (ORCPT ); Sun, 25 Jun 2023 16:26:23 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 854689E for ; Sun, 25 Jun 2023 13:26:11 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id 2adb3069b0e04-4f8735ac3e3so3375407e87.2 for ; Sun, 25 Jun 2023 13:26:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687724770; x=1690316770; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2v2jo2vlueDBgLi7osAEGDY72QrtYiWub+RBKr9UBf8=; b=yQcX4aUlMdAYIhov2f1U4yo07kKzuLanngLfnfT3zKJqJygQtE/rGulBH792tQKX5K GqE7/lXZL8veLtLOvIMVVVXQgPcmORbD6QAyeNWPTTXJh3bjSHoRpfAKVOrsyKvmRGTT WZkkdj98l2lyXl+DcWRoNRtlNdCwILgpKVWuKfbFAmxW4ZWHKJR/vMzmVw2DuA4L/eaG RgLCdmq84C+kNOQ9OhgnfMnTULyQogRD2D+CnVqZv6aPCKeUezlxRgvM45Txavk8b5WP wQTQ3l7dQ5cYWt9BBc6zDWrNGc8Y89vdKw9Q3CAn7NdODwhKkTzHaxNNt3Wy69Iy3l5V I+ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687724770; x=1690316770; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2v2jo2vlueDBgLi7osAEGDY72QrtYiWub+RBKr9UBf8=; b=cf7uwFfdTNwDp+GSW4eSLn/VhKDmoRcCF8hxN6BYgix5VK/RR91Lil5Qm/kbLsnHiu W6r4H6jvLOUKAJn7/0Lliz1xC1zn4RUo/OcVUCmixIaY7R1v6Kr6WW25E3W/FziJDzqs jCTzHwn6bRXvk7T5Vv1SosbNiPFD77Z7zkPxALk3EDLP77DrkQQMiS0muMUnwspYvd5x 9f40WIbLtzLhJkk7H6BvZCxFSylQ38KtOkHR643WMiJuNlASO5E9gsbD2uLJ1N5sh/8W pUSYa8k31ggplfLLTpLV1EeYRn64k1esImknaR4kcX/5XGwt9htH52eA9MjBqdyZ7hGr n5FQ== X-Gm-Message-State: AC+VfDx/yYrY8jFVPxE3DoQTBwlylQfwG+lRl9qSBG3BDg9yF3BaGdIq DSpnZvFWe+05LDCsoxlykbZLGw== X-Google-Smtp-Source: ACHHUZ7Wi/Att+CmRFxYOL5PfnwptwpMbcCY/RzO7cIWFEo0ICIIYpHET4zGxNWYItrkXEhYdW4lmw== X-Received: by 2002:a05:6512:3f9:b0:4fa:5fbc:bdc8 with SMTP id n25-20020a05651203f900b004fa5fbcbdc8mr1496744lfq.5.1687724769833; Sun, 25 Jun 2023 13:26:09 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id m21-20020a195215000000b004f8427f8716sm787537lfb.262.2023.06.25.13.26.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jun 2023 13:26:09 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v2 23/26] ARM: dts: qcom: apq8084: drop 'regulator' property from SAW2 device Date: Sun, 25 Jun 2023 23:25:44 +0300 Message-Id: <20230625202547.174647-24-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> References: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SAW2 device should describe the regulator constraints rather than just declaring that it has the regulator. Drop the 'regulator' property. If/when CPU voltage scaling is implemented for this platform, proper regulator node show be added instead. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-apq8084.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi index 8f178bc87e1d..6a2ff30a2f3c 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi @@ -652,7 +652,6 @@ saw3: power-controller@f90b9000 { saw_l2: power-controller@f9012000 { compatible = "qcom,saw2"; reg = <0xf9012000 0x1000>; - regulator; }; acc0: power-manager@f9088000 { From patchwork Sun Jun 25 20:25:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 696649 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 370E7C19F4F for ; Sun, 25 Jun 2023 20:26:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229754AbjFYU01 (ORCPT ); Sun, 25 Jun 2023 16:26:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60954 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230491AbjFYU0X (ORCPT ); Sun, 25 Jun 2023 16:26:23 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E4CEE5A for ; Sun, 25 Jun 2023 13:26:12 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-4fa48b5dc2eso1302401e87.1 for ; Sun, 25 Jun 2023 13:26:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687724770; x=1690316770; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TfzmpqSD79x1GTEZoTIOiNSPZieOVWfrUJaJ2GmzOH4=; b=cJdy/4OhSwkUj1088CJn/xMbpEzqiyH1HAceqyqPlu9IMXUfIRh85iaU3X5XeKfaJ0 aYdgAEvbWlsnGZSIwgiBE9tP4jSUZlxf+BkxUQmP8rGuZGZRSVS5rVggst3ZIXgsft6z HE1mmZRmp0BmmRVCjoHaVLifSR4tcsVFshd30MRs9Khpl3RkuGnqOEOHl5P5JsPgHR6a zrSldfT9jcFTsOtuHVhf1HF9EN72K0hY54R+f50vy1foDz7lrlrZioxXVHUsdeFlmg1F vPJgyBE7k90qOJ7qKW5g1lJmKs4r+ncm8YgAZL17qoaclmROhno0IDaXZJV0F5dXqkur vDdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687724770; x=1690316770; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TfzmpqSD79x1GTEZoTIOiNSPZieOVWfrUJaJ2GmzOH4=; b=ETjijdAhFtyW750ByjspEvwwQTx3j2BybLX2JxuhZcjwRA9gN5mGud9yQhJdCScxvG kIUIn1vvTknmyMW/m4GCTlpd6dJEP749HPN+97kgyVEy7O7mSTHgZ++q5CJuYoqWeK7P ILEb4q/0miJhqysoRVk7+9Yq3yWsrpwo29us/vnv7Nf3iLpn6y49deq1m2lkKb/fwmvt 8ke/cPp06oKNaobE+3gQsS2lrpjc74dSoSMyIeSqF3FWAdCCbPidtG0mjsWLg82R55vB GDXHFxKgqbr/T1xtcQNNj3WUKCJK55higWYnKKNe+wvEzcZhvHIsOpbdp2mcNWK4cbuD mcnw== X-Gm-Message-State: AC+VfDymKWtQ/qcCAcYmYZejdHQ5Vsh0Dw/nSo5+L5OvIeurnD9YdUaM dDeaUEvJj913dkfFeLVTQakaWg== X-Google-Smtp-Source: ACHHUZ4/NpURkZggRD1r3X1/yZ+cy38Mw3jmI2h3kMbN+8ZTn/hu4CYQ61UXmDt5KaXY2sezTq5W7A== X-Received: by 2002:a19:6457:0:b0:4f8:5604:4b50 with SMTP id b23-20020a196457000000b004f856044b50mr14983458lfj.64.1687724770571; Sun, 25 Jun 2023 13:26:10 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id m21-20020a195215000000b004f8427f8716sm787537lfb.262.2023.06.25.13.26.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jun 2023 13:26:10 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v2 24/26] ARM: dts: qcom: msm8974: drop 'regulator' property from SAW2 device Date: Sun, 25 Jun 2023 23:25:45 +0300 Message-Id: <20230625202547.174647-25-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> References: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SAW2 device should describe the regulator constraints rather than just declaring that it has the regulator. Drop the 'regulator' property. If/when CPU voltage scaling is implemented for this platform, proper regulator node show be added instead. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index aeca504918a0..dffab32c757d 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -416,7 +416,6 @@ saw3: power-controller@f90b9000 { saw_l2: power-controller@f9012000 { compatible = "qcom,saw2"; reg = <0xf9012000 0x1000>; - regulator; }; acc0: power-manager@f9088000 { From patchwork Sun Jun 25 20:25:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 696291 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70A7AC25B5E for ; Sun, 25 Jun 2023 20:26:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230435AbjFYU02 (ORCPT ); Sun, 25 Jun 2023 16:26:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60810 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229653AbjFYU00 (ORCPT ); Sun, 25 Jun 2023 16:26:26 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F09B10D4 for ; Sun, 25 Jun 2023 13:26:13 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id 2adb3069b0e04-4fb7589b187so206863e87.1 for ; Sun, 25 Jun 2023 13:26:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687724771; x=1690316771; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=e22bJ5odjM+mKTro24WKxPv4ydhQmUrgsro1UZPvXrQ=; b=Zo7fl8m7cSpxTd+Uaa2MxLO5oWKlct8vRbtBKNav8TO6ZsEGLAIWmehBGY1a2oM5rO c+MTx2bWXXa3BtlD/1hZF9j524Em2hy3gA909+jjuyNz8h3HJoJV2o5tSr9JULopD4j5 N/QHtStBuSsJAdh4aZ39qrKZb/nVnkjs9hVMGpz9GAu5Yh65fVYUNaUYmz2FeQLfFwPp js/zDyc+YVmvRRSwN4V3rnKwWI0/UR+rUL6TPAOQfhvfTo4x6qlNiSOttSbeCOpRDL2R 5UsjTD+trtKmpTiqp2km+WYU9k7a21fCP/LkiRy2TJvgkxmiZNT8EW1/sWYc8K6AA8W7 t/ZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687724771; x=1690316771; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e22bJ5odjM+mKTro24WKxPv4ydhQmUrgsro1UZPvXrQ=; b=FHlIjktGFhymkD84cguC13oMdVmJPFunZMP7Wy4BTOSVOWV6OkTKG4MVAQ2ITAqdxh leojnsM7QHaCXzKBObER6ZUf20nVY5NyC8lyTjuxV4tIuiU0CdI+wBRR+mOq1L2wJD1W TvNm9Z76DQ+5IBZg5677iIhKgHlHc2hu7TWdFqZYO+Nd+b6lGzIXZ4/svbpgSNIKZLnY EsQs5dV2B8P3htRcrvbb0LG2CH7lRB6XtXldCjxszA3pgA9c5tT9+t8QTU7VWrlrfmSW lSdkrPxukx7J8qf09MWcV1vvW5kpHKVgOX6tp4w/P8hMVKopYk/fXIJskawIRNLJ39jt KGzQ== X-Gm-Message-State: AC+VfDxcaKc7Mc7TIxUD5JaWJxK3Pv4+oD/54esaIXpyP1+MUlGjKLbQ YLQyPg/xi2fw3ym7Jn/VR6iY+Q== X-Google-Smtp-Source: ACHHUZ54rWODI2kWXKgGxg3+8huxLYpdqXLp90DRSLnjKscjuTRQ49vMHoRzFIpckOq7L4hZG+BwXA== X-Received: by 2002:a05:6512:ad6:b0:4f9:cb8f:3182 with SMTP id n22-20020a0565120ad600b004f9cb8f3182mr1681727lfu.25.1687724771365; Sun, 25 Jun 2023 13:26:11 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id m21-20020a195215000000b004f8427f8716sm787537lfb.262.2023.06.25.13.26.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jun 2023 13:26:10 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v2 25/26] ARM: dts: qcom: ipq4019: drop 'regulator' property from SAW2 devices Date: Sun, 25 Jun 2023 23:25:46 +0300 Message-Id: <20230625202547.174647-26-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> References: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SAW2 device should describe the regulator constraints rather than just declaring that it has the regulator. Drop the 'regulator' property. If/when CPU voltage scaling is implemented for this platform, proper regulator nodes show be added instead. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index f0ef86fadc9d..ad3c922843c7 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -350,31 +350,26 @@ acc3: power-manager@b0b8000 { saw0: regulator@b089000 { compatible = "qcom,saw2"; reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>; - regulator; }; saw1: regulator@b099000 { compatible = "qcom,saw2"; reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; - regulator; }; saw2: regulator@b0a9000 { compatible = "qcom,saw2"; reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; - regulator; }; saw3: regulator@b0b9000 { compatible = "qcom,saw2"; reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; - regulator; }; saw_l2: regulator@b012000 { compatible = "qcom,saw2"; reg = <0xb012000 0x1000>; - regulator; }; blsp1_uart1: serial@78af000 { From patchwork Sun Jun 25 20:25:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 696648 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE855EB64DD for ; Sun, 25 Jun 2023 20:26:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229827AbjFYU0b (ORCPT ); Sun, 25 Jun 2023 16:26:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60882 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230491AbjFYU03 (ORCPT ); Sun, 25 Jun 2023 16:26:29 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 39F4A10E3 for ; Sun, 25 Jun 2023 13:26:14 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-4f122ff663eso3096893e87.2 for ; Sun, 25 Jun 2023 13:26:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687724772; x=1690316772; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HiV5z5zUGyF9t+SInKUjgyhbtQRee0OBw3xrDTOT36E=; b=C5H52spIDIYjTr5qExPIoHx3cPrpxJxpZJKRuinORN+vMRj/dj6axv3iMlGXBnZaR1 uJxczyaouIvDVzPaWPBQgnsu9iieTt45YVP0DeJtVHwjZDVx1qbsNDYJhv4kLcA1jgHh 0do0bRsu2m81tfR7VN5jRlf60hHHPdXd1KmctqFKtWpb694j8VBlm/loCNOVvjyjekD5 DLVempKF0Q/F2qjToa2vWCaE3E/uvznYFj/w/SxhwuTMJFFxTLtrvE7fie3yL/w1Ki85 fhzbC7MJtrGnEACkpHhQ1zdrDcnknm/D451DiOEWYHrhmSd+3PEylp5Yrq4r38GM0Ko1 rr7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687724772; x=1690316772; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HiV5z5zUGyF9t+SInKUjgyhbtQRee0OBw3xrDTOT36E=; b=IFP68dFEExc8kJmdAcAcLE+pFTVea5Imgl1vcyhIRzDvVq+9k3kSNGmywHzu6+jYnE zedZN9bJQPmN1Mk8TJnlZq9Zz9ND/nRgz2mEGTVbbzAyBvXLtJm9QYfXM8EOULicWGu2 FOXb2ST0wP6DX5hXejdhSoMMEw1PARUZ66fYIwJYOV1Enk4dOn+aSRAg6NktVuUhXaIK OPgjHs0EK17bCrHcm+Yfq4aoDag3/MzjAIRTywuMpjYwZKE8O9lScuDurkAfneq6MngF +TkbRIgavOU5zO9ldkgxbJPLdIlzErqI4TBgf3pppXpllvNWamkr/we42X79OYauvzno 35yA== X-Gm-Message-State: AC+VfDyK1Hkp4buJAA68Y0ydwIKw/wLdkA0Tntxmi+Jgnb+Xur9FsYMy uzCLqcYbB8bOq3RUrniwvmqoHw== X-Google-Smtp-Source: ACHHUZ45iG+1Sacn3/JNwppp4cAoDOFgBmwMe5BAxdk+yGg/pGOUFqw3c/qpIFx1UwMjlfCEzqZz8w== X-Received: by 2002:ac2:5b9a:0:b0:4f8:582f:414e with SMTP id o26-20020ac25b9a000000b004f8582f414emr15324375lfn.15.1687724772115; Sun, 25 Jun 2023 13:26:12 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id m21-20020a195215000000b004f8427f8716sm787537lfb.262.2023.06.25.13.26.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jun 2023 13:26:11 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v2 26/26] ARM: dts: qcom: ipq8064: drop 'regulator' property from SAW2 devices Date: Sun, 25 Jun 2023 23:25:47 +0300 Message-Id: <20230625202547.174647-27-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> References: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SAW2 device should describe the regulator constraints rather than just declaring that it has the regulator. Drop the 'regulator' property. If/when CPU voltage scaling is implemented for this platform, proper regulator nodes show be added instead. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi index 6198f42f6a9c..ecb99e104de0 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi @@ -589,7 +589,6 @@ acc0: clock-controller@2088000 { saw0: regulator@2089000 { compatible = "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; }; acc1: clock-controller@2098000 { @@ -604,7 +603,6 @@ acc1: clock-controller@2098000 { saw1: regulator@2099000 { compatible = "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; }; nss_common: syscon@3000000 {