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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id kt19-20020a170906aad300b009894b476310sm4253038ejb.163.2023.06.27.01.28.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Jun 2023 01:28:07 -0700 (PDT) From: Luca Weiss Date: Tue, 27 Jun 2023 10:28:03 +0200 Subject: [PATCH v5 3/5] dt-bindings: ufs: qcom: Add ICE to sm8450 example MIME-Version: 1.0 Message-Id: <20221209-dt-binding-ufs-v5-3-c9a58c0a53f5@fairphone.com> References: <20221209-dt-binding-ufs-v5-0-c9a58c0a53f5@fairphone.com> In-Reply-To: <20221209-dt-binding-ufs-v5-0-c9a58c0a53f5@fairphone.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Iskren Chernev , Manivannan Sadhasivam , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.12.2 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org SM8450 actually supports ICE (Inline Crypto Engine) so adjust the example to match. Signed-off-by: Luca Weiss --- Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml index 2b0831622cf0..462ead5a1cec 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -317,5 +317,6 @@ examples: <0 0>, <0 0>, <0 0>; + qcom,ice = <&ice>; }; }; From patchwork Tue Jun 27 08:28:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 697486 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DAF0DEB64DC for ; Tue, 27 Jun 2023 08:29:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231869AbjF0I3C (ORCPT ); Tue, 27 Jun 2023 04:29:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36376 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231901AbjF0I2Q (ORCPT ); Tue, 27 Jun 2023 04:28:16 -0400 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D191F26A5 for ; Tue, 27 Jun 2023 01:28:10 -0700 (PDT) Received: by mail-ej1-x62c.google.com with SMTP id a640c23a62f3a-98e25fa6f5bso417707866b.3 for ; Tue, 27 Jun 2023 01:28:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1687854489; x=1690446489; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=j8uhdc0vGRhVZn7i76kQPqxuDPzGvhRMJMMuHesHRx0=; b=jA3lP92ZFZ2gqMx6lDW6O07ihkd3l3XzaGJxuC/g2wtwdnfKVTbxH8xMCmMBhFkAfn XhRWbXQmZW9VfqvKgM9V/ufYcXvvOcE0Pr7oqA1TBEw8ivcUkqoOPWNrFgbJc/kxkxw3 fyqQIMK2YqEJvvN/YHps3MSQuC08HiFJ5o7pDNwEVCWtwE1efv8ygroRZZlTrho0NP// 9EER9mVtiNQMkxuGU1pLiLj8pD8fcA4HObgafIcVSDg0PCVhE1Kfqz0au+iBg6dl2wRa cyN6klB5VHWvtkGIH/be8fHAYD9RHnPxEtksmQEkAZHUzs2YDxBi4nBDRKY6ZhLbl8E4 Asag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687854489; x=1690446489; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=j8uhdc0vGRhVZn7i76kQPqxuDPzGvhRMJMMuHesHRx0=; b=FHnN9fMavkH5/5pc03Azn/U6DE4hBcf786MHTmlK83xhatg3fVIqLG8cvrxyxBX/ca oElPkduAPBqzyz5dFU5PhQfATwYMBlRCseNdJ6mR9Rvi/xdHw/csQ4ekTz6usAoHZR58 3sbCs6YXm0yrK34qtjJ6N/9BvlK9Q61kFSys8FHUHWrHoVPn1WYM1W/2K/kU+/pbZaED AFj3THf3fh/y8LFU+cPJ910qvEYVfrGepPZtboFjOLsgSsbMOB4HGV238+HZVOoUftKy C1k1F1f4IyMmUX4778heztcP/wttHmB1XqjU69w/yE4GP+KxVyzlMWs+rbX7zqRvzhjG HJNA== X-Gm-Message-State: AC+VfDyZpW+rSkY3RzeoIwUrAC3Iw2u9sjHYHcgbKtN4Tt2GX1JecMmm pPw+2Y+2mOodblJcUpg6zrJk+w== X-Google-Smtp-Source: ACHHUZ4b8ooGad04xAZNZR46c7dDBigN6joEZVBjCg51B/ahsXcmBhiabKcqs0pCUO20Iz0Jg4YNQA== X-Received: by 2002:a17:907:5c8:b0:974:7713:293f with SMTP id wg8-20020a17090705c800b009747713293fmr29242940ejb.41.1687854489185; Tue, 27 Jun 2023 01:28:09 -0700 (PDT) Received: from [172.16.240.113] (144-178-202-138.static.ef-service.nl. [144.178.202.138]) by smtp.gmail.com with ESMTPSA id kt19-20020a170906aad300b009894b476310sm4253038ejb.163.2023.06.27.01.28.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Jun 2023 01:28:08 -0700 (PDT) From: Luca Weiss Date: Tue, 27 Jun 2023 10:28:05 +0200 Subject: [PATCH v5 5/5] arm64: dts: qcom: sm8450: Use standalone ICE node for UFS MIME-Version: 1.0 Message-Id: <20221209-dt-binding-ufs-v5-5-c9a58c0a53f5@fairphone.com> References: <20221209-dt-binding-ufs-v5-0-c9a58c0a53f5@fairphone.com> In-Reply-To: <20221209-dt-binding-ufs-v5-0-c9a58c0a53f5@fairphone.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Iskren Chernev , Manivannan Sadhasivam , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.12.2 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org With the ICE driver now merged let's convert the ufs node to use the new style. Signed-off-by: Luca Weiss --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 5cd7296c7660..79627117a776 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -4120,9 +4120,7 @@ system-cache-controller@19200000 { ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8450-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x3000>, - <0 0x01d88000 0 0x8000>; - reg-names = "std", "ice"; + reg = <0 0x01d84000 0 0x3000>; interrupts = ; phys = <&ufs_mem_phy_lanes>; phy-names = "ufsphy"; @@ -4147,8 +4145,7 @@ ufs_mem_hc: ufshc@1d84000 { "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", - "rx_lane1_sync_clk", - "ice_core_clk"; + "rx_lane1_sync_clk"; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, @@ -4157,8 +4154,7 @@ ufs_mem_hc: ufshc@1d84000 { <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, - <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; freq-table-hz = <75000000 300000000>, <0 0>, @@ -4167,8 +4163,9 @@ ufs_mem_hc: ufshc@1d84000 { <75000000 300000000>, <0 0>, <0 0>, - <0 0>, - <75000000 300000000>; + <0 0>; + qcom,ice = <&ice>; + status = "disabled"; }; @@ -4198,6 +4195,13 @@ ufs_mem_phy_lanes: phy@1d87400 { }; }; + ice: crypto@1d88000 { + compatible = "qcom,sm8450-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0 0x01d88000 0 0x8000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + cryptobam: dma-controller@1dc4000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0 0x01dc4000 0 0x28000>;