From patchwork Sat Jul 8 07:28:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jishnu Prakash X-Patchwork-Id: 700966 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F4C7EB64DC for ; Sat, 8 Jul 2023 07:29:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230475AbjGHH3n (ORCPT ); Sat, 8 Jul 2023 03:29:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58330 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229876AbjGHH3m (ORCPT ); Sat, 8 Jul 2023 03:29:42 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4287F210C; Sat, 8 Jul 2023 00:29:38 -0700 (PDT) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3687PrUQ022632; Sat, 8 Jul 2023 07:29:10 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=GRkhApRe4hiDdHUz/jt+9XYqISK6l7UU9XJ3gGb9sQk=; b=TBQQr8lORyP3K+5YWeMYXDBivR1XSKeLFHmwP5+NlRqRIUQt/tBl+07zURe19i7s9wcH YVz16VlQXbFZLKr+KxjEUCjv6nHLKiANq6DKzzCO52mB7kj/pCjTu8FJXsh1vKuLQLXO ClP/qrgWEVGV7BbBdGOChiKcnlDL6zoUbkmyGThhU/b+nMCcisOpfAwrvw4V8V8kxOWU 77PkdIehbF2h2++yJVUHzJIIGqZ4u22in3/8uqDPlh99cmFCDKxio/dkE30LvxVbxafY KOSctNwS9nImWN/Z8VZ3zXfNolq2edP+j1Qv5LWPZ/LrGuzdfHXeFtUOaR/YYBuPbrds gw== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rpxry093s-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 08 Jul 2023 07:29:09 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3687T9ii023714 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 8 Jul 2023 07:29:09 GMT Received: from hu-jprakash-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Sat, 8 Jul 2023 00:28:59 -0700 From: Jishnu Prakash To: , , , , , , , , , , , , , , Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , "Rafael J. Wysocki" , "Daniel Lezcano" , Amit Kucheria , "Zhang Rui" , Jishnu Prakash , "Luca Weiss" , , , CC: Subject: [PATCH 01/11] iio: adc: Update bindings for ADC7 name used on QCOM PMICs Date: Sat, 8 Jul 2023 12:58:25 +0530 Message-ID: <20230708072835.3035398-2-quic_jprakash@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230708072835.3035398-1-quic_jprakash@quicinc.com> References: <20230708072835.3035398-1-quic_jprakash@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: mZHkkGtPTjzkNBUw3mznvacL07FSDXGn X-Proofpoint-GUID: mZHkkGtPTjzkNBUw3mznvacL07FSDXGn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-08_04,2023-07-06_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 priorityscore=1501 mlxscore=0 malwarescore=0 bulkscore=0 clxscore=1011 suspectscore=0 impostorscore=0 adultscore=0 phishscore=0 lowpriorityscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307080065 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The name used initially for this version of Qualcomm Technologies, Inc. PMIC ADC was ADC7, following the convention of calling the PMIC generation PMIC7. However, the names were later amended internally to ADC5 Gen2 and PMIC5 Gen2. In addition, the latest PMIC generation now is known as PMIC5 Gen3 with ADC5 Gen3 supported on it. With this addition, it makes more sense to correct the name for this version of ADCs to ADC5 Gen2 from ADC7. Since this affects ADC devices across some PMICs, update the names accordingly. In order to avoid breaking the existing implementations of ADC7, add support for ADC5 Gen2 first now and remove the ADC7 support in a later patch. Signed-off-by: Jishnu Prakash --- .../bindings/iio/adc/qcom,spmi-vadc.yaml | 21 +++-- .../bindings/thermal/qcom-spmi-adc-tm5.yaml | 16 ++-- .../iio/qcom,spmi-adc5-gen2-pm8350.h | 64 +++++++++++++ .../iio/qcom,spmi-adc5-gen2-pm8350b.h | 89 +++++++++++++++++++ .../iio/qcom,spmi-adc5-gen2-pmk8350.h | 47 ++++++++++ .../iio/qcom,spmi-adc5-gen2-pmr735a.h | 29 ++++++ .../iio/qcom,spmi-adc5-gen2-pmr735b.h | 28 ++++++ include/dt-bindings/iio/qcom,spmi-vadc.h | 77 ++++++++++++++++ 8 files changed, 354 insertions(+), 17 deletions(-) create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350.h create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350b.h create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmk8350.h create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735a.h create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735b.h diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml index ad7d6fc49de5..f886977de165 100644 --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml @@ -13,7 +13,7 @@ maintainers: description: | SPMI PMIC voltage ADC (VADC) provides interface to clients to read voltage. The VADC is a 15-bit sigma-delta ADC. - SPMI PMIC5/PMIC7 voltage ADC (ADC) provides interface to clients to read + SPMI PMIC5/PMIC5 Gen2 voltage ADC (ADC) provides interface to clients to read voltage. The VADC is a 16-bit sigma-delta ADC. properties: @@ -27,6 +27,7 @@ properties: - qcom,spmi-adc5 - qcom,spmi-adc-rev2 - qcom,spmi-adc7 + - qcom,spmi-adc5-gen2 reg: description: VADC base address in the SPMI PMIC register map @@ -71,7 +72,7 @@ patternProperties: description: | ADC channel number. See include/dt-bindings/iio/qcom,spmi-vadc.h - For PMIC7 ADC, the channel numbers are specified separately per PMIC + For PMIC5 Gen2 ADC, the channel numbers are specified separately per PMIC in the PMIC-specific files in include/dt-bindings/iio/. label: @@ -114,7 +115,7 @@ patternProperties: channel calibration. If property is not found, channel will be calibrated with 0.625V and 1.25V reference channels, also known as absolute calibration. - - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc7" and + - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc5-gen2" and "qcom,spmi-adc-rev2", if this property is specified VADC will use the VDD reference (1.875V) and GND for channel calibration. If property is not found, channel will be calibrated with 0V and 1.25V @@ -213,7 +214,9 @@ allOf: properties: compatible: contains: - const: qcom,spmi-adc7 + enum : + - qcom,spmi-adc7 + - qcom,spmi-adc5-gen2 then: patternProperties: @@ -277,8 +280,8 @@ examples: }; - | - #include - #include + #include + #include #include spmi { @@ -286,21 +289,21 @@ examples: #size-cells = <0>; adc@3100 { reg = <0x3100>; - compatible = "qcom,spmi-adc7"; + compatible = "qcom,spmi-adc5-gen2"; #address-cells = <1>; #size-cells = <0>; #io-channel-cells = <1>; /* Other properties are omitted */ channel@44 { - reg = ; + reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; label = "xo_therm"; }; channel@47 { - reg = ; + reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; label = "conn_therm"; diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml index 3c81def03c84..01d57f13d254 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml @@ -204,29 +204,29 @@ examples: }; - | - #include - #include + #include + #include #include spmi_bus { #address-cells = <1>; #size-cells = <0>; pmk8350_vadc: adc@3100 { reg = <0x3100>; - compatible = "qcom,spmi-adc7"; + compatible = "qcom,spmi-adc5-gen2"; #address-cells = <1>; #size-cells = <0>; #io-channel-cells = <1>; /* Other properties are omitted */ channel@44 { - reg = ; + reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; label = "xo_therm"; }; channel@147 { - reg = ; + reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; label = "conn_therm"; @@ -241,9 +241,9 @@ examples: #address-cells = <1>; #size-cells = <0>; - pmk8350-xo-therm@0 { + xo-therm@0 { reg = <0>; - io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>; + io-channels = <&pmk8350_vadc PMK8350_ADC5_GEN2_AMUX_THM1_100K_PU>; qcom,decimation = <340>; qcom,ratiometric; qcom,hw-settle-time-us = <200>; @@ -251,7 +251,7 @@ examples: conn-therm@1 { reg = <1>; - io-channels = <&pmk8350_vadc PM8350_ADC7_AMUX_THM4_100K_PU(1)>; + io-channels = <&pmk8350_vadc PM8350_ADC5_GEN2_AMUX_THM4_100K_PU(1)>; qcom,avg-samples = <2>; qcom,ratiometric; qcom,hw-settle-time-us = <200>; diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350.h new file mode 100644 index 000000000000..77259beaf6e9 --- /dev/null +++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H + +/* ADC channels for PM8350_ADC for PMIC5 Gen2 */ +#define PM8350_ADC5_GEN2_REF_GND(sid) ((sid) << 8 | 0x0) +#define PM8350_ADC5_GEN2_1P25VREF(sid) ((sid) << 8 | 0x01) +#define PM8350_ADC5_GEN2_VREF_VADC(sid) ((sid) << 8 | 0x02) +#define PM8350_ADC5_GEN2_DIE_TEMP(sid) ((sid) << 8 | 0x03) + +#define PM8350_ADC5_GEN2_AMUX_THM1(sid) ((sid) << 8 | 0x04) +#define PM8350_ADC5_GEN2_AMUX_THM2(sid) ((sid) << 8 | 0x05) +#define PM8350_ADC5_GEN2_AMUX_THM3(sid) ((sid) << 8 | 0x06) +#define PM8350_ADC5_GEN2_AMUX_THM4(sid) ((sid) << 8 | 0x07) +#define PM8350_ADC5_GEN2_AMUX_THM5(sid) ((sid) << 8 | 0x08) +#define PM8350_ADC5_GEN2_GPIO1(sid) ((sid) << 8 | 0x0a) +#define PM8350_ADC5_GEN2_GPIO2(sid) ((sid) << 8 | 0x0b) +#define PM8350_ADC5_GEN2_GPIO3(sid) ((sid) << 8 | 0x0c) +#define PM8350_ADC5_GEN2_GPIO4(sid) ((sid) << 8 | 0x0d) + +/* 30k pull-up1 */ +#define PM8350_ADC5_GEN2_AMUX_THM1_30K_PU(sid) ((sid) << 8 | 0x24) +#define PM8350_ADC5_GEN2_AMUX_THM2_30K_PU(sid) ((sid) << 8 | 0x25) +#define PM8350_ADC5_GEN2_AMUX_THM3_30K_PU(sid) ((sid) << 8 | 0x26) +#define PM8350_ADC5_GEN2_AMUX_THM4_30K_PU(sid) ((sid) << 8 | 0x27) +#define PM8350_ADC5_GEN2_AMUX_THM5_30K_PU(sid) ((sid) << 8 | 0x28) +#define PM8350_ADC5_GEN2_GPIO1_30K_PU(sid) ((sid) << 8 | 0x2a) +#define PM8350_ADC5_GEN2_GPIO2_30K_PU(sid) ((sid) << 8 | 0x2b) +#define PM8350_ADC5_GEN2_GPIO3_30K_PU(sid) ((sid) << 8 | 0x2c) +#define PM8350_ADC5_GEN2_GPIO4_30K_PU(sid) ((sid) << 8 | 0x2d) + +/* 100k pull-up2 */ +#define PM8350_ADC5_GEN2_AMUX_THM1_100K_PU(sid) ((sid) << 8 | 0x44) +#define PM8350_ADC5_GEN2_AMUX_THM2_100K_PU(sid) ((sid) << 8 | 0x45) +#define PM8350_ADC5_GEN2_AMUX_THM3_100K_PU(sid) ((sid) << 8 | 0x46) +#define PM8350_ADC5_GEN2_AMUX_THM4_100K_PU(sid) ((sid) << 8 | 0x47) +#define PM8350_ADC5_GEN2_AMUX_THM5_100K_PU(sid) ((sid) << 8 | 0x48) +#define PM8350_ADC5_GEN2_GPIO1_100K_PU(sid) ((sid) << 8 | 0x4a) +#define PM8350_ADC5_GEN2_GPIO2_100K_PU(sid) ((sid) << 8 | 0x4b) +#define PM8350_ADC5_GEN2_GPIO3_100K_PU(sid) ((sid) << 8 | 0x4c) +#define PM8350_ADC5_GEN2_GPIO4_100K_PU(sid) ((sid) << 8 | 0x4d) + +/* 400k pull-up3 */ +#define PM8350_ADC5_GEN2_AMUX_THM1_400K_PU(sid) ((sid) << 8 | 0x64) +#define PM8350_ADC5_GEN2_AMUX_THM2_400K_PU(sid) ((sid) << 8 | 0x65) +#define PM8350_ADC5_GEN2_AMUX_THM3_400K_PU(sid) ((sid) << 8 | 0x66) +#define PM8350_ADC5_GEN2_AMUX_THM4_400K_PU(sid) ((sid) << 8 | 0x67) +#define PM8350_ADC5_GEN2_AMUX_THM5_400K_PU(sid) ((sid) << 8 | 0x68) +#define PM8350_ADC5_GEN2_GPIO1_400K_PU(sid) ((sid) << 8 | 0x6a) +#define PM8350_ADC5_GEN2_GPIO2_400K_PU(sid) ((sid) << 8 | 0x6b) +#define PM8350_ADC5_GEN2_GPIO3_400K_PU(sid) ((sid) << 8 | 0x6c) +#define PM8350_ADC5_GEN2_GPIO4_400K_PU(sid) ((sid) << 8 | 0x6d) + +/* 1/3 Divider */ +#define PM8350_ADC5_GEN2_GPIO4_DIV3(sid) ((sid) << 8 | 0x8d) + +#define PM8350_ADC5_GEN2_VPH_PWR(sid) ((sid) << 8 | 0x8e) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350b.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350b.h new file mode 100644 index 000000000000..c7bb54e0b6a6 --- /dev/null +++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350b.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H + +#ifndef PM8350B_SID +#define PM8350B_SID 3 +#endif + +/* ADC channels for PM8350B_ADC for PMIC5 Gen2 */ +#define PM8350B_ADC5_GEN2_REF_GND (PM8350B_SID << 8 | 0x0) +#define PM8350B_ADC5_GEN2_1P25VREF (PM8350B_SID << 8 | 0x01) +#define PM8350B_ADC5_GEN2_VREF_VADC (PM8350B_SID << 8 | 0x02) +#define PM8350B_ADC5_GEN2_DIE_TEMP (PM8350B_SID << 8 | 0x03) + +#define PM8350B_ADC5_GEN2_AMUX_THM1 (PM8350B_SID << 8 | 0x04) +#define PM8350B_ADC5_GEN2_AMUX_THM2 (PM8350B_SID << 8 | 0x05) +#define PM8350B_ADC5_GEN2_AMUX_THM3 (PM8350B_SID << 8 | 0x06) +#define PM8350B_ADC5_GEN2_AMUX_THM4 (PM8350B_SID << 8 | 0x07) +#define PM8350B_ADC5_GEN2_AMUX_THM5 (PM8350B_SID << 8 | 0x08) +#define PM8350B_ADC5_GEN2_AMUX_THM6 (PM8350B_SID << 8 | 0x09) +#define PM8350B_ADC5_GEN2_GPIO1 (PM8350B_SID << 8 | 0x0a) +#define PM8350B_ADC5_GEN2_GPIO2 (PM8350B_SID << 8 | 0x0b) +#define PM8350B_ADC5_GEN2_GPIO3 (PM8350B_SID << 8 | 0x0c) +#define PM8350B_ADC5_GEN2_GPIO4 (PM8350B_SID << 8 | 0x0d) + +#define PM8350B_ADC5_GEN2_CHG_TEMP (PM8350B_SID << 8 | 0x10) +#define PM8350B_ADC5_GEN2_USB_IN_V_16 (PM8350B_SID << 8 | 0x11) +#define PM8350B_ADC5_GEN2_VDC_16 (PM8350B_SID << 8 | 0x12) +#define PM8350B_ADC5_GEN2_CC1_ID (PM8350B_SID << 8 | 0x13) +#define PM8350B_ADC5_GEN2_VREF_BAT_THERM (PM8350B_SID << 8 | 0x15) +#define PM8350B_ADC5_GEN2_IIN_FB (PM8350B_SID << 8 | 0x17) + +/* 30k pull-up1 */ +#define PM8350B_ADC5_GEN2_AMUX_THM1_30K_PU (PM8350B_SID << 8 | 0x24) +#define PM8350B_ADC5_GEN2_AMUX_THM2_30K_PU (PM8350B_SID << 8 | 0x25) +#define PM8350B_ADC5_GEN2_AMUX_THM3_30K_PU (PM8350B_SID << 8 | 0x26) +#define PM8350B_ADC5_GEN2_AMUX_THM4_30K_PU (PM8350B_SID << 8 | 0x27) +#define PM8350B_ADC5_GEN2_AMUX_THM5_30K_PU (PM8350B_SID << 8 | 0x28) +#define PM8350B_ADC5_GEN2_AMUX_THM6_30K_PU (PM8350B_SID << 8 | 0x29) +#define PM8350B_ADC5_GEN2_GPIO1_30K_PU (PM8350B_SID << 8 | 0x2a) +#define PM8350B_ADC5_GEN2_GPIO2_30K_PU (PM8350B_SID << 8 | 0x2b) +#define PM8350B_ADC5_GEN2_GPIO3_30K_PU (PM8350B_SID << 8 | 0x2c) +#define PM8350B_ADC5_GEN2_GPIO4_30K_PU (PM8350B_SID << 8 | 0x2d) +#define PM8350B_ADC5_GEN2_CC1_ID_30K_PU (PM8350B_SID << 8 | 0x33) + +/* 100k pull-up2 */ +#define PM8350B_ADC5_GEN2_AMUX_THM1_100K_PU (PM8350B_SID << 8 | 0x44) +#define PM8350B_ADC5_GEN2_AMUX_THM2_100K_PU (PM8350B_SID << 8 | 0x45) +#define PM8350B_ADC5_GEN2_AMUX_THM3_100K_PU (PM8350B_SID << 8 | 0x46) +#define PM8350B_ADC5_GEN2_AMUX_THM4_100K_PU (PM8350B_SID << 8 | 0x47) +#define PM8350B_ADC5_GEN2_AMUX_THM5_100K_PU (PM8350B_SID << 8 | 0x48) +#define PM8350B_ADC5_GEN2_AMUX_THM6_100K_PU (PM8350B_SID << 8 | 0x49) +#define PM8350B_ADC5_GEN2_GPIO1_100K_PU (PM8350B_SID << 8 | 0x4a) +#define PM8350B_ADC5_GEN2_GPIO2_100K_PU (PM8350B_SID << 8 | 0x4b) +#define PM8350B_ADC5_GEN2_GPIO3_100K_PU (PM8350B_SID << 8 | 0x4c) +#define PM8350B_ADC5_GEN2_GPIO4_100K_PU (PM8350B_SID << 8 | 0x4d) +#define PM8350B_ADC5_GEN2_CC1_ID_100K_PU (PM8350B_SID << 8 | 0x53) + +/* 400k pull-up3 */ +#define PM8350B_ADC5_GEN2_AMUX_THM1_400K_PU (PM8350B_SID << 8 | 0x64) +#define PM8350B_ADC5_GEN2_AMUX_THM2_400K_PU (PM8350B_SID << 8 | 0x65) +#define PM8350B_ADC5_GEN2_AMUX_THM3_400K_PU (PM8350B_SID << 8 | 0x66) +#define PM8350B_ADC5_GEN2_AMUX_THM4_400K_PU (PM8350B_SID << 8 | 0x67) +#define PM8350B_ADC5_GEN2_AMUX_THM5_400K_PU (PM8350B_SID << 8 | 0x68) +#define PM8350B_ADC5_GEN2_AMUX_THM6_400K_PU (PM8350B_SID << 8 | 0x69) +#define PM8350B_ADC5_GEN2_GPIO1_400K_PU (PM8350B_SID << 8 | 0x6a) +#define PM8350B_ADC5_GEN2_GPIO2_400K_PU (PM8350B_SID << 8 | 0x6b) +#define PM8350B_ADC5_GEN2_GPIO3_400K_PU (PM8350B_SID << 8 | 0x6c) +#define PM8350B_ADC5_GEN2_GPIO4_400K_PU (PM8350B_SID << 8 | 0x6d) +#define PM8350B_ADC5_GEN2_CC1_ID_400K_PU (PM8350B_SID << 8 | 0x73) + +/* 1/3 Divider */ +#define PM8350B_ADC5_GEN2_GPIO1_DIV3 (PM8350B_SID << 8 | 0x8a) +#define PM8350B_ADC5_GEN2_GPIO2_DIV3 (PM8350B_SID << 8 | 0x8b) +#define PM8350B_ADC5_GEN2_GPIO3_DIV3 (PM8350B_SID << 8 | 0x8c) +#define PM8350B_ADC5_GEN2_GPIO4_DIV3 (PM8350B_SID << 8 | 0x8d) + +#define PM8350B_ADC5_GEN2_VPH_PWR (PM8350B_SID << 8 | 0x8e) +#define PM8350B_ADC5_GEN2_VBAT_SNS (PM8350B_SID << 8 | 0x8f) + +#define PM8350B_ADC5_GEN2_SBUx (PM8350B_SID << 8 | 0x94) +#define PM8350B_ADC5_GEN2_VBAT_2S_MID (PM8350B_SID << 8 | 0x96) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmk8350.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmk8350.h new file mode 100644 index 000000000000..8de4ee86f875 --- /dev/null +++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmk8350.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H + +#ifndef PMK8350_SID +#define PMK8350_SID 0 +#endif + +/* ADC channels for PMK8350_ADC for PMIC5 Gen2 */ +#define PMK8350_ADC5_GEN2_REF_GND (PMK8350_SID << 8 | 0x0) +#define PMK8350_ADC5_GEN2_1P25VREF (PMK8350_SID << 8 | 0x01) +#define PMK8350_ADC5_GEN2_VREF_VADC (PMK8350_SID << 8 | 0x02) +#define PMK8350_ADC5_GEN2_DIE_TEMP (PMK8350_SID << 8 | 0x03) + +#define PMK8350_ADC5_GEN2_AMUX_THM1 (PMK8350_SID << 8 | 0x04) +#define PMK8350_ADC5_GEN2_AMUX_THM2 (PMK8350_SID << 8 | 0x05) +#define PMK8350_ADC5_GEN2_AMUX_THM3 (PMK8350_SID << 8 | 0x06) +#define PMK8350_ADC5_GEN2_AMUX_THM4 (PMK8350_SID << 8 | 0x07) +#define PMK8350_ADC5_GEN2_AMUX_THM5 (PMK8350_SID << 8 | 0x08) + +/* 30k pull-up1 */ +#define PMK8350_ADC5_GEN2_AMUX_THM1_30K_PU (PMK8350_SID << 8 | 0x24) +#define PMK8350_ADC5_GEN2_AMUX_THM2_30K_PU (PMK8350_SID << 8 | 0x25) +#define PMK8350_ADC5_GEN2_AMUX_THM3_30K_PU (PMK8350_SID << 8 | 0x26) +#define PMK8350_ADC5_GEN2_AMUX_THM4_30K_PU (PMK8350_SID << 8 | 0x27) +#define PMK8350_ADC5_GEN2_AMUX_THM5_30K_PU (PMK8350_SID << 8 | 0x28) + +/* 100k pull-up2 */ +#define PMK8350_ADC5_GEN2_AMUX_THM1_100K_PU (PMK8350_SID << 8 | 0x44) +#define PMK8350_ADC5_GEN2_AMUX_THM2_100K_PU (PMK8350_SID << 8 | 0x45) +#define PMK8350_ADC5_GEN2_AMUX_THM3_100K_PU (PMK8350_SID << 8 | 0x46) +#define PMK8350_ADC5_GEN2_AMUX_THM4_100K_PU (PMK8350_SID << 8 | 0x47) +#define PMK8350_ADC5_GEN2_AMUX_THM5_100K_PU (PMK8350_SID << 8 | 0x48) + +/* 400k pull-up3 */ +#define PMK8350_ADC5_GEN2_AMUX_THM1_400K_PU (PMK8350_SID << 8 | 0x64) +#define PMK8350_ADC5_GEN2_AMUX_THM2_400K_PU (PMK8350_SID << 8 | 0x65) +#define PMK8350_ADC5_GEN2_AMUX_THM3_400K_PU (PMK8350_SID << 8 | 0x66) +#define PMK8350_ADC5_GEN2_AMUX_THM4_400K_PU (PMK8350_SID << 8 | 0x67) +#define PMK8350_ADC5_GEN2_AMUX_THM5_400K_PU (PMK8350_SID << 8 | 0x68) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735a.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735a.h new file mode 100644 index 000000000000..0f8ad745845b --- /dev/null +++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735a.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H + +#ifndef PMR735A_SID +#define PMR735A_SID 4 +#endif + +/* ADC channels for PMR735A_ADC for PMIC5 Gen2 */ +#define PMR735A_ADC5_GEN2_REF_GND (PMR735A_SID << 8 | 0x0) +#define PMR735A_ADC5_GEN2_1P25VREF (PMR735A_SID << 8 | 0x01) +#define PMR735A_ADC5_GEN2_VREF_VADC (PMR735A_SID << 8 | 0x02) +#define PMR735A_ADC5_GEN2_DIE_TEMP (PMR735A_SID << 8 | 0x03) + +#define PMR735A_ADC5_GEN2_GPIO1 (PMR735A_SID << 8 | 0x0a) +#define PMR735A_ADC5_GEN2_GPIO2 (PMR735A_SID << 8 | 0x0b) +#define PMR735A_ADC5_GEN2_GPIO3 (PMR735A_SID << 8 | 0x0c) + +/* 100k pull-up2 */ +#define PMR735A_ADC5_GEN2_GPIO1_100K_PU (PMR735A_SID << 8 | 0x4a) +#define PMR735A_ADC5_GEN2_GPIO2_100K_PU (PMR735A_SID << 8 | 0x4b) +#define PMR735A_ADC5_GEN2_GPIO3_100K_PU (PMR735A_SID << 8 | 0x4c) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735b.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735b.h new file mode 100644 index 000000000000..d05d057276e3 --- /dev/null +++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735b.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H + +#ifndef PMR735B_SID +#define PMR735B_SID 5 +#endif + +/* ADC channels for PMR735B_ADC for PMIC5 Gen2 */ +#define PMR735B_ADC5_GEN2_REF_GND (PMR735B_SID << 8 | 0x0) +#define PMR735B_ADC5_GEN2_1P25VREF (PMR735B_SID << 8 | 0x01) +#define PMR735B_ADC5_GEN2_VREF_VADC (PMR735B_SID << 8 | 0x02) +#define PMR735B_ADC5_GEN2_DIE_TEMP (PMR735B_SID << 8 | 0x03) + +#define PMR735B_ADC5_GEN2_GPIO1 (PMR735B_SID << 8 | 0x0a) +#define PMR735B_ADC5_GEN2_GPIO2 (PMR735B_SID << 8 | 0x0b) +#define PMR735B_ADC5_GEN2_GPIO3 (PMR735B_SID << 8 | 0x0c) + +/* 100k pull-up2 */ +#define PMR735B_ADC5_GEN2_GPIO1_100K_PU (PMR735B_SID << 8 | 0x4a) +#define PMR735B_ADC5_GEN2_GPIO2_100K_PU (PMR735B_SID << 8 | 0x4b) +#define PMR735B_ADC5_GEN2_GPIO3_100K_PU (PMR735B_SID << 8 | 0x4c) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-vadc.h b/include/dt-bindings/iio/qcom,spmi-vadc.h index 08adfe25964c..92a064ada796 100644 --- a/include/dt-bindings/iio/qcom,spmi-vadc.h +++ b/include/dt-bindings/iio/qcom,spmi-vadc.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H @@ -297,4 +298,80 @@ #define ADC7_SBUx 0x94 #define ADC7_VBAT_2S_MID 0x96 +/* ADC channels for ADC for PMIC5 Gen2 */ + +#define ADC5_GEN2_REF_GND 0x00 +#define ADC5_GEN2_1P25VREF 0x01 +#define ADC5_GEN2_VREF_VADC 0x02 +#define ADC5_GEN2_DIE_TEMP 0x03 + +#define ADC5_GEN2_AMUX_THM1 0x04 +#define ADC5_GEN2_AMUX_THM2 0x05 +#define ADC5_GEN2_AMUX_THM3 0x06 +#define ADC5_GEN2_AMUX_THM4 0x07 +#define ADC5_GEN2_AMUX_THM5 0x08 +#define ADC5_GEN2_AMUX_THM6 0x09 +#define ADC5_GEN2_GPIO1 0x0a +#define ADC5_GEN2_GPIO2 0x0b +#define ADC5_GEN2_GPIO3 0x0c +#define ADC5_GEN2_GPIO4 0x0d + +#define ADC5_GEN2_CHG_TEMP 0x10 +#define ADC5_GEN2_USB_IN_V_16 0x11 +#define ADC5_GEN2_VDC_16 0x12 +#define ADC5_GEN2_CC1_ID 0x13 +#define ADC5_GEN2_VREF_BAT_THERM 0x15 +#define ADC5_GEN2_IIN_FB 0x17 + +/* 30k pull-up1 */ +#define ADC5_GEN2_AMUX_THM1_30K_PU 0x24 +#define ADC5_GEN2_AMUX_THM2_30K_PU 0x25 +#define ADC5_GEN2_AMUX_THM3_30K_PU 0x26 +#define ADC5_GEN2_AMUX_THM4_30K_PU 0x27 +#define ADC5_GEN2_AMUX_THM5_30K_PU 0x28 +#define ADC5_GEN2_AMUX_THM6_30K_PU 0x29 +#define ADC5_GEN2_GPIO1_30K_PU 0x2a +#define ADC5_GEN2_GPIO2_30K_PU 0x2b +#define ADC5_GEN2_GPIO3_30K_PU 0x2c +#define ADC5_GEN2_GPIO4_30K_PU 0x2d +#define ADC5_GEN2_CC1_ID_30K_PU 0x33 + +/* 100k pull-up2 */ +#define ADC5_GEN2_AMUX_THM1_100K_PU 0x44 +#define ADC5_GEN2_AMUX_THM2_100K_PU 0x45 +#define ADC5_GEN2_AMUX_THM3_100K_PU 0x46 +#define ADC5_GEN2_AMUX_THM4_100K_PU 0x47 +#define ADC5_GEN2_AMUX_THM5_100K_PU 0x48 +#define ADC5_GEN2_AMUX_THM6_100K_PU 0x49 +#define ADC5_GEN2_GPIO1_100K_PU 0x4a +#define ADC5_GEN2_GPIO2_100K_PU 0x4b +#define ADC5_GEN2_GPIO3_100K_PU 0x4c +#define ADC5_GEN2_GPIO4_100K_PU 0x4d +#define ADC5_GEN2_CC1_ID_100K_PU 0x53 + +/* 400k pull-up3 */ +#define ADC5_GEN2_AMUX_THM1_400K_PU 0x64 +#define ADC5_GEN2_AMUX_THM2_400K_PU 0x65 +#define ADC5_GEN2_AMUX_THM3_400K_PU 0x66 +#define ADC5_GEN2_AMUX_THM4_400K_PU 0x67 +#define ADC5_GEN2_AMUX_THM5_400K_PU 0x68 +#define ADC5_GEN2_AMUX_THM6_400K_PU 0x69 +#define ADC5_GEN2_GPIO1_400K_PU 0x6a +#define ADC5_GEN2_GPIO2_400K_PU 0x6b +#define ADC5_GEN2_GPIO3_400K_PU 0x6c +#define ADC5_GEN2_GPIO4_400K_PU 0x6d +#define ADC5_GEN2_CC1_ID_400K_PU 0x73 + +/* 1/3 Divider */ +#define ADC5_GEN2_GPIO1_DIV3 0x8a +#define ADC5_GEN2_GPIO2_DIV3 0x8b +#define ADC5_GEN2_GPIO3_DIV3 0x8c +#define ADC5_GEN2_GPIO4_DIV3 0x8d + +#define ADC5_GEN2_VPH_PWR 0x8e +#define ADC5_GEN2_VBAT_SNS 0x8f + +#define ADC5_GEN2_SBUx 0x94 +#define ADC5_GEN2_VBAT_2S_MID 0x96 + #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */ From patchwork Sat Jul 8 07:28:26 2023 Content-Type: text/plain; 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Sat, 8 Jul 2023 07:29:18 GMT Received: from hu-jprakash-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Sat, 8 Jul 2023 00:29:11 -0700 From: Jishnu Prakash To: , , , , , , , , , , , , , , "Bjorn Andersson" , Konrad Dybcio , Jonathan Cameron , Lars-Peter Clausen , Jishnu Prakash , , CC: Subject: [PATCH 02/11] iio: adc: Update driver files for ADC7 rename for QCOM PMICs Date: Sat, 8 Jul 2023 12:58:26 +0530 Message-ID: <20230708072835.3035398-3-quic_jprakash@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230708072835.3035398-1-quic_jprakash@quicinc.com> References: <20230708072835.3035398-1-quic_jprakash@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Hlx1yHEIxW2vmW01Tp4u6T18VqAOLm8O X-Proofpoint-GUID: Hlx1yHEIxW2vmW01Tp4u6T18VqAOLm8O X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-08_04,2023-07-06_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 priorityscore=1501 mlxscore=0 malwarescore=0 bulkscore=0 clxscore=1015 suspectscore=0 impostorscore=0 adultscore=0 phishscore=0 lowpriorityscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307080065 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The correct name for this version of ADCs should be ADC5 Gen2 instead of ADC7. Update the driver files for this name change. Signed-off-by: Jishnu Prakash --- drivers/iio/adc/qcom-spmi-adc5.c | 93 +++++++++++++----------- drivers/iio/adc/qcom-vadc-common.c | 36 ++++----- include/linux/iio/adc/qcom-vadc-common.h | 12 +-- 3 files changed, 73 insertions(+), 68 deletions(-) diff --git a/drivers/iio/adc/qcom-spmi-adc5.c b/drivers/iio/adc/qcom-spmi-adc5.c index 0a4fd3a46113..3ac1ee500a67 100644 --- a/drivers/iio/adc/qcom-spmi-adc5.c +++ b/drivers/iio/adc/qcom-spmi-adc5.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -87,7 +88,7 @@ /* For PMIC7 */ #define ADC_APP_SID 0x40 #define ADC_APP_SID_MASK GENMASK(3, 0) -#define ADC7_CONV_TIMEOUT msecs_to_jiffies(10) +#define ADC5_GEN2_CONV_TIMEOUT msecs_to_jiffies(10) enum adc5_cal_method { ADC5_NO_CAL = 0, @@ -270,7 +271,7 @@ static int adc5_configure(struct adc5_chip *adc, return adc5_write(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf)); } -static int adc7_configure(struct adc5_chip *adc, +static int adc5_gen2_configure(struct adc5_chip *adc, struct adc5_channel_prop *prop) { int ret; @@ -352,7 +353,7 @@ static int adc5_do_conversion(struct adc5_chip *adc, return ret; } -static int adc7_do_conversion(struct adc5_chip *adc, +static int adc5_gen2_do_conversion(struct adc5_chip *adc, struct adc5_channel_prop *prop, struct iio_chan_spec const *chan, u16 *data_volt, u16 *data_cur) @@ -362,14 +363,14 @@ static int adc7_do_conversion(struct adc5_chip *adc, mutex_lock(&adc->lock); - ret = adc7_configure(adc, prop); + ret = adc5_gen2_configure(adc, prop); if (ret) { dev_err(adc->dev, "ADC configure failed with %d\n", ret); goto unlock; } /* No support for polling mode at present */ - wait_for_completion_timeout(&adc->complete, ADC7_CONV_TIMEOUT); + wait_for_completion_timeout(&adc->complete, ADC5_GEN2_CONV_TIMEOUT); ret = adc5_read(adc, ADC5_USR_STATUS1, &status, 1); if (ret) @@ -416,7 +417,7 @@ static int adc5_fwnode_xlate(struct iio_dev *indio_dev, return -EINVAL; } -static int adc7_fwnode_xlate(struct iio_dev *indio_dev, +static int adc5_gen2_fwnode_xlate(struct iio_dev *indio_dev, const struct fwnode_reference_args *iiospec) { struct adc5_chip *adc = iio_priv(indio_dev); @@ -471,12 +472,12 @@ static int adc5_read_raw(struct iio_dev *indio_dev, mask, adc5_do_conversion); } -static int adc7_read_raw(struct iio_dev *indio_dev, +static int adc5_gen2_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) { return adc_read_raw_common(indio_dev, chan, val, val2, - mask, adc7_do_conversion); + mask, adc5_gen2_do_conversion); } static const struct iio_info adc5_info = { @@ -484,9 +485,9 @@ static const struct iio_info adc5_info = { .fwnode_xlate = adc5_fwnode_xlate, }; -static const struct iio_info adc7_info = { - .read_raw = adc7_read_raw, - .fwnode_xlate = adc7_fwnode_xlate, +static const struct iio_info adc5_gen2_info = { + .read_raw = adc5_gen2_read_raw, + .fwnode_xlate = adc5_gen2_fwnode_xlate, }; struct adc5_channels { @@ -561,37 +562,37 @@ static const struct adc5_channels adc5_chans_pmic[ADC5_MAX_CHANNEL] = { SCALE_HW_CALIB_THERM_100K_PULLUP) }; -static const struct adc5_channels adc7_chans_pmic[ADC5_MAX_CHANNEL] = { - [ADC7_REF_GND] = ADC5_CHAN_VOLT("ref_gnd", 0, +static const struct adc5_channels adc5_gen2_chans_pmic[ADC5_MAX_CHANNEL] = { + [ADC5_GEN2_REF_GND] = ADC5_CHAN_VOLT("ref_gnd", 0, SCALE_HW_CALIB_DEFAULT) - [ADC7_1P25VREF] = ADC5_CHAN_VOLT("vref_1p25", 0, + [ADC5_GEN2_1P25VREF] = ADC5_CHAN_VOLT("vref_1p25", 0, SCALE_HW_CALIB_DEFAULT) - [ADC7_VPH_PWR] = ADC5_CHAN_VOLT("vph_pwr", 1, + [ADC5_GEN2_VPH_PWR] = ADC5_CHAN_VOLT("vph_pwr", 1, SCALE_HW_CALIB_DEFAULT) - [ADC7_VBAT_SNS] = ADC5_CHAN_VOLT("vbat_sns", 3, + [ADC5_GEN2_VBAT_SNS] = ADC5_CHAN_VOLT("vbat_sns", 3, SCALE_HW_CALIB_DEFAULT) - [ADC7_DIE_TEMP] = ADC5_CHAN_TEMP("die_temp", 0, - SCALE_HW_CALIB_PMIC_THERM_PM7) - [ADC7_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_pu2", 0, - SCALE_HW_CALIB_THERM_100K_PU_PM7) - [ADC7_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_pu2", 0, - SCALE_HW_CALIB_THERM_100K_PU_PM7) - [ADC7_AMUX_THM3_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_pu2", 0, - SCALE_HW_CALIB_THERM_100K_PU_PM7) - [ADC7_AMUX_THM4_100K_PU] = ADC5_CHAN_TEMP("amux_thm4_pu2", 0, - SCALE_HW_CALIB_THERM_100K_PU_PM7) - [ADC7_AMUX_THM5_100K_PU] = ADC5_CHAN_TEMP("amux_thm5_pu2", 0, - SCALE_HW_CALIB_THERM_100K_PU_PM7) - [ADC7_AMUX_THM6_100K_PU] = ADC5_CHAN_TEMP("amux_thm6_pu2", 0, - SCALE_HW_CALIB_THERM_100K_PU_PM7) - [ADC7_GPIO1_100K_PU] = ADC5_CHAN_TEMP("gpio1_pu2", 0, - SCALE_HW_CALIB_THERM_100K_PU_PM7) - [ADC7_GPIO2_100K_PU] = ADC5_CHAN_TEMP("gpio2_pu2", 0, - SCALE_HW_CALIB_THERM_100K_PU_PM7) - [ADC7_GPIO3_100K_PU] = ADC5_CHAN_TEMP("gpio3_pu2", 0, - SCALE_HW_CALIB_THERM_100K_PU_PM7) - [ADC7_GPIO4_100K_PU] = ADC5_CHAN_TEMP("gpio4_pu2", 0, - SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC5_GEN2_DIE_TEMP] = ADC5_CHAN_TEMP("die_temp", 0, + SCALE_HW_CALIB_PMIC_THERM_PM5_GEN2) + [ADC5_GEN2_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_pu2", 0, + SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2) + [ADC5_GEN2_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_pu2", 0, + SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2) + [ADC5_GEN2_AMUX_THM3_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_pu2", 0, + SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2) + [ADC5_GEN2_AMUX_THM4_100K_PU] = ADC5_CHAN_TEMP("amux_thm4_pu2", 0, + SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2) + [ADC5_GEN2_AMUX_THM5_100K_PU] = ADC5_CHAN_TEMP("amux_thm5_pu2", 0, + SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2) + [ADC5_GEN2_AMUX_THM6_100K_PU] = ADC5_CHAN_TEMP("amux_thm6_pu2", 0, + SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2) + [ADC5_GEN2_GPIO1_100K_PU] = ADC5_CHAN_TEMP("gpio1_pu2", 0, + SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2) + [ADC5_GEN2_GPIO2_100K_PU] = ADC5_CHAN_TEMP("gpio2_pu2", 0, + SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2) + [ADC5_GEN2_GPIO3_100K_PU] = ADC5_CHAN_TEMP("gpio3_pu2", 0, + SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2) + [ADC5_GEN2_GPIO4_100K_PU] = ADC5_CHAN_TEMP("gpio4_pu2", 0, + SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2) }; static const struct adc5_channels adc5_chans_rev2[ADC5_MAX_CHANNEL] = { @@ -652,7 +653,7 @@ static int adc5_get_fw_channel_data(struct adc5_chip *adc, /* virtual channel number = sid << 8 | channel number */ - if (adc->data->info == &adc7_info) { + if (adc->data->info == &adc5_gen2_info) { sid = chan >> ADC_CHANNEL_OFFSET; chan = chan & ADC_CHANNEL_MASK; } @@ -715,7 +716,7 @@ static int adc5_get_fw_channel_data(struct adc5_chip *adc, /* Digital controller >= 5.3 have hw_settle_2 option */ if ((dig_version[0] >= ADC5_HW_SETTLE_DIFF_MINOR && dig_version[1] >= ADC5_HW_SETTLE_DIFF_MAJOR) || - adc->data->info == &adc7_info) + adc->data->info == &adc5_gen2_info) ret = qcom_adc5_hw_settle_time_from_dt(value, data->hw_settle_2); else ret = qcom_adc5_hw_settle_time_from_dt(value, data->hw_settle_1); @@ -774,10 +775,10 @@ static const struct adc5_data adc5_data_pmic = { 1, 2, 4, 8, 16, 32, 64, 128}, }; -static const struct adc5_data adc7_data_pmic = { +static const struct adc5_data adc5_gen2_data_pmic = { .full_scale_code_volt = 0x70e4, - .adc_chans = adc7_chans_pmic, - .info = &adc7_info, + .adc_chans = adc5_gen2_chans_pmic, + .info = &adc5_gen2_info, .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX]) {85, 340, 1360}, .hw_settle_2 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX]) @@ -808,7 +809,11 @@ static const struct of_device_id adc5_match_table[] = { }, { .compatible = "qcom,spmi-adc7", - .data = &adc7_data_pmic, + .data = &adc5_gen2_data_pmic, + }, + { + .compatible = "qcom,spmi-adc5-gen2", + .data = &adc5_gen2_data_pmic, }, { .compatible = "qcom,spmi-adc-rev2", diff --git a/drivers/iio/adc/qcom-vadc-common.c b/drivers/iio/adc/qcom-vadc-common.c index d5209f32adb3..1f4cd3be68fa 100644 --- a/drivers/iio/adc/qcom-vadc-common.c +++ b/drivers/iio/adc/qcom-vadc-common.c @@ -100,7 +100,7 @@ static const struct vadc_map_pt adcmap_100k_104ef_104fb_1875_vref[] = { { 46, 125000 }, }; -static const struct vadc_map_pt adcmap7_die_temp[] = { +static const struct vadc_map_pt adcmap5_gen2_die_temp[] = { { 857300, 160000 }, { 820100, 140000 }, { 782500, 120000 }, @@ -118,7 +118,7 @@ static const struct vadc_map_pt adcmap7_die_temp[] = { /* * Resistance to temperature table for 100k pull up for NTCG104EF104. */ -static const struct vadc_map_pt adcmap7_100k[] = { +static const struct vadc_map_pt adcmap5_gen2_100k[] = { { 4250657, -40960 }, { 3962085, -39936 }, { 3694875, -38912 }, @@ -309,7 +309,7 @@ static int qcom_vadc_scale_hw_calib_therm( const struct u32_fract *prescale, const struct adc5_data *data, u16 adc_code, int *result_mdec); -static int qcom_vadc7_scale_hw_calib_therm( +static int qcom_vadc5_gen2_scale_hw_calib_therm( const struct u32_fract *prescale, const struct adc5_data *data, u16 adc_code, int *result_mdec); @@ -325,7 +325,7 @@ static int qcom_vadc_scale_hw_calib_die_temp( const struct u32_fract *prescale, const struct adc5_data *data, u16 adc_code, int *result_mdec); -static int qcom_vadc7_scale_hw_calib_die_temp( +static int qcom_vadc5_gen2_scale_hw_calib_die_temp( const struct u32_fract *prescale, const struct adc5_data *data, u16 adc_code, int *result_mdec); @@ -334,11 +334,11 @@ static struct qcom_adc5_scale_type scale_adc5_fn[] = { [SCALE_HW_CALIB_DEFAULT] = {qcom_vadc_scale_hw_calib_volt}, [SCALE_HW_CALIB_THERM_100K_PULLUP] = {qcom_vadc_scale_hw_calib_therm}, [SCALE_HW_CALIB_XOTHERM] = {qcom_vadc_scale_hw_calib_therm}, - [SCALE_HW_CALIB_THERM_100K_PU_PM7] = { - qcom_vadc7_scale_hw_calib_therm}, + [SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2] = { + qcom_vadc5_gen2_scale_hw_calib_therm}, [SCALE_HW_CALIB_PMIC_THERM] = {qcom_vadc_scale_hw_calib_die_temp}, - [SCALE_HW_CALIB_PMIC_THERM_PM7] = { - qcom_vadc7_scale_hw_calib_die_temp}, + [SCALE_HW_CALIB_PMIC_THERM_PM5_GEN2] = { + qcom_vadc5_gen2_scale_hw_calib_die_temp}, [SCALE_HW_CALIB_PM5_CHG_TEMP] = {qcom_vadc_scale_hw_chg5_temp}, [SCALE_HW_CALIB_PM5_SMB_TEMP] = {qcom_vadc_scale_hw_smb_temp}, }; @@ -530,7 +530,7 @@ static int qcom_vadc_scale_code_voltage_factor(u16 adc_code, return (int) voltage; } -static int qcom_vadc7_scale_hw_calib_therm( +static int qcom_vadc5_gen2_scale_hw_calib_therm( const struct u32_fract *prescale, const struct adc5_data *data, u16 adc_code, int *result_mdec) @@ -538,15 +538,15 @@ static int qcom_vadc7_scale_hw_calib_therm( s64 resistance = adc_code; int ret, result; - if (adc_code >= RATIO_MAX_ADC7) + if (adc_code >= RATIO_MAX_ADC5_GEN2) return -EINVAL; /* (ADC code * R_PULLUP (100Kohm)) / (full_scale_code - ADC code)*/ resistance *= R_PU_100K; - resistance = div64_s64(resistance, RATIO_MAX_ADC7 - adc_code); + resistance = div64_s64(resistance, RATIO_MAX_ADC5_GEN2 - adc_code); - ret = qcom_vadc_map_voltage_temp(adcmap7_100k, - ARRAY_SIZE(adcmap7_100k), + ret = qcom_vadc_map_voltage_temp(adcmap5_gen2_100k, + ARRAY_SIZE(adcmap5_gen2_100k), resistance, &result); if (ret) return ret; @@ -595,7 +595,7 @@ static int qcom_vadc_scale_hw_calib_die_temp( return 0; } -static int qcom_vadc7_scale_hw_calib_die_temp( +static int qcom_vadc5_gen2_scale_hw_calib_die_temp( const struct u32_fract *prescale, const struct adc5_data *data, u16 adc_code, int *result_mdec) @@ -606,7 +606,7 @@ static int qcom_vadc7_scale_hw_calib_die_temp( voltage = qcom_vadc_scale_code_voltage_factor(adc_code, prescale, data, 1); - return qcom_vadc_map_voltage_temp(adcmap7_die_temp, ARRAY_SIZE(adcmap7_die_temp), + return qcom_vadc_map_voltage_temp(adcmap5_gen2_die_temp, ARRAY_SIZE(adcmap5_gen2_die_temp), voltage, result_mdec); } @@ -681,10 +681,10 @@ u16 qcom_adc_tm5_gen2_temp_res_scale(int temp) { int64_t resistance; - resistance = qcom_vadc_map_temp_voltage(adcmap7_100k, - ARRAY_SIZE(adcmap7_100k), temp); + resistance = qcom_vadc_map_temp_voltage(adcmap5_gen2_100k, + ARRAY_SIZE(adcmap5_gen2_100k), temp); - return div64_s64(resistance * RATIO_MAX_ADC7, resistance + R_PU_100K); + return div64_s64(resistance * RATIO_MAX_ADC5_GEN2, resistance + R_PU_100K); } EXPORT_SYMBOL(qcom_adc_tm5_gen2_temp_res_scale); diff --git a/include/linux/iio/adc/qcom-vadc-common.h b/include/linux/iio/adc/qcom-vadc-common.h index aa21b032e861..a926e369a3ca 100644 --- a/include/linux/iio/adc/qcom-vadc-common.h +++ b/include/linux/iio/adc/qcom-vadc-common.h @@ -53,7 +53,7 @@ #define ADC5_USR_DATA_CHECK 0x8000 #define R_PU_100K 100000 -#define RATIO_MAX_ADC7 BIT(14) +#define RATIO_MAX_ADC5_GEN2 BIT(14) /* * VADC_CALIB_ABSOLUTE: uses the 625mV and 1.25V as reference channels. @@ -95,12 +95,12 @@ struct vadc_linear_graph { * lookup table. The hardware applies offset/slope to adc code. * SCALE_HW_CALIB_XOTHERM: Returns XO thermistor voltage in millidegC using * 100k pullup. The hardware applies offset/slope to adc code. - * SCALE_HW_CALIB_THERM_100K_PU_PM7: Returns temperature in millidegC using - * lookup table for PMIC7. The hardware applies offset/slope to adc code. + * SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2: Returns temperature in millidegC using + * lookup table for PMIC5 Gen2. The hardware applies offset/slope to adc code. * SCALE_HW_CALIB_PMIC_THERM: Returns result in milli degree's Centigrade. * The hardware applies offset/slope to adc code. * SCALE_HW_CALIB_PMIC_THERM: Returns result in milli degree's Centigrade. - * The hardware applies offset/slope to adc code. This is for PMIC7. + * The hardware applies offset/slope to adc code. This is for PMIC5 Gen2. * SCALE_HW_CALIB_PM5_CHG_TEMP: Returns result in millidegrees for PMIC5 * charger temperature. * SCALE_HW_CALIB_PM5_SMB_TEMP: Returns result in millidegrees for PMIC5 @@ -115,9 +115,9 @@ enum vadc_scale_fn_type { SCALE_HW_CALIB_DEFAULT, SCALE_HW_CALIB_THERM_100K_PULLUP, SCALE_HW_CALIB_XOTHERM, - SCALE_HW_CALIB_THERM_100K_PU_PM7, + SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2, SCALE_HW_CALIB_PMIC_THERM, - SCALE_HW_CALIB_PMIC_THERM_PM7, + SCALE_HW_CALIB_PMIC_THERM_PM5_GEN2, SCALE_HW_CALIB_PM5_CHG_TEMP, SCALE_HW_CALIB_PM5_SMB_TEMP, SCALE_HW_CALIB_INVALID, From patchwork Sat Jul 8 07:28:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jishnu Prakash X-Patchwork-Id: 700379 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0FA20C001E0 for ; Sat, 8 Jul 2023 07:29:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231279AbjGHH3o (ORCPT ); Sat, 8 Jul 2023 03:29:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58338 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229797AbjGHH3n (ORCPT ); Sat, 8 Jul 2023 03:29:43 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 98F4D2125; Sat, 8 Jul 2023 00:29:38 -0700 (PDT) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36872No5032041; Sat, 8 Jul 2023 07:29:26 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=VmmoJ9c6BEdevnXDrNmLULmLQ+ujIReym3TKv47zGDk=; b=mf6f0pgx3B01wZgfC7oAbpTWYWriU4rovvEQLWs8l13Ty/qJdgZfTdCS8F0D36s7juqc yVJFninYIjBQXIgxWZ+OcHeIvPiumGDUcMz5fjeLZPGdlG2bWLo/si18+DW8m445zR0c lachncEEJylk0BOzBK5VR/0dbtPG2g4O18ftYgjpgYn4oKG3h0j2u1QBoeAiiL8MfB1g E6/izkPVBgadkX+r7gudAr/DYrM9olcxe626OOC/VWVRjTbKPFwOwuonhjsAUVw11lcW at2ZdEVVAHMLi6XfDjTPRu0DH9tLSXrmQhVA3ZZKTnt5TIWlJdc/yWMBqeNOPLmDPgf1 bQ== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rq01dg6f8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 08 Jul 2023 07:29:26 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3687TPCg011655 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 8 Jul 2023 07:29:25 GMT Received: from hu-jprakash-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Sat, 8 Jul 2023 00:29:18 -0700 From: Jishnu Prakash To: , , , , , , , , , , , , , , "Bjorn Andersson" , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , CC: , , "Jishnu Prakash" Subject: [PATCH 03/11] ARM: dts: qcom: Update devicetree for ADC7 rename for QCOM PMICs Date: Sat, 8 Jul 2023 12:58:27 +0530 Message-ID: <20230708072835.3035398-4-quic_jprakash@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230708072835.3035398-1-quic_jprakash@quicinc.com> References: <20230708072835.3035398-1-quic_jprakash@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: GSnIKhcTzNz-171yaDpGkFD0-Sg5mHeQ X-Proofpoint-GUID: GSnIKhcTzNz-171yaDpGkFD0-Sg5mHeQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-08_04,2023-07-06_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxscore=0 priorityscore=1501 clxscore=1011 adultscore=0 mlxlogscore=971 malwarescore=0 lowpriorityscore=0 spamscore=0 phishscore=0 suspectscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307080065 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The name "ADC7" needs to be replaced with the name "ADC5_GEN2" everywhere to match the convention used for these ADC peripherals on Qualcomm Technologies, Inc. PMICs. Update devicetree files for the corresponding name change done in bindings and driver. Signed-off-by: Jishnu Prakash --- arch/arm64/boot/dts/qcom/pmk8350.dtsi | 4 +- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 4 +- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 4 +- arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 8 ++-- .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 48 +++++++++---------- arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi | 2 +- .../boot/dts/qcom/sm7225-fairphone-fp4.dts | 4 +- 7 files changed, 37 insertions(+), 37 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pmk8350.dtsi b/arch/arm64/boot/dts/qcom/pmk8350.dtsi index bc6297e7253e..149d2bb43d2d 100644 --- a/arch/arm64/boot/dts/qcom/pmk8350.dtsi +++ b/arch/arm64/boot/dts/qcom/pmk8350.dtsi @@ -50,7 +50,7 @@ pon_resin: resin { }; pmk8350_vadc: adc@3100 { - compatible = "qcom,spmi-adc7"; + compatible = "qcom,spmi-adc5-gen2"; reg = <0x3100>; #address-cells = <1>; #size-cells = <0>; @@ -59,7 +59,7 @@ pmk8350_vadc: adc@3100 { }; pmk8350_adc_tm: adc-tm@3400 { - compatible = "qcom,adc-tm7"; + compatible = "qcom,spmi-adc-tm5-gen2"; reg = <0x3400>; interrupts = ; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index 15222e92e3f5..bc65e6c6232f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include +#include #include "sc7280-idp.dtsi" #include "pmr735a.dtsi" @@ -74,7 +74,7 @@ &nvme_3v3_regulator { &pmk8350_vadc { pmr735a-die-temp@403 { - reg = ; + reg = ; label = "pmr735a_die_temp"; qcom,pre-scaling = <1 1>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 21027042cf13..da413694e230 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -5,7 +5,7 @@ * Copyright (c) 2021, The Linux Foundation. All rights reserved. */ -#include +#include #include #include "sc7280.dtsi" #include "pm7325.dtsi" @@ -433,7 +433,7 @@ &pcie1_phy { &pmk8350_vadc { pmk8350-die-temp@3 { - reg = ; + reg = ; label = "pmk8350_die_temp"; qcom,pre-scaling = <1 1>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi index 9137db066d9e..ed26bff7432d 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -11,8 +11,8 @@ * Copyright 2022 Google LLC. */ -#include -#include +#include +#include #include #include @@ -384,13 +384,13 @@ &pm8350c_pwm { &pmk8350_vadc { pmk8350-die-temp@3 { - reg = ; + reg = ; label = "pmk8350_die_temp"; qcom,pre-scaling = <1 1>; }; pmr735a-die-temp@403 { - reg = ; + reg = ; label = "pmr735a_die_temp"; qcom,pre-scaling = <1 1>; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 7cc3028440b6..cfd5dbbacdcb 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -7,9 +7,9 @@ /dts-v1/; #include -#include -#include -#include +#include +#include +#include #include #include #include @@ -747,7 +747,7 @@ &pmk8280_adc_tm { sys-therm@0 { reg = <0>; - io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM1_100K_PU(1)>; + io-channels = <&pmk8280_vadc PM8350_ADC5_GEN2_AMUX_THM1_100K_PU(1)>; qcom,hw-settle-time-us = <200>; qcom,avg-samples = <2>; qcom,ratiometric; @@ -755,7 +755,7 @@ sys-therm@0 { sys-therm@1 { reg = <1>; - io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM2_100K_PU(1)>; + io-channels = <&pmk8280_vadc PM8350_ADC5_GEN2_AMUX_THM2_100K_PU(1)>; qcom,hw-settle-time-us = <200>; qcom,avg-samples = <2>; qcom,ratiometric; @@ -763,7 +763,7 @@ sys-therm@1 { sys-therm@2 { reg = <2>; - io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM3_100K_PU(1)>; + io-channels = <&pmk8280_vadc PM8350_ADC5_GEN2_AMUX_THM3_100K_PU(1)>; qcom,hw-settle-time-us = <200>; qcom,avg-samples = <2>; qcom,ratiometric; @@ -771,7 +771,7 @@ sys-therm@2 { sys-therm@3 { reg = <3>; - io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM4_100K_PU(1)>; + io-channels = <&pmk8280_vadc PM8350_ADC5_GEN2_AMUX_THM4_100K_PU(1)>; qcom,hw-settle-time-us = <200>; qcom,avg-samples = <2>; qcom,ratiometric; @@ -779,7 +779,7 @@ sys-therm@3 { sys-therm@4 { reg = <4>; - io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM1_100K_PU(3)>; + io-channels = <&pmk8280_vadc PM8350_ADC5_GEN2_AMUX_THM1_100K_PU(3)>; qcom,hw-settle-time-us = <200>; qcom,avg-samples = <2>; qcom,ratiometric; @@ -787,7 +787,7 @@ sys-therm@4 { sys-therm@5 { reg = <5>; - io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM2_100K_PU(3)>; + io-channels = <&pmk8280_vadc PM8350_ADC5_GEN2_AMUX_THM2_100K_PU(3)>; qcom,hw-settle-time-us = <200>; qcom,avg-samples = <2>; qcom,ratiometric; @@ -795,7 +795,7 @@ sys-therm@5 { sys-therm@6 { reg = <6>; - io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM3_100K_PU(3)>; + io-channels = <&pmk8280_vadc PM8350_ADC5_GEN2_AMUX_THM3_100K_PU(3)>; qcom,hw-settle-time-us = <200>; qcom,avg-samples = <2>; qcom,ratiometric; @@ -803,7 +803,7 @@ sys-therm@6 { sys-therm@7 { reg = <7>; - io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM4_100K_PU(3)>; + io-channels = <&pmk8280_vadc PM8350_ADC5_GEN2_AMUX_THM4_100K_PU(3)>; qcom,hw-settle-time-us = <200>; qcom,avg-samples = <2>; qcom,ratiometric; @@ -837,88 +837,88 @@ &pmk8280_vadc { status = "okay"; pmic-die-temp@3 { - reg = ; + reg = ; qcom,pre-scaling = <1 1>; label = "pmk8350_die_temp"; }; xo-therm@44 { - reg = ; + reg = ; qcom,hw-settle-time = <200>; qcom,ratiometric; label = "pmk8350_xo_therm"; }; pmic-die-temp@103 { - reg = ; + reg = ; qcom,pre-scaling = <1 1>; label = "pmc8280_1_die_temp"; }; sys-therm@144 { - reg = ; + reg = ; qcom,hw-settle-time = <200>; qcom,ratiometric; label = "sys_therm1"; }; sys-therm@145 { - reg = ; + reg = ; qcom,hw-settle-time = <200>; qcom,ratiometric; label = "sys_therm2"; }; sys-therm@146 { - reg = ; + reg = ; qcom,hw-settle-time = <200>; qcom,ratiometric; label = "sys_therm3"; }; sys-therm@147 { - reg = ; + reg = ; qcom,hw-settle-time = <200>; qcom,ratiometric; label = "sys_therm4"; }; pmic-die-temp@303 { - reg = ; + reg = ; qcom,pre-scaling = <1 1>; label = "pmc8280_2_die_temp"; }; sys-therm@344 { - reg = ; + reg = ; qcom,hw-settle-time = <200>; qcom,ratiometric; label = "sys_therm5"; }; sys-therm@345 { - reg = ; + reg = ; qcom,hw-settle-time = <200>; qcom,ratiometric; label = "sys_therm6"; }; sys-therm@346 { - reg = ; + reg = ; qcom,hw-settle-time = <200>; qcom,ratiometric; label = "sys_therm7"; }; sys-therm@347 { - reg = ; + reg = ; qcom,hw-settle-time = <200>; qcom,ratiometric; label = "sys_therm8"; }; pmic-die-temp@403 { - reg = ; + reg = ; qcom,pre-scaling = <1 1>; label = "pmr735a_die_temp"; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi index a0ba535bb6c9..ae9491adaa6a 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi @@ -78,7 +78,7 @@ pmk8280_pon_resin: resin { }; pmk8280_vadc: adc@3100 { - compatible = "qcom,spmi-adc7"; + compatible = "qcom,spmi-adc5-gen2"; reg = <0x3100>; interrupts-extended = <&spmi_bus 0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index e3dc49951523..52119cc1250e 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -9,7 +9,7 @@ #define PMK8350_SID 6 #include -#include +#include #include #include #include @@ -517,7 +517,7 @@ &pmk8350_rtc { &pmk8350_vadc { adc-chan@644 { - reg = ; + reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; From patchwork Sat Jul 8 07:28:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jishnu Prakash X-Patchwork-Id: 700964 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BEB8FEB64DD for ; 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Sat, 8 Jul 2023 00:29:29 -0700 From: Jishnu Prakash To: , , , , , , , , , , , , , , Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , "Rafael J. Wysocki" , "Daniel Lezcano" , Amit Kucheria , "Zhang Rui" , Jishnu Prakash , "Luca Weiss" , , , CC: Subject: [PATCH 04/11] iio: adc: Update bindings to remove support for ADC7 name used on QCOM PMICs Date: Sat, 8 Jul 2023 12:58:28 +0530 Message-ID: <20230708072835.3035398-5-quic_jprakash@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230708072835.3035398-1-quic_jprakash@quicinc.com> References: <20230708072835.3035398-1-quic_jprakash@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: VfrJhO8TqiQaRXM-dh2shEAVvPJFUu2Y X-Proofpoint-GUID: VfrJhO8TqiQaRXM-dh2shEAVvPJFUu2Y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-08_04,2023-07-06_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxscore=0 bulkscore=0 impostorscore=0 adultscore=0 mlxlogscore=999 spamscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307080065 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Now that usage of "ADC7" name has been replaced with usage of "ADC5 Gen2" name everywhere, remove all support for "ADC7" name. Signed-off-by: Jishnu Prakash --- .../bindings/iio/adc/qcom,spmi-vadc.yaml | 5 +- .../bindings/thermal/qcom-spmi-adc-tm5.yaml | 1 - .../dt-bindings/iio/qcom,spmi-adc7-pm8350.h | 63 ------------- .../dt-bindings/iio/qcom,spmi-adc7-pm8350b.h | 88 ------------------- .../dt-bindings/iio/qcom,spmi-adc7-pmk8350.h | 46 ---------- .../dt-bindings/iio/qcom,spmi-adc7-pmr735a.h | 28 ------ .../dt-bindings/iio/qcom,spmi-adc7-pmr735b.h | 28 ------ include/dt-bindings/iio/qcom,spmi-vadc.h | 76 ---------------- 8 files changed, 1 insertion(+), 334 deletions(-) delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml index f886977de165..eb7d16e385ad 100644 --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml @@ -26,7 +26,6 @@ properties: - qcom,spmi-vadc - qcom,spmi-adc5 - qcom,spmi-adc-rev2 - - qcom,spmi-adc7 - qcom,spmi-adc5-gen2 reg: @@ -214,9 +213,7 @@ allOf: properties: compatible: contains: - enum : - - qcom,spmi-adc7 - - qcom,spmi-adc5-gen2 + const: qcom,spmi-adc5-gen2 then: patternProperties: diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml index 01d57f13d254..019f18a2b9e7 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml @@ -13,7 +13,6 @@ properties: enum: - qcom,spmi-adc-tm5 - qcom,spmi-adc-tm5-gen2 - - qcom,adc-tm7 # Incomplete / subject to change reg: maxItems: 1 diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h b/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h deleted file mode 100644 index 09fd169ad18e..000000000000 --- a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H -#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H - -/* ADC channels for PM8350_ADC for PMIC7 */ -#define PM8350_ADC7_REF_GND(sid) ((sid) << 8 | 0x0) -#define PM8350_ADC7_1P25VREF(sid) ((sid) << 8 | 0x01) -#define PM8350_ADC7_VREF_VADC(sid) ((sid) << 8 | 0x02) -#define PM8350_ADC7_DIE_TEMP(sid) ((sid) << 8 | 0x03) - -#define PM8350_ADC7_AMUX_THM1(sid) ((sid) << 8 | 0x04) -#define PM8350_ADC7_AMUX_THM2(sid) ((sid) << 8 | 0x05) -#define PM8350_ADC7_AMUX_THM3(sid) ((sid) << 8 | 0x06) -#define PM8350_ADC7_AMUX_THM4(sid) ((sid) << 8 | 0x07) -#define PM8350_ADC7_AMUX_THM5(sid) ((sid) << 8 | 0x08) -#define PM8350_ADC7_GPIO1(sid) ((sid) << 8 | 0x0a) -#define PM8350_ADC7_GPIO2(sid) ((sid) << 8 | 0x0b) -#define PM8350_ADC7_GPIO3(sid) ((sid) << 8 | 0x0c) -#define PM8350_ADC7_GPIO4(sid) ((sid) << 8 | 0x0d) - -/* 30k pull-up1 */ -#define PM8350_ADC7_AMUX_THM1_30K_PU(sid) ((sid) << 8 | 0x24) -#define PM8350_ADC7_AMUX_THM2_30K_PU(sid) ((sid) << 8 | 0x25) -#define PM8350_ADC7_AMUX_THM3_30K_PU(sid) ((sid) << 8 | 0x26) -#define PM8350_ADC7_AMUX_THM4_30K_PU(sid) ((sid) << 8 | 0x27) -#define PM8350_ADC7_AMUX_THM5_30K_PU(sid) ((sid) << 8 | 0x28) -#define PM8350_ADC7_GPIO1_30K_PU(sid) ((sid) << 8 | 0x2a) -#define PM8350_ADC7_GPIO2_30K_PU(sid) ((sid) << 8 | 0x2b) -#define PM8350_ADC7_GPIO3_30K_PU(sid) ((sid) << 8 | 0x2c) -#define PM8350_ADC7_GPIO4_30K_PU(sid) ((sid) << 8 | 0x2d) - -/* 100k pull-up2 */ -#define PM8350_ADC7_AMUX_THM1_100K_PU(sid) ((sid) << 8 | 0x44) -#define PM8350_ADC7_AMUX_THM2_100K_PU(sid) ((sid) << 8 | 0x45) -#define PM8350_ADC7_AMUX_THM3_100K_PU(sid) ((sid) << 8 | 0x46) -#define PM8350_ADC7_AMUX_THM4_100K_PU(sid) ((sid) << 8 | 0x47) -#define PM8350_ADC7_AMUX_THM5_100K_PU(sid) ((sid) << 8 | 0x48) -#define PM8350_ADC7_GPIO1_100K_PU(sid) ((sid) << 8 | 0x4a) -#define PM8350_ADC7_GPIO2_100K_PU(sid) ((sid) << 8 | 0x4b) -#define PM8350_ADC7_GPIO3_100K_PU(sid) ((sid) << 8 | 0x4c) -#define PM8350_ADC7_GPIO4_100K_PU(sid) ((sid) << 8 | 0x4d) - -/* 400k pull-up3 */ -#define PM8350_ADC7_AMUX_THM1_400K_PU(sid) ((sid) << 8 | 0x64) -#define PM8350_ADC7_AMUX_THM2_400K_PU(sid) ((sid) << 8 | 0x65) -#define PM8350_ADC7_AMUX_THM3_400K_PU(sid) ((sid) << 8 | 0x66) -#define PM8350_ADC7_AMUX_THM4_400K_PU(sid) ((sid) << 8 | 0x67) -#define PM8350_ADC7_AMUX_THM5_400K_PU(sid) ((sid) << 8 | 0x68) -#define PM8350_ADC7_GPIO1_400K_PU(sid) ((sid) << 8 | 0x6a) -#define PM8350_ADC7_GPIO2_400K_PU(sid) ((sid) << 8 | 0x6b) -#define PM8350_ADC7_GPIO3_400K_PU(sid) ((sid) << 8 | 0x6c) -#define PM8350_ADC7_GPIO4_400K_PU(sid) ((sid) << 8 | 0x6d) - -/* 1/3 Divider */ -#define PM8350_ADC7_GPIO4_DIV3(sid) ((sid) << 8 | 0x8d) - -#define PM8350_ADC7_VPH_PWR(sid) ((sid) << 8 | 0x8e) - -#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h b/include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h deleted file mode 100644 index dc2497c27e16..000000000000 --- a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2020 The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H -#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H - -#ifndef PM8350B_SID -#define PM8350B_SID 3 -#endif - -/* ADC channels for PM8350B_ADC for PMIC7 */ -#define PM8350B_ADC7_REF_GND (PM8350B_SID << 8 | 0x0) -#define PM8350B_ADC7_1P25VREF (PM8350B_SID << 8 | 0x01) -#define PM8350B_ADC7_VREF_VADC (PM8350B_SID << 8 | 0x02) -#define PM8350B_ADC7_DIE_TEMP (PM8350B_SID << 8 | 0x03) - -#define PM8350B_ADC7_AMUX_THM1 (PM8350B_SID << 8 | 0x04) -#define PM8350B_ADC7_AMUX_THM2 (PM8350B_SID << 8 | 0x05) -#define PM8350B_ADC7_AMUX_THM3 (PM8350B_SID << 8 | 0x06) -#define PM8350B_ADC7_AMUX_THM4 (PM8350B_SID << 8 | 0x07) -#define PM8350B_ADC7_AMUX_THM5 (PM8350B_SID << 8 | 0x08) -#define PM8350B_ADC7_AMUX_THM6 (PM8350B_SID << 8 | 0x09) -#define PM8350B_ADC7_GPIO1 (PM8350B_SID << 8 | 0x0a) -#define PM8350B_ADC7_GPIO2 (PM8350B_SID << 8 | 0x0b) -#define PM8350B_ADC7_GPIO3 (PM8350B_SID << 8 | 0x0c) -#define PM8350B_ADC7_GPIO4 (PM8350B_SID << 8 | 0x0d) - -#define PM8350B_ADC7_CHG_TEMP (PM8350B_SID << 8 | 0x10) -#define PM8350B_ADC7_USB_IN_V_16 (PM8350B_SID << 8 | 0x11) -#define PM8350B_ADC7_VDC_16 (PM8350B_SID << 8 | 0x12) -#define PM8350B_ADC7_CC1_ID (PM8350B_SID << 8 | 0x13) -#define PM8350B_ADC7_VREF_BAT_THERM (PM8350B_SID << 8 | 0x15) -#define PM8350B_ADC7_IIN_FB (PM8350B_SID << 8 | 0x17) - -/* 30k pull-up1 */ -#define PM8350B_ADC7_AMUX_THM1_30K_PU (PM8350B_SID << 8 | 0x24) -#define PM8350B_ADC7_AMUX_THM2_30K_PU (PM8350B_SID << 8 | 0x25) -#define PM8350B_ADC7_AMUX_THM3_30K_PU (PM8350B_SID << 8 | 0x26) -#define PM8350B_ADC7_AMUX_THM4_30K_PU (PM8350B_SID << 8 | 0x27) -#define PM8350B_ADC7_AMUX_THM5_30K_PU (PM8350B_SID << 8 | 0x28) -#define PM8350B_ADC7_AMUX_THM6_30K_PU (PM8350B_SID << 8 | 0x29) -#define PM8350B_ADC7_GPIO1_30K_PU (PM8350B_SID << 8 | 0x2a) -#define PM8350B_ADC7_GPIO2_30K_PU (PM8350B_SID << 8 | 0x2b) -#define PM8350B_ADC7_GPIO3_30K_PU (PM8350B_SID << 8 | 0x2c) -#define PM8350B_ADC7_GPIO4_30K_PU (PM8350B_SID << 8 | 0x2d) -#define PM8350B_ADC7_CC1_ID_30K_PU (PM8350B_SID << 8 | 0x33) - -/* 100k pull-up2 */ -#define PM8350B_ADC7_AMUX_THM1_100K_PU (PM8350B_SID << 8 | 0x44) -#define PM8350B_ADC7_AMUX_THM2_100K_PU (PM8350B_SID << 8 | 0x45) -#define PM8350B_ADC7_AMUX_THM3_100K_PU (PM8350B_SID << 8 | 0x46) -#define PM8350B_ADC7_AMUX_THM4_100K_PU (PM8350B_SID << 8 | 0x47) -#define PM8350B_ADC7_AMUX_THM5_100K_PU (PM8350B_SID << 8 | 0x48) -#define PM8350B_ADC7_AMUX_THM6_100K_PU (PM8350B_SID << 8 | 0x49) -#define PM8350B_ADC7_GPIO1_100K_PU (PM8350B_SID << 8 | 0x4a) -#define PM8350B_ADC7_GPIO2_100K_PU (PM8350B_SID << 8 | 0x4b) -#define PM8350B_ADC7_GPIO3_100K_PU (PM8350B_SID << 8 | 0x4c) -#define PM8350B_ADC7_GPIO4_100K_PU (PM8350B_SID << 8 | 0x4d) -#define PM8350B_ADC7_CC1_ID_100K_PU (PM8350B_SID << 8 | 0x53) - -/* 400k pull-up3 */ -#define PM8350B_ADC7_AMUX_THM1_400K_PU (PM8350B_SID << 8 | 0x64) -#define PM8350B_ADC7_AMUX_THM2_400K_PU (PM8350B_SID << 8 | 0x65) -#define PM8350B_ADC7_AMUX_THM3_400K_PU (PM8350B_SID << 8 | 0x66) -#define PM8350B_ADC7_AMUX_THM4_400K_PU (PM8350B_SID << 8 | 0x67) -#define PM8350B_ADC7_AMUX_THM5_400K_PU (PM8350B_SID << 8 | 0x68) -#define PM8350B_ADC7_AMUX_THM6_400K_PU (PM8350B_SID << 8 | 0x69) -#define PM8350B_ADC7_GPIO1_400K_PU (PM8350B_SID << 8 | 0x6a) -#define PM8350B_ADC7_GPIO2_400K_PU (PM8350B_SID << 8 | 0x6b) -#define PM8350B_ADC7_GPIO3_400K_PU (PM8350B_SID << 8 | 0x6c) -#define PM8350B_ADC7_GPIO4_400K_PU (PM8350B_SID << 8 | 0x6d) -#define PM8350B_ADC7_CC1_ID_400K_PU (PM8350B_SID << 8 | 0x73) - -/* 1/3 Divider */ -#define PM8350B_ADC7_GPIO1_DIV3 (PM8350B_SID << 8 | 0x8a) -#define PM8350B_ADC7_GPIO2_DIV3 (PM8350B_SID << 8 | 0x8b) -#define PM8350B_ADC7_GPIO3_DIV3 (PM8350B_SID << 8 | 0x8c) -#define PM8350B_ADC7_GPIO4_DIV3 (PM8350B_SID << 8 | 0x8d) - -#define PM8350B_ADC7_VPH_PWR (PM8350B_SID << 8 | 0x8e) -#define PM8350B_ADC7_VBAT_SNS (PM8350B_SID << 8 | 0x8f) - -#define PM8350B_ADC7_SBUx (PM8350B_SID << 8 | 0x94) -#define PM8350B_ADC7_VBAT_2S_MID (PM8350B_SID << 8 | 0x96) - -#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h b/include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h deleted file mode 100644 index 6c296870e95b..000000000000 --- a/include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2020 The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H -#define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H - -#ifndef PMK8350_SID -#define PMK8350_SID 0 -#endif - -/* ADC channels for PMK8350_ADC for PMIC7 */ -#define PMK8350_ADC7_REF_GND (PMK8350_SID << 8 | 0x0) -#define PMK8350_ADC7_1P25VREF (PMK8350_SID << 8 | 0x01) -#define PMK8350_ADC7_VREF_VADC (PMK8350_SID << 8 | 0x02) -#define PMK8350_ADC7_DIE_TEMP (PMK8350_SID << 8 | 0x03) - -#define PMK8350_ADC7_AMUX_THM1 (PMK8350_SID << 8 | 0x04) -#define PMK8350_ADC7_AMUX_THM2 (PMK8350_SID << 8 | 0x05) -#define PMK8350_ADC7_AMUX_THM3 (PMK8350_SID << 8 | 0x06) -#define PMK8350_ADC7_AMUX_THM4 (PMK8350_SID << 8 | 0x07) -#define PMK8350_ADC7_AMUX_THM5 (PMK8350_SID << 8 | 0x08) - -/* 30k pull-up1 */ -#define PMK8350_ADC7_AMUX_THM1_30K_PU (PMK8350_SID << 8 | 0x24) -#define PMK8350_ADC7_AMUX_THM2_30K_PU (PMK8350_SID << 8 | 0x25) -#define PMK8350_ADC7_AMUX_THM3_30K_PU (PMK8350_SID << 8 | 0x26) -#define PMK8350_ADC7_AMUX_THM4_30K_PU (PMK8350_SID << 8 | 0x27) -#define PMK8350_ADC7_AMUX_THM5_30K_PU (PMK8350_SID << 8 | 0x28) - -/* 100k pull-up2 */ -#define PMK8350_ADC7_AMUX_THM1_100K_PU (PMK8350_SID << 8 | 0x44) -#define PMK8350_ADC7_AMUX_THM2_100K_PU (PMK8350_SID << 8 | 0x45) -#define PMK8350_ADC7_AMUX_THM3_100K_PU (PMK8350_SID << 8 | 0x46) -#define PMK8350_ADC7_AMUX_THM4_100K_PU (PMK8350_SID << 8 | 0x47) -#define PMK8350_ADC7_AMUX_THM5_100K_PU (PMK8350_SID << 8 | 0x48) - -/* 400k pull-up3 */ -#define PMK8350_ADC7_AMUX_THM1_400K_PU (PMK8350_SID << 8 | 0x64) -#define PMK8350_ADC7_AMUX_THM2_400K_PU (PMK8350_SID << 8 | 0x65) -#define PMK8350_ADC7_AMUX_THM3_400K_PU (PMK8350_SID << 8 | 0x66) -#define PMK8350_ADC7_AMUX_THM4_400K_PU (PMK8350_SID << 8 | 0x67) -#define PMK8350_ADC7_AMUX_THM5_400K_PU (PMK8350_SID << 8 | 0x68) - -#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h b/include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h deleted file mode 100644 index d6df1b19e5ff..000000000000 --- a/include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2020 The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H -#define _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H - -#ifndef PMR735A_SID -#define PMR735A_SID 4 -#endif - -/* ADC channels for PMR735A_ADC for PMIC7 */ -#define PMR735A_ADC7_REF_GND (PMR735A_SID << 8 | 0x0) -#define PMR735A_ADC7_1P25VREF (PMR735A_SID << 8 | 0x01) -#define PMR735A_ADC7_VREF_VADC (PMR735A_SID << 8 | 0x02) -#define PMR735A_ADC7_DIE_TEMP (PMR735A_SID << 8 | 0x03) - -#define PMR735A_ADC7_GPIO1 (PMR735A_SID << 8 | 0x0a) -#define PMR735A_ADC7_GPIO2 (PMR735A_SID << 8 | 0x0b) -#define PMR735A_ADC7_GPIO3 (PMR735A_SID << 8 | 0x0c) - -/* 100k pull-up2 */ -#define PMR735A_ADC7_GPIO1_100K_PU (PMR735A_SID << 8 | 0x4a) -#define PMR735A_ADC7_GPIO2_100K_PU (PMR735A_SID << 8 | 0x4b) -#define PMR735A_ADC7_GPIO3_100K_PU (PMR735A_SID << 8 | 0x4c) - -#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h b/include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h deleted file mode 100644 index 8da0e7dab315..000000000000 --- a/include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2020 The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H -#define _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H - -#ifndef PMR735B_SID -#define PMR735B_SID 5 -#endif - -/* ADC channels for PMR735B_ADC for PMIC7 */ -#define PMR735B_ADC7_REF_GND (PMR735B_SID << 8 | 0x0) -#define PMR735B_ADC7_1P25VREF (PMR735B_SID << 8 | 0x01) -#define PMR735B_ADC7_VREF_VADC (PMR735B_SID << 8 | 0x02) -#define PMR735B_ADC7_DIE_TEMP (PMR735B_SID << 8 | 0x03) - -#define PMR735B_ADC7_GPIO1 (PMR735B_SID << 8 | 0x0a) -#define PMR735B_ADC7_GPIO2 (PMR735B_SID << 8 | 0x0b) -#define PMR735B_ADC7_GPIO3 (PMR735B_SID << 8 | 0x0c) - -/* 100k pull-up2 */ -#define PMR735B_ADC7_GPIO1_100K_PU (PMR735B_SID << 8 | 0x4a) -#define PMR735B_ADC7_GPIO2_100K_PU (PMR735B_SID << 8 | 0x4b) -#define PMR735B_ADC7_GPIO3_100K_PU (PMR735B_SID << 8 | 0x4c) - -#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-vadc.h b/include/dt-bindings/iio/qcom,spmi-vadc.h index 92a064ada796..b1413c62ad27 100644 --- a/include/dt-bindings/iio/qcom,spmi-vadc.h +++ b/include/dt-bindings/iio/qcom,spmi-vadc.h @@ -222,82 +222,6 @@ #define ADC5_MAX_CHANNEL 0xc0 -/* ADC channels for ADC for PMIC7 */ - -#define ADC7_REF_GND 0x00 -#define ADC7_1P25VREF 0x01 -#define ADC7_VREF_VADC 0x02 -#define ADC7_DIE_TEMP 0x03 - -#define ADC7_AMUX_THM1 0x04 -#define ADC7_AMUX_THM2 0x05 -#define ADC7_AMUX_THM3 0x06 -#define ADC7_AMUX_THM4 0x07 -#define ADC7_AMUX_THM5 0x08 -#define ADC7_AMUX_THM6 0x09 -#define ADC7_GPIO1 0x0a -#define ADC7_GPIO2 0x0b -#define ADC7_GPIO3 0x0c -#define ADC7_GPIO4 0x0d - -#define ADC7_CHG_TEMP 0x10 -#define ADC7_USB_IN_V_16 0x11 -#define ADC7_VDC_16 0x12 -#define ADC7_CC1_ID 0x13 -#define ADC7_VREF_BAT_THERM 0x15 -#define ADC7_IIN_FB 0x17 - -/* 30k pull-up1 */ -#define ADC7_AMUX_THM1_30K_PU 0x24 -#define ADC7_AMUX_THM2_30K_PU 0x25 -#define ADC7_AMUX_THM3_30K_PU 0x26 -#define ADC7_AMUX_THM4_30K_PU 0x27 -#define ADC7_AMUX_THM5_30K_PU 0x28 -#define ADC7_AMUX_THM6_30K_PU 0x29 -#define ADC7_GPIO1_30K_PU 0x2a -#define ADC7_GPIO2_30K_PU 0x2b -#define ADC7_GPIO3_30K_PU 0x2c -#define ADC7_GPIO4_30K_PU 0x2d -#define ADC7_CC1_ID_30K_PU 0x33 - -/* 100k pull-up2 */ -#define ADC7_AMUX_THM1_100K_PU 0x44 -#define ADC7_AMUX_THM2_100K_PU 0x45 -#define ADC7_AMUX_THM3_100K_PU 0x46 -#define ADC7_AMUX_THM4_100K_PU 0x47 -#define ADC7_AMUX_THM5_100K_PU 0x48 -#define ADC7_AMUX_THM6_100K_PU 0x49 -#define ADC7_GPIO1_100K_PU 0x4a -#define ADC7_GPIO2_100K_PU 0x4b -#define ADC7_GPIO3_100K_PU 0x4c -#define ADC7_GPIO4_100K_PU 0x4d -#define ADC7_CC1_ID_100K_PU 0x53 - -/* 400k pull-up3 */ -#define ADC7_AMUX_THM1_400K_PU 0x64 -#define ADC7_AMUX_THM2_400K_PU 0x65 -#define ADC7_AMUX_THM3_400K_PU 0x66 -#define ADC7_AMUX_THM4_400K_PU 0x67 -#define ADC7_AMUX_THM5_400K_PU 0x68 -#define ADC7_AMUX_THM6_400K_PU 0x69 -#define ADC7_GPIO1_400K_PU 0x6a -#define ADC7_GPIO2_400K_PU 0x6b -#define ADC7_GPIO3_400K_PU 0x6c -#define ADC7_GPIO4_400K_PU 0x6d -#define ADC7_CC1_ID_400K_PU 0x73 - -/* 1/3 Divider */ -#define ADC7_GPIO1_DIV3 0x8a -#define ADC7_GPIO2_DIV3 0x8b -#define ADC7_GPIO3_DIV3 0x8c -#define ADC7_GPIO4_DIV3 0x8d - -#define ADC7_VPH_PWR 0x8e -#define ADC7_VBAT_SNS 0x8f - -#define ADC7_SBUx 0x94 -#define ADC7_VBAT_2S_MID 0x96 - /* ADC channels for ADC for PMIC5 Gen2 */ #define ADC5_GEN2_REF_GND 0x00 From patchwork Sat Jul 8 07:28:29 2023 Content-Type: text/plain; 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Sat, 8 Jul 2023 07:29:45 GMT Received: from hu-jprakash-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Sat, 8 Jul 2023 00:29:38 -0700 From: Jishnu Prakash To: , , , , , , , , , , , , , , "Bjorn Andersson" , Konrad Dybcio , Jonathan Cameron , Lars-Peter Clausen , , CC: , Jishnu Prakash Subject: [PATCH 05/11] iio: adc: qcom-spmi-adc5: remove support for ADC7 compatible string Date: Sat, 8 Jul 2023 12:58:29 +0530 Message-ID: <20230708072835.3035398-6-quic_jprakash@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230708072835.3035398-1-quic_jprakash@quicinc.com> References: <20230708072835.3035398-1-quic_jprakash@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: IqNPqMj5cR2sAece8oFQeJEs18eSlFCN X-Proofpoint-ORIG-GUID: IqNPqMj5cR2sAece8oFQeJEs18eSlFCN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-08_03,2023-07-06_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 impostorscore=0 adultscore=0 spamscore=0 phishscore=0 mlxlogscore=999 priorityscore=1501 clxscore=1015 bulkscore=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307080065 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Now that usage of "ADC7" name has been replaced with usage of "ADC5 Gen2" name everywhere, remove the "qcom,spmi-adc7" compatible string. Signed-off-by: Jishnu Prakash --- drivers/iio/adc/qcom-spmi-adc5.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/iio/adc/qcom-spmi-adc5.c b/drivers/iio/adc/qcom-spmi-adc5.c index 3ac1ee500a67..6cebeaa69a75 100644 --- a/drivers/iio/adc/qcom-spmi-adc5.c +++ b/drivers/iio/adc/qcom-spmi-adc5.c @@ -807,10 +807,6 @@ static const struct of_device_id adc5_match_table[] = { .compatible = "qcom,spmi-adc5", .data = &adc5_data_pmic, }, - { - .compatible = "qcom,spmi-adc7", - .data = &adc5_gen2_data_pmic, - }, { .compatible = "qcom,spmi-adc5-gen2", .data = &adc5_gen2_data_pmic, From patchwork Sat Jul 8 07:28:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jishnu Prakash X-Patchwork-Id: 700377 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E7F5EB64DA for ; Sat, 8 Jul 2023 07:31:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229627AbjGHHbQ (ORCPT ); Sat, 8 Jul 2023 03:31:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59494 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231909AbjGHHbP (ORCPT ); Sat, 8 Jul 2023 03:31:15 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4DFBF2705; Sat, 8 Jul 2023 00:30:26 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3687PCZF027502; Sat, 8 Jul 2023 07:29:57 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=VQ6vGIZBy2Q/ERTkoV4CefPy8cImEpDSqFa7X1e0bvU=; b=Qr3YTgcjpLuqr4XYUCX0k6r2E5/X4CXzdSR7kAXcuRyBAiTqRalnLOJQThSPMGwQmXTb 5RtbEebtYUDZJgxF0mZ3yzH8jP37WV97eXqY1u9/pTMncH8qEqq2HujdPSq5tG0C/3JJ t0mxke8O0p0h5uH7iG3wjOGptAcNcWSzjTAPMM78YHopqRzubr6cTzyxno1HfiMmuCXM tNAEVEgqz/N/w5y35yaqudbgtcrTZpIv1sj7G02qSdshLlzTMv22IWlMfpCv2LYQUIwZ Iloc2GX0h1mktMi7031byPECGeFgvvGIrTUpmzwnKdE/rxpywHtcMuXBqmxN+hEG7KQp Uw== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rq13f04my-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 08 Jul 2023 07:29:56 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3687TuoR011771 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 8 Jul 2023 07:29:56 GMT Received: from hu-jprakash-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Sat, 8 Jul 2023 00:29:48 -0700 From: Jishnu Prakash To: , , , , , , , , , , , , , , Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Jishnu Prakash , "Luca Weiss" , , CC: Subject: [PATCH 06/11] iio: adc: Add QCOM PMIC5 Gen3 ADC bindings Date: Sat, 8 Jul 2023 12:58:30 +0530 Message-ID: <20230708072835.3035398-7-quic_jprakash@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230708072835.3035398-1-quic_jprakash@quicinc.com> References: <20230708072835.3035398-1-quic_jprakash@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: U7oEr49fHUARJrxt5Y_40EAmv91qglgn X-Proofpoint-ORIG-GUID: U7oEr49fHUARJrxt5Y_40EAmv91qglgn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-08_04,2023-07-06_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 adultscore=0 impostorscore=0 malwarescore=0 mlxscore=0 spamscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307080065 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs. It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs going through PBS firmware through a single register interface. This interface is implemented on an SDAM peripheral on the master PMIC PMK8550 rather than a dedicated ADC peripheral. Signed-off-by: Jishnu Prakash --- .../bindings/iio/adc/qcom,spmi-vadc.yaml | 117 ++++++++++++++++-- .../iio/qcom,spmi-adc5-gen3-pm8550.h | 48 +++++++ .../iio/qcom,spmi-adc5-gen3-pm8550b.h | 97 +++++++++++++++ .../iio/qcom,spmi-adc5-gen3-pm8550vx.h | 20 +++ .../iio/qcom,spmi-adc5-gen3-pmk8550.h | 54 ++++++++ include/dt-bindings/iio/qcom,spmi-vadc.h | 78 ++++++++++++ 6 files changed, 402 insertions(+), 12 deletions(-) create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml index eb7d16e385ad..090113e62d52 100644 --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml @@ -13,8 +13,8 @@ maintainers: description: | SPMI PMIC voltage ADC (VADC) provides interface to clients to read voltage. The VADC is a 15-bit sigma-delta ADC. - SPMI PMIC5/PMIC5 Gen2 voltage ADC (ADC) provides interface to clients to read - voltage. The VADC is a 16-bit sigma-delta ADC. + SPMI PMIC5/PMIC5 Gen2/PMIC5 Gen3 voltage ADC (ADC) provides interface to + clients to read voltage. The VADC is a 16-bit sigma-delta ADC. properties: compatible: @@ -27,10 +27,11 @@ properties: - qcom,spmi-adc5 - qcom,spmi-adc-rev2 - qcom,spmi-adc5-gen2 + - qcom,spmi-adc5-gen3 reg: description: VADC base address in the SPMI PMIC register map - maxItems: 1 + minItems: 1 '#address-cells': const: 1 @@ -38,6 +39,12 @@ properties: '#size-cells': const: 0 + "#thermal-sensor-cells": + const: 1 + description: + Number of cells required to uniquely identify the thermal sensors. Since + we have multiple sensors this is set to 1. + '#io-channel-cells': const: 1 @@ -71,8 +78,8 @@ patternProperties: description: | ADC channel number. See include/dt-bindings/iio/qcom,spmi-vadc.h - For PMIC5 Gen2 ADC, the channel numbers are specified separately per PMIC - in the PMIC-specific files in include/dt-bindings/iio/. + For PMIC5 Gen2 and PMIC5 Gen3 ADC, the channel numbers are specified separately per + PMIC in the PMIC-specific files in include/dt-bindings/iio/. label: $ref: /schemas/types.yaml#/definitions/string @@ -114,11 +121,12 @@ patternProperties: channel calibration. If property is not found, channel will be calibrated with 0.625V and 1.25V reference channels, also known as absolute calibration. - - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc5-gen2" and - "qcom,spmi-adc-rev2", if this property is specified VADC will use - the VDD reference (1.875V) and GND for channel calibration. If - property is not found, channel will be calibrated with 0V and 1.25V - reference channels, also known as absolute calibration. + - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc5-gen2", + "qcom,spmi-adc-rev2" and "qcom,spmi-adc5-gen3", if this property + is specified VADC will use the VDD reference (1.875V) and GND for + channel calibration. If property is not found, channel will be + calibrated with 0V and 1.25V reference channels, also known as + absolute calibration. type: boolean qcom,hw-settle-time: @@ -136,6 +144,12 @@ patternProperties: from the ADC that is an average of multiple samples. The value selected is 2^(value). + qcom,adc-tm-type: + description: | + Indicates if ADC_TM monitoring is done on this channel. + Defined for compatible property "qcom,spmi-adc5-gen3". + type: boolean + required: - reg @@ -213,7 +227,9 @@ allOf: properties: compatible: contains: - const: qcom,spmi-adc5-gen2 + enum: + - qcom,spmi-adc5-gen2 + - qcom,spmi-adc5-gen3 then: patternProperties: @@ -299,7 +315,7 @@ examples: label = "xo_therm"; }; - channel@47 { + channel@147 { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; @@ -307,3 +323,80 @@ examples: }; }; }; + + - | + #include + #include + #include + #include + + pmic { + #address-cells = <1>; + #size-cells = <0>; + + /* VADC node */ + pmk8550_vadc: vadc@9000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x9000>; + interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + #thermal-sensor-cells = <1>; + + /* PMK8550 Channel nodes */ + channel@3 { + reg = ; + label = "pmk8550_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@44 { + reg = ; + label = "pmk8550_xo_therm"; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,adc-tm-type; + }; + + /* PM8550 Channel nodes */ + channel@103 { + reg = ; + label = "pm8550_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@18e { + reg = ; + label = "pm8550_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + /* PM8550B Channel nodes */ + channel@703 { + reg = ; + label = "pm8550b_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@78e { + reg = ; + label = "pm8550b_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + channel@78f { + reg = ; + label = "pm8550b_vbat_sns_qbg"; + qcom,pre-scaling = <1 3>; + }; + + /* PM8550VS_C Channel nodes */ + channel@203 { + reg = ; + label = "pm8550vs_c_die_temp"; + qcom,pre-scaling = <1 1>; + }; + }; + }; diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h new file mode 100644 index 000000000000..74e6e2f6f9ed --- /dev/null +++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H + +#ifndef PM8550_SID +#define PM8550_SID 1 +#endif + +/* ADC channels for PM8550_ADC for PMIC5 Gen3 */ +#define PM8550_ADC5_GEN3_OFFSET_REF (PM8550_SID << 8 | 0x00) +#define PM8550_ADC5_GEN3_1P25VREF (PM8550_SID << 8 | 0x01) +#define PM8550_ADC5_GEN3_VREF_VADC (PM8550_SID << 8 | 0x02) +#define PM8550_ADC5_GEN3_DIE_TEMP (PM8550_SID << 8 | 0x03) + +#define PM8550_ADC5_GEN3_AMUX_THM1 (PM8550_SID << 8 | 0x04) +#define PM8550_ADC5_GEN3_AMUX_THM2 (PM8550_SID << 8 | 0x05) +#define PM8550_ADC5_GEN3_AMUX_THM3 (PM8550_SID << 8 | 0x06) +#define PM8550_ADC5_GEN3_AMUX_THM4 (PM8550_SID << 8 | 0x07) +#define PM8550_ADC5_GEN3_AMUX_THM5 (PM8550_SID << 8 | 0x08) +#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2 (PM8550_SID << 8 | 0x09) +#define PM8550_ADC5_GEN3_AMUX1_GPIO3 (PM8550_SID << 8 | 0x0a) +#define PM8550_ADC5_GEN3_AMUX2_GPIO4 (PM8550_SID << 8 | 0x0b) +#define PM8550_ADC5_GEN3_AMUX3_GPIO7 (PM8550_SID << 8 | 0x0c) +#define PM8550_ADC5_GEN3_AMUX4_GPIO12 (PM8550_SID << 8 | 0x0d) + +/* 100k pull-up */ +#define PM8550_ADC5_GEN3_AMUX_THM1_100K_PU (PM8550_SID << 8 | 0x44) +#define PM8550_ADC5_GEN3_AMUX_THM2_100K_PU (PM8550_SID << 8 | 0x45) +#define PM8550_ADC5_GEN3_AMUX_THM3_100K_PU (PM8550_SID << 8 | 0x46) +#define PM8550_ADC5_GEN3_AMUX_THM4_100K_PU (PM8550_SID << 8 | 0x47) +#define PM8550_ADC5_GEN3_AMUX_THM5_100K_PU (PM8550_SID << 8 | 0x48) +#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2_100K_PU (PM8550_SID << 8 | 0x49) +#define PM8550_ADC5_GEN3_AMUX1_GPIO3_100K_PU (PM8550_SID << 8 | 0x4a) +#define PM8550_ADC5_GEN3_AMUX2_GPIO4_100K_PU (PM8550_SID << 8 | 0x4b) +#define PM8550_ADC5_GEN3_AMUX3_GPIO7_100K_PU (PM8550_SID << 8 | 0x4c) +#define PM8550_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550_SID << 8 | 0x4d) + +/* 1/3 Divider */ +#define PM8550_ADC5_GEN3_AMUX3_GPIO7_DIV3 (PM8550_SID << 8 | 0x8c) +#define PM8550_ADC5_GEN3_AMUX4_GPIO12_DIV3 (PM8550_SID << 8 | 0x8d) + +#define PM8550_ADC5_GEN3_VPH_PWR (PM8550_SID << 8 | 0x8e) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h new file mode 100644 index 000000000000..35483dfd970e --- /dev/null +++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H + +#ifndef PM8550B_SID +#define PM8550B_SID 7 +#endif + +/* ADC channels for PM8550B_ADC for PMIC5 Gen3 */ +#define PM8550B_ADC5_GEN3_OFFSET_REF (PM8550B_SID << 8 | 0x00) +#define PM8550B_ADC5_GEN3_1P25VREF (PM8550B_SID << 8 | 0x01) +#define PM8550B_ADC5_GEN3_VREF_VADC (PM8550B_SID << 8 | 0x02) +#define PM8550B_ADC5_GEN3_DIE_TEMP (PM8550B_SID << 8 | 0x03) + +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM (PM8550B_SID << 8 | 0x04) +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID (PM8550B_SID << 8 | 0x05) +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V (PM8550B_SID << 8 | 0x06) +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM (PM8550B_SID << 8 | 0x07) +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION (PM8550B_SID << 8 | 0x08) +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10 (PM8550B_SID << 8 | 0x09) +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1 (PM8550B_SID << 8 | 0x0a) +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5 (PM8550B_SID << 8 | 0x0b) +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6 (PM8550B_SID << 8 | 0x0c) +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12 (PM8550B_SID << 8 | 0x0d) + +#define PM8550B_ADC5_GEN3_CHG_TEMP (PM8550B_SID << 8 | 0x10) +#define PM8550B_ADC5_GEN3_USB_SNS_V_16 (PM8550B_SID << 8 | 0x11) +#define PM8550B_ADC5_GEN3_VIN_DIV16_MUX (PM8550B_SID << 8 | 0x12) +#define PM8550B_ADC5_GEN3_USBC_MUX (PM8550B_SID << 8 | 0x13) +#define PM8550B_ADC5_GEN3_VREF_BAT_THERM (PM8550B_SID << 8 | 0x15) +#define PM8550B_ADC5_GEN3_IIN_FB (PM8550B_SID << 8 | 0x17) +#define PM8550B_ADC5_GEN3_TEMP_ALARM_LITE (PM8550B_SID << 8 | 0x18) +#define PM8550B_ADC5_GEN3_SMB_IIN (PM8550B_SID << 8 | 0x19) +#define PM8550B_ADC5_GEN3_VREF_BAT2_THERM (PM8550B_SID << 8 | 0x1a) +#define PM8550B_ADC5_GEN3_SMB_ICHG (PM8550B_SID << 8 | 0x1b) +#define PM8550B_ADC5_GEN3_SMB_TEMP_I (PM8550B_SID << 8 | 0x1e) +#define PM8550B_ADC5_GEN3_CHG_TEMP_I (PM8550B_SID << 8 | 0x1f) +#define PM8550B_ADC5_GEN3_ICHG_FB (PM8550B_SID << 8 | 0xa1) + +/* 30k pull-up */ +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_30K_PU (PM8550B_SID << 8 | 0x24) +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_30K_PU (PM8550B_SID << 8 | 0x25) +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_30K_PU (PM8550B_SID << 8 | 0x26) +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_30K_PU (PM8550B_SID << 8 | 0x27) +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_30K_PU (PM8550B_SID << 8 | 0x28) +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_30K_PU (PM8550B_SID << 8 | 0x29) +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_30K_PU (PM8550B_SID << 8 | 0x2a) +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_30K_PU (PM8550B_SID << 8 | 0x2b) +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_30K_PU (PM8550B_SID << 8 | 0x2c) +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_30K_PU (PM8550B_SID << 8 | 0x2d) + +#define PM8550B_ADC5_GEN3_USBC_MUX_30K_PU (PM8550B_SID << 8 | 0x33) + +/* 100k pull-up */ +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_100K_PU (PM8550B_SID << 8 | 0x44) +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_100K_PU (PM8550B_SID << 8 | 0x45) +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_100K_PU (PM8550B_SID << 8 | 0x46) +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU (PM8550B_SID << 8 | 0x47) +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_100K_PU (PM8550B_SID << 8 | 0x48) +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_100K_PU (PM8550B_SID << 8 | 0x49) +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_100K_PU (PM8550B_SID << 8 | 0x4a) +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_100K_PU (PM8550B_SID << 8 | 0x4b) +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_100K_PU (PM8550B_SID << 8 | 0x4c) +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550B_SID << 8 | 0x4d) + +#define PM8550B_ADC5_GEN3_USBC_MUX_100K_PU (PM8550B_SID << 8 | 0x53) + +/* 400k pull-up */ +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_400K_PU (PM8550B_SID << 8 | 0x64) +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_400K_PU (PM8550B_SID << 8 | 0x65) +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_400K_PU (PM8550B_SID << 8 | 0x66) +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_400K_PU (PM8550B_SID << 8 | 0x67) +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_400K_PU (PM8550B_SID << 8 | 0x68) +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_400K_PU (PM8550B_SID << 8 | 0x69) +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_400K_PU (PM8550B_SID << 8 | 0x6a) +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_400K_PU (PM8550B_SID << 8 | 0x6b) +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_400K_PU (PM8550B_SID << 8 | 0x6c) +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_400K_PU (PM8550B_SID << 8 | 0x6d) + +#define PM8550B_ADC5_GEN3_USBC_MUX_400K_PU (PM8550B_SID << 8 | 0x73) + +/* 1/3 Divider */ +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_DIV3 (PM8550B_SID << 8 | 0x8a) +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_DIV3 (PM8550B_SID << 8 | 0x8b) +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_DIV3 (PM8550B_SID << 8 | 0x8c) + +#define PM8550B_ADC5_GEN3_VPH_PWR (PM8550B_SID << 8 | 0x8e) +#define PM8550B_ADC5_GEN3_VBAT_SNS_QBG (PM8550B_SID << 8 | 0x8f) +#define PM8550B_ADC5_GEN3_VBAT_SNS_CHGR (PM8550B_SID << 8 | 0x94) +#define PM8550B_ADC5_GEN3_VBAT_2S_MID_QBG (PM8550B_SID << 8 | 0x96) +#define PM8550B_ADC5_GEN3_VBAT_2S_MID_CHGR (PM8550B_SID << 8 | 0x9d) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h new file mode 100644 index 000000000000..337e13f7f56f --- /dev/null +++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H + +/* ADC channels for PM8550VX_ADC for PMIC5 Gen3 */ +#define PM8550VS_ADC5_GEN3_OFFSET_REF(sid) ((sid) << 8 | 0x00) +#define PM8550VS_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | 0x01) +#define PM8550VS_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | 0X02) +#define PM8550VS_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | 0x03) + +#define PM8550VE_ADC5_GEN3_OFFSET_REF(sid) ((sid) << 8 | 0x00) +#define PM8550VE_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | 0x01) +#define PM8550VE_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | 0X02) +#define PM8550VE_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | 0x03) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h new file mode 100644 index 000000000000..126fc16d5b20 --- /dev/null +++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H + +#ifndef PMK8550_SID +#define PMK8550_SID 0 +#endif + +/* ADC channels for PMK8550_ADC for PMIC5 Gen3 */ +#define PMK8550_ADC5_GEN3_OFFSET_REF (PMK8550_SID << 8 | 0x00) +#define PMK8550_ADC5_GEN3_1P25VREF (PMK8550_SID << 8 | 0x01) +#define PMK8550_ADC5_GEN3_VREF_VADC (PMK8550_SID << 8 | 0x02) +#define PMK8550_ADC5_GEN3_DIE_TEMP (PMK8550_SID << 8 | 0x03) + +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM (PMK8550_SID << 8 | 0x04) +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1 (PMK8550_SID << 8 | 0x05) +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2 (PMK8550_SID << 8 | 0x06) +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3 (PMK8550_SID << 8 | 0x07) +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4 (PMK8550_SID << 8 | 0x08) +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5 (PMK8550_SID << 8 | 0x09) +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6 (PMK8550_SID << 8 | 0x0a) + +/* 30k pull-up */ +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_30K_PU (PMK8550_SID << 8 | 0x24) +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_30K_PU (PMK8550_SID << 8 | 0x25) +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_30K_PU (PMK8550_SID << 8 | 0x26) +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_30K_PU (PMK8550_SID << 8 | 0x27) +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_30K_PU (PMK8550_SID << 8 | 0x28) +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_30K_PU (PMK8550_SID << 8 | 0x29) +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_30K_PU (PMK8550_SID << 8 | 0x2a) + +/* 100k pull-up */ +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU (PMK8550_SID << 8 | 0x44) +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_100K_PU (PMK8550_SID << 8 | 0x45) +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_100K_PU (PMK8550_SID << 8 | 0x46) +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_100K_PU (PMK8550_SID << 8 | 0x47) +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_100K_PU (PMK8550_SID << 8 | 0x48) +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_100K_PU (PMK8550_SID << 8 | 0x49) +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_100K_PU (PMK8550_SID << 8 | 0x4a) + +/* 400k pull-up */ +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_400K_PU (PMK8550_SID << 8 | 0x64) +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_400K_PU (PMK8550_SID << 8 | 0x65) +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_400K_PU (PMK8550_SID << 8 | 0x66) +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_400K_PU (PMK8550_SID << 8 | 0x67) +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_400K_PU (PMK8550_SID << 8 | 0x68) +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_400K_PU (PMK8550_SID << 8 | 0x69) +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_400K_PU (PMK8550_SID << 8 | 0x6a) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-vadc.h b/include/dt-bindings/iio/qcom,spmi-vadc.h index b1413c62ad27..ca5a0a947b3b 100644 --- a/include/dt-bindings/iio/qcom,spmi-vadc.h +++ b/include/dt-bindings/iio/qcom,spmi-vadc.h @@ -298,4 +298,82 @@ #define ADC5_GEN2_SBUx 0x94 #define ADC5_GEN2_VBAT_2S_MID 0x96 +/* ADC channels for PMIC5 Gen3 */ + +#define ADC5_GEN3_OFFSET_REF 0x00 +#define ADC5_GEN3_1P25VREF 0x01 +#define ADC5_GEN3_VREF_VADC 0x02 +#define ADC5_GEN3_DIE_TEMP 0x03 + +#define ADC5_GEN3_AMUX1_THM 0x04 +#define ADC5_GEN3_AMUX2_THM 0x05 +#define ADC5_GEN3_AMUX3_THM 0x06 +#define ADC5_GEN3_AMUX4_THM 0x07 +#define ADC5_GEN3_AMUX5_THM 0x08 +#define ADC5_GEN3_AMUX6_THM 0x09 +#define ADC5_GEN3_AMUX1_GPIO 0x0a +#define ADC5_GEN3_AMUX2_GPIO 0x0b +#define ADC5_GEN3_AMUX3_GPIO 0x0c +#define ADC5_GEN3_AMUX4_GPIO 0x0d + +#define ADC5_GEN3_CHG_TEMP 0x10 +#define ADC5_GEN3_USB_SNS_V_16 0x11 +#define ADC5_GEN3_VIN_DIV16_MUX 0x12 +#define ADC5_GEN3_VREF_BAT_THERM 0x15 +#define ADC5_GEN3_IIN_FB 0x17 +#define ADC5_GEN3_TEMP_ALARM_LITE 0x18 +#define ADC5_GEN3_IIN_SMB 0x19 +#define ADC5_GEN3_ICHG_SMB 0x1b +#define ADC5_GEN3_ICHG_FB 0xa1 + +/* 30k pull-up1 */ +#define ADC5_GEN3_AMUX1_THM_30K_PU 0x24 +#define ADC5_GEN3_AMUX2_THM_30K_PU 0x25 +#define ADC5_GEN3_AMUX3_THM_30K_PU 0x26 +#define ADC5_GEN3_AMUX4_THM_30K_PU 0x27 +#define ADC5_GEN3_AMUX5_THM_30K_PU 0x28 +#define ADC5_GEN3_AMUX6_THM_30K_PU 0x29 +#define ADC5_GEN3_AMUX1_GPIO_30K_PU 0x2a +#define ADC5_GEN3_AMUX2_GPIO_30K_PU 0x2b +#define ADC5_GEN3_AMUX3_GPIO_30K_PU 0x2c +#define ADC5_GEN3_AMUX4_GPIO_30K_PU 0x2d + +/* 100k pull-up2 */ +#define ADC5_GEN3_AMUX1_THM_100K_PU 0x44 +#define ADC5_GEN3_AMUX2_THM_100K_PU 0x45 +#define ADC5_GEN3_AMUX3_THM_100K_PU 0x46 +#define ADC5_GEN3_AMUX4_THM_100K_PU 0x47 +#define ADC5_GEN3_AMUX5_THM_100K_PU 0x48 +#define ADC5_GEN3_AMUX6_THM_100K_PU 0x49 +#define ADC5_GEN3_AMUX1_GPIO_100K_PU 0x4a +#define ADC5_GEN3_AMUX2_GPIO_100K_PU 0x4b +#define ADC5_GEN3_AMUX3_GPIO_100K_PU 0x4c +#define ADC5_GEN3_AMUX4_GPIO_100K_PU 0x4d + +/* 400k pull-up3 */ +#define ADC5_GEN3_AMUX1_THM_400K_PU 0x64 +#define ADC5_GEN3_AMUX2_THM_400K_PU 0x65 +#define ADC5_GEN3_AMUX3_THM_400K_PU 0x66 +#define ADC5_GEN3_AMUX4_THM_400K_PU 0x67 +#define ADC5_GEN3_AMUX5_THM_400K_PU 0x68 +#define ADC5_GEN3_AMUX6_THM_400K_PU 0x69 +#define ADC5_GEN3_AMUX1_GPIO_400K_PU 0x6a +#define ADC5_GEN3_AMUX2_GPIO_400K_PU 0x6b +#define ADC5_GEN3_AMUX3_GPIO_400K_PU 0x6c +#define ADC5_GEN3_AMUX4_GPIO_400K_PU 0x6d + +/* 1/3 Divider */ +#define ADC5_GEN3_AMUX1_GPIO_DIV3 0x8a +#define ADC5_GEN3_AMUX2_GPIO_DIV3 0x8b +#define ADC5_GEN3_AMUX3_GPIO_DIV3 0x8c + +#define ADC5_GEN3_VPH_PWR 0x8e +#define ADC5_GEN3_VBAT_SNS_QBG 0x8f + +#define ADC5_GEN3_VBAT_SNS_CHGR 0x94 +#define ADC5_GEN3_VBAT_2S_MID_QBG 0x96 +#define ADC5_GEN3_VBAT_2S_MID_CHGR 0x9d + +#define ADC5_GEN3_OFFSET_EXT2 0xf8 + #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */ From patchwork Sat Jul 8 07:28:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jishnu Prakash X-Patchwork-Id: 700963 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org 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hu-jprakash-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Sat, 8 Jul 2023 00:30:01 -0700 From: Jishnu Prakash To: , , , , , , , , , , , , , , Jonathan Cameron , Lars-Peter Clausen , Bjorn Andersson , Konrad Dybcio , Arnd Bergmann , Cosmin Tanislav , Mike Looijmans , "Jishnu Prakash" , Ramona Bolboaca , ChiYuan Huang , "Ibrahim Tilki" , William Breathitt Gray , Lee Jones , =?utf-8?q?Leonard_G=C3=B6hrs?= , Haibo Chen , , CC: Subject: [PATCH 07/11] iio: adc: Add support for QCOM PMIC5 Gen3 ADC Date: Sat, 8 Jul 2023 12:58:31 +0530 Message-ID: <20230708072835.3035398-8-quic_jprakash@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230708072835.3035398-1-quic_jprakash@quicinc.com> References: <20230708072835.3035398-1-quic_jprakash@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: L3WeLP2MDrWZsI1Hvc1AsXCsrfD7U0rw X-Proofpoint-ORIG-GUID: L3WeLP2MDrWZsI1Hvc1AsXCsrfD7U0rw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-08_03,2023-07-06_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 impostorscore=0 adultscore=0 spamscore=0 phishscore=0 mlxlogscore=999 priorityscore=1501 clxscore=1011 bulkscore=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307080065 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The ADC architecture on PMIC5 Gen3 is similar to that on PMIC5 Gen2, with all SW communication to ADC going through PMK8550 which communicates with other PMICs through PBS. One major difference is that the register interface used here is that of an SDAM present on PMK8550. There may be more than one SDAM used for ADC5 Gen3 and each has eight channels, which may be used for either immediate reads (same functionality as previous PMIC5 and PMIC5 Gen2 ADC peripherals) or recurring measurements (same as ADC_TM functionality). In this case, we have VADC and ADC_TM functionality combined into the same driver. By convention, we reserve the first channel of the first SDAM for all immediate reads and use the remaining channels across all SDAMs for ADC_TM monitoring functionality. Signed-off-by: Jishnu Prakash --- drivers/iio/adc/Kconfig | 25 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/qcom-spmi-adc5-gen3.c | 1193 +++++++++++++++++++++++++ 3 files changed, 1219 insertions(+) create mode 100644 drivers/iio/adc/qcom-spmi-adc5-gen3.c diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index dc14bde31ac1..bd9d74f7b76b 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -961,6 +961,31 @@ config QCOM_SPMI_ADC5 To compile this driver as a module, choose M here: the module will be called qcom-spmi-adc5. +config QCOM_SPMI_ADC5_GEN3 + tristate "Qualcomm Technologies Inc. SPMI PMIC5 GEN3 ADC" + depends on SPMI && THERMAL + select REGMAP_SPMI + select QCOM_VADC_COMMON + help + This is the IIO Voltage PMIC5 Gen3 ADC driver for Qualcomm Technologies Inc. PMICs. + + The driver supports reading multiple channels. The ADC is a 16-bit + sigma-delta ADC. The hardware supports calibrated results for + conversion requests and clients include reading voltage phone + power, on board system thermistors connected to the PMIC ADC, + PMIC die temperature, charger temperature, battery current, USB voltage + input and voltage signals connected to supported PMIC GPIO pins. The + hardware supports internal pull-up for thermistors and can choose between + a 30k, 100k or 400k ohm pull up using the ADC channels. + + In addition, the same driver supports ADC thermal monitoring devices too. + They appear as thermal zones with multiple trip points. A thermal client sets + threshold temperature for both warm and cool trips and gets updated when a + threshold is reached. + + To compile this driver as a module, choose M here: the module will + be called qcom-spmi-adc5-gen3. + config RCAR_GYRO_ADC tristate "Renesas R-Car GyroADC driver" depends on ARCH_RCAR_GEN2 || COMPILE_TEST diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index eb6e891790fb..5e88b205bf85 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -83,6 +83,7 @@ obj-$(CONFIG_NAU7802) += nau7802.o obj-$(CONFIG_NPCM_ADC) += npcm_adc.o obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o obj-$(CONFIG_QCOM_SPMI_ADC5) += qcom-spmi-adc5.o +obj-$(CONFIG_QCOM_SPMI_ADC5_GEN3) += qcom-spmi-adc5-gen3.o obj-$(CONFIG_QCOM_SPMI_IADC) += qcom-spmi-iadc.o obj-$(CONFIG_QCOM_SPMI_RRADC) += qcom-spmi-rradc.o obj-$(CONFIG_QCOM_VADC_COMMON) += qcom-vadc-common.o diff --git a/drivers/iio/adc/qcom-spmi-adc5-gen3.c b/drivers/iio/adc/qcom-spmi-adc5-gen3.c new file mode 100644 index 000000000000..fe5515ee8451 --- /dev/null +++ b/drivers/iio/adc/qcom-spmi-adc5-gen3.c @@ -0,0 +1,1193 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define ADC5_GEN3_HS 0x45 +#define ADC5_GEN3_HS_BUSY BIT(7) +#define ADC5_GEN3_HS_READY BIT(0) + +#define ADC5_GEN3_STATUS1 0x46 +#define ADC5_GEN3_STATUS1_CONV_FAULT BIT(7) +#define ADC5_GEN3_STATUS1_THR_CROSS BIT(6) +#define ADC5_GEN3_STATUS1_EOC BIT(0) + +#define ADC5_GEN3_TM_EN_STS 0x47 +#define ADC5_GEN3_TM_HIGH_STS 0x48 +#define ADC5_GEN3_TM_LOW_STS 0x49 + +#define ADC5_GEN3_EOC_STS 0x4a +#define ADC5_GEN3_EOC_CHAN_0 BIT(0) + +#define ADC5_GEN3_EOC_CLR 0x4b +#define ADC5_GEN3_TM_HIGH_STS_CLR 0x4c +#define ADC5_GEN3_TM_LOW_STS_CLR 0x4d +#define ADC5_GEN3_CONV_ERR_CLR 0x4e +#define ADC5_GEN3_CONV_ERR_CLR_REQ BIT(0) + +#define ADC5_GEN3_SID 0x4f +#define ADC5_GEN3_SID_MASK GENMASK(3, 0) + +#define ADC5_GEN3_PERPH_CH 0x50 +#define ADC5_GEN3_CHAN_CONV_REQ BIT(7) + +#define ADC5_GEN3_TIMER_SEL 0x51 +#define ADC5_GEN3_TIME_IMMEDIATE 0x1 + +#define ADC5_GEN3_DIG_PARAM 0x52 +#define ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK GENMASK(5, 4) +#define ADC5_GEN3_DIG_PARAM_CAL_SEL_SHIFT 4 +#define ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK GENMASK(3, 2) +#define ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_SHIFT 2 + +#define ADC5_GEN3_FAST_AVG 0x53 +#define ADC5_GEN3_FAST_AVG_CTL_EN BIT(7) +#define ADC5_GEN3_FAST_AVG_CTL_SAMPLES_MASK GENMASK(2, 0) + +#define ADC5_GEN3_ADC_CH_SEL_CTL 0x54 +#define ADC5_GEN3_DELAY_CTL 0x55 +#define ADC5_GEN3_HW_SETTLE_DELAY_MASK 0xf + +#define ADC5_GEN3_CH_EN 0x56 +#define ADC5_GEN3_HIGH_THR_INT_EN BIT(1) +#define ADC5_GEN3_LOW_THR_INT_EN BIT(0) + +#define ADC5_GEN3_LOW_THR0 0x57 +#define ADC5_GEN3_LOW_THR1 0x58 +#define ADC5_GEN3_HIGH_THR0 0x59 +#define ADC5_GEN3_HIGH_THR1 0x5a + +#define ADC5_GEN3_CH_DATA0(channel) (0x5c + (channel) * 2) +#define ADC5_GEN3_CH_DATA1(channel) (0x5d + (channel) * 2) + +#define ADC5_GEN3_CONV_REQ 0xe5 +#define ADC5_GEN3_CONV_REQ_REQ BIT(0) + +#define ADC5_GEN3_SID_OFFSET 0x8 +#define ADC5_GEN3_CHANNEL_MASK GENMASK(7, 0) +#define V_CHAN(x) (((x).sid << ADC5_GEN3_SID_OFFSET) | (x).channel) + +enum adc5_cal_method { + ADC5_NO_CAL = 0, + ADC5_RATIOMETRIC_CAL, + ADC5_ABSOLUTE_CAL +}; + +enum adc_time_select { + MEAS_INT_DISABLE = 0, + MEAS_INT_IMMEDIATE, + MEAS_INT_50MS, + MEAS_INT_100MS, + MEAS_INT_1S, + MEAS_INT_NONE, +}; + +struct adc5_sdam_data { + u16 base_addr; + const char *irq_name; + int irq; +}; + +/** + * struct adc5_channel_prop - ADC channel property. + * @channel: channel number, refer to the channel list. + * @cal_method: calibration method. + * @decimation: sampling rate supported for the channel. + * @sid: slave id of PMIC owning the channel. + * @prescale: channel scaling performed on the input signal. + * @hw_settle_time: the time between AMUX being configured and the + * start of conversion. + * @avg_samples: ability to provide single result from the ADC + * that is an average of multiple measurements. + * @sdam_index: Index for which SDAM this channel is on. + * @scale_fn_type: Represents the scaling function to convert voltage + * physical units desired by the client for the channel. + * @datasheet_name: Channel name used in device tree. + * @chip: pointer to top-level ADC device structure. + * @adc_tm: indicates if the channel is used for TM measurements. + * @tm_chan_index: TM channel number used (ranging from 1-7). + * @timer: time period of recurring TM measurement. + * @tzd: pointer to thermal device corresponding to TM channel. + * @high_thr_en: TM high threshold crossing detection enabled. + * @low_thr_en: TM low threshold crossing detection enabled. + * @last_temp: last temperature that caused threshold violation, + * or a thermal TM channel. + * @last_temp_set: indicates if last_temp is stored. + */ +struct adc5_channel_prop { + unsigned int channel; + enum adc5_cal_method cal_method; + unsigned int decimation; + unsigned int sid; + unsigned int prescale; + unsigned int hw_settle_time; + unsigned int avg_samples; + unsigned int sdam_index; + + enum vadc_scale_fn_type scale_fn_type; + const char *datasheet_name; + + struct adc5_chip *chip; + /* TM properties */ + bool adc_tm; + unsigned int tm_chan_index; + unsigned int timer; + struct thermal_zone_device *tzd; + bool high_thr_en; + bool low_thr_en; + int last_temp; + bool last_temp_set; +}; + +/** + * struct adc5_chip - ADC private structure. + * @regmap: SPMI ADC5 Gen3 peripheral register map field. + * @dev: SPMI ADC5 Gen3 device. + * @base: pointer to array of ADC peripheral base and interrupt. + * @num_sdams: number of SDAMs being used. + * @nchannels: number of ADC channels. + * @chan_props: array of ADC channel properties. + * @iio_chans: array of IIO channels specification. + * @complete: ADC result notification after interrupt is received. + * @lock: ADC lock for access to the peripheral. + * @data: software configuration data. + * @n_tm_channels: number of ADC channels used for TM measurements. + * @tm_handler_work: scheduled work for handling TM threshold violation. + */ +struct adc5_chip { + struct regmap *regmap; + struct device *dev; + struct adc5_sdam_data *base; + unsigned int num_sdams; + unsigned int nchannels; + struct adc5_channel_prop *chan_props; + struct iio_chan_spec *iio_chans; + struct completion complete; + struct mutex lock; + const struct adc5_data *data; + /* TM properties */ + unsigned int n_tm_channels; + struct work_struct tm_handler_work; +}; + +static int adc5_gen3_read(struct adc5_chip *adc, unsigned int sdam_index, u16 offset, u8 *data, int len) +{ + return regmap_bulk_read(adc->regmap, adc->base[sdam_index].base_addr + offset, data, len); +} + +static int adc5_gen3_write(struct adc5_chip *adc, unsigned int sdam_index, u16 offset, u8 *data, int len) +{ + return regmap_bulk_write(adc->regmap, adc->base[sdam_index].base_addr + offset, data, len); +} + +static int adc5_gen3_read_voltage_data(struct adc5_chip *adc, u16 *data, u8 sdam_index) +{ + int ret; + u8 rslt[2]; + + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_CH_DATA0(0), rslt, 2); + if (ret) + return ret; + + *data = (rslt[1] << 8) | rslt[0]; + + if (*data == ADC5_USR_DATA_CHECK) { + dev_err(adc->dev, "Invalid data:%#x\n", *data); + return -EINVAL; + } + + dev_dbg(adc->dev, "voltage raw code:%#x\n", *data); + + return 0; +} + +static void adc5_gen3_update_dig_param(struct adc5_chip *adc, + struct adc5_channel_prop *prop, u8 *data) +{ + /* Update calibration select */ + *data &= ~ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK; + *data |= (prop->cal_method << ADC5_GEN3_DIG_PARAM_CAL_SEL_SHIFT); + + /* Update decimation ratio select */ + *data &= ~ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK; + *data |= (prop->decimation << ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_SHIFT); +} + +static int adc5_gen3_configure(struct adc5_chip *adc, + struct adc5_channel_prop *prop) +{ + u8 sdam_index = prop->sdam_index; + u8 conv_req = 0; + u8 buf[7]; + int ret; + + /* Reserve channel 0 of first SDAM for immediate conversions */ + if (prop->adc_tm) + sdam_index = 0; + + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_SID, buf, sizeof(buf)); + if (ret) + return ret; + + /* Write SID */ + buf[0] = prop->sid & ADC5_GEN3_SID_MASK; + + /* + * Use channel 0 by default for immediate conversion and + * to indicate there is an actual conversion request + */ + buf[1] = ADC5_GEN3_CHAN_CONV_REQ | 0; + + buf[2] = ADC5_GEN3_TIME_IMMEDIATE; + + /* Digital param selection */ + adc5_gen3_update_dig_param(adc, prop, &buf[3]); + + /* Update fast average sample value */ + buf[4] &= (u8) ~ADC5_GEN3_FAST_AVG_CTL_SAMPLES_MASK; + buf[4] |= prop->avg_samples | ADC5_GEN3_FAST_AVG_CTL_EN; + + /* Select ADC channel */ + buf[5] = prop->channel; + + /* Select HW settle delay for channel */ + buf[6] &= (u8) ~ADC5_GEN3_HW_SETTLE_DELAY_MASK; + buf[6] |= prop->hw_settle_time; + + reinit_completion(&adc->complete); + + ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_SID, buf, sizeof(buf)); + if (ret) + return ret; + + conv_req = ADC5_GEN3_CONV_REQ_REQ; + return adc5_gen3_write(adc, sdam_index, ADC5_GEN3_CONV_REQ, &conv_req, 1); +} + +#define ADC5_GEN3_HS_DELAY_MIN_US 100 +#define ADC5_GEN3_HS_DELAY_MAX_US 110 +#define ADC5_GEN3_HS_RETRY_COUNT 150 + +static int adc5_gen3_poll_wait_hs(struct adc5_chip *adc, + unsigned int sdam_index) +{ + u8 conv_req = ADC5_GEN3_CONV_REQ_REQ; + u8 status = 0; + int ret, count; + + for (count = 0; count < ADC5_GEN3_HS_RETRY_COUNT; count++) { + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_HS, &status, 1); + if (ret) + return ret; + + if (status == ADC5_GEN3_HS_READY) { + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_CONV_REQ, + &conv_req, 1); + if (ret) + return ret; + + if (!conv_req) + return 0; + } + + usleep_range(ADC5_GEN3_HS_DELAY_MIN_US, + ADC5_GEN3_HS_DELAY_MAX_US); + } + + dev_err(adc->dev, "Setting HS ready bit timed out, status:%#x\n", status); + return -ETIMEDOUT; +} + +#define ADC5_GEN3_CONV_TIMEOUT_MS 501 + +static int adc5_gen3_do_conversion(struct adc5_chip *adc, + struct adc5_channel_prop *prop, + u16 *data_volt) +{ + u8 val, sdam_index = prop->sdam_index; + unsigned long rc; + int ret; + + /* Reserve channel 0 of first SDAM for immediate conversions */ + if (prop->adc_tm) + sdam_index = 0; + + mutex_lock(&adc->lock); + ret = adc5_gen3_poll_wait_hs(adc, 0); + if (ret) + goto unlock; + + ret = adc5_gen3_configure(adc, prop); + if (ret) { + dev_err(adc->dev, "ADC configure failed with %d\n", ret); + goto unlock; + } + + /* No support for polling mode at present*/ + rc = wait_for_completion_timeout(&adc->complete, + msecs_to_jiffies(ADC5_GEN3_CONV_TIMEOUT_MS)); + if (!rc) { + dev_err(adc->dev, "Reading ADC channel %s timed out\n", + prop->datasheet_name); + ret = -ETIMEDOUT; + goto unlock; + } + + ret = adc5_gen3_read_voltage_data(adc, data_volt, sdam_index); + if (ret) + goto unlock; + + val = BIT(0); + ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_EOC_CLR, &val, 1); + if (ret) + goto unlock; + + /* To indicate conversion request is only to clear a status */ + val = 0; + ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_PERPH_CH, &val, 1); + if (ret) + goto unlock; + + val = ADC5_GEN3_CONV_REQ_REQ; + ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_CONV_REQ, &val, 1); + +unlock: + mutex_unlock(&adc->lock); + + return ret; +} + +static int get_sdam_from_irq(struct adc5_chip *adc, int irq) +{ + int i; + + for (i = 0; i < adc->num_sdams; i++) { + if (adc->base[i].irq == irq) + return i; + } + return -ENOENT; +} + +static irqreturn_t adc5_gen3_isr(int irq, void *dev_id) +{ + struct adc5_chip *adc = dev_id; + u8 status, tm_status[2], eoc_status, val; + int ret, sdam_num; + + sdam_num = get_sdam_from_irq(adc, irq); + if (sdam_num < 0) { + dev_err(adc->dev, "adc irq %d not associated with an sdam\n", irq); + goto handler_end; + } + + ret = adc5_gen3_read(adc, sdam_num, ADC5_GEN3_EOC_STS, &eoc_status, 1); + if (ret) { + dev_err(adc->dev, "adc read eoc status failed with %d\n", ret); + goto handler_end; + } + + /* CHAN0 is the preconfigured channel for immediate conversion */ + if (eoc_status & ADC5_GEN3_EOC_CHAN_0) + complete(&adc->complete); + + ret = adc5_gen3_read(adc, sdam_num, ADC5_GEN3_TM_HIGH_STS, tm_status, 2); + if (ret) { + dev_err(adc->dev, "adc read TM status failed with %d\n", ret); + goto handler_end; + } + + if (tm_status[0] || tm_status[1]) + schedule_work(&adc->tm_handler_work); + + ret = adc5_gen3_read(adc, sdam_num, ADC5_GEN3_STATUS1, &status, 1); + if (ret) { + dev_err(adc->dev, "adc read status1 failed with %d\n", ret); + goto handler_end; + } + + dev_dbg(adc->dev, "Interrupt status:%#x, EOC status:%#x, high:%#x, low:%#x\n", + status, eoc_status, tm_status[0], tm_status[1]); + + if (status & ADC5_GEN3_STATUS1_CONV_FAULT) { + dev_err_ratelimited(adc->dev, "Unexpected conversion fault, status:%#x, eoc_status:%#x\n", + status, eoc_status); + val = ADC5_GEN3_CONV_ERR_CLR_REQ; + ret = adc5_gen3_write(adc, sdam_num, ADC5_GEN3_CONV_ERR_CLR, &val, 1); + if (ret < 0) + goto handler_end; + + /* To indicate conversion request is only to clear a status */ + val = 0; + ret = adc5_gen3_write(adc, sdam_num, ADC5_GEN3_PERPH_CH, &val, 1); + if (ret < 0) + goto handler_end; + + val = ADC5_GEN3_CONV_REQ_REQ; + ret = adc5_gen3_write(adc, sdam_num, ADC5_GEN3_CONV_REQ, &val, 1); + if (ret < 0) + goto handler_end; + } + + return IRQ_HANDLED; + +handler_end: + return IRQ_NONE; +} + +static void tm_handler_work(struct work_struct *work) +{ + struct adc5_chip *adc = container_of(work, struct adc5_chip, tm_handler_work); + struct adc5_channel_prop *chan_prop; + u8 tm_status[2] = {0}; + u8 buf[16] = {0}; + u8 val; + int ret, i, sdam_index = -1; + + for (i = 0; i < adc->nchannels; i++) { + bool upper_set = false, lower_set = false; + int temp, offset; + u8 data_low = 0, data_high = 0; + u16 code = 0; + + chan_prop = &adc->chan_props[i]; + offset = chan_prop->tm_chan_index; + + if (!chan_prop->adc_tm) + continue; + + mutex_lock(&adc->lock); + if (chan_prop->sdam_index != sdam_index) { + sdam_index = chan_prop->sdam_index; + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_TM_HIGH_STS, tm_status, 2); + if (ret) { + dev_err(adc->dev, "adc read TM status failed with %d\n", ret); + goto out; + } + + ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_TM_HIGH_STS_CLR, tm_status, 2); + if (ret) { + dev_err(adc->dev, "adc write TM status failed with %d\n", ret); + goto out; + } + + /* To indicate conversion request is only to clear a status */ + val = 0; + ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_PERPH_CH, &val, 1); + if (ret) { + dev_err(adc->dev, "adc write status clear conv_req failed with %d\n", ret); + goto out; + } + + val = ADC5_GEN3_CONV_REQ_REQ; + ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_CONV_REQ, &val, 1); + if (ret) { + dev_err(adc->dev, "adc write conv_req failed with %d\n", ret); + goto out; + } + + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_CH_DATA0(0), buf, sizeof(buf)); + if (ret < 0) { + dev_err(adc->dev, "adc read data failed with %d\n", ret); + goto out; + } + } + + if ((tm_status[0] & BIT(offset)) && (chan_prop->high_thr_en)) + upper_set = true; + + if ((tm_status[1] & BIT(offset)) && (chan_prop->low_thr_en)) + lower_set = true; + + mutex_unlock(&adc->lock); + + if (!(upper_set || lower_set)) + continue; + + data_low = buf[2 * offset]; + data_high = buf[2 * offset + 1]; + code = ((data_high << 8) | data_low); + pr_debug("ADC_TM threshold code:%#x\n", code); + + ret = qcom_adc5_hw_scale(chan_prop->scale_fn_type, + chan_prop->prescale, adc->data, code, &temp); + if (ret) { + dev_err(adc->dev, "Invalid temperature reading, ret=%d, code=%#x\n", + ret, code); + continue; + } + + chan_prop->last_temp = temp; + chan_prop->last_temp_set = true; + thermal_zone_device_update(chan_prop->tzd, THERMAL_TRIP_VIOLATED); + } + + return; + +out: + mutex_unlock(&adc->lock); +} + +static int adc5_gen3_fwnode_xlate(struct iio_dev *indio_dev, + const struct fwnode_reference_args *iiospec) +{ + struct adc5_chip *adc = iio_priv(indio_dev); + int i, v_channel; + + for (i = 0; i < adc->nchannels; i++) { + v_channel = V_CHAN(adc->chan_props[i]); + if (v_channel == iiospec->args[0]) + return i; + } + + return -ENOENT; +} + +static int adc5_gen3_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val, int *val2, + long mask) +{ + struct adc5_chip *adc = iio_priv(indio_dev); + struct adc5_channel_prop *prop; + u16 adc_code_volt; + int ret; + + prop = &adc->chan_props[chan->address]; + + switch (mask) { + case IIO_CHAN_INFO_PROCESSED: + ret = adc5_gen3_do_conversion(adc, prop, + &adc_code_volt); + if (ret) + return ret; + + ret = qcom_adc5_hw_scale(prop->scale_fn_type, + prop->prescale, adc->data, + adc_code_volt, val); + if (ret) + return ret; + + return IIO_VAL_INT; + case IIO_CHAN_INFO_RAW: + ret = adc5_gen3_do_conversion(adc, prop, + &adc_code_volt); + if (ret) + return ret; + *val = (int)adc_code_volt; + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +static const struct iio_info adc5_gen3_info = { + .read_raw = adc5_gen3_read_raw, + .fwnode_xlate = adc5_gen3_fwnode_xlate, +}; + +int adc_tm_gen3_get_temp(struct thermal_zone_device *tz, int *temp) +{ + struct adc5_channel_prop *prop = tz->devdata; + struct adc5_chip *adc; + u16 adc_code_volt; + int ret; + + if (!prop || !prop->chip) + return -EINVAL; + + adc = prop->chip; + + if (prop->last_temp_set) { + pr_debug("last_temp: %d\n", prop->last_temp); + prop->last_temp_set = false; + *temp = prop->last_temp; + return 0; + } + + ret = adc5_gen3_do_conversion(adc, prop, &adc_code_volt); + if (ret < 0) + return ret; + + return qcom_adc5_hw_scale(prop->scale_fn_type, + prop->prescale, adc->data, + adc_code_volt, temp); +} + +static int adc_tm5_gen3_disable_channel(struct adc5_channel_prop *prop) +{ + struct adc5_chip *adc = prop->chip; + int ret; + u8 val; + + prop->high_thr_en = false; + prop->low_thr_en = false; + + val = MEAS_INT_DISABLE; + ret = adc5_gen3_write(adc, prop->sdam_index, ADC5_GEN3_TIMER_SEL, &val, 1); + if (ret) + return ret; + + /* To indicate there is an actual conversion request */ + val = ADC5_GEN3_CHAN_CONV_REQ | prop->tm_chan_index; + ret = adc5_gen3_write(adc, prop->sdam_index, ADC5_GEN3_PERPH_CH, &val, 1); + if (ret) + return ret; + + val = ADC5_GEN3_CONV_REQ_REQ; + return adc5_gen3_write(adc, prop->sdam_index, ADC5_GEN3_CONV_REQ, &val, 1); +} + +static int adc_tm5_gen3_configure(struct adc5_channel_prop *prop, + int low_temp, int high_temp) +{ + struct adc5_chip *adc = prop->chip; + u8 conv_req = 0, buf[12]; + u16 adc_code; + int ret; + + ret = adc5_gen3_poll_wait_hs(adc, prop->sdam_index); + if (ret < 0) + return ret; + + ret = adc5_gen3_read(adc, prop->sdam_index, ADC5_GEN3_SID, buf, sizeof(buf)); + if (ret < 0) + return ret; + + /* Write SID */ + buf[0] = prop->sid & ADC5_GEN3_SID_MASK; + + /* + * Select TM channel and indicate there is an actual + * conversion request + */ + buf[1] = ADC5_GEN3_CHAN_CONV_REQ | prop->tm_chan_index; + + buf[2] = prop->timer; + + /* Digital param selection */ + adc5_gen3_update_dig_param(adc, prop, &buf[3]); + + /* Update fast average sample value */ + buf[4] &= (u8) ~ADC5_GEN3_FAST_AVG_CTL_SAMPLES_MASK; + buf[4] |= prop->avg_samples | ADC5_GEN3_FAST_AVG_CTL_EN; + + /* Select ADC channel */ + buf[5] = prop->channel; + + /* Select HW settle delay for channel */ + buf[6] &= (u8) ~ADC5_GEN3_HW_SETTLE_DELAY_MASK; + buf[6] |= prop->hw_settle_time; + + /* High temperature corresponds to low voltage threshold */ + if (high_temp != INT_MAX) { + prop->low_thr_en = true; + adc_code = qcom_adc_tm5_gen2_temp_res_scale(high_temp); + put_unaligned_le16(adc_code, &buf[8]); + } else { + prop->low_thr_en = false; + } + + /* Low temperature corresponds to high voltage threshold */ + if (low_temp != -INT_MAX) { + prop->high_thr_en = true; + adc_code = qcom_adc_tm5_gen2_temp_res_scale(low_temp); + put_unaligned_le16(adc_code, &buf[10]); + } else { + prop->high_thr_en = false; + } + + buf[7] = 0; + if (prop->high_thr_en) + buf[7] |= ADC5_GEN3_HIGH_THR_INT_EN; + if (prop->low_thr_en) + buf[7] |= ADC5_GEN3_LOW_THR_INT_EN; + + ret = adc5_gen3_write(adc, prop->sdam_index, ADC5_GEN3_SID, buf, sizeof(buf)); + if (ret < 0) + return ret; + + conv_req = ADC5_GEN3_CONV_REQ_REQ; + return adc5_gen3_write(adc, prop->sdam_index, ADC5_GEN3_CONV_REQ, &conv_req, 1); +} + +static int adc_tm5_gen3_set_trip_temp(struct thermal_zone_device *tz, + int low_temp, int high_temp) +{ + struct adc5_channel_prop *prop = tz->devdata; + struct adc5_chip *adc; + int ret; + + if (!prop || !prop->chip) + return -EINVAL; + + adc = prop->chip; + + dev_dbg(adc->dev, "channel:%s, low_temp(mdegC):%d, high_temp(mdegC):%d\n", + prop->datasheet_name, low_temp, high_temp); + + mutex_lock(&adc->lock); + if (high_temp == INT_MAX && low_temp <= -INT_MAX) + ret = adc_tm5_gen3_disable_channel(prop); + else + ret = adc_tm5_gen3_configure(prop, low_temp, high_temp); + mutex_unlock(&adc->lock); + + return ret; +} + +static const struct thermal_zone_device_ops adc_tm_ops = { + .get_temp = adc_tm_gen3_get_temp, + .set_trips = adc_tm5_gen3_set_trip_temp, +}; + +static int adc_tm_register_tzd(struct adc5_chip *adc) +{ + unsigned int i, channel; + struct thermal_zone_device *tzd; + + for (i = 0; i < adc->nchannels; i++) { + channel = V_CHAN(adc->chan_props[i]); + + if (!adc->chan_props[i].adc_tm) + continue; + tzd = devm_thermal_of_zone_register( + adc->dev, channel, + &adc->chan_props[i], &adc_tm_ops); + + if (IS_ERR(tzd)) { + if (PTR_ERR(tzd) == -ENODEV) { + dev_warn(adc->dev, "thermal sensor on channel %d is not used\n", + channel); + continue; + } + + dev_err(adc->dev, "Error registering TZ zone:%ld for channel:%d\n", + PTR_ERR(tzd), adc->chan_props[i].channel); + return PTR_ERR(tzd); + } + adc->chan_props[i].tzd = tzd; + } + + return 0; +} + +struct adc5_channels { + const char *datasheet_name; + unsigned int prescale_index; + enum iio_chan_type type; + long info_mask; + enum vadc_scale_fn_type scale_fn_type; +}; + +/* In these definitions, _pre refers to an index into adc5_prescale_ratios. */ +#define ADC5_CHAN(_dname, _type, _mask, _pre, _scale) \ + { \ + .datasheet_name = _dname, \ + .prescale_index = _pre, \ + .type = _type, \ + .info_mask = _mask, \ + .scale_fn_type = _scale, \ + }, \ + +#define ADC5_CHAN_TEMP(_dname, _pre, _scale) \ + ADC5_CHAN(_dname, IIO_TEMP, \ + BIT(IIO_CHAN_INFO_PROCESSED), \ + _pre, _scale) \ + +#define ADC5_CHAN_VOLT(_dname, _pre, _scale) \ + ADC5_CHAN(_dname, IIO_VOLTAGE, \ + BIT(IIO_CHAN_INFO_PROCESSED), \ + _pre, _scale) \ + +#define ADC5_CHAN_CUR(_dname, _pre, _scale) \ + ADC5_CHAN(_dname, IIO_CURRENT, \ + BIT(IIO_CHAN_INFO_PROCESSED), \ + _pre, _scale) \ + +static const struct adc5_channels adc5_gen3_chans_pmic[ADC5_MAX_CHANNEL] = { + [ADC5_GEN3_OFFSET_REF] = ADC5_CHAN_VOLT("ref_gnd", 0, + SCALE_HW_CALIB_DEFAULT) + [ADC5_GEN3_1P25VREF] = ADC5_CHAN_VOLT("vref_1p25", 0, + SCALE_HW_CALIB_DEFAULT) + [ADC5_GEN3_VPH_PWR] = ADC5_CHAN_VOLT("vph_pwr", 1, + SCALE_HW_CALIB_DEFAULT) + [ADC5_GEN3_VBAT_SNS_QBG] = ADC5_CHAN_VOLT("vbat_sns", 1, + SCALE_HW_CALIB_DEFAULT) + [ADC5_GEN3_USB_SNS_V_16] = ADC5_CHAN_TEMP("usb_sns_v_div_16", 8, + SCALE_HW_CALIB_DEFAULT) + [ADC5_GEN3_VIN_DIV16_MUX] = ADC5_CHAN_TEMP("vin_div_16", 8, + SCALE_HW_CALIB_DEFAULT) + [ADC5_GEN3_DIE_TEMP] = ADC5_CHAN_TEMP("die_temp", 0, + SCALE_HW_CALIB_PMIC_THERM_PM5_GEN2) + [ADC5_GEN3_TEMP_ALARM_LITE] = ADC5_CHAN_TEMP("die_temp_lite", 0, + SCALE_HW_CALIB_PMIC_THERM_PM5_GEN2) + [ADC5_GEN3_AMUX1_THM_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_pu2", 0, + SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2) + [ADC5_GEN3_AMUX2_THM_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_pu2", 0, + SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2) + [ADC5_GEN3_AMUX3_THM_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_pu2", 0, + SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2) + [ADC5_GEN3_AMUX4_THM_100K_PU] = ADC5_CHAN_TEMP("amux_thm4_pu2", 0, + SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2) + [ADC5_GEN3_AMUX5_THM_100K_PU] = ADC5_CHAN_TEMP("amux_thm5_pu2", 0, + SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2) + [ADC5_GEN3_AMUX6_THM_100K_PU] = ADC5_CHAN_TEMP("amux_thm6_pu2", 0, + SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2) + [ADC5_GEN3_AMUX1_GPIO_100K_PU] = ADC5_CHAN_TEMP("amux1_gpio_pu2", 0, + SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2) + [ADC5_GEN3_AMUX2_GPIO_100K_PU] = ADC5_CHAN_TEMP("amux2_gpio_pu2", 0, + SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2) + [ADC5_GEN3_AMUX3_GPIO_100K_PU] = ADC5_CHAN_TEMP("amux3_gpio_pu2", 0, + SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2) + [ADC5_GEN3_AMUX4_GPIO_100K_PU] = ADC5_CHAN_TEMP("amux4_gpio_pu2", 0, + SCALE_HW_CALIB_THERM_100K_PU_PM5_GEN2) +}; + +static int adc5_gen3_get_fw_channel_data(struct adc5_chip *adc, + struct adc5_channel_prop *prop, + struct fwnode_handle *fwnode, + const struct adc5_data *data) +{ + const char *name = fwnode_get_name(fwnode), *channel_name; + struct device *dev = adc->dev; + u32 chan, value, varr[2], sid = 0; + int ret, val; + + ret = fwnode_property_read_u32(fwnode, "reg", &chan); + if (ret < 0) { + dev_err(dev, "invalid channel number %s\n", name); + return ret; + } + + /* + * Value read from "reg" is virtual channel number + * virtual channel number = sid << 8 | channel number + */ + + sid = (chan >> ADC5_GEN3_SID_OFFSET); + chan = (chan & ADC5_GEN3_CHANNEL_MASK); + + if (chan > ADC5_GEN3_OFFSET_EXT2 || + !data->adc_chans[chan].datasheet_name) { + dev_err(dev, "%s invalid channel number %d\n", name, chan); + return -EINVAL; + } + + prop->channel = chan; + prop->sid = sid; + + ret = fwnode_property_read_string(fwnode, "label", &channel_name); + if (ret) + channel_name = name; + prop->datasheet_name = channel_name; + + prop->decimation = ADC5_DECIMATION_DEFAULT; + ret = fwnode_property_read_u32(fwnode, "qcom,decimation", &value); + if (!ret) { + ret = qcom_adc5_decimation_from_dt(value, data->decimation); + if (ret < 0) { + dev_err(dev, "%#x invalid decimation %d\n", + chan, value); + return ret; + } + prop->decimation = ret; + } + + prop->prescale = adc->data->adc_chans[prop->channel].prescale_index; + ret = fwnode_property_read_u32_array(fwnode, "qcom,pre-scaling", varr, 2); + if (!ret) { + ret = qcom_adc5_prescaling_from_dt(varr[0], varr[1]); + if (ret < 0) { + dev_err(dev, "%#x invalid pre-scaling <%d %d>\n", + chan, varr[0], varr[1]); + return ret; + } + prop->prescale = ret; + } + + prop->hw_settle_time = VADC_DEF_HW_SETTLE_TIME; + ret = fwnode_property_read_u32(fwnode, "qcom,hw-settle-time", &value); + if (!ret) { + ret = qcom_adc5_hw_settle_time_from_dt(value, + data->hw_settle_1); + if (ret < 0) { + dev_err(dev, "%#x invalid hw-settle-time %d us\n", + chan, value); + return ret; + } + prop->hw_settle_time = ret; + } + + prop->avg_samples = VADC_DEF_AVG_SAMPLES; + ret = fwnode_property_read_u32(fwnode, "qcom,avg-samples", &value); + if (!ret) { + ret = qcom_adc5_avg_samples_from_dt(value); + if (ret < 0) { + dev_err(dev, "%#x invalid avg-samples %d\n", + chan, value); + return ret; + } + prop->avg_samples = ret; + } + + if (fwnode_property_read_bool(fwnode, "qcom,ratiometric")) + prop->cal_method = ADC5_RATIOMETRIC_CAL; + else + prop->cal_method = ADC5_ABSOLUTE_CAL; + + prop->timer = MEAS_INT_IMMEDIATE; + + prop->adc_tm = fwnode_property_read_bool(fwnode, "qcom,adc-tm-type"); + + if (prop->adc_tm) { + adc->n_tm_channels++; + if (adc->n_tm_channels > ((adc->num_sdams * 8) - 1)) { + dev_err(adc->dev, "Number of TM nodes %u greater than channels supported:%u\n", + adc->n_tm_channels, (adc->num_sdams * 8) - 1); + return -EINVAL; + } + + val = adc->n_tm_channels / 8; + prop->sdam_index = val; + prop->tm_chan_index = adc->n_tm_channels - (8*val); + + prop->timer = MEAS_INT_1S; + } + + return 0; +} + +static const struct adc5_data adc5_gen3_data_pmic = { + .full_scale_code_volt = 0x70e4, + .adc_chans = adc5_gen3_chans_pmic, + .info = &adc5_gen3_info, + .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX]) + {85, 340, 1360}, + .hw_settle_1 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX]) + {15, 100, 200, 300, 400, 500, 600, 700, + 1000, 2000, 4000, 8000, 16000, 32000, + 64000, 128000}, +}; + +static const struct of_device_id adc5_match_table[] = { + { + .compatible = "qcom,spmi-adc5-gen3", + .data = &adc5_gen3_data_pmic, + }, + { } +}; +MODULE_DEVICE_TABLE(of, adc5_match_table); + +static int adc5_get_fw_data(struct adc5_chip *adc) +{ + const struct adc5_channels *adc_chan; + struct iio_chan_spec *iio_chan; + struct adc5_channel_prop *chan_props; + struct fwnode_handle *child; + unsigned int index = 0; + int ret; + + adc->nchannels = device_get_child_node_count(adc->dev); + if (!adc->nchannels) + return -EINVAL; + + adc->iio_chans = devm_kcalloc(adc->dev, adc->nchannels, + sizeof(*adc->iio_chans), GFP_KERNEL); + if (!adc->iio_chans) + return -ENOMEM; + + adc->chan_props = devm_kcalloc(adc->dev, adc->nchannels, + sizeof(*adc->chan_props), GFP_KERNEL); + if (!adc->chan_props) + return -ENOMEM; + + chan_props = adc->chan_props; + adc->n_tm_channels = 0; + iio_chan = adc->iio_chans; + adc->data = device_get_match_data(adc->dev); + if (!adc->data) + adc->data = &adc5_gen3_data_pmic; + + device_for_each_child_node(adc->dev, child) { + ret = adc5_gen3_get_fw_channel_data(adc, chan_props, child, adc->data); + if (ret < 0) { + fwnode_handle_put(child); + return ret; + } + + chan_props->chip = adc; + chan_props->scale_fn_type = + adc->data->adc_chans[chan_props->channel].scale_fn_type; + adc_chan = &adc->data->adc_chans[chan_props->channel]; + + iio_chan->channel = chan_props->channel; + iio_chan->datasheet_name = chan_props->datasheet_name; + iio_chan->extend_name = chan_props->datasheet_name; + iio_chan->info_mask_separate = adc_chan->info_mask; + iio_chan->type = adc_chan->type; + iio_chan->address = index; + iio_chan++; + chan_props++; + index++; + } + + return 0; +} + +static int adc5_gen3_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct iio_dev *indio_dev; + struct adc5_chip *adc; + struct regmap *regmap; + int ret, i, irq; + u32 *reg; + char buf[20]; + + regmap = dev_get_regmap(dev->parent, NULL); + if (!regmap) + return -ENODEV; + + indio_dev = devm_iio_device_alloc(dev, sizeof(*adc)); + if (!indio_dev) + return -ENOMEM; + + adc = iio_priv(indio_dev); + adc->regmap = regmap; + adc->dev = dev; + + ret = device_property_count_u32(dev, "reg"); + if (ret < 0) + return ret; + + adc->num_sdams = ret; + + reg = devm_kcalloc(dev, adc->num_sdams, sizeof(u32), GFP_KERNEL); + if (!reg) + return -ENOMEM; + + ret = device_property_read_u32_array(dev, "reg", reg, adc->num_sdams); + if (ret) { + dev_err(adc->dev, "Failed to read reg property, ret=%d\n", ret); + return ret; + } + + adc->base = devm_kcalloc(adc->dev, adc->num_sdams, sizeof(*adc->base), GFP_KERNEL); + if (!adc->base) + return -ENOMEM; + + for (i = 0; i < adc->num_sdams; i++) { + adc->base[i].base_addr = reg[i]; + + irq = platform_get_irq(pdev, i); + if (irq < 0) { + dev_err(adc->dev, "Failed to get SDAM%d irq, ret=%d\n", i, irq); + return irq; + } + adc->base[i].irq = irq; + + scnprintf(buf, sizeof(buf), "adc-sdam%d", i); + adc->base[i].irq_name = devm_kstrdup(adc->dev, buf, GFP_KERNEL); + if (!adc->base[i].irq_name) + return -ENOMEM; + } + + platform_set_drvdata(pdev, adc); + + init_completion(&adc->complete); + mutex_init(&adc->lock); + + ret = adc5_get_fw_data(adc); + if (ret < 0) { + dev_err(adc->dev, "adc get dt data failed, ret=%d\n", ret); + return ret; + } + + for (i = 0; i < adc->num_sdams; i++) { + ret = devm_request_irq(dev, adc->base[i].irq, adc5_gen3_isr, + 0, adc->base[i].irq_name, adc); + if (ret < 0) { + dev_err(adc->dev, "Getting IRQ %d failed, ret=%d\n", adc->base[i].irq, ret); + return ret; + } + } + + ret = adc_tm_register_tzd(adc); + if (ret < 0) + return ret; + + if (adc->n_tm_channels) + INIT_WORK(&adc->tm_handler_work, tm_handler_work); + + indio_dev->name = pdev->name; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->info = &adc5_gen3_info; + indio_dev->channels = adc->iio_chans; + indio_dev->num_channels = adc->nchannels; + + return devm_iio_device_register(dev, indio_dev); +} + +static int adc5_gen3_exit(struct platform_device *pdev) +{ + struct adc5_chip *adc = platform_get_drvdata(pdev); + u8 data = 0; + int i, sdam_index; + + mutex_lock(&adc->lock); + /* Disable all available channels */ + for (i = 0; i < adc->num_sdams * 8; i++) { + sdam_index = i / 8; + data = MEAS_INT_DISABLE; + adc5_gen3_write(adc, sdam_index, ADC5_GEN3_TIMER_SEL, &data, 1); + + /* To indicate there is an actual conversion request */ + data = ADC5_GEN3_CHAN_CONV_REQ | (i - (sdam_index * 8)); + adc5_gen3_write(adc, sdam_index, ADC5_GEN3_PERPH_CH, &data, 1); + + data = ADC5_GEN3_CONV_REQ_REQ; + adc5_gen3_write(adc, sdam_index, ADC5_GEN3_CONV_REQ, &data, 1); + } + + mutex_unlock(&adc->lock); + + if (adc->n_tm_channels) + cancel_work_sync(&adc->tm_handler_work); + + return 0; +} + +static struct platform_driver adc5_gen3_driver = { + .driver = { + .name = "qcom-spmi-adc5-gen3", + .of_match_table = adc5_match_table, + }, + .probe = adc5_gen3_probe, + .remove = adc5_gen3_exit, +}; +module_platform_driver(adc5_gen3_driver); + +MODULE_ALIAS("platform:qcom-spmi-adc5-gen3"); +MODULE_DESCRIPTION("Qualcomm Technologies Inc. PMIC5 Gen3 ADC driver"); +MODULE_LICENSE("GPL"); From patchwork Sat Jul 8 07:28:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jishnu Prakash X-Patchwork-Id: 700962 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 415EDEB64DD for ; Sat, 8 Jul 2023 07:32:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232526AbjGHHcH (ORCPT ); Sat, 8 Jul 2023 03:32:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59798 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231998AbjGHHbx (ORCPT ); Sat, 8 Jul 2023 03:31:53 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E1AE72712; Sat, 8 Jul 2023 00:31:22 -0700 (PDT) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3687UY6S019596; Sat, 8 Jul 2023 07:30:55 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=A+V7/4U+AjSAkMYfHgmVKMEzzwCbaP9SwrYZJmtzqbE=; b=UKrcu5EPSU2k/d4QvH8/HrF1F7h6ahyqIXiME2AMJr13xKV/tBfUabUuQsK88TQ5hVM0 pXFzT7+nVgfDKEsQbIRAG5S+hRERQEcKZAJn7uR1HnII26T9hVlTXRx81WPNXfuCZruI VOe7gsL/6HZ5pATicQJ2jePJICax7iWoTDg1JColrpC4B/syCcMJ9jzZbt5/zTDit2wZ jS/2KueWrYZGfNtRvnmcQxvfKqw0lm5CyQdOehr88e/e1PZb1pgawqu/OgFleVx3UiXF mqFbDMwPkhHdPh4hI/8EH5XGffaD/MhrwwbPRJTcu66/ZCKt4RTy6TWQaXQXHfh4WxeH gQ== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rq0jpg5j9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 08 Jul 2023 07:30:55 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3687UsqJ025084 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 8 Jul 2023 07:30:54 GMT Received: from hu-jprakash-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Sat, 8 Jul 2023 00:30:45 -0700 From: Jishnu Prakash To: , , , , , , , , , , , , , , Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , "Rafael J. Wysocki" , "Daniel Lezcano" , Amit Kucheria , "Zhang Rui" , Jishnu Prakash , "Luca Weiss" , , , CC: Subject: [PATCH 08/11] dt-bindings: iio: adc: Copy QCOM ADC bindings files Date: Sat, 8 Jul 2023 12:58:32 +0530 Message-ID: <20230708072835.3035398-9-quic_jprakash@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230708072835.3035398-1-quic_jprakash@quicinc.com> References: <20230708072835.3035398-1-quic_jprakash@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: McxiU2aQTDoLB-qDG8hIJAejIPzCeJHb X-Proofpoint-GUID: McxiU2aQTDoLB-qDG8hIJAejIPzCeJHb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-08_04,2023-07-06_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 mlxlogscore=999 adultscore=0 lowpriorityscore=0 suspectscore=0 spamscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 clxscore=1015 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307080065 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org At present, the QCOM ADC bindings files are located in the dt-bindings/iio folder. As they are all specifically for ADC, copy them into the dt-bindings/iio/adc folder. Also update documentation to reflect the change in paths. Signed-off-by: Jishnu Prakash --- .../bindings/iio/adc/qcom,spmi-vadc.yaml | 16 +- .../bindings/thermal/qcom-spmi-adc-tm5.yaml | 6 +- .../iio/adc/qcom,spmi-adc5-gen2-pm8350.h | 64 +++ .../iio/adc/qcom,spmi-adc5-gen2-pm8350b.h | 89 ++++ .../iio/adc/qcom,spmi-adc5-gen2-pmk8350.h | 47 +++ .../iio/adc/qcom,spmi-adc5-gen2-pmr735a.h | 29 ++ .../iio/adc/qcom,spmi-adc5-gen2-pmr735b.h | 28 ++ .../iio/adc/qcom,spmi-adc5-gen3-pm8550.h | 48 +++ .../iio/adc/qcom,spmi-adc5-gen3-pm8550b.h | 97 +++++ .../iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h | 20 + .../iio/adc/qcom,spmi-adc5-gen3-pmk8550.h | 54 +++ include/dt-bindings/iio/adc/qcom,spmi-vadc.h | 379 ++++++++++++++++++ 12 files changed, 866 insertions(+), 11 deletions(-) create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pm8350.h create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pm8350b.h create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmk8350.h create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmr735a.h create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmr735b.h create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-vadc.h diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml index 090113e62d52..b6a545aae9d2 100644 --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml @@ -77,9 +77,9 @@ patternProperties: maxItems: 1 description: | ADC channel number. - See include/dt-bindings/iio/qcom,spmi-vadc.h + See include/dt-bindings/iio/adc/qcom,spmi-vadc.h For PMIC5 Gen2 and PMIC5 Gen3 ADC, the channel numbers are specified separately per - PMIC in the PMIC-specific files in include/dt-bindings/iio/. + PMIC in the PMIC-specific files in include/dt-bindings/iio/adc. label: $ref: /schemas/types.yaml#/definitions/string @@ -293,8 +293,8 @@ examples: }; - | - #include - #include + #include + #include #include spmi { @@ -325,10 +325,10 @@ examples: }; - | - #include - #include - #include - #include + #include + #include + #include + #include pmic { #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml index 019f18a2b9e7..50a5308e3c6b 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml @@ -164,7 +164,7 @@ additionalProperties: false examples: - | - #include + #include #include spmi_bus { #address-cells = <1>; @@ -203,8 +203,8 @@ examples: }; - | - #include - #include + #include + #include #include spmi_bus { #address-cells = <1>; diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pm8350.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pm8350.h new file mode 100644 index 000000000000..77259beaf6e9 --- /dev/null +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pm8350.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H + +/* ADC channels for PM8350_ADC for PMIC5 Gen2 */ +#define PM8350_ADC5_GEN2_REF_GND(sid) ((sid) << 8 | 0x0) +#define PM8350_ADC5_GEN2_1P25VREF(sid) ((sid) << 8 | 0x01) +#define PM8350_ADC5_GEN2_VREF_VADC(sid) ((sid) << 8 | 0x02) +#define PM8350_ADC5_GEN2_DIE_TEMP(sid) ((sid) << 8 | 0x03) + +#define PM8350_ADC5_GEN2_AMUX_THM1(sid) ((sid) << 8 | 0x04) +#define PM8350_ADC5_GEN2_AMUX_THM2(sid) ((sid) << 8 | 0x05) +#define PM8350_ADC5_GEN2_AMUX_THM3(sid) ((sid) << 8 | 0x06) +#define PM8350_ADC5_GEN2_AMUX_THM4(sid) ((sid) << 8 | 0x07) +#define PM8350_ADC5_GEN2_AMUX_THM5(sid) ((sid) << 8 | 0x08) +#define PM8350_ADC5_GEN2_GPIO1(sid) ((sid) << 8 | 0x0a) +#define PM8350_ADC5_GEN2_GPIO2(sid) ((sid) << 8 | 0x0b) +#define PM8350_ADC5_GEN2_GPIO3(sid) ((sid) << 8 | 0x0c) +#define PM8350_ADC5_GEN2_GPIO4(sid) ((sid) << 8 | 0x0d) + +/* 30k pull-up1 */ +#define PM8350_ADC5_GEN2_AMUX_THM1_30K_PU(sid) ((sid) << 8 | 0x24) +#define PM8350_ADC5_GEN2_AMUX_THM2_30K_PU(sid) ((sid) << 8 | 0x25) +#define PM8350_ADC5_GEN2_AMUX_THM3_30K_PU(sid) ((sid) << 8 | 0x26) +#define PM8350_ADC5_GEN2_AMUX_THM4_30K_PU(sid) ((sid) << 8 | 0x27) +#define PM8350_ADC5_GEN2_AMUX_THM5_30K_PU(sid) ((sid) << 8 | 0x28) +#define PM8350_ADC5_GEN2_GPIO1_30K_PU(sid) ((sid) << 8 | 0x2a) +#define PM8350_ADC5_GEN2_GPIO2_30K_PU(sid) ((sid) << 8 | 0x2b) +#define PM8350_ADC5_GEN2_GPIO3_30K_PU(sid) ((sid) << 8 | 0x2c) +#define PM8350_ADC5_GEN2_GPIO4_30K_PU(sid) ((sid) << 8 | 0x2d) + +/* 100k pull-up2 */ +#define PM8350_ADC5_GEN2_AMUX_THM1_100K_PU(sid) ((sid) << 8 | 0x44) +#define PM8350_ADC5_GEN2_AMUX_THM2_100K_PU(sid) ((sid) << 8 | 0x45) +#define PM8350_ADC5_GEN2_AMUX_THM3_100K_PU(sid) ((sid) << 8 | 0x46) +#define PM8350_ADC5_GEN2_AMUX_THM4_100K_PU(sid) ((sid) << 8 | 0x47) +#define PM8350_ADC5_GEN2_AMUX_THM5_100K_PU(sid) ((sid) << 8 | 0x48) +#define PM8350_ADC5_GEN2_GPIO1_100K_PU(sid) ((sid) << 8 | 0x4a) +#define PM8350_ADC5_GEN2_GPIO2_100K_PU(sid) ((sid) << 8 | 0x4b) +#define PM8350_ADC5_GEN2_GPIO3_100K_PU(sid) ((sid) << 8 | 0x4c) +#define PM8350_ADC5_GEN2_GPIO4_100K_PU(sid) ((sid) << 8 | 0x4d) + +/* 400k pull-up3 */ +#define PM8350_ADC5_GEN2_AMUX_THM1_400K_PU(sid) ((sid) << 8 | 0x64) +#define PM8350_ADC5_GEN2_AMUX_THM2_400K_PU(sid) ((sid) << 8 | 0x65) +#define PM8350_ADC5_GEN2_AMUX_THM3_400K_PU(sid) ((sid) << 8 | 0x66) +#define PM8350_ADC5_GEN2_AMUX_THM4_400K_PU(sid) ((sid) << 8 | 0x67) +#define PM8350_ADC5_GEN2_AMUX_THM5_400K_PU(sid) ((sid) << 8 | 0x68) +#define PM8350_ADC5_GEN2_GPIO1_400K_PU(sid) ((sid) << 8 | 0x6a) +#define PM8350_ADC5_GEN2_GPIO2_400K_PU(sid) ((sid) << 8 | 0x6b) +#define PM8350_ADC5_GEN2_GPIO3_400K_PU(sid) ((sid) << 8 | 0x6c) +#define PM8350_ADC5_GEN2_GPIO4_400K_PU(sid) ((sid) << 8 | 0x6d) + +/* 1/3 Divider */ +#define PM8350_ADC5_GEN2_GPIO4_DIV3(sid) ((sid) << 8 | 0x8d) + +#define PM8350_ADC5_GEN2_VPH_PWR(sid) ((sid) << 8 | 0x8e) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H */ diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pm8350b.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pm8350b.h new file mode 100644 index 000000000000..c7bb54e0b6a6 --- /dev/null +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pm8350b.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H + +#ifndef PM8350B_SID +#define PM8350B_SID 3 +#endif + +/* ADC channels for PM8350B_ADC for PMIC5 Gen2 */ +#define PM8350B_ADC5_GEN2_REF_GND (PM8350B_SID << 8 | 0x0) +#define PM8350B_ADC5_GEN2_1P25VREF (PM8350B_SID << 8 | 0x01) +#define PM8350B_ADC5_GEN2_VREF_VADC (PM8350B_SID << 8 | 0x02) +#define PM8350B_ADC5_GEN2_DIE_TEMP (PM8350B_SID << 8 | 0x03) + +#define PM8350B_ADC5_GEN2_AMUX_THM1 (PM8350B_SID << 8 | 0x04) +#define PM8350B_ADC5_GEN2_AMUX_THM2 (PM8350B_SID << 8 | 0x05) +#define PM8350B_ADC5_GEN2_AMUX_THM3 (PM8350B_SID << 8 | 0x06) +#define PM8350B_ADC5_GEN2_AMUX_THM4 (PM8350B_SID << 8 | 0x07) +#define PM8350B_ADC5_GEN2_AMUX_THM5 (PM8350B_SID << 8 | 0x08) +#define PM8350B_ADC5_GEN2_AMUX_THM6 (PM8350B_SID << 8 | 0x09) +#define PM8350B_ADC5_GEN2_GPIO1 (PM8350B_SID << 8 | 0x0a) +#define PM8350B_ADC5_GEN2_GPIO2 (PM8350B_SID << 8 | 0x0b) +#define PM8350B_ADC5_GEN2_GPIO3 (PM8350B_SID << 8 | 0x0c) +#define PM8350B_ADC5_GEN2_GPIO4 (PM8350B_SID << 8 | 0x0d) + +#define PM8350B_ADC5_GEN2_CHG_TEMP (PM8350B_SID << 8 | 0x10) +#define PM8350B_ADC5_GEN2_USB_IN_V_16 (PM8350B_SID << 8 | 0x11) +#define PM8350B_ADC5_GEN2_VDC_16 (PM8350B_SID << 8 | 0x12) +#define PM8350B_ADC5_GEN2_CC1_ID (PM8350B_SID << 8 | 0x13) +#define PM8350B_ADC5_GEN2_VREF_BAT_THERM (PM8350B_SID << 8 | 0x15) +#define PM8350B_ADC5_GEN2_IIN_FB (PM8350B_SID << 8 | 0x17) + +/* 30k pull-up1 */ +#define PM8350B_ADC5_GEN2_AMUX_THM1_30K_PU (PM8350B_SID << 8 | 0x24) +#define PM8350B_ADC5_GEN2_AMUX_THM2_30K_PU (PM8350B_SID << 8 | 0x25) +#define PM8350B_ADC5_GEN2_AMUX_THM3_30K_PU (PM8350B_SID << 8 | 0x26) +#define PM8350B_ADC5_GEN2_AMUX_THM4_30K_PU (PM8350B_SID << 8 | 0x27) +#define PM8350B_ADC5_GEN2_AMUX_THM5_30K_PU (PM8350B_SID << 8 | 0x28) +#define PM8350B_ADC5_GEN2_AMUX_THM6_30K_PU (PM8350B_SID << 8 | 0x29) +#define PM8350B_ADC5_GEN2_GPIO1_30K_PU (PM8350B_SID << 8 | 0x2a) +#define PM8350B_ADC5_GEN2_GPIO2_30K_PU (PM8350B_SID << 8 | 0x2b) +#define PM8350B_ADC5_GEN2_GPIO3_30K_PU (PM8350B_SID << 8 | 0x2c) +#define PM8350B_ADC5_GEN2_GPIO4_30K_PU (PM8350B_SID << 8 | 0x2d) +#define PM8350B_ADC5_GEN2_CC1_ID_30K_PU (PM8350B_SID << 8 | 0x33) + +/* 100k pull-up2 */ +#define PM8350B_ADC5_GEN2_AMUX_THM1_100K_PU (PM8350B_SID << 8 | 0x44) +#define PM8350B_ADC5_GEN2_AMUX_THM2_100K_PU (PM8350B_SID << 8 | 0x45) +#define PM8350B_ADC5_GEN2_AMUX_THM3_100K_PU (PM8350B_SID << 8 | 0x46) +#define PM8350B_ADC5_GEN2_AMUX_THM4_100K_PU (PM8350B_SID << 8 | 0x47) +#define PM8350B_ADC5_GEN2_AMUX_THM5_100K_PU (PM8350B_SID << 8 | 0x48) +#define PM8350B_ADC5_GEN2_AMUX_THM6_100K_PU (PM8350B_SID << 8 | 0x49) +#define PM8350B_ADC5_GEN2_GPIO1_100K_PU (PM8350B_SID << 8 | 0x4a) +#define PM8350B_ADC5_GEN2_GPIO2_100K_PU (PM8350B_SID << 8 | 0x4b) +#define PM8350B_ADC5_GEN2_GPIO3_100K_PU (PM8350B_SID << 8 | 0x4c) +#define PM8350B_ADC5_GEN2_GPIO4_100K_PU (PM8350B_SID << 8 | 0x4d) +#define PM8350B_ADC5_GEN2_CC1_ID_100K_PU (PM8350B_SID << 8 | 0x53) + +/* 400k pull-up3 */ +#define PM8350B_ADC5_GEN2_AMUX_THM1_400K_PU (PM8350B_SID << 8 | 0x64) +#define PM8350B_ADC5_GEN2_AMUX_THM2_400K_PU (PM8350B_SID << 8 | 0x65) +#define PM8350B_ADC5_GEN2_AMUX_THM3_400K_PU (PM8350B_SID << 8 | 0x66) +#define PM8350B_ADC5_GEN2_AMUX_THM4_400K_PU (PM8350B_SID << 8 | 0x67) +#define PM8350B_ADC5_GEN2_AMUX_THM5_400K_PU (PM8350B_SID << 8 | 0x68) +#define PM8350B_ADC5_GEN2_AMUX_THM6_400K_PU (PM8350B_SID << 8 | 0x69) +#define PM8350B_ADC5_GEN2_GPIO1_400K_PU (PM8350B_SID << 8 | 0x6a) +#define PM8350B_ADC5_GEN2_GPIO2_400K_PU (PM8350B_SID << 8 | 0x6b) +#define PM8350B_ADC5_GEN2_GPIO3_400K_PU (PM8350B_SID << 8 | 0x6c) +#define PM8350B_ADC5_GEN2_GPIO4_400K_PU (PM8350B_SID << 8 | 0x6d) +#define PM8350B_ADC5_GEN2_CC1_ID_400K_PU (PM8350B_SID << 8 | 0x73) + +/* 1/3 Divider */ +#define PM8350B_ADC5_GEN2_GPIO1_DIV3 (PM8350B_SID << 8 | 0x8a) +#define PM8350B_ADC5_GEN2_GPIO2_DIV3 (PM8350B_SID << 8 | 0x8b) +#define PM8350B_ADC5_GEN2_GPIO3_DIV3 (PM8350B_SID << 8 | 0x8c) +#define PM8350B_ADC5_GEN2_GPIO4_DIV3 (PM8350B_SID << 8 | 0x8d) + +#define PM8350B_ADC5_GEN2_VPH_PWR (PM8350B_SID << 8 | 0x8e) +#define PM8350B_ADC5_GEN2_VBAT_SNS (PM8350B_SID << 8 | 0x8f) + +#define PM8350B_ADC5_GEN2_SBUx (PM8350B_SID << 8 | 0x94) +#define PM8350B_ADC5_GEN2_VBAT_2S_MID (PM8350B_SID << 8 | 0x96) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H */ diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmk8350.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmk8350.h new file mode 100644 index 000000000000..8de4ee86f875 --- /dev/null +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmk8350.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H + +#ifndef PMK8350_SID +#define PMK8350_SID 0 +#endif + +/* ADC channels for PMK8350_ADC for PMIC5 Gen2 */ +#define PMK8350_ADC5_GEN2_REF_GND (PMK8350_SID << 8 | 0x0) +#define PMK8350_ADC5_GEN2_1P25VREF (PMK8350_SID << 8 | 0x01) +#define PMK8350_ADC5_GEN2_VREF_VADC (PMK8350_SID << 8 | 0x02) +#define PMK8350_ADC5_GEN2_DIE_TEMP (PMK8350_SID << 8 | 0x03) + +#define PMK8350_ADC5_GEN2_AMUX_THM1 (PMK8350_SID << 8 | 0x04) +#define PMK8350_ADC5_GEN2_AMUX_THM2 (PMK8350_SID << 8 | 0x05) +#define PMK8350_ADC5_GEN2_AMUX_THM3 (PMK8350_SID << 8 | 0x06) +#define PMK8350_ADC5_GEN2_AMUX_THM4 (PMK8350_SID << 8 | 0x07) +#define PMK8350_ADC5_GEN2_AMUX_THM5 (PMK8350_SID << 8 | 0x08) + +/* 30k pull-up1 */ +#define PMK8350_ADC5_GEN2_AMUX_THM1_30K_PU (PMK8350_SID << 8 | 0x24) +#define PMK8350_ADC5_GEN2_AMUX_THM2_30K_PU (PMK8350_SID << 8 | 0x25) +#define PMK8350_ADC5_GEN2_AMUX_THM3_30K_PU (PMK8350_SID << 8 | 0x26) +#define PMK8350_ADC5_GEN2_AMUX_THM4_30K_PU (PMK8350_SID << 8 | 0x27) +#define PMK8350_ADC5_GEN2_AMUX_THM5_30K_PU (PMK8350_SID << 8 | 0x28) + +/* 100k pull-up2 */ +#define PMK8350_ADC5_GEN2_AMUX_THM1_100K_PU (PMK8350_SID << 8 | 0x44) +#define PMK8350_ADC5_GEN2_AMUX_THM2_100K_PU (PMK8350_SID << 8 | 0x45) +#define PMK8350_ADC5_GEN2_AMUX_THM3_100K_PU (PMK8350_SID << 8 | 0x46) +#define PMK8350_ADC5_GEN2_AMUX_THM4_100K_PU (PMK8350_SID << 8 | 0x47) +#define PMK8350_ADC5_GEN2_AMUX_THM5_100K_PU (PMK8350_SID << 8 | 0x48) + +/* 400k pull-up3 */ +#define PMK8350_ADC5_GEN2_AMUX_THM1_400K_PU (PMK8350_SID << 8 | 0x64) +#define PMK8350_ADC5_GEN2_AMUX_THM2_400K_PU (PMK8350_SID << 8 | 0x65) +#define PMK8350_ADC5_GEN2_AMUX_THM3_400K_PU (PMK8350_SID << 8 | 0x66) +#define PMK8350_ADC5_GEN2_AMUX_THM4_400K_PU (PMK8350_SID << 8 | 0x67) +#define PMK8350_ADC5_GEN2_AMUX_THM5_400K_PU (PMK8350_SID << 8 | 0x68) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H */ diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmr735a.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmr735a.h new file mode 100644 index 000000000000..0f8ad745845b --- /dev/null +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmr735a.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H + +#ifndef PMR735A_SID +#define PMR735A_SID 4 +#endif + +/* ADC channels for PMR735A_ADC for PMIC5 Gen2 */ +#define PMR735A_ADC5_GEN2_REF_GND (PMR735A_SID << 8 | 0x0) +#define PMR735A_ADC5_GEN2_1P25VREF (PMR735A_SID << 8 | 0x01) +#define PMR735A_ADC5_GEN2_VREF_VADC (PMR735A_SID << 8 | 0x02) +#define PMR735A_ADC5_GEN2_DIE_TEMP (PMR735A_SID << 8 | 0x03) + +#define PMR735A_ADC5_GEN2_GPIO1 (PMR735A_SID << 8 | 0x0a) +#define PMR735A_ADC5_GEN2_GPIO2 (PMR735A_SID << 8 | 0x0b) +#define PMR735A_ADC5_GEN2_GPIO3 (PMR735A_SID << 8 | 0x0c) + +/* 100k pull-up2 */ +#define PMR735A_ADC5_GEN2_GPIO1_100K_PU (PMR735A_SID << 8 | 0x4a) +#define PMR735A_ADC5_GEN2_GPIO2_100K_PU (PMR735A_SID << 8 | 0x4b) +#define PMR735A_ADC5_GEN2_GPIO3_100K_PU (PMR735A_SID << 8 | 0x4c) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H */ diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmr735b.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmr735b.h new file mode 100644 index 000000000000..d05d057276e3 --- /dev/null +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen2-pmr735b.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H + +#ifndef PMR735B_SID +#define PMR735B_SID 5 +#endif + +/* ADC channels for PMR735B_ADC for PMIC5 Gen2 */ +#define PMR735B_ADC5_GEN2_REF_GND (PMR735B_SID << 8 | 0x0) +#define PMR735B_ADC5_GEN2_1P25VREF (PMR735B_SID << 8 | 0x01) +#define PMR735B_ADC5_GEN2_VREF_VADC (PMR735B_SID << 8 | 0x02) +#define PMR735B_ADC5_GEN2_DIE_TEMP (PMR735B_SID << 8 | 0x03) + +#define PMR735B_ADC5_GEN2_GPIO1 (PMR735B_SID << 8 | 0x0a) +#define PMR735B_ADC5_GEN2_GPIO2 (PMR735B_SID << 8 | 0x0b) +#define PMR735B_ADC5_GEN2_GPIO3 (PMR735B_SID << 8 | 0x0c) + +/* 100k pull-up2 */ +#define PMR735B_ADC5_GEN2_GPIO1_100K_PU (PMR735B_SID << 8 | 0x4a) +#define PMR735B_ADC5_GEN2_GPIO2_100K_PU (PMR735B_SID << 8 | 0x4b) +#define PMR735B_ADC5_GEN2_GPIO3_100K_PU (PMR735B_SID << 8 | 0x4c) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H */ diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h new file mode 100644 index 000000000000..74e6e2f6f9ed --- /dev/null +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H + +#ifndef PM8550_SID +#define PM8550_SID 1 +#endif + +/* ADC channels for PM8550_ADC for PMIC5 Gen3 */ +#define PM8550_ADC5_GEN3_OFFSET_REF (PM8550_SID << 8 | 0x00) +#define PM8550_ADC5_GEN3_1P25VREF (PM8550_SID << 8 | 0x01) +#define PM8550_ADC5_GEN3_VREF_VADC (PM8550_SID << 8 | 0x02) +#define PM8550_ADC5_GEN3_DIE_TEMP (PM8550_SID << 8 | 0x03) + +#define PM8550_ADC5_GEN3_AMUX_THM1 (PM8550_SID << 8 | 0x04) +#define PM8550_ADC5_GEN3_AMUX_THM2 (PM8550_SID << 8 | 0x05) +#define PM8550_ADC5_GEN3_AMUX_THM3 (PM8550_SID << 8 | 0x06) +#define PM8550_ADC5_GEN3_AMUX_THM4 (PM8550_SID << 8 | 0x07) +#define PM8550_ADC5_GEN3_AMUX_THM5 (PM8550_SID << 8 | 0x08) +#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2 (PM8550_SID << 8 | 0x09) +#define PM8550_ADC5_GEN3_AMUX1_GPIO3 (PM8550_SID << 8 | 0x0a) +#define PM8550_ADC5_GEN3_AMUX2_GPIO4 (PM8550_SID << 8 | 0x0b) +#define PM8550_ADC5_GEN3_AMUX3_GPIO7 (PM8550_SID << 8 | 0x0c) +#define PM8550_ADC5_GEN3_AMUX4_GPIO12 (PM8550_SID << 8 | 0x0d) + +/* 100k pull-up */ +#define PM8550_ADC5_GEN3_AMUX_THM1_100K_PU (PM8550_SID << 8 | 0x44) +#define PM8550_ADC5_GEN3_AMUX_THM2_100K_PU (PM8550_SID << 8 | 0x45) +#define PM8550_ADC5_GEN3_AMUX_THM3_100K_PU (PM8550_SID << 8 | 0x46) +#define PM8550_ADC5_GEN3_AMUX_THM4_100K_PU (PM8550_SID << 8 | 0x47) +#define PM8550_ADC5_GEN3_AMUX_THM5_100K_PU (PM8550_SID << 8 | 0x48) +#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2_100K_PU (PM8550_SID << 8 | 0x49) +#define PM8550_ADC5_GEN3_AMUX1_GPIO3_100K_PU (PM8550_SID << 8 | 0x4a) +#define PM8550_ADC5_GEN3_AMUX2_GPIO4_100K_PU (PM8550_SID << 8 | 0x4b) +#define PM8550_ADC5_GEN3_AMUX3_GPIO7_100K_PU (PM8550_SID << 8 | 0x4c) +#define PM8550_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550_SID << 8 | 0x4d) + +/* 1/3 Divider */ +#define PM8550_ADC5_GEN3_AMUX3_GPIO7_DIV3 (PM8550_SID << 8 | 0x8c) +#define PM8550_ADC5_GEN3_AMUX4_GPIO12_DIV3 (PM8550_SID << 8 | 0x8d) + +#define PM8550_ADC5_GEN3_VPH_PWR (PM8550_SID << 8 | 0x8e) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H */ diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h new file mode 100644 index 000000000000..35483dfd970e --- /dev/null +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H + +#ifndef PM8550B_SID +#define PM8550B_SID 7 +#endif + +/* ADC channels for PM8550B_ADC for PMIC5 Gen3 */ +#define PM8550B_ADC5_GEN3_OFFSET_REF (PM8550B_SID << 8 | 0x00) +#define PM8550B_ADC5_GEN3_1P25VREF (PM8550B_SID << 8 | 0x01) +#define PM8550B_ADC5_GEN3_VREF_VADC (PM8550B_SID << 8 | 0x02) +#define PM8550B_ADC5_GEN3_DIE_TEMP (PM8550B_SID << 8 | 0x03) + +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM (PM8550B_SID << 8 | 0x04) +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID (PM8550B_SID << 8 | 0x05) +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V (PM8550B_SID << 8 | 0x06) +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM (PM8550B_SID << 8 | 0x07) +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION (PM8550B_SID << 8 | 0x08) +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10 (PM8550B_SID << 8 | 0x09) +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1 (PM8550B_SID << 8 | 0x0a) +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5 (PM8550B_SID << 8 | 0x0b) +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6 (PM8550B_SID << 8 | 0x0c) +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12 (PM8550B_SID << 8 | 0x0d) + +#define PM8550B_ADC5_GEN3_CHG_TEMP (PM8550B_SID << 8 | 0x10) +#define PM8550B_ADC5_GEN3_USB_SNS_V_16 (PM8550B_SID << 8 | 0x11) +#define PM8550B_ADC5_GEN3_VIN_DIV16_MUX (PM8550B_SID << 8 | 0x12) +#define PM8550B_ADC5_GEN3_USBC_MUX (PM8550B_SID << 8 | 0x13) +#define PM8550B_ADC5_GEN3_VREF_BAT_THERM (PM8550B_SID << 8 | 0x15) +#define PM8550B_ADC5_GEN3_IIN_FB (PM8550B_SID << 8 | 0x17) +#define PM8550B_ADC5_GEN3_TEMP_ALARM_LITE (PM8550B_SID << 8 | 0x18) +#define PM8550B_ADC5_GEN3_SMB_IIN (PM8550B_SID << 8 | 0x19) +#define PM8550B_ADC5_GEN3_VREF_BAT2_THERM (PM8550B_SID << 8 | 0x1a) +#define PM8550B_ADC5_GEN3_SMB_ICHG (PM8550B_SID << 8 | 0x1b) +#define PM8550B_ADC5_GEN3_SMB_TEMP_I (PM8550B_SID << 8 | 0x1e) +#define PM8550B_ADC5_GEN3_CHG_TEMP_I (PM8550B_SID << 8 | 0x1f) +#define PM8550B_ADC5_GEN3_ICHG_FB (PM8550B_SID << 8 | 0xa1) + +/* 30k pull-up */ +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_30K_PU (PM8550B_SID << 8 | 0x24) +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_30K_PU (PM8550B_SID << 8 | 0x25) +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_30K_PU (PM8550B_SID << 8 | 0x26) +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_30K_PU (PM8550B_SID << 8 | 0x27) +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_30K_PU (PM8550B_SID << 8 | 0x28) +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_30K_PU (PM8550B_SID << 8 | 0x29) +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_30K_PU (PM8550B_SID << 8 | 0x2a) +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_30K_PU (PM8550B_SID << 8 | 0x2b) +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_30K_PU (PM8550B_SID << 8 | 0x2c) +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_30K_PU (PM8550B_SID << 8 | 0x2d) + +#define PM8550B_ADC5_GEN3_USBC_MUX_30K_PU (PM8550B_SID << 8 | 0x33) + +/* 100k pull-up */ +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_100K_PU (PM8550B_SID << 8 | 0x44) +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_100K_PU (PM8550B_SID << 8 | 0x45) +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_100K_PU (PM8550B_SID << 8 | 0x46) +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU (PM8550B_SID << 8 | 0x47) +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_100K_PU (PM8550B_SID << 8 | 0x48) +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_100K_PU (PM8550B_SID << 8 | 0x49) +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_100K_PU (PM8550B_SID << 8 | 0x4a) +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_100K_PU (PM8550B_SID << 8 | 0x4b) +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_100K_PU (PM8550B_SID << 8 | 0x4c) +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550B_SID << 8 | 0x4d) + +#define PM8550B_ADC5_GEN3_USBC_MUX_100K_PU (PM8550B_SID << 8 | 0x53) + +/* 400k pull-up */ +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_400K_PU (PM8550B_SID << 8 | 0x64) +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_400K_PU (PM8550B_SID << 8 | 0x65) +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_400K_PU (PM8550B_SID << 8 | 0x66) +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_400K_PU (PM8550B_SID << 8 | 0x67) +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_400K_PU (PM8550B_SID << 8 | 0x68) +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_400K_PU (PM8550B_SID << 8 | 0x69) +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_400K_PU (PM8550B_SID << 8 | 0x6a) +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_400K_PU (PM8550B_SID << 8 | 0x6b) +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_400K_PU (PM8550B_SID << 8 | 0x6c) +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_400K_PU (PM8550B_SID << 8 | 0x6d) + +#define PM8550B_ADC5_GEN3_USBC_MUX_400K_PU (PM8550B_SID << 8 | 0x73) + +/* 1/3 Divider */ +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_DIV3 (PM8550B_SID << 8 | 0x8a) +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_DIV3 (PM8550B_SID << 8 | 0x8b) +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_DIV3 (PM8550B_SID << 8 | 0x8c) + +#define PM8550B_ADC5_GEN3_VPH_PWR (PM8550B_SID << 8 | 0x8e) +#define PM8550B_ADC5_GEN3_VBAT_SNS_QBG (PM8550B_SID << 8 | 0x8f) +#define PM8550B_ADC5_GEN3_VBAT_SNS_CHGR (PM8550B_SID << 8 | 0x94) +#define PM8550B_ADC5_GEN3_VBAT_2S_MID_QBG (PM8550B_SID << 8 | 0x96) +#define PM8550B_ADC5_GEN3_VBAT_2S_MID_CHGR (PM8550B_SID << 8 | 0x9d) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H */ diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h new file mode 100644 index 000000000000..337e13f7f56f --- /dev/null +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H + +/* ADC channels for PM8550VX_ADC for PMIC5 Gen3 */ +#define PM8550VS_ADC5_GEN3_OFFSET_REF(sid) ((sid) << 8 | 0x00) +#define PM8550VS_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | 0x01) +#define PM8550VS_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | 0X02) +#define PM8550VS_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | 0x03) + +#define PM8550VE_ADC5_GEN3_OFFSET_REF(sid) ((sid) << 8 | 0x00) +#define PM8550VE_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | 0x01) +#define PM8550VE_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | 0X02) +#define PM8550VE_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | 0x03) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H */ diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h new file mode 100644 index 000000000000..126fc16d5b20 --- /dev/null +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H + +#ifndef PMK8550_SID +#define PMK8550_SID 0 +#endif + +/* ADC channels for PMK8550_ADC for PMIC5 Gen3 */ +#define PMK8550_ADC5_GEN3_OFFSET_REF (PMK8550_SID << 8 | 0x00) +#define PMK8550_ADC5_GEN3_1P25VREF (PMK8550_SID << 8 | 0x01) +#define PMK8550_ADC5_GEN3_VREF_VADC (PMK8550_SID << 8 | 0x02) +#define PMK8550_ADC5_GEN3_DIE_TEMP (PMK8550_SID << 8 | 0x03) + +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM (PMK8550_SID << 8 | 0x04) +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1 (PMK8550_SID << 8 | 0x05) +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2 (PMK8550_SID << 8 | 0x06) +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3 (PMK8550_SID << 8 | 0x07) +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4 (PMK8550_SID << 8 | 0x08) +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5 (PMK8550_SID << 8 | 0x09) +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6 (PMK8550_SID << 8 | 0x0a) + +/* 30k pull-up */ +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_30K_PU (PMK8550_SID << 8 | 0x24) +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_30K_PU (PMK8550_SID << 8 | 0x25) +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_30K_PU (PMK8550_SID << 8 | 0x26) +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_30K_PU (PMK8550_SID << 8 | 0x27) +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_30K_PU (PMK8550_SID << 8 | 0x28) +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_30K_PU (PMK8550_SID << 8 | 0x29) +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_30K_PU (PMK8550_SID << 8 | 0x2a) + +/* 100k pull-up */ +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU (PMK8550_SID << 8 | 0x44) +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_100K_PU (PMK8550_SID << 8 | 0x45) +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_100K_PU (PMK8550_SID << 8 | 0x46) +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_100K_PU (PMK8550_SID << 8 | 0x47) +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_100K_PU (PMK8550_SID << 8 | 0x48) +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_100K_PU (PMK8550_SID << 8 | 0x49) +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_100K_PU (PMK8550_SID << 8 | 0x4a) + +/* 400k pull-up */ +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_400K_PU (PMK8550_SID << 8 | 0x64) +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_400K_PU (PMK8550_SID << 8 | 0x65) +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_400K_PU (PMK8550_SID << 8 | 0x66) +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_400K_PU (PMK8550_SID << 8 | 0x67) +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_400K_PU (PMK8550_SID << 8 | 0x68) +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_400K_PU (PMK8550_SID << 8 | 0x69) +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_400K_PU (PMK8550_SID << 8 | 0x6a) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H */ diff --git a/include/dt-bindings/iio/adc/qcom,spmi-vadc.h b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h new file mode 100644 index 000000000000..ca5a0a947b3b --- /dev/null +++ b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h @@ -0,0 +1,379 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_H + +/* Voltage ADC channels */ +#define VADC_USBIN 0x00 +#define VADC_DCIN 0x01 +#define VADC_VCHG_SNS 0x02 +#define VADC_SPARE1_03 0x03 +#define VADC_USB_ID_MV 0x04 +#define VADC_VCOIN 0x05 +#define VADC_VBAT_SNS 0x06 +#define VADC_VSYS 0x07 +#define VADC_DIE_TEMP 0x08 +#define VADC_REF_625MV 0x09 +#define VADC_REF_1250MV 0x0a +#define VADC_CHG_TEMP 0x0b +#define VADC_SPARE1 0x0c +#define VADC_SPARE2 0x0d +#define VADC_GND_REF 0x0e +#define VADC_VDD_VADC 0x0f + +#define VADC_P_MUX1_1_1 0x10 +#define VADC_P_MUX2_1_1 0x11 +#define VADC_P_MUX3_1_1 0x12 +#define VADC_P_MUX4_1_1 0x13 +#define VADC_P_MUX5_1_1 0x14 +#define VADC_P_MUX6_1_1 0x15 +#define VADC_P_MUX7_1_1 0x16 +#define VADC_P_MUX8_1_1 0x17 +#define VADC_P_MUX9_1_1 0x18 +#define VADC_P_MUX10_1_1 0x19 +#define VADC_P_MUX11_1_1 0x1a +#define VADC_P_MUX12_1_1 0x1b +#define VADC_P_MUX13_1_1 0x1c +#define VADC_P_MUX14_1_1 0x1d +#define VADC_P_MUX15_1_1 0x1e +#define VADC_P_MUX16_1_1 0x1f + +#define VADC_P_MUX1_1_3 0x20 +#define VADC_P_MUX2_1_3 0x21 +#define VADC_P_MUX3_1_3 0x22 +#define VADC_P_MUX4_1_3 0x23 +#define VADC_P_MUX5_1_3 0x24 +#define VADC_P_MUX6_1_3 0x25 +#define VADC_P_MUX7_1_3 0x26 +#define VADC_P_MUX8_1_3 0x27 +#define VADC_P_MUX9_1_3 0x28 +#define VADC_P_MUX10_1_3 0x29 +#define VADC_P_MUX11_1_3 0x2a +#define VADC_P_MUX12_1_3 0x2b +#define VADC_P_MUX13_1_3 0x2c +#define VADC_P_MUX14_1_3 0x2d +#define VADC_P_MUX15_1_3 0x2e +#define VADC_P_MUX16_1_3 0x2f + +#define VADC_LR_MUX1_BAT_THERM 0x30 +#define VADC_LR_MUX2_BAT_ID 0x31 +#define VADC_LR_MUX3_XO_THERM 0x32 +#define VADC_LR_MUX4_AMUX_THM1 0x33 +#define VADC_LR_MUX5_AMUX_THM2 0x34 +#define VADC_LR_MUX6_AMUX_THM3 0x35 +#define VADC_LR_MUX7_HW_ID 0x36 +#define VADC_LR_MUX8_AMUX_THM4 0x37 +#define VADC_LR_MUX9_AMUX_THM5 0x38 +#define VADC_LR_MUX10_USB_ID 0x39 +#define VADC_AMUX_PU1 0x3a +#define VADC_AMUX_PU2 0x3b +#define VADC_LR_MUX3_BUF_XO_THERM 0x3c + +#define VADC_LR_MUX1_PU1_BAT_THERM 0x70 +#define VADC_LR_MUX2_PU1_BAT_ID 0x71 +#define VADC_LR_MUX3_PU1_XO_THERM 0x72 +#define VADC_LR_MUX4_PU1_AMUX_THM1 0x73 +#define VADC_LR_MUX5_PU1_AMUX_THM2 0x74 +#define VADC_LR_MUX6_PU1_AMUX_THM3 0x75 +#define VADC_LR_MUX7_PU1_AMUX_HW_ID 0x76 +#define VADC_LR_MUX8_PU1_AMUX_THM4 0x77 +#define VADC_LR_MUX9_PU1_AMUX_THM5 0x78 +#define VADC_LR_MUX10_PU1_AMUX_USB_ID 0x79 +#define VADC_LR_MUX3_BUF_PU1_XO_THERM 0x7c + +#define VADC_LR_MUX1_PU2_BAT_THERM 0xb0 +#define VADC_LR_MUX2_PU2_BAT_ID 0xb1 +#define VADC_LR_MUX3_PU2_XO_THERM 0xb2 +#define VADC_LR_MUX4_PU2_AMUX_THM1 0xb3 +#define VADC_LR_MUX5_PU2_AMUX_THM2 0xb4 +#define VADC_LR_MUX6_PU2_AMUX_THM3 0xb5 +#define VADC_LR_MUX7_PU2_AMUX_HW_ID 0xb6 +#define VADC_LR_MUX8_PU2_AMUX_THM4 0xb7 +#define VADC_LR_MUX9_PU2_AMUX_THM5 0xb8 +#define VADC_LR_MUX10_PU2_AMUX_USB_ID 0xb9 +#define VADC_LR_MUX3_BUF_PU2_XO_THERM 0xbc + +#define VADC_LR_MUX1_PU1_PU2_BAT_THERM 0xf0 +#define VADC_LR_MUX2_PU1_PU2_BAT_ID 0xf1 +#define VADC_LR_MUX3_PU1_PU2_XO_THERM 0xf2 +#define VADC_LR_MUX4_PU1_PU2_AMUX_THM1 0xf3 +#define VADC_LR_MUX5_PU1_PU2_AMUX_THM2 0xf4 +#define VADC_LR_MUX6_PU1_PU2_AMUX_THM3 0xf5 +#define VADC_LR_MUX7_PU1_PU2_AMUX_HW_ID 0xf6 +#define VADC_LR_MUX8_PU1_PU2_AMUX_THM4 0xf7 +#define VADC_LR_MUX9_PU1_PU2_AMUX_THM5 0xf8 +#define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID 0xf9 +#define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM 0xfc + +/* ADC channels for SPMI PMIC5 */ + +#define ADC5_REF_GND 0x00 +#define ADC5_1P25VREF 0x01 +#define ADC5_VREF_VADC 0x02 +#define ADC5_VREF_VADC5_DIV_3 0x82 +#define ADC5_VPH_PWR 0x83 +#define ADC5_VBAT_SNS 0x84 +#define ADC5_VCOIN 0x85 +#define ADC5_DIE_TEMP 0x06 +#define ADC5_USB_IN_I 0x07 +#define ADC5_USB_IN_V_16 0x08 +#define ADC5_CHG_TEMP 0x09 +#define ADC5_BAT_THERM 0x0a +#define ADC5_BAT_ID 0x0b +#define ADC5_XO_THERM 0x0c +#define ADC5_AMUX_THM1 0x0d +#define ADC5_AMUX_THM2 0x0e +#define ADC5_AMUX_THM3 0x0f +#define ADC5_AMUX_THM4 0x10 +#define ADC5_AMUX_THM5 0x11 +#define ADC5_GPIO1 0x12 +#define ADC5_GPIO2 0x13 +#define ADC5_GPIO3 0x14 +#define ADC5_GPIO4 0x15 +#define ADC5_GPIO5 0x16 +#define ADC5_GPIO6 0x17 +#define ADC5_GPIO7 0x18 +#define ADC5_SBUx 0x99 +#define ADC5_MID_CHG_DIV6 0x1e +#define ADC5_OFF 0xff + +/* 30k pull-up1 */ +#define ADC5_BAT_THERM_30K_PU 0x2a +#define ADC5_BAT_ID_30K_PU 0x2b +#define ADC5_XO_THERM_30K_PU 0x2c +#define ADC5_AMUX_THM1_30K_PU 0x2d +#define ADC5_AMUX_THM2_30K_PU 0x2e +#define ADC5_AMUX_THM3_30K_PU 0x2f +#define ADC5_AMUX_THM4_30K_PU 0x30 +#define ADC5_AMUX_THM5_30K_PU 0x31 +#define ADC5_GPIO1_30K_PU 0x32 +#define ADC5_GPIO2_30K_PU 0x33 +#define ADC5_GPIO3_30K_PU 0x34 +#define ADC5_GPIO4_30K_PU 0x35 +#define ADC5_GPIO5_30K_PU 0x36 +#define ADC5_GPIO6_30K_PU 0x37 +#define ADC5_GPIO7_30K_PU 0x38 +#define ADC5_SBUx_30K_PU 0x39 + +/* 100k pull-up2 */ +#define ADC5_BAT_THERM_100K_PU 0x4a +#define ADC5_BAT_ID_100K_PU 0x4b +#define ADC5_XO_THERM_100K_PU 0x4c +#define ADC5_AMUX_THM1_100K_PU 0x4d +#define ADC5_AMUX_THM2_100K_PU 0x4e +#define ADC5_AMUX_THM3_100K_PU 0x4f +#define ADC5_AMUX_THM4_100K_PU 0x50 +#define ADC5_AMUX_THM5_100K_PU 0x51 +#define ADC5_GPIO1_100K_PU 0x52 +#define ADC5_GPIO2_100K_PU 0x53 +#define ADC5_GPIO3_100K_PU 0x54 +#define ADC5_GPIO4_100K_PU 0x55 +#define ADC5_GPIO5_100K_PU 0x56 +#define ADC5_GPIO6_100K_PU 0x57 +#define ADC5_GPIO7_100K_PU 0x58 +#define ADC5_SBUx_100K_PU 0x59 + +/* 400k pull-up3 */ +#define ADC5_BAT_THERM_400K_PU 0x6a +#define ADC5_BAT_ID_400K_PU 0x6b +#define ADC5_XO_THERM_400K_PU 0x6c +#define ADC5_AMUX_THM1_400K_PU 0x6d +#define ADC5_AMUX_THM2_400K_PU 0x6e +#define ADC5_AMUX_THM3_400K_PU 0x6f +#define ADC5_AMUX_THM4_400K_PU 0x70 +#define ADC5_AMUX_THM5_400K_PU 0x71 +#define ADC5_GPIO1_400K_PU 0x72 +#define ADC5_GPIO2_400K_PU 0x73 +#define ADC5_GPIO3_400K_PU 0x74 +#define ADC5_GPIO4_400K_PU 0x75 +#define ADC5_GPIO5_400K_PU 0x76 +#define ADC5_GPIO6_400K_PU 0x77 +#define ADC5_GPIO7_400K_PU 0x78 +#define ADC5_SBUx_400K_PU 0x79 + +/* 1/3 Divider */ +#define ADC5_GPIO1_DIV3 0x92 +#define ADC5_GPIO2_DIV3 0x93 +#define ADC5_GPIO3_DIV3 0x94 +#define ADC5_GPIO4_DIV3 0x95 +#define ADC5_GPIO5_DIV3 0x96 +#define ADC5_GPIO6_DIV3 0x97 +#define ADC5_GPIO7_DIV3 0x98 +#define ADC5_SBUx_DIV3 0x99 + +/* Current and combined current/voltage channels */ +#define ADC5_INT_EXT_ISENSE 0xa1 +#define ADC5_PARALLEL_ISENSE 0xa5 +#define ADC5_CUR_REPLICA_VDS 0xa7 +#define ADC5_CUR_SENS_BATFET_VDS_OFFSET 0xa9 +#define ADC5_CUR_SENS_REPLICA_VDS_OFFSET 0xab +#define ADC5_EXT_SENS_OFFSET 0xad + +#define ADC5_INT_EXT_ISENSE_VBAT_VDATA 0xb0 +#define ADC5_INT_EXT_ISENSE_VBAT_IDATA 0xb1 +#define ADC5_EXT_ISENSE_VBAT_VDATA 0xb2 +#define ADC5_EXT_ISENSE_VBAT_IDATA 0xb3 +#define ADC5_PARALLEL_ISENSE_VBAT_VDATA 0xb4 +#define ADC5_PARALLEL_ISENSE_VBAT_IDATA 0xb5 + +#define ADC5_MAX_CHANNEL 0xc0 + +/* ADC channels for ADC for PMIC5 Gen2 */ + +#define ADC5_GEN2_REF_GND 0x00 +#define ADC5_GEN2_1P25VREF 0x01 +#define ADC5_GEN2_VREF_VADC 0x02 +#define ADC5_GEN2_DIE_TEMP 0x03 + +#define ADC5_GEN2_AMUX_THM1 0x04 +#define ADC5_GEN2_AMUX_THM2 0x05 +#define ADC5_GEN2_AMUX_THM3 0x06 +#define ADC5_GEN2_AMUX_THM4 0x07 +#define ADC5_GEN2_AMUX_THM5 0x08 +#define ADC5_GEN2_AMUX_THM6 0x09 +#define ADC5_GEN2_GPIO1 0x0a +#define ADC5_GEN2_GPIO2 0x0b +#define ADC5_GEN2_GPIO3 0x0c +#define ADC5_GEN2_GPIO4 0x0d + +#define ADC5_GEN2_CHG_TEMP 0x10 +#define ADC5_GEN2_USB_IN_V_16 0x11 +#define ADC5_GEN2_VDC_16 0x12 +#define ADC5_GEN2_CC1_ID 0x13 +#define ADC5_GEN2_VREF_BAT_THERM 0x15 +#define ADC5_GEN2_IIN_FB 0x17 + +/* 30k pull-up1 */ +#define ADC5_GEN2_AMUX_THM1_30K_PU 0x24 +#define ADC5_GEN2_AMUX_THM2_30K_PU 0x25 +#define ADC5_GEN2_AMUX_THM3_30K_PU 0x26 +#define ADC5_GEN2_AMUX_THM4_30K_PU 0x27 +#define ADC5_GEN2_AMUX_THM5_30K_PU 0x28 +#define ADC5_GEN2_AMUX_THM6_30K_PU 0x29 +#define ADC5_GEN2_GPIO1_30K_PU 0x2a +#define ADC5_GEN2_GPIO2_30K_PU 0x2b +#define ADC5_GEN2_GPIO3_30K_PU 0x2c +#define ADC5_GEN2_GPIO4_30K_PU 0x2d +#define ADC5_GEN2_CC1_ID_30K_PU 0x33 + +/* 100k pull-up2 */ +#define ADC5_GEN2_AMUX_THM1_100K_PU 0x44 +#define ADC5_GEN2_AMUX_THM2_100K_PU 0x45 +#define ADC5_GEN2_AMUX_THM3_100K_PU 0x46 +#define ADC5_GEN2_AMUX_THM4_100K_PU 0x47 +#define ADC5_GEN2_AMUX_THM5_100K_PU 0x48 +#define ADC5_GEN2_AMUX_THM6_100K_PU 0x49 +#define ADC5_GEN2_GPIO1_100K_PU 0x4a +#define ADC5_GEN2_GPIO2_100K_PU 0x4b +#define ADC5_GEN2_GPIO3_100K_PU 0x4c +#define ADC5_GEN2_GPIO4_100K_PU 0x4d +#define ADC5_GEN2_CC1_ID_100K_PU 0x53 + +/* 400k pull-up3 */ +#define ADC5_GEN2_AMUX_THM1_400K_PU 0x64 +#define ADC5_GEN2_AMUX_THM2_400K_PU 0x65 +#define ADC5_GEN2_AMUX_THM3_400K_PU 0x66 +#define ADC5_GEN2_AMUX_THM4_400K_PU 0x67 +#define ADC5_GEN2_AMUX_THM5_400K_PU 0x68 +#define ADC5_GEN2_AMUX_THM6_400K_PU 0x69 +#define ADC5_GEN2_GPIO1_400K_PU 0x6a +#define ADC5_GEN2_GPIO2_400K_PU 0x6b +#define ADC5_GEN2_GPIO3_400K_PU 0x6c +#define ADC5_GEN2_GPIO4_400K_PU 0x6d +#define ADC5_GEN2_CC1_ID_400K_PU 0x73 + +/* 1/3 Divider */ +#define ADC5_GEN2_GPIO1_DIV3 0x8a +#define ADC5_GEN2_GPIO2_DIV3 0x8b +#define ADC5_GEN2_GPIO3_DIV3 0x8c +#define ADC5_GEN2_GPIO4_DIV3 0x8d + +#define ADC5_GEN2_VPH_PWR 0x8e +#define ADC5_GEN2_VBAT_SNS 0x8f + +#define ADC5_GEN2_SBUx 0x94 +#define ADC5_GEN2_VBAT_2S_MID 0x96 + +/* ADC channels for PMIC5 Gen3 */ + +#define ADC5_GEN3_OFFSET_REF 0x00 +#define ADC5_GEN3_1P25VREF 0x01 +#define ADC5_GEN3_VREF_VADC 0x02 +#define ADC5_GEN3_DIE_TEMP 0x03 + +#define ADC5_GEN3_AMUX1_THM 0x04 +#define ADC5_GEN3_AMUX2_THM 0x05 +#define ADC5_GEN3_AMUX3_THM 0x06 +#define ADC5_GEN3_AMUX4_THM 0x07 +#define ADC5_GEN3_AMUX5_THM 0x08 +#define ADC5_GEN3_AMUX6_THM 0x09 +#define ADC5_GEN3_AMUX1_GPIO 0x0a +#define ADC5_GEN3_AMUX2_GPIO 0x0b +#define ADC5_GEN3_AMUX3_GPIO 0x0c +#define ADC5_GEN3_AMUX4_GPIO 0x0d + +#define ADC5_GEN3_CHG_TEMP 0x10 +#define ADC5_GEN3_USB_SNS_V_16 0x11 +#define ADC5_GEN3_VIN_DIV16_MUX 0x12 +#define ADC5_GEN3_VREF_BAT_THERM 0x15 +#define ADC5_GEN3_IIN_FB 0x17 +#define ADC5_GEN3_TEMP_ALARM_LITE 0x18 +#define ADC5_GEN3_IIN_SMB 0x19 +#define ADC5_GEN3_ICHG_SMB 0x1b +#define ADC5_GEN3_ICHG_FB 0xa1 + +/* 30k pull-up1 */ +#define ADC5_GEN3_AMUX1_THM_30K_PU 0x24 +#define ADC5_GEN3_AMUX2_THM_30K_PU 0x25 +#define ADC5_GEN3_AMUX3_THM_30K_PU 0x26 +#define ADC5_GEN3_AMUX4_THM_30K_PU 0x27 +#define ADC5_GEN3_AMUX5_THM_30K_PU 0x28 +#define ADC5_GEN3_AMUX6_THM_30K_PU 0x29 +#define ADC5_GEN3_AMUX1_GPIO_30K_PU 0x2a +#define ADC5_GEN3_AMUX2_GPIO_30K_PU 0x2b +#define ADC5_GEN3_AMUX3_GPIO_30K_PU 0x2c +#define ADC5_GEN3_AMUX4_GPIO_30K_PU 0x2d + +/* 100k pull-up2 */ +#define ADC5_GEN3_AMUX1_THM_100K_PU 0x44 +#define ADC5_GEN3_AMUX2_THM_100K_PU 0x45 +#define ADC5_GEN3_AMUX3_THM_100K_PU 0x46 +#define ADC5_GEN3_AMUX4_THM_100K_PU 0x47 +#define ADC5_GEN3_AMUX5_THM_100K_PU 0x48 +#define ADC5_GEN3_AMUX6_THM_100K_PU 0x49 +#define ADC5_GEN3_AMUX1_GPIO_100K_PU 0x4a +#define ADC5_GEN3_AMUX2_GPIO_100K_PU 0x4b +#define ADC5_GEN3_AMUX3_GPIO_100K_PU 0x4c +#define ADC5_GEN3_AMUX4_GPIO_100K_PU 0x4d + +/* 400k pull-up3 */ +#define ADC5_GEN3_AMUX1_THM_400K_PU 0x64 +#define ADC5_GEN3_AMUX2_THM_400K_PU 0x65 +#define ADC5_GEN3_AMUX3_THM_400K_PU 0x66 +#define ADC5_GEN3_AMUX4_THM_400K_PU 0x67 +#define ADC5_GEN3_AMUX5_THM_400K_PU 0x68 +#define ADC5_GEN3_AMUX6_THM_400K_PU 0x69 +#define ADC5_GEN3_AMUX1_GPIO_400K_PU 0x6a +#define ADC5_GEN3_AMUX2_GPIO_400K_PU 0x6b +#define ADC5_GEN3_AMUX3_GPIO_400K_PU 0x6c +#define ADC5_GEN3_AMUX4_GPIO_400K_PU 0x6d + +/* 1/3 Divider */ +#define ADC5_GEN3_AMUX1_GPIO_DIV3 0x8a +#define ADC5_GEN3_AMUX2_GPIO_DIV3 0x8b +#define ADC5_GEN3_AMUX3_GPIO_DIV3 0x8c + +#define ADC5_GEN3_VPH_PWR 0x8e +#define ADC5_GEN3_VBAT_SNS_QBG 0x8f + +#define ADC5_GEN3_VBAT_SNS_CHGR 0x94 +#define ADC5_GEN3_VBAT_2S_MID_QBG 0x96 +#define ADC5_GEN3_VBAT_2S_MID_CHGR 0x9d + +#define ADC5_GEN3_OFFSET_EXT2 0xf8 + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */ From patchwork Sat Jul 8 07:28:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 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files to match the dt-bindings change moving the files from 'iio' to 'iio/adc' folder. Signed-off-by: Jishnu Prakash --- drivers/iio/adc/qcom-spmi-adc5-gen3.c | 2 +- drivers/iio/adc/qcom-spmi-adc5.c | 2 +- drivers/iio/adc/qcom-spmi-vadc.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/iio/adc/qcom-spmi-adc5-gen3.c b/drivers/iio/adc/qcom-spmi-adc5-gen3.c index fe5515ee8451..78ece8fccbae 100644 --- a/drivers/iio/adc/qcom-spmi-adc5-gen3.c +++ b/drivers/iio/adc/qcom-spmi-adc5-gen3.c @@ -23,7 +23,7 @@ #include #include -#include +#include #define ADC5_GEN3_HS 0x45 #define ADC5_GEN3_HS_BUSY BIT(7) diff --git a/drivers/iio/adc/qcom-spmi-adc5.c b/drivers/iio/adc/qcom-spmi-adc5.c index 6cebeaa69a75..5dfcb770d663 100644 --- a/drivers/iio/adc/qcom-spmi-adc5.c +++ b/drivers/iio/adc/qcom-spmi-adc5.c @@ -21,7 +21,7 @@ #include #include -#include +#include #define ADC5_USR_REVISION1 0x0 #define ADC5_USR_STATUS1 0x8 diff --git a/drivers/iio/adc/qcom-spmi-vadc.c b/drivers/iio/adc/qcom-spmi-vadc.c index f5c6f1f27b2c..c3602c53968a 100644 --- a/drivers/iio/adc/qcom-spmi-vadc.c +++ b/drivers/iio/adc/qcom-spmi-vadc.c @@ -20,7 +20,7 @@ #include #include -#include +#include /* VADC register and bit definitions */ #define VADC_REVISION2 0x1 From patchwork Sat Jul 8 07:28:34 2023 Content-Type: text/plain; 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Signed-off-by: Jishnu Prakash --- arch/arm64/boot/dts/qcom/pm6125.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm6150.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm6150l.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm660.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm660l.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm7250b.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm8150.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm8150b.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm8150l.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm8916.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm8950.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm8953.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm8994.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm8998.dtsi | 2 +- arch/arm64/boot/dts/qcom/pmi632.dtsi | 2 +- arch/arm64/boot/dts/qcom/pmi8950.dtsi | 2 +- arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi | 2 +- arch/arm64/boot/dts/qcom/pmp8074.dtsi | 2 +- arch/arm64/boot/dts/qcom/pms405.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 2 +- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 6 +++--- arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 2 +- 24 files changed, 27 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm6125.dtsi b/arch/arm64/boot/dts/qcom/pm6125.dtsi index 59092a551a16..f7f716dfcbd1 100644 --- a/arch/arm64/boot/dts/qcom/pm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6125.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause -#include +#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi index 2e6afa296141..673bbcd69538 100644 --- a/arch/arm64/boot/dts/qcom/pm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi @@ -3,7 +3,7 @@ * Copyright (c) 2019, The Linux Foundation. All rights reserved. */ -#include +#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/qcom/pm6150l.dtsi index 6f7aa67501e2..d606520e05b7 100644 --- a/arch/arm64/boot/dts/qcom/pm6150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150l.dtsi @@ -3,7 +3,7 @@ * Copyright (c) 2019, The Linux Foundation. All rights reserved. */ -#include +#include #include #include diff --git a/arch/arm64/boot/dts/qcom/pm660.dtsi b/arch/arm64/boot/dts/qcom/pm660.dtsi index 4bc717917f44..e9cf14fef96d 100644 --- a/arch/arm64/boot/dts/qcom/pm660.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660.dtsi @@ -3,7 +3,7 @@ * Copyright (c) 2020, Konrad Dybcio */ -#include +#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/pm660l.dtsi b/arch/arm64/boot/dts/qcom/pm660l.dtsi index 87b71b7205b8..dfbe9bb0d25c 100644 --- a/arch/arm64/boot/dts/qcom/pm660l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660l.dtsi @@ -3,7 +3,7 @@ * Copyright (c) 2020, Konrad Dybcio */ -#include +#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/pm7250b.dtsi b/arch/arm64/boot/dts/qcom/pm7250b.dtsi index daa6f1d30efa..f5d14bde5300 100644 --- a/arch/arm64/boot/dts/qcom/pm7250b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm7250b.dtsi @@ -3,7 +3,7 @@ * Copyright (C) 2022 Luca Weiss */ -#include +#include #include #include diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi index db90c55fa2cf..a2d0168f4a2c 100644 --- a/arch/arm64/boot/dts/qcom/pm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi @@ -7,7 +7,7 @@ #include #include #include -#include +#include / { thermal-zones { diff --git a/arch/arm64/boot/dts/qcom/pm8150b.dtsi b/arch/arm64/boot/dts/qcom/pm8150b.dtsi index 66752cc063d6..9cb9603180d9 100644 --- a/arch/arm64/boot/dts/qcom/pm8150b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150b.dtsi @@ -4,7 +4,7 @@ * Copyright (c) 2019, Linaro Limited */ -#include +#include #include #include diff --git a/arch/arm64/boot/dts/qcom/pm8150l.dtsi b/arch/arm64/boot/dts/qcom/pm8150l.dtsi index cca45fad75ac..5a7cf8947dc4 100644 --- a/arch/arm64/boot/dts/qcom/pm8150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150l.dtsi @@ -4,7 +4,7 @@ * Copyright (c) 2019, Linaro Limited */ -#include +#include #include #include diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index 1ea8920ff369..91990a7175b1 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 -#include +#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/pm8950.dtsi b/arch/arm64/boot/dts/qcom/pm8950.dtsi index 5ec38b7e335a..e8d707edc4cd 100644 --- a/arch/arm64/boot/dts/qcom/pm8950.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8950.dtsi @@ -5,7 +5,7 @@ * Copyright (c) 2022, Marijn Suijten */ -#include +#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/pm8953.dtsi b/arch/arm64/boot/dts/qcom/pm8953.dtsi index 2268daf27fa7..025e851a6d2c 100644 --- a/arch/arm64/boot/dts/qcom/pm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8953.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: BSD-3-Clause /* Copyright (c) 2022, The Linux Foundation. All rights reserved. */ -#include +#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi index 672094c8ca58..8d150358b6ac 100644 --- a/arch/arm64/boot/dts/qcom/pm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 -#include +#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi index 695d79116cde..34462b5172da 100644 --- a/arch/arm64/boot/dts/qcom/pm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* Copyright 2018 Google LLC. */ -#include +#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/pmi632.dtsi b/arch/arm64/boot/dts/qcom/pmi632.dtsi index 4eb79e0ce40a..09f7af85d39b 100644 --- a/arch/arm64/boot/dts/qcom/pmi632.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi632.dtsi @@ -3,7 +3,7 @@ * Copyright (C) 2023 Luca Weiss */ -#include +#include #include #include diff --git a/arch/arm64/boot/dts/qcom/pmi8950.dtsi b/arch/arm64/boot/dts/qcom/pmi8950.dtsi index 4891be3cd68a..ce6f79c14015 100644 --- a/arch/arm64/boot/dts/qcom/pmi8950.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8950.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 // Copyright (c) 2019, AngeloGioacchino Del Regno -#include +#include #include #include diff --git a/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi index ee1e428d3a6e..35838492ea99 100644 --- a/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi +++ b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi @@ -6,7 +6,7 @@ #include #include #include -#include +#include / { thermal-zones { diff --git a/arch/arm64/boot/dts/qcom/pmp8074.dtsi b/arch/arm64/boot/dts/qcom/pmp8074.dtsi index 580684411d74..76438b4cda14 100644 --- a/arch/arm64/boot/dts/qcom/pmp8074.dtsi +++ b/arch/arm64/boot/dts/qcom/pmp8074.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause #include -#include +#include &spmi_bus { pmic@0 { diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi index 22edb47c6a84..2c87eae3d140 100644 --- a/arch/arm64/boot/dts/qcom/pms405.dtsi +++ b/arch/arm64/boot/dts/qcom/pms405.dtsi @@ -5,7 +5,7 @@ #include #include -#include +#include #include / { diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index bc65e6c6232f..e4afb554ba66 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include +#include #include "sc7280-idp.dtsi" #include "pmr735a.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index da413694e230..ac8922a222e7 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -5,7 +5,7 @@ * Copyright (c) 2021, The Linux Foundation. All rights reserved. */ -#include +#include #include #include "sc7280.dtsi" #include "pm7325.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi index ed26bff7432d..2abe5ce2af74 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -11,8 +11,8 @@ * Copyright 2022 Google LLC. */ -#include -#include +#include +#include #include #include diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index cfd5dbbacdcb..dedfefd94a63 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -7,9 +7,9 @@ /dts-v1/; #include -#include -#include -#include +#include +#include +#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index 52119cc1250e..e9c06953a490 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -9,7 +9,7 @@ #define PMK8350_SID 6 #include -#include +#include #include #include #include From patchwork Sat Jul 8 07:28:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jishnu Prakash X-Patchwork-Id: 700961 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8227EEB64DA for ; Sat, 8 Jul 2023 07:33:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232503AbjGHHdI (ORCPT ); Sat, 8 Jul 2023 03:33:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60584 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232692AbjGHHcx (ORCPT ); Sat, 8 Jul 2023 03:32:53 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24BF4271C; Sat, 8 Jul 2023 00:32:10 -0700 (PDT) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3687R9SC024197; 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Sat, 8 Jul 2023 07:31:20 GMT Received: from hu-jprakash-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Sat, 8 Jul 2023 00:31:12 -0700 From: Jishnu Prakash To: , , , , , , , , , , , , , , "Bjorn Andersson" , Konrad Dybcio , Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , CC: , Jishnu Prakash Subject: [PATCH 11/11] dt-bindings: iio: remove QCOM ADC files from iio folder Date: Sat, 8 Jul 2023 12:58:35 +0530 Message-ID: <20230708072835.3035398-12-quic_jprakash@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230708072835.3035398-1-quic_jprakash@quicinc.com> References: <20230708072835.3035398-1-quic_jprakash@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: lwRZrpc5zNpHb8Jn7ic75SEHd-b6JDPF X-Proofpoint-GUID: lwRZrpc5zNpHb8Jn7ic75SEHd-b6JDPF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-08_04,2023-07-06_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 mlxscore=0 phishscore=0 priorityscore=1501 suspectscore=0 mlxlogscore=999 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307080065 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Now that the ADC dt-binding paths have been updated everywhere to use the files copied to the 'iio/adc' folder, remove them from the 'iio' folder. Signed-off-by: Jishnu Prakash --- .../iio/qcom,spmi-adc5-gen2-pm8350.h | 64 --- .../iio/qcom,spmi-adc5-gen2-pm8350b.h | 89 ---- .../iio/qcom,spmi-adc5-gen2-pmk8350.h | 47 --- .../iio/qcom,spmi-adc5-gen2-pmr735a.h | 29 -- .../iio/qcom,spmi-adc5-gen2-pmr735b.h | 28 -- .../iio/qcom,spmi-adc5-gen3-pm8550.h | 48 --- .../iio/qcom,spmi-adc5-gen3-pm8550b.h | 97 ----- .../iio/qcom,spmi-adc5-gen3-pm8550vx.h | 20 - .../iio/qcom,spmi-adc5-gen3-pmk8550.h | 54 --- include/dt-bindings/iio/qcom,spmi-vadc.h | 379 ------------------ 10 files changed, 855 deletions(-) delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350.h delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350b.h delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmk8350.h delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735a.h delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735b.h delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h delete mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h delete mode 100644 include/dt-bindings/iio/qcom,spmi-vadc.h diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350.h deleted file mode 100644 index 77259beaf6e9..000000000000 --- a/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350.h +++ /dev/null @@ -1,64 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H -#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H - -/* ADC channels for PM8350_ADC for PMIC5 Gen2 */ -#define PM8350_ADC5_GEN2_REF_GND(sid) ((sid) << 8 | 0x0) -#define PM8350_ADC5_GEN2_1P25VREF(sid) ((sid) << 8 | 0x01) -#define PM8350_ADC5_GEN2_VREF_VADC(sid) ((sid) << 8 | 0x02) -#define PM8350_ADC5_GEN2_DIE_TEMP(sid) ((sid) << 8 | 0x03) - -#define PM8350_ADC5_GEN2_AMUX_THM1(sid) ((sid) << 8 | 0x04) -#define PM8350_ADC5_GEN2_AMUX_THM2(sid) ((sid) << 8 | 0x05) -#define PM8350_ADC5_GEN2_AMUX_THM3(sid) ((sid) << 8 | 0x06) -#define PM8350_ADC5_GEN2_AMUX_THM4(sid) ((sid) << 8 | 0x07) -#define PM8350_ADC5_GEN2_AMUX_THM5(sid) ((sid) << 8 | 0x08) -#define PM8350_ADC5_GEN2_GPIO1(sid) ((sid) << 8 | 0x0a) -#define PM8350_ADC5_GEN2_GPIO2(sid) ((sid) << 8 | 0x0b) -#define PM8350_ADC5_GEN2_GPIO3(sid) ((sid) << 8 | 0x0c) -#define PM8350_ADC5_GEN2_GPIO4(sid) ((sid) << 8 | 0x0d) - -/* 30k pull-up1 */ -#define PM8350_ADC5_GEN2_AMUX_THM1_30K_PU(sid) ((sid) << 8 | 0x24) -#define PM8350_ADC5_GEN2_AMUX_THM2_30K_PU(sid) ((sid) << 8 | 0x25) -#define PM8350_ADC5_GEN2_AMUX_THM3_30K_PU(sid) ((sid) << 8 | 0x26) -#define PM8350_ADC5_GEN2_AMUX_THM4_30K_PU(sid) ((sid) << 8 | 0x27) -#define PM8350_ADC5_GEN2_AMUX_THM5_30K_PU(sid) ((sid) << 8 | 0x28) -#define PM8350_ADC5_GEN2_GPIO1_30K_PU(sid) ((sid) << 8 | 0x2a) -#define PM8350_ADC5_GEN2_GPIO2_30K_PU(sid) ((sid) << 8 | 0x2b) -#define PM8350_ADC5_GEN2_GPIO3_30K_PU(sid) ((sid) << 8 | 0x2c) -#define PM8350_ADC5_GEN2_GPIO4_30K_PU(sid) ((sid) << 8 | 0x2d) - -/* 100k pull-up2 */ -#define PM8350_ADC5_GEN2_AMUX_THM1_100K_PU(sid) ((sid) << 8 | 0x44) -#define PM8350_ADC5_GEN2_AMUX_THM2_100K_PU(sid) ((sid) << 8 | 0x45) -#define PM8350_ADC5_GEN2_AMUX_THM3_100K_PU(sid) ((sid) << 8 | 0x46) -#define PM8350_ADC5_GEN2_AMUX_THM4_100K_PU(sid) ((sid) << 8 | 0x47) -#define PM8350_ADC5_GEN2_AMUX_THM5_100K_PU(sid) ((sid) << 8 | 0x48) -#define PM8350_ADC5_GEN2_GPIO1_100K_PU(sid) ((sid) << 8 | 0x4a) -#define PM8350_ADC5_GEN2_GPIO2_100K_PU(sid) ((sid) << 8 | 0x4b) -#define PM8350_ADC5_GEN2_GPIO3_100K_PU(sid) ((sid) << 8 | 0x4c) -#define PM8350_ADC5_GEN2_GPIO4_100K_PU(sid) ((sid) << 8 | 0x4d) - -/* 400k pull-up3 */ -#define PM8350_ADC5_GEN2_AMUX_THM1_400K_PU(sid) ((sid) << 8 | 0x64) -#define PM8350_ADC5_GEN2_AMUX_THM2_400K_PU(sid) ((sid) << 8 | 0x65) -#define PM8350_ADC5_GEN2_AMUX_THM3_400K_PU(sid) ((sid) << 8 | 0x66) -#define PM8350_ADC5_GEN2_AMUX_THM4_400K_PU(sid) ((sid) << 8 | 0x67) -#define PM8350_ADC5_GEN2_AMUX_THM5_400K_PU(sid) ((sid) << 8 | 0x68) -#define PM8350_ADC5_GEN2_GPIO1_400K_PU(sid) ((sid) << 8 | 0x6a) -#define PM8350_ADC5_GEN2_GPIO2_400K_PU(sid) ((sid) << 8 | 0x6b) -#define PM8350_ADC5_GEN2_GPIO3_400K_PU(sid) ((sid) << 8 | 0x6c) -#define PM8350_ADC5_GEN2_GPIO4_400K_PU(sid) ((sid) << 8 | 0x6d) - -/* 1/3 Divider */ -#define PM8350_ADC5_GEN2_GPIO4_DIV3(sid) ((sid) << 8 | 0x8d) - -#define PM8350_ADC5_GEN2_VPH_PWR(sid) ((sid) << 8 | 0x8e) - -#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350b.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350b.h deleted file mode 100644 index c7bb54e0b6a6..000000000000 --- a/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pm8350b.h +++ /dev/null @@ -1,89 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H -#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H - -#ifndef PM8350B_SID -#define PM8350B_SID 3 -#endif - -/* ADC channels for PM8350B_ADC for PMIC5 Gen2 */ -#define PM8350B_ADC5_GEN2_REF_GND (PM8350B_SID << 8 | 0x0) -#define PM8350B_ADC5_GEN2_1P25VREF (PM8350B_SID << 8 | 0x01) -#define PM8350B_ADC5_GEN2_VREF_VADC (PM8350B_SID << 8 | 0x02) -#define PM8350B_ADC5_GEN2_DIE_TEMP (PM8350B_SID << 8 | 0x03) - -#define PM8350B_ADC5_GEN2_AMUX_THM1 (PM8350B_SID << 8 | 0x04) -#define PM8350B_ADC5_GEN2_AMUX_THM2 (PM8350B_SID << 8 | 0x05) -#define PM8350B_ADC5_GEN2_AMUX_THM3 (PM8350B_SID << 8 | 0x06) -#define PM8350B_ADC5_GEN2_AMUX_THM4 (PM8350B_SID << 8 | 0x07) -#define PM8350B_ADC5_GEN2_AMUX_THM5 (PM8350B_SID << 8 | 0x08) -#define PM8350B_ADC5_GEN2_AMUX_THM6 (PM8350B_SID << 8 | 0x09) -#define PM8350B_ADC5_GEN2_GPIO1 (PM8350B_SID << 8 | 0x0a) -#define PM8350B_ADC5_GEN2_GPIO2 (PM8350B_SID << 8 | 0x0b) -#define PM8350B_ADC5_GEN2_GPIO3 (PM8350B_SID << 8 | 0x0c) -#define PM8350B_ADC5_GEN2_GPIO4 (PM8350B_SID << 8 | 0x0d) - -#define PM8350B_ADC5_GEN2_CHG_TEMP (PM8350B_SID << 8 | 0x10) -#define PM8350B_ADC5_GEN2_USB_IN_V_16 (PM8350B_SID << 8 | 0x11) -#define PM8350B_ADC5_GEN2_VDC_16 (PM8350B_SID << 8 | 0x12) -#define PM8350B_ADC5_GEN2_CC1_ID (PM8350B_SID << 8 | 0x13) -#define PM8350B_ADC5_GEN2_VREF_BAT_THERM (PM8350B_SID << 8 | 0x15) -#define PM8350B_ADC5_GEN2_IIN_FB (PM8350B_SID << 8 | 0x17) - -/* 30k pull-up1 */ -#define PM8350B_ADC5_GEN2_AMUX_THM1_30K_PU (PM8350B_SID << 8 | 0x24) -#define PM8350B_ADC5_GEN2_AMUX_THM2_30K_PU (PM8350B_SID << 8 | 0x25) -#define PM8350B_ADC5_GEN2_AMUX_THM3_30K_PU (PM8350B_SID << 8 | 0x26) -#define PM8350B_ADC5_GEN2_AMUX_THM4_30K_PU (PM8350B_SID << 8 | 0x27) -#define PM8350B_ADC5_GEN2_AMUX_THM5_30K_PU (PM8350B_SID << 8 | 0x28) -#define PM8350B_ADC5_GEN2_AMUX_THM6_30K_PU (PM8350B_SID << 8 | 0x29) -#define PM8350B_ADC5_GEN2_GPIO1_30K_PU (PM8350B_SID << 8 | 0x2a) -#define PM8350B_ADC5_GEN2_GPIO2_30K_PU (PM8350B_SID << 8 | 0x2b) -#define PM8350B_ADC5_GEN2_GPIO3_30K_PU (PM8350B_SID << 8 | 0x2c) -#define PM8350B_ADC5_GEN2_GPIO4_30K_PU (PM8350B_SID << 8 | 0x2d) -#define PM8350B_ADC5_GEN2_CC1_ID_30K_PU (PM8350B_SID << 8 | 0x33) - -/* 100k pull-up2 */ -#define PM8350B_ADC5_GEN2_AMUX_THM1_100K_PU (PM8350B_SID << 8 | 0x44) -#define PM8350B_ADC5_GEN2_AMUX_THM2_100K_PU (PM8350B_SID << 8 | 0x45) -#define PM8350B_ADC5_GEN2_AMUX_THM3_100K_PU (PM8350B_SID << 8 | 0x46) -#define PM8350B_ADC5_GEN2_AMUX_THM4_100K_PU (PM8350B_SID << 8 | 0x47) -#define PM8350B_ADC5_GEN2_AMUX_THM5_100K_PU (PM8350B_SID << 8 | 0x48) -#define PM8350B_ADC5_GEN2_AMUX_THM6_100K_PU (PM8350B_SID << 8 | 0x49) -#define PM8350B_ADC5_GEN2_GPIO1_100K_PU (PM8350B_SID << 8 | 0x4a) -#define PM8350B_ADC5_GEN2_GPIO2_100K_PU (PM8350B_SID << 8 | 0x4b) -#define PM8350B_ADC5_GEN2_GPIO3_100K_PU (PM8350B_SID << 8 | 0x4c) -#define PM8350B_ADC5_GEN2_GPIO4_100K_PU (PM8350B_SID << 8 | 0x4d) -#define PM8350B_ADC5_GEN2_CC1_ID_100K_PU (PM8350B_SID << 8 | 0x53) - -/* 400k pull-up3 */ -#define PM8350B_ADC5_GEN2_AMUX_THM1_400K_PU (PM8350B_SID << 8 | 0x64) -#define PM8350B_ADC5_GEN2_AMUX_THM2_400K_PU (PM8350B_SID << 8 | 0x65) -#define PM8350B_ADC5_GEN2_AMUX_THM3_400K_PU (PM8350B_SID << 8 | 0x66) -#define PM8350B_ADC5_GEN2_AMUX_THM4_400K_PU (PM8350B_SID << 8 | 0x67) -#define PM8350B_ADC5_GEN2_AMUX_THM5_400K_PU (PM8350B_SID << 8 | 0x68) -#define PM8350B_ADC5_GEN2_AMUX_THM6_400K_PU (PM8350B_SID << 8 | 0x69) -#define PM8350B_ADC5_GEN2_GPIO1_400K_PU (PM8350B_SID << 8 | 0x6a) -#define PM8350B_ADC5_GEN2_GPIO2_400K_PU (PM8350B_SID << 8 | 0x6b) -#define PM8350B_ADC5_GEN2_GPIO3_400K_PU (PM8350B_SID << 8 | 0x6c) -#define PM8350B_ADC5_GEN2_GPIO4_400K_PU (PM8350B_SID << 8 | 0x6d) -#define PM8350B_ADC5_GEN2_CC1_ID_400K_PU (PM8350B_SID << 8 | 0x73) - -/* 1/3 Divider */ -#define PM8350B_ADC5_GEN2_GPIO1_DIV3 (PM8350B_SID << 8 | 0x8a) -#define PM8350B_ADC5_GEN2_GPIO2_DIV3 (PM8350B_SID << 8 | 0x8b) -#define PM8350B_ADC5_GEN2_GPIO3_DIV3 (PM8350B_SID << 8 | 0x8c) -#define PM8350B_ADC5_GEN2_GPIO4_DIV3 (PM8350B_SID << 8 | 0x8d) - -#define PM8350B_ADC5_GEN2_VPH_PWR (PM8350B_SID << 8 | 0x8e) -#define PM8350B_ADC5_GEN2_VBAT_SNS (PM8350B_SID << 8 | 0x8f) - -#define PM8350B_ADC5_GEN2_SBUx (PM8350B_SID << 8 | 0x94) -#define PM8350B_ADC5_GEN2_VBAT_2S_MID (PM8350B_SID << 8 | 0x96) - -#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmk8350.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmk8350.h deleted file mode 100644 index 8de4ee86f875..000000000000 --- a/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmk8350.h +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H -#define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H - -#ifndef PMK8350_SID -#define PMK8350_SID 0 -#endif - -/* ADC channels for PMK8350_ADC for PMIC5 Gen2 */ -#define PMK8350_ADC5_GEN2_REF_GND (PMK8350_SID << 8 | 0x0) -#define PMK8350_ADC5_GEN2_1P25VREF (PMK8350_SID << 8 | 0x01) -#define PMK8350_ADC5_GEN2_VREF_VADC (PMK8350_SID << 8 | 0x02) -#define PMK8350_ADC5_GEN2_DIE_TEMP (PMK8350_SID << 8 | 0x03) - -#define PMK8350_ADC5_GEN2_AMUX_THM1 (PMK8350_SID << 8 | 0x04) -#define PMK8350_ADC5_GEN2_AMUX_THM2 (PMK8350_SID << 8 | 0x05) -#define PMK8350_ADC5_GEN2_AMUX_THM3 (PMK8350_SID << 8 | 0x06) -#define PMK8350_ADC5_GEN2_AMUX_THM4 (PMK8350_SID << 8 | 0x07) -#define PMK8350_ADC5_GEN2_AMUX_THM5 (PMK8350_SID << 8 | 0x08) - -/* 30k pull-up1 */ -#define PMK8350_ADC5_GEN2_AMUX_THM1_30K_PU (PMK8350_SID << 8 | 0x24) -#define PMK8350_ADC5_GEN2_AMUX_THM2_30K_PU (PMK8350_SID << 8 | 0x25) -#define PMK8350_ADC5_GEN2_AMUX_THM3_30K_PU (PMK8350_SID << 8 | 0x26) -#define PMK8350_ADC5_GEN2_AMUX_THM4_30K_PU (PMK8350_SID << 8 | 0x27) -#define PMK8350_ADC5_GEN2_AMUX_THM5_30K_PU (PMK8350_SID << 8 | 0x28) - -/* 100k pull-up2 */ -#define PMK8350_ADC5_GEN2_AMUX_THM1_100K_PU (PMK8350_SID << 8 | 0x44) -#define PMK8350_ADC5_GEN2_AMUX_THM2_100K_PU (PMK8350_SID << 8 | 0x45) -#define PMK8350_ADC5_GEN2_AMUX_THM3_100K_PU (PMK8350_SID << 8 | 0x46) -#define PMK8350_ADC5_GEN2_AMUX_THM4_100K_PU (PMK8350_SID << 8 | 0x47) -#define PMK8350_ADC5_GEN2_AMUX_THM5_100K_PU (PMK8350_SID << 8 | 0x48) - -/* 400k pull-up3 */ -#define PMK8350_ADC5_GEN2_AMUX_THM1_400K_PU (PMK8350_SID << 8 | 0x64) -#define PMK8350_ADC5_GEN2_AMUX_THM2_400K_PU (PMK8350_SID << 8 | 0x65) -#define PMK8350_ADC5_GEN2_AMUX_THM3_400K_PU (PMK8350_SID << 8 | 0x66) -#define PMK8350_ADC5_GEN2_AMUX_THM4_400K_PU (PMK8350_SID << 8 | 0x67) -#define PMK8350_ADC5_GEN2_AMUX_THM5_400K_PU (PMK8350_SID << 8 | 0x68) - -#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735a.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735a.h deleted file mode 100644 index 0f8ad745845b..000000000000 --- a/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735a.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H -#define _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H - -#ifndef PMR735A_SID -#define PMR735A_SID 4 -#endif - -/* ADC channels for PMR735A_ADC for PMIC5 Gen2 */ -#define PMR735A_ADC5_GEN2_REF_GND (PMR735A_SID << 8 | 0x0) -#define PMR735A_ADC5_GEN2_1P25VREF (PMR735A_SID << 8 | 0x01) -#define PMR735A_ADC5_GEN2_VREF_VADC (PMR735A_SID << 8 | 0x02) -#define PMR735A_ADC5_GEN2_DIE_TEMP (PMR735A_SID << 8 | 0x03) - -#define PMR735A_ADC5_GEN2_GPIO1 (PMR735A_SID << 8 | 0x0a) -#define PMR735A_ADC5_GEN2_GPIO2 (PMR735A_SID << 8 | 0x0b) -#define PMR735A_ADC5_GEN2_GPIO3 (PMR735A_SID << 8 | 0x0c) - -/* 100k pull-up2 */ -#define PMR735A_ADC5_GEN2_GPIO1_100K_PU (PMR735A_SID << 8 | 0x4a) -#define PMR735A_ADC5_GEN2_GPIO2_100K_PU (PMR735A_SID << 8 | 0x4b) -#define PMR735A_ADC5_GEN2_GPIO3_100K_PU (PMR735A_SID << 8 | 0x4c) - -#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735b.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735b.h deleted file mode 100644 index d05d057276e3..000000000000 --- a/include/dt-bindings/iio/qcom,spmi-adc5-gen2-pmr735b.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H -#define _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H - -#ifndef PMR735B_SID -#define PMR735B_SID 5 -#endif - -/* ADC channels for PMR735B_ADC for PMIC5 Gen2 */ -#define PMR735B_ADC5_GEN2_REF_GND (PMR735B_SID << 8 | 0x0) -#define PMR735B_ADC5_GEN2_1P25VREF (PMR735B_SID << 8 | 0x01) -#define PMR735B_ADC5_GEN2_VREF_VADC (PMR735B_SID << 8 | 0x02) -#define PMR735B_ADC5_GEN2_DIE_TEMP (PMR735B_SID << 8 | 0x03) - -#define PMR735B_ADC5_GEN2_GPIO1 (PMR735B_SID << 8 | 0x0a) -#define PMR735B_ADC5_GEN2_GPIO2 (PMR735B_SID << 8 | 0x0b) -#define PMR735B_ADC5_GEN2_GPIO3 (PMR735B_SID << 8 | 0x0c) - -/* 100k pull-up2 */ -#define PMR735B_ADC5_GEN2_GPIO1_100K_PU (PMR735B_SID << 8 | 0x4a) -#define PMR735B_ADC5_GEN2_GPIO2_100K_PU (PMR735B_SID << 8 | 0x4b) -#define PMR735B_ADC5_GEN2_GPIO3_100K_PU (PMR735B_SID << 8 | 0x4c) - -#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h deleted file mode 100644 index 74e6e2f6f9ed..000000000000 --- a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H -#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H - -#ifndef PM8550_SID -#define PM8550_SID 1 -#endif - -/* ADC channels for PM8550_ADC for PMIC5 Gen3 */ -#define PM8550_ADC5_GEN3_OFFSET_REF (PM8550_SID << 8 | 0x00) -#define PM8550_ADC5_GEN3_1P25VREF (PM8550_SID << 8 | 0x01) -#define PM8550_ADC5_GEN3_VREF_VADC (PM8550_SID << 8 | 0x02) -#define PM8550_ADC5_GEN3_DIE_TEMP (PM8550_SID << 8 | 0x03) - -#define PM8550_ADC5_GEN3_AMUX_THM1 (PM8550_SID << 8 | 0x04) -#define PM8550_ADC5_GEN3_AMUX_THM2 (PM8550_SID << 8 | 0x05) -#define PM8550_ADC5_GEN3_AMUX_THM3 (PM8550_SID << 8 | 0x06) -#define PM8550_ADC5_GEN3_AMUX_THM4 (PM8550_SID << 8 | 0x07) -#define PM8550_ADC5_GEN3_AMUX_THM5 (PM8550_SID << 8 | 0x08) -#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2 (PM8550_SID << 8 | 0x09) -#define PM8550_ADC5_GEN3_AMUX1_GPIO3 (PM8550_SID << 8 | 0x0a) -#define PM8550_ADC5_GEN3_AMUX2_GPIO4 (PM8550_SID << 8 | 0x0b) -#define PM8550_ADC5_GEN3_AMUX3_GPIO7 (PM8550_SID << 8 | 0x0c) -#define PM8550_ADC5_GEN3_AMUX4_GPIO12 (PM8550_SID << 8 | 0x0d) - -/* 100k pull-up */ -#define PM8550_ADC5_GEN3_AMUX_THM1_100K_PU (PM8550_SID << 8 | 0x44) -#define PM8550_ADC5_GEN3_AMUX_THM2_100K_PU (PM8550_SID << 8 | 0x45) -#define PM8550_ADC5_GEN3_AMUX_THM3_100K_PU (PM8550_SID << 8 | 0x46) -#define PM8550_ADC5_GEN3_AMUX_THM4_100K_PU (PM8550_SID << 8 | 0x47) -#define PM8550_ADC5_GEN3_AMUX_THM5_100K_PU (PM8550_SID << 8 | 0x48) -#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2_100K_PU (PM8550_SID << 8 | 0x49) -#define PM8550_ADC5_GEN3_AMUX1_GPIO3_100K_PU (PM8550_SID << 8 | 0x4a) -#define PM8550_ADC5_GEN3_AMUX2_GPIO4_100K_PU (PM8550_SID << 8 | 0x4b) -#define PM8550_ADC5_GEN3_AMUX3_GPIO7_100K_PU (PM8550_SID << 8 | 0x4c) -#define PM8550_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550_SID << 8 | 0x4d) - -/* 1/3 Divider */ -#define PM8550_ADC5_GEN3_AMUX3_GPIO7_DIV3 (PM8550_SID << 8 | 0x8c) -#define PM8550_ADC5_GEN3_AMUX4_GPIO12_DIV3 (PM8550_SID << 8 | 0x8d) - -#define PM8550_ADC5_GEN3_VPH_PWR (PM8550_SID << 8 | 0x8e) - -#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h deleted file mode 100644 index 35483dfd970e..000000000000 --- a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H -#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H - -#ifndef PM8550B_SID -#define PM8550B_SID 7 -#endif - -/* ADC channels for PM8550B_ADC for PMIC5 Gen3 */ -#define PM8550B_ADC5_GEN3_OFFSET_REF (PM8550B_SID << 8 | 0x00) -#define PM8550B_ADC5_GEN3_1P25VREF (PM8550B_SID << 8 | 0x01) -#define PM8550B_ADC5_GEN3_VREF_VADC (PM8550B_SID << 8 | 0x02) -#define PM8550B_ADC5_GEN3_DIE_TEMP (PM8550B_SID << 8 | 0x03) - -#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM (PM8550B_SID << 8 | 0x04) -#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID (PM8550B_SID << 8 | 0x05) -#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V (PM8550B_SID << 8 | 0x06) -#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM (PM8550B_SID << 8 | 0x07) -#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION (PM8550B_SID << 8 | 0x08) -#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10 (PM8550B_SID << 8 | 0x09) -#define PM8550B_ADC5_GEN3_AMUX1_GPIO1 (PM8550B_SID << 8 | 0x0a) -#define PM8550B_ADC5_GEN3_AMUX2_GPIO5 (PM8550B_SID << 8 | 0x0b) -#define PM8550B_ADC5_GEN3_AMUX3_GPIO6 (PM8550B_SID << 8 | 0x0c) -#define PM8550B_ADC5_GEN3_AMUX4_GPIO12 (PM8550B_SID << 8 | 0x0d) - -#define PM8550B_ADC5_GEN3_CHG_TEMP (PM8550B_SID << 8 | 0x10) -#define PM8550B_ADC5_GEN3_USB_SNS_V_16 (PM8550B_SID << 8 | 0x11) -#define PM8550B_ADC5_GEN3_VIN_DIV16_MUX (PM8550B_SID << 8 | 0x12) -#define PM8550B_ADC5_GEN3_USBC_MUX (PM8550B_SID << 8 | 0x13) -#define PM8550B_ADC5_GEN3_VREF_BAT_THERM (PM8550B_SID << 8 | 0x15) -#define PM8550B_ADC5_GEN3_IIN_FB (PM8550B_SID << 8 | 0x17) -#define PM8550B_ADC5_GEN3_TEMP_ALARM_LITE (PM8550B_SID << 8 | 0x18) -#define PM8550B_ADC5_GEN3_SMB_IIN (PM8550B_SID << 8 | 0x19) -#define PM8550B_ADC5_GEN3_VREF_BAT2_THERM (PM8550B_SID << 8 | 0x1a) -#define PM8550B_ADC5_GEN3_SMB_ICHG (PM8550B_SID << 8 | 0x1b) -#define PM8550B_ADC5_GEN3_SMB_TEMP_I (PM8550B_SID << 8 | 0x1e) -#define PM8550B_ADC5_GEN3_CHG_TEMP_I (PM8550B_SID << 8 | 0x1f) -#define PM8550B_ADC5_GEN3_ICHG_FB (PM8550B_SID << 8 | 0xa1) - -/* 30k pull-up */ -#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_30K_PU (PM8550B_SID << 8 | 0x24) -#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_30K_PU (PM8550B_SID << 8 | 0x25) -#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_30K_PU (PM8550B_SID << 8 | 0x26) -#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_30K_PU (PM8550B_SID << 8 | 0x27) -#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_30K_PU (PM8550B_SID << 8 | 0x28) -#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_30K_PU (PM8550B_SID << 8 | 0x29) -#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_30K_PU (PM8550B_SID << 8 | 0x2a) -#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_30K_PU (PM8550B_SID << 8 | 0x2b) -#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_30K_PU (PM8550B_SID << 8 | 0x2c) -#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_30K_PU (PM8550B_SID << 8 | 0x2d) - -#define PM8550B_ADC5_GEN3_USBC_MUX_30K_PU (PM8550B_SID << 8 | 0x33) - -/* 100k pull-up */ -#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_100K_PU (PM8550B_SID << 8 | 0x44) -#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_100K_PU (PM8550B_SID << 8 | 0x45) -#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_100K_PU (PM8550B_SID << 8 | 0x46) -#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU (PM8550B_SID << 8 | 0x47) -#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_100K_PU (PM8550B_SID << 8 | 0x48) -#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_100K_PU (PM8550B_SID << 8 | 0x49) -#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_100K_PU (PM8550B_SID << 8 | 0x4a) -#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_100K_PU (PM8550B_SID << 8 | 0x4b) -#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_100K_PU (PM8550B_SID << 8 | 0x4c) -#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550B_SID << 8 | 0x4d) - -#define PM8550B_ADC5_GEN3_USBC_MUX_100K_PU (PM8550B_SID << 8 | 0x53) - -/* 400k pull-up */ -#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_400K_PU (PM8550B_SID << 8 | 0x64) -#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_400K_PU (PM8550B_SID << 8 | 0x65) -#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_400K_PU (PM8550B_SID << 8 | 0x66) -#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_400K_PU (PM8550B_SID << 8 | 0x67) -#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_400K_PU (PM8550B_SID << 8 | 0x68) -#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_400K_PU (PM8550B_SID << 8 | 0x69) -#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_400K_PU (PM8550B_SID << 8 | 0x6a) -#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_400K_PU (PM8550B_SID << 8 | 0x6b) -#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_400K_PU (PM8550B_SID << 8 | 0x6c) -#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_400K_PU (PM8550B_SID << 8 | 0x6d) - -#define PM8550B_ADC5_GEN3_USBC_MUX_400K_PU (PM8550B_SID << 8 | 0x73) - -/* 1/3 Divider */ -#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_DIV3 (PM8550B_SID << 8 | 0x8a) -#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_DIV3 (PM8550B_SID << 8 | 0x8b) -#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_DIV3 (PM8550B_SID << 8 | 0x8c) - -#define PM8550B_ADC5_GEN3_VPH_PWR (PM8550B_SID << 8 | 0x8e) -#define PM8550B_ADC5_GEN3_VBAT_SNS_QBG (PM8550B_SID << 8 | 0x8f) -#define PM8550B_ADC5_GEN3_VBAT_SNS_CHGR (PM8550B_SID << 8 | 0x94) -#define PM8550B_ADC5_GEN3_VBAT_2S_MID_QBG (PM8550B_SID << 8 | 0x96) -#define PM8550B_ADC5_GEN3_VBAT_2S_MID_CHGR (PM8550B_SID << 8 | 0x9d) - -#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h deleted file mode 100644 index 337e13f7f56f..000000000000 --- a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H -#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H - -/* ADC channels for PM8550VX_ADC for PMIC5 Gen3 */ -#define PM8550VS_ADC5_GEN3_OFFSET_REF(sid) ((sid) << 8 | 0x00) -#define PM8550VS_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | 0x01) -#define PM8550VS_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | 0X02) -#define PM8550VS_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | 0x03) - -#define PM8550VE_ADC5_GEN3_OFFSET_REF(sid) ((sid) << 8 | 0x00) -#define PM8550VE_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | 0x01) -#define PM8550VE_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | 0X02) -#define PM8550VE_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | 0x03) - -#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h deleted file mode 100644 index 126fc16d5b20..000000000000 --- a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H -#define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H - -#ifndef PMK8550_SID -#define PMK8550_SID 0 -#endif - -/* ADC channels for PMK8550_ADC for PMIC5 Gen3 */ -#define PMK8550_ADC5_GEN3_OFFSET_REF (PMK8550_SID << 8 | 0x00) -#define PMK8550_ADC5_GEN3_1P25VREF (PMK8550_SID << 8 | 0x01) -#define PMK8550_ADC5_GEN3_VREF_VADC (PMK8550_SID << 8 | 0x02) -#define PMK8550_ADC5_GEN3_DIE_TEMP (PMK8550_SID << 8 | 0x03) - -#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM (PMK8550_SID << 8 | 0x04) -#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1 (PMK8550_SID << 8 | 0x05) -#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2 (PMK8550_SID << 8 | 0x06) -#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3 (PMK8550_SID << 8 | 0x07) -#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4 (PMK8550_SID << 8 | 0x08) -#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5 (PMK8550_SID << 8 | 0x09) -#define PMK8550_ADC5_GEN3_AMUX1_GPIO6 (PMK8550_SID << 8 | 0x0a) - -/* 30k pull-up */ -#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_30K_PU (PMK8550_SID << 8 | 0x24) -#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_30K_PU (PMK8550_SID << 8 | 0x25) -#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_30K_PU (PMK8550_SID << 8 | 0x26) -#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_30K_PU (PMK8550_SID << 8 | 0x27) -#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_30K_PU (PMK8550_SID << 8 | 0x28) -#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_30K_PU (PMK8550_SID << 8 | 0x29) -#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_30K_PU (PMK8550_SID << 8 | 0x2a) - -/* 100k pull-up */ -#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU (PMK8550_SID << 8 | 0x44) -#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_100K_PU (PMK8550_SID << 8 | 0x45) -#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_100K_PU (PMK8550_SID << 8 | 0x46) -#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_100K_PU (PMK8550_SID << 8 | 0x47) -#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_100K_PU (PMK8550_SID << 8 | 0x48) -#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_100K_PU (PMK8550_SID << 8 | 0x49) -#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_100K_PU (PMK8550_SID << 8 | 0x4a) - -/* 400k pull-up */ -#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_400K_PU (PMK8550_SID << 8 | 0x64) -#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_400K_PU (PMK8550_SID << 8 | 0x65) -#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_400K_PU (PMK8550_SID << 8 | 0x66) -#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_400K_PU (PMK8550_SID << 8 | 0x67) -#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_400K_PU (PMK8550_SID << 8 | 0x68) -#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_400K_PU (PMK8550_SID << 8 | 0x69) -#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_400K_PU (PMK8550_SID << 8 | 0x6a) - -#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-vadc.h b/include/dt-bindings/iio/qcom,spmi-vadc.h deleted file mode 100644 index ca5a0a947b3b..000000000000 --- a/include/dt-bindings/iio/qcom,spmi-vadc.h +++ /dev/null @@ -1,379 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved. - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H -#define _DT_BINDINGS_QCOM_SPMI_VADC_H - -/* Voltage ADC channels */ -#define VADC_USBIN 0x00 -#define VADC_DCIN 0x01 -#define VADC_VCHG_SNS 0x02 -#define VADC_SPARE1_03 0x03 -#define VADC_USB_ID_MV 0x04 -#define VADC_VCOIN 0x05 -#define VADC_VBAT_SNS 0x06 -#define VADC_VSYS 0x07 -#define VADC_DIE_TEMP 0x08 -#define VADC_REF_625MV 0x09 -#define VADC_REF_1250MV 0x0a -#define VADC_CHG_TEMP 0x0b -#define VADC_SPARE1 0x0c -#define VADC_SPARE2 0x0d -#define VADC_GND_REF 0x0e -#define VADC_VDD_VADC 0x0f - -#define VADC_P_MUX1_1_1 0x10 -#define VADC_P_MUX2_1_1 0x11 -#define VADC_P_MUX3_1_1 0x12 -#define VADC_P_MUX4_1_1 0x13 -#define VADC_P_MUX5_1_1 0x14 -#define VADC_P_MUX6_1_1 0x15 -#define VADC_P_MUX7_1_1 0x16 -#define VADC_P_MUX8_1_1 0x17 -#define VADC_P_MUX9_1_1 0x18 -#define VADC_P_MUX10_1_1 0x19 -#define VADC_P_MUX11_1_1 0x1a -#define VADC_P_MUX12_1_1 0x1b -#define VADC_P_MUX13_1_1 0x1c -#define VADC_P_MUX14_1_1 0x1d -#define VADC_P_MUX15_1_1 0x1e -#define VADC_P_MUX16_1_1 0x1f - -#define VADC_P_MUX1_1_3 0x20 -#define VADC_P_MUX2_1_3 0x21 -#define VADC_P_MUX3_1_3 0x22 -#define VADC_P_MUX4_1_3 0x23 -#define VADC_P_MUX5_1_3 0x24 -#define VADC_P_MUX6_1_3 0x25 -#define VADC_P_MUX7_1_3 0x26 -#define VADC_P_MUX8_1_3 0x27 -#define VADC_P_MUX9_1_3 0x28 -#define VADC_P_MUX10_1_3 0x29 -#define VADC_P_MUX11_1_3 0x2a -#define VADC_P_MUX12_1_3 0x2b -#define VADC_P_MUX13_1_3 0x2c -#define VADC_P_MUX14_1_3 0x2d -#define VADC_P_MUX15_1_3 0x2e -#define VADC_P_MUX16_1_3 0x2f - -#define VADC_LR_MUX1_BAT_THERM 0x30 -#define VADC_LR_MUX2_BAT_ID 0x31 -#define VADC_LR_MUX3_XO_THERM 0x32 -#define VADC_LR_MUX4_AMUX_THM1 0x33 -#define VADC_LR_MUX5_AMUX_THM2 0x34 -#define VADC_LR_MUX6_AMUX_THM3 0x35 -#define VADC_LR_MUX7_HW_ID 0x36 -#define VADC_LR_MUX8_AMUX_THM4 0x37 -#define VADC_LR_MUX9_AMUX_THM5 0x38 -#define VADC_LR_MUX10_USB_ID 0x39 -#define VADC_AMUX_PU1 0x3a -#define VADC_AMUX_PU2 0x3b -#define VADC_LR_MUX3_BUF_XO_THERM 0x3c - -#define VADC_LR_MUX1_PU1_BAT_THERM 0x70 -#define VADC_LR_MUX2_PU1_BAT_ID 0x71 -#define VADC_LR_MUX3_PU1_XO_THERM 0x72 -#define VADC_LR_MUX4_PU1_AMUX_THM1 0x73 -#define VADC_LR_MUX5_PU1_AMUX_THM2 0x74 -#define VADC_LR_MUX6_PU1_AMUX_THM3 0x75 -#define VADC_LR_MUX7_PU1_AMUX_HW_ID 0x76 -#define VADC_LR_MUX8_PU1_AMUX_THM4 0x77 -#define VADC_LR_MUX9_PU1_AMUX_THM5 0x78 -#define VADC_LR_MUX10_PU1_AMUX_USB_ID 0x79 -#define VADC_LR_MUX3_BUF_PU1_XO_THERM 0x7c - -#define VADC_LR_MUX1_PU2_BAT_THERM 0xb0 -#define VADC_LR_MUX2_PU2_BAT_ID 0xb1 -#define VADC_LR_MUX3_PU2_XO_THERM 0xb2 -#define VADC_LR_MUX4_PU2_AMUX_THM1 0xb3 -#define VADC_LR_MUX5_PU2_AMUX_THM2 0xb4 -#define VADC_LR_MUX6_PU2_AMUX_THM3 0xb5 -#define VADC_LR_MUX7_PU2_AMUX_HW_ID 0xb6 -#define VADC_LR_MUX8_PU2_AMUX_THM4 0xb7 -#define VADC_LR_MUX9_PU2_AMUX_THM5 0xb8 -#define VADC_LR_MUX10_PU2_AMUX_USB_ID 0xb9 -#define VADC_LR_MUX3_BUF_PU2_XO_THERM 0xbc - -#define VADC_LR_MUX1_PU1_PU2_BAT_THERM 0xf0 -#define VADC_LR_MUX2_PU1_PU2_BAT_ID 0xf1 -#define VADC_LR_MUX3_PU1_PU2_XO_THERM 0xf2 -#define VADC_LR_MUX4_PU1_PU2_AMUX_THM1 0xf3 -#define VADC_LR_MUX5_PU1_PU2_AMUX_THM2 0xf4 -#define VADC_LR_MUX6_PU1_PU2_AMUX_THM3 0xf5 -#define VADC_LR_MUX7_PU1_PU2_AMUX_HW_ID 0xf6 -#define VADC_LR_MUX8_PU1_PU2_AMUX_THM4 0xf7 -#define VADC_LR_MUX9_PU1_PU2_AMUX_THM5 0xf8 -#define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID 0xf9 -#define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM 0xfc - -/* ADC channels for SPMI PMIC5 */ - -#define ADC5_REF_GND 0x00 -#define ADC5_1P25VREF 0x01 -#define ADC5_VREF_VADC 0x02 -#define ADC5_VREF_VADC5_DIV_3 0x82 -#define ADC5_VPH_PWR 0x83 -#define ADC5_VBAT_SNS 0x84 -#define ADC5_VCOIN 0x85 -#define ADC5_DIE_TEMP 0x06 -#define ADC5_USB_IN_I 0x07 -#define ADC5_USB_IN_V_16 0x08 -#define ADC5_CHG_TEMP 0x09 -#define ADC5_BAT_THERM 0x0a -#define ADC5_BAT_ID 0x0b -#define ADC5_XO_THERM 0x0c -#define ADC5_AMUX_THM1 0x0d -#define ADC5_AMUX_THM2 0x0e -#define ADC5_AMUX_THM3 0x0f -#define ADC5_AMUX_THM4 0x10 -#define ADC5_AMUX_THM5 0x11 -#define ADC5_GPIO1 0x12 -#define ADC5_GPIO2 0x13 -#define ADC5_GPIO3 0x14 -#define ADC5_GPIO4 0x15 -#define ADC5_GPIO5 0x16 -#define ADC5_GPIO6 0x17 -#define ADC5_GPIO7 0x18 -#define ADC5_SBUx 0x99 -#define ADC5_MID_CHG_DIV6 0x1e -#define ADC5_OFF 0xff - -/* 30k pull-up1 */ -#define ADC5_BAT_THERM_30K_PU 0x2a -#define ADC5_BAT_ID_30K_PU 0x2b -#define ADC5_XO_THERM_30K_PU 0x2c -#define ADC5_AMUX_THM1_30K_PU 0x2d -#define ADC5_AMUX_THM2_30K_PU 0x2e -#define ADC5_AMUX_THM3_30K_PU 0x2f -#define ADC5_AMUX_THM4_30K_PU 0x30 -#define ADC5_AMUX_THM5_30K_PU 0x31 -#define ADC5_GPIO1_30K_PU 0x32 -#define ADC5_GPIO2_30K_PU 0x33 -#define ADC5_GPIO3_30K_PU 0x34 -#define ADC5_GPIO4_30K_PU 0x35 -#define ADC5_GPIO5_30K_PU 0x36 -#define ADC5_GPIO6_30K_PU 0x37 -#define ADC5_GPIO7_30K_PU 0x38 -#define ADC5_SBUx_30K_PU 0x39 - -/* 100k pull-up2 */ -#define ADC5_BAT_THERM_100K_PU 0x4a -#define ADC5_BAT_ID_100K_PU 0x4b -#define ADC5_XO_THERM_100K_PU 0x4c -#define ADC5_AMUX_THM1_100K_PU 0x4d -#define ADC5_AMUX_THM2_100K_PU 0x4e -#define ADC5_AMUX_THM3_100K_PU 0x4f -#define ADC5_AMUX_THM4_100K_PU 0x50 -#define ADC5_AMUX_THM5_100K_PU 0x51 -#define ADC5_GPIO1_100K_PU 0x52 -#define ADC5_GPIO2_100K_PU 0x53 -#define ADC5_GPIO3_100K_PU 0x54 -#define ADC5_GPIO4_100K_PU 0x55 -#define ADC5_GPIO5_100K_PU 0x56 -#define ADC5_GPIO6_100K_PU 0x57 -#define ADC5_GPIO7_100K_PU 0x58 -#define ADC5_SBUx_100K_PU 0x59 - -/* 400k pull-up3 */ -#define ADC5_BAT_THERM_400K_PU 0x6a -#define ADC5_BAT_ID_400K_PU 0x6b -#define ADC5_XO_THERM_400K_PU 0x6c -#define ADC5_AMUX_THM1_400K_PU 0x6d -#define ADC5_AMUX_THM2_400K_PU 0x6e -#define ADC5_AMUX_THM3_400K_PU 0x6f -#define ADC5_AMUX_THM4_400K_PU 0x70 -#define ADC5_AMUX_THM5_400K_PU 0x71 -#define ADC5_GPIO1_400K_PU 0x72 -#define ADC5_GPIO2_400K_PU 0x73 -#define ADC5_GPIO3_400K_PU 0x74 -#define ADC5_GPIO4_400K_PU 0x75 -#define ADC5_GPIO5_400K_PU 0x76 -#define ADC5_GPIO6_400K_PU 0x77 -#define ADC5_GPIO7_400K_PU 0x78 -#define ADC5_SBUx_400K_PU 0x79 - -/* 1/3 Divider */ -#define ADC5_GPIO1_DIV3 0x92 -#define ADC5_GPIO2_DIV3 0x93 -#define ADC5_GPIO3_DIV3 0x94 -#define ADC5_GPIO4_DIV3 0x95 -#define ADC5_GPIO5_DIV3 0x96 -#define ADC5_GPIO6_DIV3 0x97 -#define ADC5_GPIO7_DIV3 0x98 -#define ADC5_SBUx_DIV3 0x99 - -/* Current and combined current/voltage channels */ -#define ADC5_INT_EXT_ISENSE 0xa1 -#define ADC5_PARALLEL_ISENSE 0xa5 -#define ADC5_CUR_REPLICA_VDS 0xa7 -#define ADC5_CUR_SENS_BATFET_VDS_OFFSET 0xa9 -#define ADC5_CUR_SENS_REPLICA_VDS_OFFSET 0xab -#define ADC5_EXT_SENS_OFFSET 0xad - -#define ADC5_INT_EXT_ISENSE_VBAT_VDATA 0xb0 -#define ADC5_INT_EXT_ISENSE_VBAT_IDATA 0xb1 -#define ADC5_EXT_ISENSE_VBAT_VDATA 0xb2 -#define ADC5_EXT_ISENSE_VBAT_IDATA 0xb3 -#define ADC5_PARALLEL_ISENSE_VBAT_VDATA 0xb4 -#define ADC5_PARALLEL_ISENSE_VBAT_IDATA 0xb5 - -#define ADC5_MAX_CHANNEL 0xc0 - -/* ADC channels for ADC for PMIC5 Gen2 */ - -#define ADC5_GEN2_REF_GND 0x00 -#define ADC5_GEN2_1P25VREF 0x01 -#define ADC5_GEN2_VREF_VADC 0x02 -#define ADC5_GEN2_DIE_TEMP 0x03 - -#define ADC5_GEN2_AMUX_THM1 0x04 -#define ADC5_GEN2_AMUX_THM2 0x05 -#define ADC5_GEN2_AMUX_THM3 0x06 -#define ADC5_GEN2_AMUX_THM4 0x07 -#define ADC5_GEN2_AMUX_THM5 0x08 -#define ADC5_GEN2_AMUX_THM6 0x09 -#define ADC5_GEN2_GPIO1 0x0a -#define ADC5_GEN2_GPIO2 0x0b -#define ADC5_GEN2_GPIO3 0x0c -#define ADC5_GEN2_GPIO4 0x0d - -#define ADC5_GEN2_CHG_TEMP 0x10 -#define ADC5_GEN2_USB_IN_V_16 0x11 -#define ADC5_GEN2_VDC_16 0x12 -#define ADC5_GEN2_CC1_ID 0x13 -#define ADC5_GEN2_VREF_BAT_THERM 0x15 -#define ADC5_GEN2_IIN_FB 0x17 - -/* 30k pull-up1 */ -#define ADC5_GEN2_AMUX_THM1_30K_PU 0x24 -#define ADC5_GEN2_AMUX_THM2_30K_PU 0x25 -#define ADC5_GEN2_AMUX_THM3_30K_PU 0x26 -#define ADC5_GEN2_AMUX_THM4_30K_PU 0x27 -#define ADC5_GEN2_AMUX_THM5_30K_PU 0x28 -#define ADC5_GEN2_AMUX_THM6_30K_PU 0x29 -#define ADC5_GEN2_GPIO1_30K_PU 0x2a -#define ADC5_GEN2_GPIO2_30K_PU 0x2b -#define ADC5_GEN2_GPIO3_30K_PU 0x2c -#define ADC5_GEN2_GPIO4_30K_PU 0x2d -#define ADC5_GEN2_CC1_ID_30K_PU 0x33 - -/* 100k pull-up2 */ -#define ADC5_GEN2_AMUX_THM1_100K_PU 0x44 -#define ADC5_GEN2_AMUX_THM2_100K_PU 0x45 -#define ADC5_GEN2_AMUX_THM3_100K_PU 0x46 -#define ADC5_GEN2_AMUX_THM4_100K_PU 0x47 -#define ADC5_GEN2_AMUX_THM5_100K_PU 0x48 -#define ADC5_GEN2_AMUX_THM6_100K_PU 0x49 -#define ADC5_GEN2_GPIO1_100K_PU 0x4a -#define ADC5_GEN2_GPIO2_100K_PU 0x4b -#define ADC5_GEN2_GPIO3_100K_PU 0x4c -#define ADC5_GEN2_GPIO4_100K_PU 0x4d -#define ADC5_GEN2_CC1_ID_100K_PU 0x53 - -/* 400k pull-up3 */ -#define ADC5_GEN2_AMUX_THM1_400K_PU 0x64 -#define ADC5_GEN2_AMUX_THM2_400K_PU 0x65 -#define ADC5_GEN2_AMUX_THM3_400K_PU 0x66 -#define ADC5_GEN2_AMUX_THM4_400K_PU 0x67 -#define ADC5_GEN2_AMUX_THM5_400K_PU 0x68 -#define ADC5_GEN2_AMUX_THM6_400K_PU 0x69 -#define ADC5_GEN2_GPIO1_400K_PU 0x6a -#define ADC5_GEN2_GPIO2_400K_PU 0x6b -#define ADC5_GEN2_GPIO3_400K_PU 0x6c -#define ADC5_GEN2_GPIO4_400K_PU 0x6d -#define ADC5_GEN2_CC1_ID_400K_PU 0x73 - -/* 1/3 Divider */ -#define ADC5_GEN2_GPIO1_DIV3 0x8a -#define ADC5_GEN2_GPIO2_DIV3 0x8b -#define ADC5_GEN2_GPIO3_DIV3 0x8c -#define ADC5_GEN2_GPIO4_DIV3 0x8d - -#define ADC5_GEN2_VPH_PWR 0x8e -#define ADC5_GEN2_VBAT_SNS 0x8f - -#define ADC5_GEN2_SBUx 0x94 -#define ADC5_GEN2_VBAT_2S_MID 0x96 - -/* ADC channels for PMIC5 Gen3 */ - -#define ADC5_GEN3_OFFSET_REF 0x00 -#define ADC5_GEN3_1P25VREF 0x01 -#define ADC5_GEN3_VREF_VADC 0x02 -#define ADC5_GEN3_DIE_TEMP 0x03 - -#define ADC5_GEN3_AMUX1_THM 0x04 -#define ADC5_GEN3_AMUX2_THM 0x05 -#define ADC5_GEN3_AMUX3_THM 0x06 -#define ADC5_GEN3_AMUX4_THM 0x07 -#define ADC5_GEN3_AMUX5_THM 0x08 -#define ADC5_GEN3_AMUX6_THM 0x09 -#define ADC5_GEN3_AMUX1_GPIO 0x0a -#define ADC5_GEN3_AMUX2_GPIO 0x0b -#define ADC5_GEN3_AMUX3_GPIO 0x0c -#define ADC5_GEN3_AMUX4_GPIO 0x0d - -#define ADC5_GEN3_CHG_TEMP 0x10 -#define ADC5_GEN3_USB_SNS_V_16 0x11 -#define ADC5_GEN3_VIN_DIV16_MUX 0x12 -#define ADC5_GEN3_VREF_BAT_THERM 0x15 -#define ADC5_GEN3_IIN_FB 0x17 -#define ADC5_GEN3_TEMP_ALARM_LITE 0x18 -#define ADC5_GEN3_IIN_SMB 0x19 -#define ADC5_GEN3_ICHG_SMB 0x1b -#define ADC5_GEN3_ICHG_FB 0xa1 - -/* 30k pull-up1 */ -#define ADC5_GEN3_AMUX1_THM_30K_PU 0x24 -#define ADC5_GEN3_AMUX2_THM_30K_PU 0x25 -#define ADC5_GEN3_AMUX3_THM_30K_PU 0x26 -#define ADC5_GEN3_AMUX4_THM_30K_PU 0x27 -#define ADC5_GEN3_AMUX5_THM_30K_PU 0x28 -#define ADC5_GEN3_AMUX6_THM_30K_PU 0x29 -#define ADC5_GEN3_AMUX1_GPIO_30K_PU 0x2a -#define ADC5_GEN3_AMUX2_GPIO_30K_PU 0x2b -#define ADC5_GEN3_AMUX3_GPIO_30K_PU 0x2c -#define ADC5_GEN3_AMUX4_GPIO_30K_PU 0x2d - -/* 100k pull-up2 */ -#define ADC5_GEN3_AMUX1_THM_100K_PU 0x44 -#define ADC5_GEN3_AMUX2_THM_100K_PU 0x45 -#define ADC5_GEN3_AMUX3_THM_100K_PU 0x46 -#define ADC5_GEN3_AMUX4_THM_100K_PU 0x47 -#define ADC5_GEN3_AMUX5_THM_100K_PU 0x48 -#define ADC5_GEN3_AMUX6_THM_100K_PU 0x49 -#define ADC5_GEN3_AMUX1_GPIO_100K_PU 0x4a -#define ADC5_GEN3_AMUX2_GPIO_100K_PU 0x4b -#define ADC5_GEN3_AMUX3_GPIO_100K_PU 0x4c -#define ADC5_GEN3_AMUX4_GPIO_100K_PU 0x4d - -/* 400k pull-up3 */ -#define ADC5_GEN3_AMUX1_THM_400K_PU 0x64 -#define ADC5_GEN3_AMUX2_THM_400K_PU 0x65 -#define ADC5_GEN3_AMUX3_THM_400K_PU 0x66 -#define ADC5_GEN3_AMUX4_THM_400K_PU 0x67 -#define ADC5_GEN3_AMUX5_THM_400K_PU 0x68 -#define ADC5_GEN3_AMUX6_THM_400K_PU 0x69 -#define ADC5_GEN3_AMUX1_GPIO_400K_PU 0x6a -#define ADC5_GEN3_AMUX2_GPIO_400K_PU 0x6b -#define ADC5_GEN3_AMUX3_GPIO_400K_PU 0x6c -#define ADC5_GEN3_AMUX4_GPIO_400K_PU 0x6d - -/* 1/3 Divider */ -#define ADC5_GEN3_AMUX1_GPIO_DIV3 0x8a -#define ADC5_GEN3_AMUX2_GPIO_DIV3 0x8b -#define ADC5_GEN3_AMUX3_GPIO_DIV3 0x8c - -#define ADC5_GEN3_VPH_PWR 0x8e -#define ADC5_GEN3_VBAT_SNS_QBG 0x8f - -#define ADC5_GEN3_VBAT_SNS_CHGR 0x94 -#define ADC5_GEN3_VBAT_2S_MID_QBG 0x96 -#define ADC5_GEN3_VBAT_2S_MID_CHGR 0x9d - -#define ADC5_GEN3_OFFSET_EXT2 0xf8 - -#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */